WO2024000451A1 - 薄膜晶体管、移位寄存器单元、栅极驱动电路和显示面板 - Google Patents

薄膜晶体管、移位寄存器单元、栅极驱动电路和显示面板 Download PDF

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WO2024000451A1
WO2024000451A1 PCT/CN2022/102945 CN2022102945W WO2024000451A1 WO 2024000451 A1 WO2024000451 A1 WO 2024000451A1 CN 2022102945 W CN2022102945 W CN 2022102945W WO 2024000451 A1 WO2024000451 A1 WO 2024000451A1
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source
drain
units
thin film
output
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PCT/CN2022/102945
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English (en)
French (fr)
Inventor
王利忠
袁广才
宁策
胡合合
姚念琦
王东方
李正亮
雷利平
许晨
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京东方科技集团股份有限公司
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Priority to CN202280002073.7A priority Critical patent/CN117642865A/zh
Priority to PCT/CN2022/102945 priority patent/WO2024000451A1/zh
Publication of WO2024000451A1 publication Critical patent/WO2024000451A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • At least one embodiment of the present disclosure provides a thin film transistor, a shift register unit, a gate driving circuit and a display panel.
  • Switching elements in the field of display technology play an important role in high-definition display devices.
  • the conductive performance of the switching element Thin Film Transistor (TFT) directly affects the opening degree of the TFT, affects the deflection degree of the liquid crystal molecules, and thus affects the image display screen.
  • TFT Thin Film Transistor
  • the charging current of the TFT is increased by increasing the width-to-length ratio of the TFT channel.
  • the charging current requirements of the TFTs in the circuit are higher, and the TFTs fabricated in the non-display area of the array substrate are , its TFT size requirements are lower than those designed in pixels, so a TFT with a larger area and higher charging current is designed.
  • the materials of the TFT semiconductor layer mainly include amorphous silicon (a-Si) or oxides (such as IGZO, Indium Gallium Zinc Oxide, indium gallium zinc oxide), etc., as people pay more attention to high PPI (Pixels Per Inch, pixel density) , high refresh frequency, narrow frame products, traditional a-Si thin film transistor products can no longer meet the needs of device performance, and oxide technology, as the most likely new technology to replace a-Si thin film transistor products, has become the current focus of research.
  • a-Si amorphous silicon
  • oxides such as IGZO, Indium Gallium Zinc Oxide, indium gallium zinc oxide
  • At least one embodiment of the present disclosure provides a thin film transistor, which includes a source electrode, a drain electrode, a gate electrode, and a semiconductor layer.
  • the source includes source wiring and P source units electrically connected to the source wiring.
  • Each of the P source units includes M source branches, and each of the M source branches is along the first direction.
  • the drain electrode includes a drain wiring and P drain units electrically connected to the drain wiring and corresponding one-to-one with P source units, P
  • Each of the drain units includes N drain branches, each of the N drain branches extends along the first direction and is spaced apart in the second direction;
  • the thin film transistor includes P source-drain units, one source unit and A corresponding drain unit constitutes a source-drain unit.
  • M source branches and N drain branches are alternately arranged, spaced apart from each other, and insulated. M is greater than or equal to N.
  • the gate is insulated from the source and drain; the semiconductor layer is electrically connected to M source branches and N drain branches of each source and drain unit, and the semiconductor layer is included in each of the P source and drain units.
  • a plurality of sub-channel regions, each of the plurality of sub-channel regions is located between adjacent drain branches and source branches; the sum of the widths of the multiple sub-channel regions of the P source-drain units in the first direction is W, the average length of multiple sub-channel regions of P source-drain units in the direction perpendicular to the first direction is L; 12 ⁇ W/L ⁇ 400, P, M and N are all integers greater than or equal to 1, P ⁇ N ⁇ 4.
  • the thin film transistor provided by at least one embodiment of the present disclosure, 112 ⁇ W/L ⁇ 400 and P ⁇ N ⁇ 6.
  • P ⁇ N ⁇ 16 In the thin film transistor provided by at least one embodiment of the present disclosure, P ⁇ N ⁇ 16.
  • 235 ⁇ W/L ⁇ 400 and P ⁇ N ⁇ 32 are examples of the thin film transistor provided by at least one embodiment of the present disclosure.
  • W/L ⁇ 180, and W ranges from 10 ⁇ m to 1600 ⁇ m.
  • the plurality of source and drain units are arranged into at least one unit row, and each of the at least one unit row includes at least one source and drain unit; the same In the unit row, the distance between adjacent source and drain units is d, W ⁇ 500 ⁇ m, and d ranges from 50 ⁇ m to 500 ⁇ m.
  • the plurality of source and drain units are arranged into at least one unit row, and each of the at least one unit row includes at least one source and drain unit; the same In the unit row, the distance between adjacent source and drain units is d, W ⁇ 500 ⁇ m, and d ranges from 20 ⁇ m to 300 ⁇ m.
  • the plurality of source and drain units are arranged into at least two unit rows, and each of the at least one unit row includes at least one source and drain unit.
  • the semiconductor layer includes a sub-portion that overlaps each of the plurality of source-drain units, and the sub-portion includes Q semiconductor branches.
  • the plurality of sub-channel regions include sub-channel units of the Q semiconductor branches located between the adjacent source branches and the drain branches, Q is an integer greater than or equal to 1; W is The sum of the widths of the sub-channel units of the Q semiconductor branches of the P source-drain units in the first direction, L is the plurality of sub-channel units of the P source-drain units and the The average length in the direction perpendicular to the first direction.
  • the semiconductor layer includes a sub-portion overlapping with each source-drain unit in the plurality of source-drain units, and a sub-portion overlapping the source-drain unit A plurality of said sub-sections form a continuous integrated structure.
  • the plurality of source-drain units are disposed in a region between the adjacent source lines and the drain lines, so as to connect the plurality of source and drain units.
  • the source and drain units are arranged into at least two unit rows, each of the at least two unit rows includes at least one of the source and drain units; the at least one source and drain unit in each of the unit rows
  • the source branches are electrically connected to the same source line, and the drain branches of the at least one source-drain unit in each unit row are electrically connected to the same drain line.
  • At least one embodiment of the present disclosure also provides a shift register unit, the shift register unit including any thin film transistor provided by the implementation of the present disclosure.
  • the gate row driving circuit includes an input circuit, an output circuit and a first node reset circuit; the input circuit is connected to the first node and is configured as charging the first node in response to an input signal; the output circuit is connected to the first node and configured to output an output signal at an output end under the control of a level signal of the first node; The first node reset circuit is connected to the first node and configured to reset the first node in response to a reset signal; the output circuit, the input circuit and the first node reset circuit all include a The thin film transistor of claim 1.
  • the output terminal includes a shift output terminal and a scan signal output terminal;
  • the output circuit includes a first output transistor and a second output transistor; and the third The gate of an output transistor is connected to the first node, the first pole of the first output transistor is connected to the clock signal terminal to receive the clock signal, and the second pole of the first output transistor is connected to the shift output.
  • both the first output transistor and the second output transistor are according to claim 1 Thin film transistor; both the first output transistor and the second output transistor satisfy P ⁇ 3 and N ⁇ 2, or the first output transistor and the second output transistor both satisfy P ⁇ N ⁇ 12, or the third output transistor satisfies P ⁇ N ⁇ 12. Both the first output transistor and the second output transistor satisfy P ⁇ N ⁇ 16.
  • the first output transistor satisfies 235 ⁇ W/L ⁇ 400 and P ⁇ N ⁇ 32.
  • At least one embodiment of the present disclosure also provides a gate drive circuit, the gate drive circuit includes any one of the shift register units provided by the embodiments of the present disclosure, and the gate drive circuit includes a plurality of cascaded shift register units; Except for the shift register units from the 1st level to the sth level, the precharge control terminals of the shift register units at all other levels are connected to the output terminals of the upper-level shift register units that are at least s levels away from them; except for the 1st level to the sth level.
  • the input terminals of the remaining shift register units are connected to the output terminals of the upper-level shift register unit that is s-1 level away from it; except for the last s-level shift register unit, the remaining shift register units
  • the reset terminal of the register unit is connected to the output terminal of the lower-level shift register unit that is s-1 level away from it; where s is an integer greater than 2.
  • At least one embodiment of the present disclosure also provides a display panel, including any gate driving circuit provided by the embodiment of the present disclosure.
  • the display panel includes a display area and a non-display area at least partially surrounding the display area; the non-display area includes: a gate drive circuit area and circuit leads area.
  • the gate drive circuit area extends along the longitudinal direction and is provided with the gate drive circuit, wherein the plurality of cascaded shift register units are arranged along the longitudinal direction; circuit leads are provided in the circuit lead area, along with the A transverse extension that intersects longitudinally and is adjacent to the gate drive circuit area, the circuit leads include a first lead connected to the gate drive circuit and a second lead connected to the display area; the plurality of stages
  • the connected shift register unit includes an end shift register unit located at one end of the circuit area close to the circuit lead area; in each of the shift registers, the output end includes a shift output end and a scan signal Output terminal; the output circuit includes a first output transistor and a second output transistor; the gate of the first output transistor is connected to the first node, and the first pole of the first output transistor
  • the second pole of the first output transistor is connected to the shift output terminal; the gate of the second output transistor is connected to the first node, and the first pole of the second output transistor is connected to the first node.
  • the second pole of the second output transistor is connected to the clock signal terminal to receive the clock signal, and the second pole of the second output transistor is connected to the scan signal output terminal; the clock signal is transmitted to the output terminal as the output signal.
  • the first output transistor and the second output transistor are both thin film transistors according to claim 1; the P ⁇ N value of the first output transistor in the end shift register unit and the end shift The P ⁇ N value of the second output transistor in the bit register unit is respectively greater than the P ⁇ N value of the first output transistor in other shift register units in the plurality of cascaded shift register units and the The value of P ⁇ N for the second output transistor in the end shift register cell.
  • Figure 1 is a schematic structural diagram of a thin film transistor provided by at least one embodiment of the present disclosure
  • Figure 2 is a partially enlarged schematic diagram of a source-drain unit of the thin film transistor shown in Figure 1;
  • Figure 3A is a schematic structural diagram of two transistors in a shift register unit provided by at least one embodiment of the present disclosure
  • 3B is a schematic structural diagram of two transistors in another shift register unit provided by at least one embodiment of the present disclosure
  • 4A is a relationship between the total width W of the channel region of the thin film transistor and the threshold voltage drift amount ⁇ th of the thin film transistor provided by at least one embodiment of the present disclosure
  • 4B is a relationship between the average length L of the sub-channel region of the thin film transistor and the threshold voltage drift amount ⁇ th of the thin film transistor provided by at least one embodiment of the present disclosure
  • 4C is a relationship between the ratio W/L of the total width W of the channel region of the thin film transistor and the average length L of the sub-channel region and the threshold voltage drift amount ⁇ th of the thin film transistor provided by at least one embodiment of the present disclosure
  • Figure 5A is a relationship between the number of source/drain branches of a source-drain unit of a thin film transistor provided by at least one embodiment of the present disclosure and the threshold voltage drift amount ⁇ th of the thin film transistor;
  • FIG. 5B is a relationship between the number of source-drain units of the thin film transistor and the threshold voltage drift amount ⁇ th of the thin film transistor provided by at least one embodiment of the present disclosure
  • 5C is a relationship between the distance between adjacent source-drain units of the thin film transistor provided by at least one embodiment of the present disclosure and the threshold voltage drift amount ⁇ th of the thin film transistor;
  • FIG. 6A is a schematic structural diagram of another thin film transistor provided by at least one embodiment of the present disclosure.
  • FIG. 6B is a schematic structural diagram of yet another thin film transistor provided by at least one embodiment of the present disclosure.
  • Figure 7 is an exemplary circuit diagram of a shift register unit provided by at least one embodiment of the present disclosure.
  • Figure 8 is an exemplary circuit diagram of another shift register unit provided by at least one embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a display panel further provided by at least one embodiment of the present disclosure.
  • GOA Gate Driver on array, array substrate row drive
  • COF chip-on-flex/film
  • COG Chip On Glass
  • the main feature of GOA technology is that it relies on the GOA drive unit integrated on the array substrate for continuous triggering. Realizing its shift register function replaces the original Gate Driver IC's bonding area and Fan-out wiring space, allowing the panel to achieve a symmetrical and beautiful design on both sides, achieving a narrow frame design, reducing costs, and at the same time It is also beneficial to increase production capacity and yield rate.
  • the materials of the TFT semiconductor layer mainly include amorphous silicon (a-Si) or oxides (such as IGZO, Indium Gallium Zinc Oxide, indium gallium zinc oxide), etc., as people pay more attention to high PPI (Pixels Per Inch) , pixel density), high refresh frequency, narrow frame products, traditional a-Si thin film transistor products can no longer meet the needs of device performance, and oxide technology, as the most likely new technology to replace aSi thin film transistor products, has become the most popular technology in various display devices. The focus of manufacturer research.
  • a GOA circuit includes multiple thin film transistors.
  • Each thin film transistor includes multiple source branches, multiple drain branches, multiple semiconductor branches, source wiring and drain wiring.
  • the multiple source branches are connected to the source.
  • On the electrode trace multiple drain branches are connected to the drain trace, and multiple source branches and multiple drain branches are divided into multiple units (TFT units).
  • the mobility of conventional oxide transistors is below 10.
  • high mobility oxides have very large instability in device characteristics. Problems, especially the large width-to-length ratio will lead to a substantial increase in on-state current (Ion), prominent device heating problems, and an increase in the drift of the maximum threshold voltage, ultimately leading to poor reliability of the display device and affecting the quality of the GOA display panel. display effect.
  • At least one embodiment of the present disclosure provides a thin film transistor, which includes a source electrode, a drain electrode, a gate electrode, and a semiconductor layer.
  • the source includes source wiring and P source units electrically connected to the source wiring.
  • Each of the P source units includes M source branches, and each of the M source branches is along the first direction.
  • the drain electrode includes a drain wiring and P drain units electrically connected to the drain wiring and corresponding one-to-one with P source units, P
  • Each of the drain units includes N drain branches, each of the N drain branches extends along the first direction and is spaced apart in the second direction;
  • the thin film transistor includes P source-drain units, one source unit and A corresponding drain unit constitutes a source-drain unit.
  • M source branches and N drain branches are alternately arranged, spaced apart from each other, and insulated. M is greater than or equal to N.
  • the gate is insulated from the source and drain; the semiconductor layer is electrically connected to M source branches and N drain branches of each source and drain unit, and the semiconductor layer is included in each of the P source and drain units.
  • a plurality of sub-channel regions, each of the plurality of sub-channel regions is located between adjacent drain branches and source branches; the sum of the widths of the multiple sub-channel regions of the P source-drain units in the first direction is W, the average length of multiple sub-channel regions of P source-drain units in the direction perpendicular to the first direction is L; 12 ⁇ W/L ⁇ 400, P, M and N are all integers greater than or equal to 1, P ⁇ N ⁇ 4.
  • At least one embodiment of the present disclosure also provides a shift register unit, the shift register unit including any thin film transistor provided by the implementation of the present disclosure.
  • At least one embodiment of the present disclosure also provides a gate drive circuit, the gate drive circuit includes any one of the shift register units provided by the embodiments of the present disclosure, and the gate drive circuit includes a plurality of cascaded shift register units; Except for the shift register units from the 1st level to the sth level, the precharge control terminals of the shift register units at all other levels are connected to the output terminals of the upper-level shift register units that are at least s levels away from them; except for the 1st level to the sth level.
  • the input terminals of the remaining shift register units are connected to the output terminals of the upper-level shift register unit that is s-1 level away from it; except for the last s-level shift register unit, the remaining shift register units
  • the reset terminal of the register unit is connected to the output terminal of the lower-level shift register unit that is s-1 level away from it; where s is an integer greater than 2.
  • At least one embodiment of the present disclosure also provides a display panel, including any gate driving circuit provided by the embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a thin film transistor provided by at least one embodiment of the present disclosure.
  • the thin film transistor includes: a source electrode 100 , a drain electrode 200 , a gate electrode 300 and a semiconductor layer 400 .
  • the source 100 includes a source wiring 110 and P source units electrically connected to the source wiring 110.
  • Each of the P source units includes N source branches 120, and each of the N source branches 120
  • the drain electrodes 200 include drain wires 210 and are electrically connected to the drain wires 210 and are connected to P source units.
  • a corresponding P drain unit, each of the P drain units includes M drain branches 220, each of the M drain branches 220 extends along the first direction D1 and is spaced apart in the second direction D2.
  • the thin film transistor includes P source-drain units 10.
  • One source unit and a corresponding drain unit constitute a source-drain unit 10.
  • N source electrodes Branches 120 and M drain branches 220 are alternately arranged, spaced apart from each other, and insulated, M is greater than or equal to N; the gate 300 is insulated from the source 100 and the drain 200 ; the semiconductor layer 400 is insulated from the N sources of each source-drain unit 10
  • the branch 120 is electrically connected to the M drain branches 220.
  • the semiconductor layer 400 includes a plurality of sub-channel regions 40 located in each of the P source-drain units 10, and each of the plurality of sub-channel regions 40 is located with each other.
  • the sum of the widths of the plurality of sub-channel regions 40 of the P source-drain units 10 in the first direction D1 is W (hereinafter referred to as the total width of the channel region )
  • the average length of the plurality of sub-channel regions 40 of the P source-drain units 10 in the direction perpendicular to the first direction D1 is L (the average length of the sub-channel regions); 12 ⁇ W/L ⁇ 400, P, Both M and N are integers greater than or equal to 1, and P ⁇ N ⁇ 4.
  • Figure 4A shows the case where the total width W of the channel region of the thin film transistor is 500 ⁇ m, 800 ⁇ m, 1000 ⁇ m, 2100 ⁇ m and 3000 ⁇ m respectively. It can be seen that the offset ⁇ th of the threshold voltage of the thin film transistor is positively related to W. .
  • Figure 4B shows the case where the average lengths L of the sub-channel regions of the thin film transistor are 4.5 ⁇ m, 5.5 ⁇ m, 6.5 ⁇ m, 7.5 ⁇ m and 8.5 ⁇ m respectively. It can be seen that the threshold voltage of the thin film transistor shifts.
  • the quantity ⁇ th is negatively related to L.
  • Reducing the threshold voltage offset ⁇ th is beneficial to improving the charging rate of the thin film transistor, and the better the performance of the thin film transistor.
  • an increase in the on-state current Ion will cause serious heating of the thin film transistor.
  • the offset ⁇ th of the threshold voltage will also become larger. Therefore, it is important to explore the design boundaries of thin film transistors.
  • the inventor established the relationship between W/L and P ⁇ N.
  • P ⁇ N ⁇ 4 can Effectively reduce the heat generation of the thin film transistor, reduce the threshold voltage offset ⁇ th of the thin film transistor, improve the charging rate of the thin film transistor, maintain the stability of the performance of the thin film transistor during operation, thereby improving the display of the GOA drive circuit including the thin film transistor.
  • the display effect of the panel will not cause excessively high on-state current Ion, and avoid blindly increasing the number of source-drain units, the number of source branches and drain branches, which will cause source branches and drain branches.
  • the branches are arranged in a high-density arrangement to avoid heat accumulation caused by this high-density arrangement.
  • the product of the appropriate number P of source-drain units and the number N of source branches in a source-drain unit can be found to achieve a better technical effect of reducing the heating of thin film transistors. It is of great significance to the rational design of transistors. Especially for transistors with larger W (for example, W greater than 100 ⁇ m), the effect of reducing the heat generation of thin film transistors is more obvious.
  • the design boundaries of the quantities of P and N can be controlled, and the design rules are clearer, so that the heating problem can be reasonably improved on the basis of predictability.
  • Arranging multiple thin film transistors in the circuit (such as GOA driving circuit) area of the display panel also facilitates the reasonable arrangement of multiple thin film transistors in the limited GOA area (non-display area, such as at least partially surrounding the display area) of the display panel.
  • Thin film transistors, setting more shift register units to drive more rows of pixels in the display area of the display panel are conducive to driving a high PPI display panel, and in the GOA area of the high PPI display panel, the GOA drive circuit
  • the arrangement of thin film transistors in the thin film transistor is more dense.
  • the lengths of the multiple sub-channel regions 40 may not all be equal.
  • the above-mentioned L is the width of the multiple sub-channel regions 40 of the P source-drain units 10 in the first direction D1
  • the sum of is W, the average length of the plurality of sub-channel regions 40 of the P source-drain units 10 in the direction perpendicular to the first direction D1.
  • the thin film transistor shown in FIG. 1 is used as an example to explain this below.
  • N sources in one source-drain unit 10 The pole branches 120 constitute a source unit, and the M drain branches 220 in a source-drain unit 10 constitute a drain unit.
  • alternating arrangement refers to the regular arrangement of one source branch 120, one drain branch 220, one source branch 120, one drain branch 220..., or, according to a drain branch A branch 220, a source branch 120, a drain branch 220, a source branch 120... are arranged regularly.
  • FIG. 3A shows a structure of the thin film transistor M13 and the thin film transistor M3.
  • P ⁇ N ⁇ 12 is used to further effectively reduce the heat generation of the thin film transistor.
  • the thin film transistor M3 also satisfies 112 ⁇ W/L ⁇ 400.
  • the heating problem of the thin film transistor M3 has been significantly improved and can be controlled.
  • the design boundaries for the number of P and N are more clear, and the design rules are clearer.
  • P ⁇ N ⁇ 16 can further effectively reduce the heat generation of the thin film transistor.
  • FIG. 3B shows another structure of the thin film transistor M13 and the thin film transistor M3.
  • 235 ⁇ W/L ⁇ 400, P ⁇ N ⁇ 32 For example, further, 235 ⁇ W/L ⁇ 400, P ⁇ N ⁇ 32. That is, for a relatively larger W/L value (at least 235), after experimental exploration, it satisfies 235 ⁇ W/L ⁇ 400, and P ⁇ N ⁇ 32 can significantly reduce the heating degree of the thin film transistor and lower the threshold of the thin film transistor.
  • the voltage offset ⁇ th maintains the stability of the performance of the thin film transistor during operation, thereby improving the display effect of a display panel using a GOA drive circuit including the thin film transistor.
  • P ⁇ 8 and N ⁇ 4 can further effectively reduce the heat generation of the thin film transistor.
  • Figure 5A shows the case where W is 1200 ⁇ m, L is 4.5 ⁇ m, and the number of source branches N (the number of source branches N here represents the number of source/drain branches) is 9 and 39 respectively, W is 1200 ⁇ m, When L is 6m, the number of source branches N is 9 and 39 respectively, W is 1200 ⁇ m, L is 8.5 ⁇ m, and the number N of source branches is 9 and 39 respectively. Therefore, appropriately increasing the number of source/drain branches is beneficial to reducing the threshold voltage offset ⁇ th and reducing the heat generation of the thin film transistor.
  • Figure 5B shows the case where the number of source and drain cells P is 2, 12, and 16 respectively. It can be seen that within a certain range, the offset ⁇ th of the threshold voltage is negative with the number of source and drain cells P. Related, and increasing the number of source/drain branches is also beneficial to reducing the heat generation of thin film transistors.
  • adjusting the total width W of the channel region can more effectively adjust the offset ⁇ th of the threshold voltage and improve the operating performance of the thin film transistor.
  • the range of W is 10 ⁇ m ⁇ 1600 ⁇ m, which can better reduce the offset of the threshold voltage ⁇ th, improve the heating problem of thin film transistors, and provide the optimal channel area size for thin film transistors. Design provides guidance.
  • W/L>180 W/L>180
  • L ranges from 4 ⁇ m to 15 ⁇ m.
  • W/L>180 the total width W of the channel region has a small impact on the offset ⁇ th of the threshold voltage.
  • the sub-channel region The average length L has a greater impact on the offset ⁇ th. Therefore, when W/L>180, adjusting the average length L of the sub-channel region can more effectively adjust the offset ⁇ th of the threshold voltage and improve the operating performance of the thin film transistor.
  • the range of L is 4 ⁇ m ⁇ 15 ⁇ m, which can better reduce the offset of the threshold voltage ⁇ th, improve the heating problem of thin film transistors, and provide the optimal channel area size for thin film transistors. Design provides guidance.
  • L 6 ⁇ m to 8.5 ⁇ m, so that it is easier to control the value of W/L and realize appropriate transistor size design.
  • a plurality of source-drain units 10 are arranged into at least one unit row 1, and each unit row 1 in at least one unit row 1 includes at least one source-drain unit 10; in the same unit row 1, adjacent source-drain units 10 The distance between them is d.
  • FIG. 5C shows the shift amount ⁇ th of the threshold voltage in the case where the distance d between adjacent source-drain cells 10 is 50 ⁇ m, 100 ⁇ m, 150 ⁇ m, 200 ⁇ m, and 250 ⁇ m respectively in the same unit row 1 . and the on-state current Ion. According to FIG.
  • the offset ⁇ th of the threshold voltage of the thin film transistor is negatively correlated with the distance d between adjacent source-drain cells 10.
  • the distance d between adjacent cells 10 in each cell row 1 The larger the distance d between them, the stronger the heat dissipation capability, and the smaller the threshold voltage offset ⁇ th, which is conducive to improving the charging rate of the thin film transistor and the better the performance of the thin film transistor.
  • the on-state current Ion increases.
  • We hope to obtain a smaller threshold voltage offset ⁇ th and we do not want the on-state current Ion to be too high.
  • the threshold voltage offset ⁇ th will also become larger. Therefore, it is important to explore design boundaries.
  • W ⁇ 500 ⁇ m, and the distance d between adjacent source and drain units 10 in the same unit row 1 ranges from 50 ⁇ m to 500 ⁇ m.
  • the condition that W ⁇ 500 ⁇ m and the range of d is 50 ⁇ m ⁇ 500 ⁇ m is consistent with the condition of 12 ⁇ W/L ⁇ 400 and P ⁇
  • the combination of N ⁇ 4 conditions can achieve a better effect of reducing the offset ⁇ th of the threshold voltage of the thin film transistor and reducing the heat generation of the thin film transistor when the total width W of the channel region of the thin film transistor is large.
  • Thin film transistors that satisfy W ⁇ 500 ⁇ m provide design boundaries for the design of thin film transistors with the purpose of effectively reducing the offset ⁇ th of the threshold voltage of the thin film transistor and reducing the degree of heat generation of the thin film transistor.
  • W ⁇ 500 ⁇ m the distance between adjacent source and drain units 10 in the same unit row 1 is d, and the range of d is 20 ⁇ m to 300 ⁇ m.
  • the condition that W ⁇ 500 ⁇ m and the range of d is 20 ⁇ m ⁇ 300 ⁇ m is consistent with the condition of 12 ⁇ W/L ⁇ 400 and P ⁇
  • the combination of N ⁇ 4 conditions can achieve a better effect of reducing the offset ⁇ th of the threshold voltage of the thin film transistor and reducing the heat generation of the thin film transistor when the total width W of the channel region of the thin film transistor is large.
  • Thin film transistors that satisfy W ⁇ 500 ⁇ m provide design boundaries for the design of thin film transistors with the purpose of effectively reducing the offset ⁇ th of the threshold voltage of the thin film transistor and reducing the degree of heat generation of the thin film transistor.
  • the distance d between adjacent source and drain units 10 in the same unit row 1 is not limited to this.
  • a plurality of source-drain units 10 are arranged into at least two unit rows 1 , and each of the at least one unit row 1 includes at least one source-drain unit 10 .
  • a plurality of source-drain units 10 are disposed in a region between adjacent source lines 110 and drain lines 210 to arrange the plurality of source-drain units 10 into at least two unit rows 1 .
  • the first source trace 110a, the first drain trace 210a and the second drain trace 210b are arranged in parallel and spaced apart; and the first source trace 110a is located between the first drain trace 210a and the second drain trace 210a.
  • a plurality of source and drain units 10 are arranged at intervals between the first source trace 110a and the first drain trace 210a to form the first unit row 11; in the first source trace 110a A plurality of source-drain cells 10 are arranged at intervals between the second drain wiring 210b and the second drain wiring 210b to form a second cell row 12.
  • the drain branches 220 of each unit 10 in the first unit row 11 are connected to the first drain wiring 210a, and the drain branches 220 of each unit 10 in the second unit row 12 are connected to the second drain wiring 210b.
  • the source branch 120 of at least one source-drain unit 10 in each unit row 1 is electrically connected to the same source wiring 110
  • the drain branch 220 of at least one source-drain unit 10 in each unit row 1 is electrically connected to the same source line 110.
  • the source branches 120 of each source-drain unit 10 in the first unit row 11 are connected to one side of the first source trace 110a
  • the source branches 120 of each source-drain unit 10 in the second unit row 12 are connected to the first source line 110a.
  • the other side of a source trace 110a that is, the source branches 120 in the first unit row 11 and the source branches 120 in the second unit row 12 share the same first source trace 110a.
  • the source-drain units 10 of the thin film transistors may also be arranged in only one unit row.
  • the number of source-drain units 10 in the first unit row 11 is 4, and the number q of units 10 in the second unit row 12 is 4.
  • the total number of units 10 is 8.
  • the number q of source-drain units 10 in each unit row 1 is not limited to this.
  • the number q of source-drain units 10 in each unit row 1 can also be only 2.
  • the total number of source and drain units 10 in the two unit rows 1 of the thin film transistor is still greater than 3 to improve the heat dissipation performance of the thin film transistor.
  • the number of source and drain units 10 in the thin film transistor can also be less than 3. Or equal to 3.
  • the semiconductor layer 400 includes a sub-portion overlapped with each source-drain unit 10 of the plurality of source-drain units 10 , that is, the sub-portion overlaps with each drain unit 10 in the first direction D1 There is overlap with the orthographic projection on the plane defined by the second direction D2.
  • Each sub-section includes Q semiconductor branches 410.
  • the plurality of sub-channel regions 40 includes adjacent source branches 120 and drain branches of the Q semiconductor branches 410.
  • the sub-channel unit 401 between the pole branches 220 is represented by a small rectangle as shown in FIG. 2 , and Q is an integer greater than or equal to 1.
  • the total width W of the channel region is the sum of the widths of the sub-channel units 401 of the Q semiconductor branches 410 of the P source-drain units 10 in the first direction D1.
  • One sub-channel unit 401 is in the first direction D1.
  • L is the average length of the plurality of sub-channel units 401 of the P source-drain units 10 in the direction perpendicular to the first direction D1, for example,
  • the two directions D2 are perpendicular to the first direction D1,
  • L the sum of the lengths of the plurality of sub-channel units 401 of the P source-drain units 10 in the second direction D2/the total number of sub-channel units 401, for example, in the plurality of sub-channel units 401
  • L L'.
  • the orthographic projection of the gate 300 on the base substrate does not overlap with the orthographic projection of the source trace 110 on the base substrate, and the gate The orthographic projection of the pole 300 on the base substrate overlaps the orthographic projection of the drain trace 210 on the base substrate.
  • the orthographic projection of the gate 300 on the base substrate does not overlap with the orthographic projection of the first source trace 110a on the base substrate, for example, as illustrated in FIG. 1 , the gate 300 is designed to be hollowed out at the position where the first source trace 110a is arranged. In this way, the overlapping area of the gate 300 and the first source trace 110a can be reduced, thereby reducing the CGS capacitance. That is, the capacitance between the gate 300 and the first source trace 110a is reduced to reduce the signal DELAY; and the orthographic projection of the gate 300 on the base substrate is in contact with the first drain
  • the orthographic projections of the trace 210a and the second drain trace 210b on the base substrate overlap. For example, as shown in FIG.
  • the source branch 120 and the drain electrode in each unit 10 of the thin film transistor are identical to each unit 10 of the thin film transistor.
  • the orthographic projections of the electrode branches 220, the first drain wiring 210a, and the second drain wiring 210b on the base substrate all fall on the orthographic projection of the gate 300 on the base substrate, so that , the CGD capacitance, that is, the capacitance between the drain electrode 200 and the gate electrode 300, can be increased to reduce signal noise.
  • the first end of the first source trace 110 a is connected to the clock pulse signal trace 600 in the GOA circuit.
  • the orthographic projection of the gate 300 on the substrate does not overlap with the orthographic projection of the clock pulse signal trace 600 on the substrate, and the gate 300 is connected to the gate trace 310, and the gate trace 310 is on the substrate.
  • the orthographic projection on the base substrate intersects and overlaps with the orthographic projection of the clock pulse signal trace 600 on the base substrate.
  • reducing the overlapping area between the gate 300 and the clock pulse signal trace 600 can further reduce the CGS capacitance, that is, reducing the capacitance between the gate 300 and the clock pulse signal trace 600,
  • DELAY delay
  • the gate electrodes 300 are connected by a gate trace 310.
  • the gate trace 310 is arranged on the side of the gate 300 close to the clock pulse signal trace 600.
  • the gate 300 has a hollow pattern on the side where the clock pulse signal trace 600 is located.
  • the hollow pattern can increase the gap between the gate electrodes 300 of adjacent thin film transistors. spacing, thereby reducing the heating problem of the gate 300.
  • a drain electrode block 230 formed by a metal layer of the drain electrode 200 is disposed between two adjacent units 10 .
  • the drain electrode block 230 and the gate electrode 300 are on the base substrate.
  • drain electrode block 230 may not be disposed between two adjacent units 10 according to actual requirements.
  • one end of the drain trace 210 is connected to the signal output terminal 500 , and a first gate metal pattern 320 formed by the metal layer of the gate electrode 300 is also provided on the substrate.
  • the first gate metal pattern 320 is located on one side of the signal output terminal 500, and is independent and insulated from the gate 300; a plurality of first via holes 510 are provided on the signal output terminal 500, and the first gate A plurality of second via holes 321 are provided on the metal pattern 320, and the signal output terminal 500 is connected to an ITO layer (indium tin oxide) 330 through the first via hole 510, and the first gate metal pattern 320 is connected through the second via hole 321 to the ITO layer 330 to achieve electrical connection between the signal output terminal 500 and the first gate metal pattern 320, and the first gate metal pattern 320 is electrically connected to the pixel electrode of the display device through the second via hole 321.
  • one end of the first source trace 110 a is connected to the clock pulse signal trace 600 , and the trace direction of the clock pulse signal trace 600 is perpendicular to the first source trace 110 a Setup; the signal output terminal 500 is connected to the same end of the first drain trace 210a and the second drain trace 210b, and is arranged vertically with the first drain trace 210a, and the clock pulse signal trace 600 is connected to the signal output terminal 500 are located on opposite sides of the thin film transistor.
  • the location of the clock pulse signal trace and the signal output terminal 500 is not limited to this case.
  • FIG. 6A is a schematic structural diagram of another thin film transistor provided by at least one embodiment of the present disclosure.
  • the thin film transistor shown in FIG. 6A has the following differences from the thin film transistor shown in FIG. 1 .
  • at least one semiconductor branch 410 is designed to compensate for the semiconductor branch 411 .
  • the total channel length of the compensation semiconductor branch 411 is smaller than the channels of other semiconductor branches 410 .
  • Other features and corresponding technical effects of the embodiment shown in FIG. 6A are the same as those in FIG. 1 . Please refer to the previous description, which will not be repeated here.
  • FIG. 6B is a schematic structural diagram of yet another thin film transistor provided by at least one embodiment of the present disclosure.
  • the thin film transistor shown in FIG. 6B has the following differences from the thin film transistor shown in FIG. 1 .
  • the semiconductor layer 400 includes a sub-portion that overlaps each of the plurality of source-drain units 10 , that is, the sub-portion overlaps with each drain unit 10 in the first direction.
  • the orthographic projections on the plane defined by D1 and the second direction D2 overlap, and the sub-sections overlapping with the plurality of source and drain units 10 form a continuous integrated structure.
  • W W2 ⁇ P.
  • the thin film transistor can be a P-type thin film transistor or an N-type thin film transistor, and the structure can be a bottom gate type, a top gate type, or a double gate type.
  • the embodiments of the present disclosure do not specify the specific type of the thin film transistor. limited.
  • At least one embodiment of the present disclosure also provides a shift register unit, the shift register unit including any thin film transistor provided by the implementation of the present disclosure.
  • FIG. 7 is an exemplary circuit diagram of a shift register unit provided by at least one embodiment of the present disclosure.
  • the gate row driving circuit includes an input circuit 101, an output circuit 102/103 and a first node reset circuit 104; the input circuit 101 is connected to the first node PU and is configured as The first node PU is charged in response to the input signal; the output circuit 102/103 is connected to the first node PU, and is configured to output the output signal at the output terminal Output1 under the control of the level signal of the first node PU; A node reset circuit 104 is connected to the first node PU and is configured to reset the first node PU in response to a reset signal; the output circuits 102/103, the input circuit 101 and the first node reset circuit 104 all include any of the methods provided by the present disclosure.
  • a thin film transistor is connected to the first node PU and is configured as The first node PU is charged in response to the input signal;
  • the output circuit 102/103 is connected to the first node PU,
  • the output terminal Output1 includes a scan signal output terminal, which is the first output terminal Output1, and a shift output terminal, which is the second output terminal Output2.
  • the output circuit includes a first output sub-circuit 102 and a second output sub-circuit 103 .
  • the shift register unit 01 also includes a monitoring subcircuit 105 .
  • the input circuit 101 is configured to respond to the input signal and precharge the pull-up node PU (ie, the above-mentioned first node PU) through the input signal;
  • the pull-up node PU is the input circuit 101, the first output sub-circuit 102, the second output The connection node between the sub-circuit 103 and the reset sub-circuit 104;
  • the first output sub-circuit 102 is configured to output the clock signal through the first output terminal Output1 in response to the potential of the pull-up node PU;
  • the second output sub-circuit 103 is configured to respond to the potential of the pull-up node PU, and output the synchronization signal outputted by the first output terminal Output1 through the second output terminal Output2;
  • the reset subcircuit 104 is configured to respond to the reset signal, through the second power supply voltage
  • the potential of the pull-up node PU is reset;
  • the monitoring subcircuit 104 is configured to monitor the second output terminal Output2 and output the
  • the first output sub-circuit 102 can output a GOA signal, such as a clock signal, through the first output terminal Output1, and the second output sub-circuit 103 can output the first output terminal through the second output terminal Output2.
  • the monitoring sub-circuit 104 can monitor the second output terminal Output2, and at the same time, can output the monitoring result through the third output terminal Output3.
  • the GOA signal output by the second output terminal Output2 can be monitored.
  • the first shift register may further include at least one pull-down control sub-circuit 106, at least one pull-down sub-circuit 107, at least one first noise reduction sub-circuit 108, at least one second Noise reduction sub-circuit 109 and at least one third noise reduction sub-circuit 110 .
  • the pull-down control sub-circuit 106 is configured to control the potential of the pull-down node PD through the first power supply voltage in response to the first power supply voltage; the pull-down node PD is a connection node between the pull-down control sub-circuit 106 and the pull-down sub-circuit 107; the pull-down sub-circuit 107 is configured to pull down the potential of the pull-down node PD through the second power supply voltage in response to the potential of the pull-up node PU; the first noise reduction sub-circuit 108 is configured to respond to the potential of the pull-down node PD, through the second power supply voltage.
  • An output terminal Output1 performs noise reduction;
  • the second noise reduction sub-circuit 109 is configured to perform noise reduction on the second output terminal Output2 through the second power supply voltage in response to the potential of the pull-down node PD;
  • a third noise reduction sub-circuit 110 is configured In response to the potential of the pull-down node PD, the pull-up node PU is denoised by the second power supply voltage.
  • the first shift register unit may further include an initialization sub-circuit 111; the initialization sub-circuit 111 is configured to respond to the initialization signal, through the second power supply voltage to the pull-up node PU potential to initialize.
  • the input circuit 101 includes a first transistor M1 (input transistor).
  • the gate and source of the first transistor M1 are both connected to the input signal terminal Input, and the drain is connected to the pull-up node PU.
  • the reset sub-circuit 104 includes a second transistor M2 (ie, the above-mentioned reset transistor).
  • the gate of the second transistor M2 is connected to the reset control signal terminal Reset, the source is connected to the second power supply voltage terminal VSS, and the drain is connected to the pull-up node PU.
  • the first output sub-circuit 102 includes a third transistor M3 (ie, the above-mentioned output transistor) and a storage capacitor C.
  • the gate of the third transistor M3 is connected to the pull-up node PU, the source is connected to the clock signal terminal CLK, and the drain is connected to the first output terminal.
  • the second output sub-circuit 103 includes a thirteenth transistor M13 (this transistor is also an output transistor); the gate of the thirteenth transistor M13 is connected to the pull-up node PU, the source is connected to the clock signal terminal CLK, and the drain is connected to the second output terminal.
  • Output2 is also an output transistor
  • a high-level signal is written into the signal input terminal Input, the first transistor M1 is turned on, and the high-level signal can precharge the pull-up node PU through the first transistor M1.
  • the first transistor M1 is turned off, and the storage capacitor C discharges to further pull the potential of the pull-up node PU high.
  • the third transistor M3 and the thirteenth transistor M13 are both turned on.
  • the first output terminal Output1 outputs the high-level signal written by the clock signal terminal CLK.
  • the second output terminal Output2 synchronizes the signal output by the first output terminal Output1. signal output.
  • a high level signal is written into the reset control signal terminal Reset, the second transistor M2 is turned on, and the potential of the pull-up node PU is reset by the low power supply voltage written into the second power supply voltage terminal VSS.
  • the monitoring subcircuit 105 includes a fourth transistor M4.
  • the gate and source of the fourth transistor M4 are both connected to the second output terminal Output2, and the drain is connected to the third output terminal Output3.
  • the gate and source of the fourth transistor M4 are connected to the second output terminal Output2, and the drain is connected to the third output terminal Output3.
  • the fourth transistor M4 When the GOA signal output by the second output terminal Output2 is a high-level signal, the fourth transistor M4 The transistor M4 can be turned on under the control of a high-level signal, and the high-level signal is output through the third output terminal Output3, by comparing the high-level signal output by the third output terminal Output3 with the reference high-level signal.
  • the signal output by the third output terminal Output3 is the same as the reference high-level signal, it means that the GOA signal output by the second output terminal Output2 is normal; if the signal output by the third output terminal Output3 is different from the reference high-level signal or the third output If there is no output signal at terminal Output3, it means that the GOA signal output by the second output terminal Output2 is abnormal. Therefore, real-time monitoring of the GOA signal can be realized, so that the changes in the GOA working status can be monitored during the product reliability process, and then the GOA signal can be monitored in the next step. Detect abnormal GOA signal points at once to avoid AD and other defects.
  • the pull-down control sub-circuit 106 includes a ninth transistor M9 and a fifth transistor M5.
  • the gate and source of the ninth transistor M9 are both connected to the first power supply voltage terminal VDD, and the drain is connected to the gate of M5 of the fifth transistor;
  • the gate of the transistor M5 is connected to the drain of the ninth transistor M9, the source is connected to the first power supply voltage terminal VDD, and the drain is connected to the pull-down node PD.
  • the pull-down sub-circuit 107 includes a sixth transistor M6 and an eighth transistor M8.
  • the gate of the sixth transistor M6 is connected to the pull-up node PU, the source is connected to the pull-down node PD, and the drain is connected to the second power supply voltage terminal VSS; the eighth transistor M8 The gate is connected to the pull-up node PU, the source is connected to the drain of the ninth transistor M9, and the drain is connected to the second power supply voltage terminal VSS.
  • the first noise reduction sub-circuit 108 includes an eleventh transistor M11. The gate of the eleventh transistor M11 is connected to the pull-down node PD, the source is connected to the first output terminal Output1, and the drain is connected to the second power supply voltage terminal VSS.
  • the second noise reduction sub-circuit 109 includes a twelfth transistor M12.
  • the gate of the twelfth transistor M12 is connected to the pull-down node PD, the source is connected to the second output terminal Output2, and the drain is connected to the second power supply voltage terminal VSS.
  • the third noise reduction sub-circuit 110 includes a tenth transistor M10. The gate of the tenth transistor M10 is connected to the pull-down node PD, the source is connected to the pull-up node PU, and the drain is connected to the second power supply voltage terminal VSS.
  • two pull-down control sub-circuits 106 two pull-down sub-circuits 107 , two first noise reduction sub-circuits 108 , two second noise reduction sub-circuits 109 and Two third noise reduction sub-circuits 110 are taken as an example for description. It can be understood that the number of each of the above-mentioned sub-circuits can also be one or other numbers, and the implementation principles are the same, which will not be described again here.
  • the fifth transistors in the first and second pull-down control sub-circuits 106 are represented by M5 and M5' respectively, and the ninth transistors are represented by M9 and M9' respectively; the first and second The sixth transistor in the pull-down circuit 5 is represented by M6 and M6′ respectively, the eighth transistor M8 is represented by M8 and M8′ respectively; the eleventh transistor in the first and second first noise reduction circuit 108 is represented by M11 respectively.
  • the twelfth transistor M12 in the first and second second noise reduction circuit 109 is represented by M12 and M12′ respectively
  • the tenth transistor M12 in the first and second third noise reduction circuit 110 is represented by M12 and M12′ respectively
  • the transistors are represented by M10 and M10' respectively
  • the first power supply voltage terminals connected to the first and second pull-down control sub-circuit 106 are represented by VDD1 and VDD2 respectively.
  • first pull-down control sub-circuit 106 is connected to the first pull-down circuit 107, and the connection node between the two is represented by pull-down node PD1; the second pull-down control sub-circuit 106 is connected to the second pull-down circuit 107, and the second pull-down control sub-circuit 106 is connected to the second pull-down circuit 107.
  • connection node between them is represented by the pull-down node PD2; the first first noise reduction circuit 108 is connected to PD1, the second first noise reduction circuit 108 is connected to PD2; the first second noise reduction circuit 109 is connected to PD1, and the second The second second noise reduction circuit 109 is connected to PD2; the first third noise reduction circuit 110 is connected to PD1, and the second third noise reduction circuit 110 is connected to PD2.
  • the first third noise reduction circuit 110 operates, or the second pull-down control sub-circuit 106, the second first pull-down circuit 107, the second first noise reduction circuit 108, and the second second noise reduction circuit 109.
  • the second and third noise reduction circuit 110 operates.
  • the number of the pull-down control sub-circuit 106, the first pull-down circuit 107, the first noise reduction circuit 108, the second noise reduction circuit 109, and the third noise reduction circuit 110 can each be multiple, and the sub-circuits with the same function When a frame of image is scanned, only one of them works, and at the same time, it can switch to another one at the preset time, thereby extending the life of the shift register.
  • the pull-up node PU is pulled down to a low level during the reset stage, and the fifth transistor M5 and the ninth transistor M9 are always controlled by the first power supply voltage written in the first power supply voltage terminal VDD1, at this time
  • the potential of the pull-down node PD1 is a high-level signal
  • the eleventh transistor M11 is turned on, and the second power supply voltage written in the second power supply voltage terminal VSS denoises the output of the first output terminal Output1 through the eleventh transistor M11 .
  • the twelfth transistor M12 and the tenth transistor M10 are also turned on, and the second power supply voltage written in the second power supply voltage terminal VSS passes through the twelfth transistor M12 and the tenth transistor M10 to the second output terminal Output2 respectively.
  • the output of the pull-up node PU is used for noise reduction.
  • the initialization sub-circuit 111 includes a seventh transistor M7.
  • the gate of the seventh transistor M7 is connected to the initialization signal terminal STV, the source is connected to the pull-up node PU, and the drain is connected to the second power supply voltage terminal VSS.
  • the initialization signal terminal STV writes a high level signal
  • the seventh transistor M7 is turned on
  • the low power supply voltage written through the second power supply voltage terminal VSS causes the pull-up node PU to The potential is initialized to prevent the display images of adjacent frames from interfering with each other and affecting the display effect.
  • the first shift register unit and the second shift register unit provided by the embodiment of the present disclosure can also be other circuit structures, such as the 17T1C structure, the 18T2C structure, and the 21T1C structure. Structure, etc., the embodiments of the present disclosure do not limit the specific structures of the first shift register unit and the second shift register unit.
  • the structure of the first shift register unit and the second shift register unit is a 17T1C structure
  • the 17T1C may not have the ninth transistors M9 and M9′, but its implementation principle is the same as that of the above-mentioned 19T1C structure.
  • the implementation principles of the shift register unit are the same and will not be described again here.
  • the first output sub-circuit 102 includes a first output transistor, and the third transistor M3 serves as the first output transistor; the second output sub-circuit 103 includes a second output transistor, and the thirteenth transistor M13 serves as the second output transistor; first output The gate electrode 300 of the transistor is connected to the first node PU, the first pole of the first output transistor is connected to the clock signal terminal to receive the clock signal, the second pole of the first output transistor is connected to the shift output terminal Output2; the second output transistor The gate 300 is connected to the first node PU, the first pole of the second output transistor is connected to the clock signal terminal to receive the clock signal, and the second pole of the second output transistor is connected to the scan signal output terminal Output1; the clock signal is transmitted to The output terminal Output1 serves as an output signal; both the first output transistor and the second output transistor are thin film transistors provided by embodiments of the present disclosure.
  • the total width W of the channel region of the third transistor M3 and the thirteenth transistor M13 is relatively large, the threshold voltage offset ⁇ th is particularly large, and the heat generation is particularly severe.
  • the third transistor M3 and the thirteenth transistor M13 both satisfy P ⁇ 3 and N ⁇ 2, that is, the first output transistor and the second output transistor both satisfy P ⁇ 3 and N ⁇ 2; or, the third transistor M3 and the third transistor M13 satisfy P ⁇ 3 and N ⁇ 2.
  • the thirteen transistors M13 all satisfy P ⁇ N ⁇ 12, that is, the first output transistor and the second output transistor both satisfy P ⁇ N ⁇ 12; or, the third transistor M3 and the thirteenth transistor M13 both satisfy P ⁇ N ⁇ 16, That is, both the first output transistor and the second output transistor satisfy P ⁇ N ⁇ 16, so as to better reduce the offset ⁇ th of the threshold voltages of the third transistor M3 and the thirteenth transistor M13, and reduce the
  • the heat generated by the thirteenth transistor M13 ensures that the shift register unit 01 has better and more stable working performance, and ensures that the display panel using the gate drive circuit including the shift register unit 01 as the scan drive circuit has better display Effect.
  • the source of the third transistor M3 and the source of the thirteenth transistor M13 are both connected to the same clock signal line CLK; the drain of the third transistor M3 and the drain of the thirteenth transistor M13 are connected to the first drain respectively.
  • 210A is connected to the second drain trace 210B.
  • the third transistor M3 satisfies 235 ⁇ W/L ⁇ 400 and P ⁇ N ⁇ 32.
  • the third transistor M3 and the thirteenth transistor M13 are the transistors shown in FIG. 3B respectively.
  • the thirteenth transistor M13 satisfies 112 ⁇ W/L ⁇ 400.
  • the source of the third transistor M3 and the source of the thirteenth transistor M13 are respectively connected to the first source line 110A and the second source line 110B.
  • the first source line 110A is connected to the same clock signal line CLK. ;
  • the drain of the third transistor M3 and the drain of the thirteenth transistor M13 are respectively connected to the first drain wiring 210A and the second drain wiring 210B.
  • the first transistor M1, the second transistor M2, the sixth transistor M6, the eighth transistor M8/M8', the tenth transistor M10/M10', and the eleventh transistor M11/M11' are all thin films provided by embodiments of the present disclosure.
  • Transistors all satisfy 12 ⁇ W/L ⁇ 400, P and N are both integers greater than or equal to 1, M is an integer greater than or equal to 2, and P ⁇ N ⁇ 4. Therefore, by relying on the relationship between W/L and P and N, the design limits of the number of P and N can be controlled, and the design rules are clearer, so that the heating problem can be improved based on the predictability.
  • a plurality of thin film transistors can be reasonably arranged in a limited GOA area (non-display area, such as at least partially surrounding the display area) of the display panel, setting More shift register units are used to drive more rows of pixels in the display area of the display panel, which is conducive to driving a high-PPI display panel.
  • the thin film transistors in the GOA drive circuit are The arrangement is more dense. In this case, it is particularly necessary to improve the heat dissipation of the thin film transistor. Designing based on the relationship between W/L and the product of P and N in this application can effectively obtain the design boundary and improve the thin film transistor. The problem of transistor heating and the problem of preventing the threshold voltage offset ⁇ th of the thin film transistor from being too large.
  • any other transistor except M10/M10', the eleventh transistor M11/M11', the third transistor M3 and the thirteenth transistor M13 can use the thin film transistor provided by the embodiment of the present disclosure, according to the design requirements of different transistors. , perform specific design based on the design boundaries of the thin film transistor provided by the embodiments of the present disclosure.
  • the design data used for each thin film transistor in the shift register unit 01 shown in FIG. 7 is shown in Table 1 below. This solution can be used to rationally design each thin film transistor according to the functional needs of each thin film transistor, taking into account space and performance.
  • FIG. 8 is an exemplary circuit diagram of another shift register unit provided by at least one embodiment of the present disclosure.
  • Each thin film transistor in FIG. 8 performs a similar function to the corresponding thin film transistor in FIG. 7 .
  • the third transistor M3 and the thirteenth transistor M13 are respectively the first output transistor and the second output transistor, and the second transistor M2 is a reset transistor. wait.
  • the connection relationship between each transistor and the capacitor is shown in Figure 8, which will not be introduced one by one here. You can refer to the description of Figure 7 to understand the exemplary circuit of the shift register unit shown in Figure 8 using conventional techniques in the art.
  • the total width W of the channel region of the third transistor M3 and the thirteenth transistor M13 is relatively large, the threshold voltage offset ⁇ th is particularly large, and the heat generation is particularly serious.
  • the third transistor M3 and the thirteenth transistor M13 both satisfy P ⁇ 3 and N ⁇ 2, that is, the first output transistor and the second output transistor both satisfy P ⁇ 3 and N ⁇ 2; or, the third transistor M3 and the third transistor M13 satisfy P ⁇ 3 and N ⁇ 2.
  • the thirteen transistors M13 all satisfy P ⁇ N ⁇ 12, that is, the first output transistor and the second output transistor both satisfy P ⁇ N ⁇ 12; or, the third transistor M3 and the thirteenth transistor M13 both satisfy P ⁇ N ⁇ 16, That is, both the first output transistor and the second output transistor satisfy P ⁇ N ⁇ 16, so as to better reduce the offset ⁇ th of the threshold voltages of the third transistor M3 and the thirteenth transistor M13, and reduce the
  • the heat generated by the thirteenth transistor M13 ensures that the shift register unit has better and more stable working performance, and ensures that the display panel using the gate drive circuit including the shift register unit as the scan drive circuit has better display effects.
  • the third transistor M3 and the thirteenth transistor M13 are respectively the transistors shown in FIG. 3A, and the thirteenth transistor M13 satisfies 112 ⁇ W/L ⁇ 400.
  • the third transistor M3 satisfies 235 ⁇ W/L ⁇ 400 and P ⁇ N ⁇ 32.
  • the third transistor M3 and the thirteenth transistor M13 are the transistors shown in FIG. 3B respectively.
  • the thirteenth transistor M13 satisfies 112 ⁇ W/L ⁇ 400.
  • the first transistor M1, the second transistor M2, the sixth transistor M6/M6', the tenth transistor M10/M10', the eleventh transistor M11/M11', and the sixteenth transistor M16/M16' are all of the present disclosure.
  • the thin film transistors provided in the embodiment all satisfy 12 ⁇ W/L ⁇ 400, P and N are both integers greater than or equal to 1, M is an integer greater than or equal to 2, and P ⁇ N ⁇ 4. Therefore, by relying on the relationship between W/L and P and N, the design limits of the number of P and N can be controlled, and the design rules are clearer, so that the heating problem can be improved based on the predictability.
  • multiple thin film transistors can be reasonably arranged in the limited GOA area (non-display area, such as at least partially surrounding the display area) of the display panel, and the setting is more More shift register units are used to drive more rows of pixels in the display area of the display panel, which is conducive to driving a high-PPI display panel.
  • the arrangement of thin film transistors in the GOA drive circuit is The cloth is denser. In this case, it is particularly necessary to improve the heat dissipation of the thin film transistor. Designing based on the relationship between W/L and the product of P and N in this application can effectively obtain the design boundary and improve the thin film transistor. Heating problems and preventing the threshold voltage offset ⁇ th of the thin film transistor from being too large.
  • At least one embodiment of the present disclosure also provides a gate drive circuit, the gate drive circuit includes any one of the shift register units provided by the embodiments of the present disclosure, and the gate drive circuit includes a plurality of cascaded shift register units; Except for the shift register units from the 1st level to the sth level, the precharge control terminals of the shift register units at all other levels are connected to the output terminals of the upper-level shift register units that are at least s levels away from them; except for the 1st level to the sth level.
  • the input terminals of the remaining shift register units are connected to the output terminals of the upper-level shift register unit that is s-1 level away from it; except for the last s-level shift register unit, the remaining shift register units
  • the reset terminal of the register unit is connected to the output terminal of the lower-level shift register unit that is s-1 level away from it; where s is an integer greater than 2.
  • At least one embodiment of the present disclosure further provides a display panel, including the gate driving circuit provided by any embodiment of the present disclosure.
  • the display panel provided by the embodiment of the present disclosure may be an organic light-emitting diode display panel or a liquid crystal display panel.
  • FIG. 9 is a schematic diagram of a display panel further provided by at least one embodiment of the present disclosure.
  • the display panel 1000 includes a display area 10A and a non-display area at least partially surrounding the display area 10A.
  • the non-display area includes the gate driving circuit area 10B/10C and the circuit lead area 10D.
  • the non-display area includes a first circuit area 10B and a second circuit area 10C.
  • the first circuit area 10B and the second circuit area 10C both extend in the longitudinal direction.
  • the first circuit area 10B and the second circuit area 10C both extend in the longitudinal direction.
  • a plurality of cascaded shift register units 01 are respectively arranged in them, and the multiple cascaded shift register units 01 are arranged longitudinally; the circuit lead area 10D, that is, the Fanout area, is provided with circuit leads (not shown), and the circuit The lead area 10D extends along the transverse direction intersecting with the longitudinal direction and is adjacent to the gate drive circuit area 10B/10C.
  • the circuit leads include a first lead connected to the gate drive circuit and a second lead connected to the display area 10A; a plurality of cascade connections
  • the shift register unit 01 includes a first end shift register unit 01a located at one end of the first circuit area 10B close to the circuit lead area 10D and a second end located at one end of the second circuit area 10C close to the circuit lead area 10D.
  • the value of P ⁇ N of the first output transistor in the first end shift register unit 01a and the value of P ⁇ N of the second output transistor in the first end shift register unit 01a are respectively larger than P ⁇ N value of the second output transistor.
  • the wiring at the position of the first end shift register unit 01a and the area of the circuit lead area 10D close to the first end shift register unit 01a are relatively dense, and the heat generation is particularly serious.
  • the present disclosure further provides a display device, which includes the display panel provided by any embodiment of the present disclosure.
  • the display device can be a liquid crystal panel, an LCD TV, a monitor, an OLED panel, an OLED TV, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • the display device may also include other conventional components such as a display panel, which is not limited in the embodiments of the present disclosure.

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Abstract

一种薄膜晶体管、移位寄存器单元、栅极驱动电路和显示面板，薄膜晶体管中，每个源极单元包括M个源极分支，源极分支和漏极分支均沿第一方向延伸且在与第一方向相交的第二方向上间隔排列；一个源极单元与对应的一个漏极单元构成一个源漏单元，薄膜晶体管包括P个源漏单元，每个源漏单元内M个源极分支与N个漏极分支交替设置，M大于等于N；半导体层与M个源极分支和N个漏极分支电连接，半导体层包括位于相邻的漏极分支和源极分支之间的多个子沟道区；P个源漏单元的多个子沟道区在第一方向上的宽度的总和为W，P个源漏单元的多个子沟道区在与第一方向垂直的方向上的平均长度为L；12≤W/L≤400，P、M和N均为大于等于1的整数，P×N≥4。

Description

薄膜晶体管、移位寄存器单元、栅极驱动电路和显示面板 技术领域
本公开至少一实施例提供一种薄膜晶体管、移位寄存器单元、栅极驱动电路和显示面板。
背景技术
在显示技术领域的开关元件对高画质显示装置起着重要的作用。例如开关元件薄膜晶体管(Thin Film Transistor，TFT)的导电性能直接影响TFT的开启程度，影响液晶分子的偏转程度，从而影响图像的显示画面。
目前主要是对TFT的充电电流提出更高的要求。一般地，通过增加TFT沟道的宽长比，以增加TFT的充电电流。例如，尤其是针对制作在阵列基板上非显示区域的栅极行驱动电路(GOA电路)，对其电路中的TFT的充电电流要求更高，并且制作在阵列基板的非显示区域的中的TFT，其TFT的尺寸要求相比较在像素中的设计会低一些，因此，设计出了面积较大充电电流较高的TFT。
TFT半导体层的材料主要包括非晶硅(a-Si)或氧化物(如IGZO，即Indium Gallium Zinc Oxide，铟镓锌氧化物)等，随着人们对高PPI(Pixels Per Inch，像素密度)、高刷新频率、窄边框产品的需要，传统的a-Si薄膜晶体管产品已经无法满足器件性能的需求，而氧化物技术作为最可能替代a-Si薄膜晶体管产品的新型技术成为目前的研究重点。
发明内容
本公开至少一实施例中提供一种薄膜晶体管，该薄膜晶体管包括源极、漏极、栅极和半导体层。源极包括源极走线和与源极走线电连接的P个源极单元，P个源极单元中的每个包括M个源极分支，M个源极分支的每个沿第一方向延伸且在与第一方向相交的第二方向上间隔排列；漏极包括漏极走线和与漏极走线电连接且与P个源极单元一一对应的P个漏极单元，P个漏极单元中的每个包括N个漏极分支，N个漏极分支的每个沿第一方向延伸且在第二方向上间隔排列；薄膜晶体管包括P个源漏单元，一个源极单元与对应的一个漏极单元构成一个源漏单元，在P个源漏单元中的每个源漏单元内，M个源极分支与N个漏极分支交替设置、彼此间隔且绝缘，M大于等于N；栅极与源极和漏极绝缘；半导体层与每个源漏单元的M个源极分支和N个漏极分支电连接，半导体层包括位于P个源漏单元中每个源漏单元中的多个子沟道区，多个子沟道区的每个位于彼此相邻的漏极分支和源极分支之间；P个源漏单元的多个子沟道区在第一方向上的宽度的总和为W，P个源漏单元的多个子沟道区在与第一方向垂直的方向上的平均长度为L；12≤W/L≤400，P、M和N均为大于等于1的整数，P×N≥4。
例如，在本公开至少一实施例提供的薄膜晶体管中，112≤W/L≤400，P×N≥6。
例如，在本公开至少一实施例提供的薄膜晶体管中，P≥3且N≥2。
例如，在本公开至少一实施例提供的薄膜晶体管中，P×N≥12。
例如，在本公开至少一实施例提供的薄膜晶体管中，P×N≥16。
例如，在本公开至少一实施例提供的薄膜晶体管中，235≤W/L≤400，P×N≥32。
例如，在本公开至少一实施例提供的薄膜晶体管中，W/L<180，W的范围是10μm～1600μm。
例如，在本公开至少一实施例提供的薄膜晶体管中，W/L>180，L的范围是4μm～15μm。
例如，在本公开至少一实施例提供的薄膜晶体管中，所述多个源漏单元排列成至少一个单元行，所述至少一个单元行中的每个单元行包括至少一个源漏单元；同一所述单元行中，相邻的所述源漏单元之间的距离为d，W≥500μm，d的范围为是50μm～500μm。
例如，在本公开至少一实施例提供的薄膜晶体管中，所述多个源漏单元排列成至少一个单元行，所述至少一个单元行中的每个单元行包括至少一个源漏单元；同一所述单元行中，相邻的所述源漏单元之间的距离为d，W<500μm，d的范围为是20μm～300μm。
例如，在本公开至少一实施例提供的薄膜晶体管中，所述多个源漏单元排列成至少两个单元行，所述至少一个单元行中的每个单元行包括至少一个源漏单元。
例如，在本公开至少一实施例提供的薄膜晶体管中，所述半导体层包括与所述多个源漏单元中的每个源漏单元交叠的子部，所述子部包括Q个半导体分支，所述多个子沟道区包括所述Q个半导体分支的位于相邻的所述源极分支和所述漏极分支之间的子沟道单元，Q为大于或等于1的整数；W为所述P个源漏单元的Q个半导体分支的子沟道单元在所述第一方向上的宽度的总和，L为所述P个源漏单元的多个所述子沟道单元在与所述第一方向垂直的方向上的平均长度。
例如，在本公开至少一实施例提供的薄膜晶体管中，所述半导体层包括与所述多个源漏单元中的每个源漏单元交叠的子部，与所述源漏单元交叠的多个所述子部构成连续的一体化结构。
例如，在本公开至少一实施例提供的薄膜晶体管中，所述多个源漏单元设置在相邻的所述源极走线与所述漏极走线之间的区域，以将所述多个源漏单元排列为至少两个单元行，所述至少两个单元行中的每个单元行包括至少一个所述源漏单元；每个所述单元行内所述至少一个源漏单元的所述源极分支电连接同一条所述源极走线，每一所述单元行内所述至少一个源漏单元的所述漏极分支电连接同一条所述漏极走线。
本公开至少一实施例还提供一种移位寄存器单元，该移位寄存器单元包括本公开实施提供的任意一种薄膜晶体管。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述栅极行驱动电路包括输入电路、输出电路和第一节点复位电路；所述输入电路与第一节点连接，且配置为响应于 输入信号对所述第一节点进行充电；所述输出电路与所述第一节点连接，且配置为在所述第一节点的电平信号的控制下，将输出信号在输出端输出；所述第一节点复位电路与所述第一节点连接，配置为响应于复位信号对所述第一节点进行复位；所述输出电路、所述输入电路和所述第一节点复位电路均包括根据权利要求1所述的薄膜晶体管。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述输出端包括移位输出端和扫描信号输出端；所述输出电路包括第一输出晶体管和第二输出晶体管；所述第一输出晶体管的栅极和所述第一节点连接，所述第一输出晶体管的第一极和时钟信号端连接以接收时钟信号，所述第一输出晶体管的第二极和所述移位输出端连接；所述第二输出晶体管的栅极和所述第一节点连接，所述第二输出晶体管的第一极和所述时钟信号端连接以接收所述时钟信号，所述第二输出晶体管的第二极和所述扫描信号输出端连接；所述时钟信号被传输至所述输出端作为所述输出信号；所述第一输出晶体管和第二输出晶体管均为根据权利要求1所述的薄膜晶体管；所述第一输出晶体管和第二输出晶体管均满足P≥3且N≥2，或者，所述第一输出晶体管和第二输出晶体管均满足P×N≥12，或者，所述第一输出晶体管和第二输出晶体管均满足P×N≥16。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述第一输出晶体管满足235≤W/L≤400，P×N≥32。
本公开至少一实施例还提供一种栅极驱动电路，该栅极驱动电路包括本公开实施例提供的任意一种移位寄存器单元，栅极驱动电路包括多个级联的移位寄存器单元；除第1级至第s级移位寄存器单元外，其余各级移位寄存器单元的预充控制端和与其相隔至少s级的上级移位寄存器单元的输出端连接；除第1级至第s级移位寄存器单元外，其余各级移位寄存器单元的输入端和与其相隔s-1级的上级移位寄存器单元的输出端连接；除最后s级移位寄存器单元外，其余各级移位寄存器单元的复位端和与其相隔s-1级的下级移位寄存器单元的输出端连接；其中，s为大于2的整数。
本公开至少一实施例还提供一种显示面板，包括本公开实施例提供的任意一种栅极驱动电路。
例如，在本公开至少一实施例提供的显示面板中，所述显示面板包括显示区和至少部分围绕所述显示区的非显示区；所述非显示区包括：栅极驱动电路区域和电路引线区域。栅极驱动电路区域沿纵向延伸，设置有所述栅极驱动电路，其中，所述多个级联的移位寄存器单元沿所述纵向排列；电路引线区域中设置有电路引线，沿与所述纵向相交的横向延伸，与所述栅极驱动电路区域相邻，所述电路引线包括与所述栅极驱动电路连接第一引线和连接至所述显示区的第二引线；所述多个级联的移位寄存器单元包括位于所述电路区域的靠近所述电路引线区域的一端的端部移位寄存器单元；每个所述移位寄存器中，所述输出端包括移位输出端和扫描信号输出端；所述输出电路包括第一输出晶体管和第二输出晶体管；所述第一输出晶体管的栅极和所述第一节点连接，所述第一输出晶体管的第一极和时钟信号端连接以接收时钟信号，所述第一输出晶体管的第二极和所述移位输出端连接； 所述第二输出晶体管的栅极和所述第一节点连接，所述第二输出晶体管的第一极和所述时钟信号端连接以接收所述时钟信号，所述第二输出晶体管的第二极和所述扫描信号输出端连接；所述时钟信号被传输至所述输出端作为所述输出信号；所述第一输出晶体管和第二输出晶体管均为根据权利要求1所述的薄膜晶体管；所述端部移位寄存器单元中的第一输出晶体管的P×N的值和所述端部移位寄存器单元中的第二输出晶体管的P×N的值分别大于所述多个级联的移位寄存器单元中的其他移位寄存器单元中的第一输出晶体管的P×N的值和所述端部移位寄存器单元中的第二输出晶体管的P×N的值。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1是本公开至少一实施例提供的一种薄膜晶体管的结构示意图；
图2是图1所示的薄膜晶体管的一个源漏单元的局部放大示意图；
图3A是本公开至少一实施例提供的一种移位寄存器单元中的两个晶体管的结构示意图；
图3B是本公开至少一实施例提供的另一种移位寄存器单元中的两个晶体管的结构示意图；
图4A是本公开至少一实施例提供的薄膜晶体管的沟道区的总宽度W与薄膜晶体管的阈值电压漂移量Δth之间的关系；
图4B是本公开至少一实施例提供的薄膜晶体管的子沟道区的平均长度L与薄膜晶体管的阈值电压漂移量Δth之间的关系；
图4C是本公开至少一实施例提供的薄膜晶体管的沟道区的总宽度W与子沟道区的平均长度L的比值W/L与薄膜晶体管的阈值电压漂移量Δth之间的关系；
图5A是本公开至少一实施例提供的薄膜晶体管的一个源漏单元的源/漏分支数与薄膜晶体管的阈值电压漂移量Δth之间的关系；
图5B是本公开至少一实施例提供的薄膜晶体管的源漏单元的个数与薄膜晶体管的阈值电压漂移量Δth之间的关系；
图5C是本公开至少一实施例提供的薄膜晶体管的相邻的源漏单元之间的距离与薄膜晶体管的阈值电压漂移量Δth之间的关系；
图6A是本公开至少一实施例提供的另一种薄膜晶体管的结构示意图；
图6B是本公开至少一实施例提供的再一种薄膜晶体管的结构示意图；
图7是本公开至少一实施例提供的一种移位寄存器单元的示例性电路图；
图8是本公开至少一实施例提供的另一种移位寄存器单元的示例性电路图；
图9是本公开至少一实施例还提供的一种显示面板的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。以下所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现在该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在相关技术中，GOA(Gate Driver on array，阵列基板行驱动)技术是指将栅极驱动器(Gate Driver)集成在阵列基板上，形成对面板的扫描驱动。相比传统覆晶薄膜(Chip On Flex/Film，COF)和直接绑定在玻璃上(Chip On Glass，COG)的工艺，GOA技术的主要特点是依靠集成在阵列基板上的GOA驱动单元连续触发实现其移位寄存功能，替代了原来的Gate Driver IC的绑定(Bonding)区域以及Fan-out布线空间，使得面板可以做到两边对称美观设计，实现了窄边框的设计，降低了成本，同时对产能和良品率提升也比较有利。
GOA电路中，TFT半导体层的材料主要包括非晶硅(a-Si)或氧化物(如IGZO，即Indium Gallium Zinc Oxide，铟镓锌氧化物)等，随着人们对高PPI(Pixels Per Inch，像素密度)、高刷新频率、窄边框产品的需要，传统的a-Si薄膜晶体管产品已经无法满足器件性能的需求，而氧化物技术作为最可能替代aSi薄膜晶体管产品的新型技术成为目前各个显示厂商研究的重点。
通常，GOA电路中包括多个薄膜晶体管，各薄膜晶体管包括多个源极分支、多个漏极分支、多个半导体分支、源极走线和漏极走线，多个源极分支连接至源极走线上，多个漏极分支连接至漏极走线上，多个源极分支和多个漏极分支被分割为多个单元(TFT unit)。
由于源极分支和漏极分支上的电流大小与热量的大小关系密切，因此，通过增加分支数，来减小每个分支上的电流，进而减小每个分支的热量，是解决GOA电路发热最直接和有效的方法。但是，这种方法适合于迁移率小的非晶硅薄膜晶体管(a-si TFT)，对于大尺寸氧化物薄膜晶体管(Oxide TFT)来说，由于Oxide TFT的离子(Ion)迁移率高，容易发热，发热问题更加严重，主要原因在于，一是，源、漏极分支数量过多，以高聚集形式布置，这种高聚集布置形式容易导致热量聚集，热量无法散失；二是，氧化物半导体层与源、漏极分支接触位置发热最严重，同时，由于源、漏极分支与半导体层的接触部分 都在电流汇聚的导线上，电流聚集的导线也容易产生高热，进一步加重了热量的聚集，而聚集的热量会降低显示面板的信赖性。并且，沟道区的宽度过大、源、漏极分支数量不合适还会造成薄膜晶体管的阈值电压的偏移量增加，影响薄膜晶体管性能的稳定性和工作的可靠性。
目前，常规的氧化物晶体管，例如IGZO TFT，的迁移率在10以下，但随着对更高分辨率、更高刷新频率产品来说，高迁移率氧化物存在非常大的器件特性不稳定的问题，尤其是大的宽长比会导致开态电流(Ion)的大幅增加，器件发热问题突出，且导致最阈值电压的漂移量增加，终导致显示器件信赖性差的问题，影响GOA显示面板的显示效果。
本公开至少一实施例中提供一种薄膜晶体管，该薄膜晶体管包括源极、漏极、栅极和半导体层。源极包括源极走线和与源极走线电连接的P个源极单元，P个源极单元中的每个包括M个源极分支，M个源极分支的每个沿第一方向延伸且在与第一方向相交的第二方向上间隔排列；漏极包括漏极走线和与漏极走线电连接且与P个源极单元一一对应的P个漏极单元，P个漏极单元中的每个包括N个漏极分支，N个漏极分支的每个沿第一方向延伸且在第二方向上间隔排列；薄膜晶体管包括P个源漏单元，一个源极单元与对应的一个漏极单元构成一个源漏单元，在P个源漏单元中的每个源漏单元内，M个源极分支与N个漏极分支交替设置、彼此间隔且绝缘，M大于等于N；栅极与源极和漏极绝缘；半导体层与每个源漏单元的M个源极分支和N个漏极分支电连接，半导体层包括位于P个源漏单元中每个源漏单元中的多个子沟道区，多个子沟道区的每个位于彼此相邻的漏极分支和源极分支之间；P个源漏单元的多个子沟道区在第一方向上的宽度的总和为W，P个源漏单元的多个子沟道区在与第一方向垂直的方向上的平均长度为L；12≤W/L≤400，P、M和N均为大于等于1的整数，P×N≥4。
本公开至少一实施例还提供一种移位寄存器单元，该移位寄存器单元包括本公开实施提供的任意一种薄膜晶体管。
本公开至少一实施例还提供一种栅极驱动电路，该栅极驱动电路包括本公开实施例提供的任意一种移位寄存器单元，栅极驱动电路包括多个级联的移位寄存器单元；除第1级至第s级移位寄存器单元外，其余各级移位寄存器单元的预充控制端和与其相隔至少s级的上级移位寄存器单元的输出端连接；除第1级至第s级移位寄存器单元外，其余各级移位寄存器单元的输入端和与其相隔s-1级的上级移位寄存器单元的输出端连接；除最后s级移位寄存器单元外，其余各级移位寄存器单元的复位端和与其相隔s-1级的下级移位寄存器单元的输出端连接；其中，s为大于2的整数。
本公开至少一实施例还提供一种显示面板，包括本公开实施例提供的任意一种栅极驱动电路。
示例性地，图1是本公开至少一实施例提供的一种薄膜晶体管的结构示意图。如图1所示，该薄膜晶体管包括：源极100、漏极200、栅极300和半导体层400。源极100包括源极走线110和与源极走线110电连接的P个源极单元，P个源极单元中的每个包括N 个源极分支120，N个源极分支120的每个沿第一方向D1延伸且在与第一方向D1相交的第二方向D2上间隔排列；漏极200包括漏极走线210和与漏极走线210电连接且与P个源极单元一一对应的P个漏极单元，P个漏极单元中的每个包括M个漏极分支220，M个漏极分支220的每个沿第一方向D1延伸且在第二方向D2上间隔排列；薄膜晶体管包括P个源漏单元10，一个源极单元与对应的一个漏极单元构成一个源漏单元10，在P个源漏单元10中的每个源漏单元10内，N个源极分支120与M个漏极分支220交替设置、彼此间隔且绝缘，M大于等于N；栅极300与源极100和漏极200绝缘；半导体层400与每个源漏单元10的N个源极分支120和M个漏极分支220电连接，半导体层400包括位于P个源漏单元10中每个源漏单元10中的多个子沟道区40，多个子沟道区40的每个位于彼此相邻的漏极分支220和源极分支120之间；P个源漏单元10的多个子沟道区40在第一方向D1上的宽度的总和为W(下文称作沟道区的总宽度)，P个源漏单元10的多个子沟道区40在与第一方向D1垂直的方向上的平均长度为L(子沟道区的平均长度)；12≤W/L≤400，P、M和N均为大于等于1的整数，P×N≥4。
参考图4A，图4A展示了薄膜晶体管的沟道区的总宽度W分别为500μm、800μm、1000μm、2100μm和3000μm的情况，由此可见，薄膜晶体管的阈值电压的偏移量Δth与W呈正相关。
参考图4B，图4B展示了薄膜晶体管的子沟道区的平均长度L分别为4.5μm、5.5μm、6.5μm、7.5μm和8.5μm的情况，由此可见，薄膜晶体管的阈值电压的偏移量Δth与L呈负相关。
减小阈值电压的偏移量Δth有利于提高薄膜晶体管的充电率，薄膜晶体管的性能越好。但是，开态电流Ion提高会造成薄膜晶体管发热严重，我们希望获得较小的阈值电压的偏移量Δth，同时也不希望开态电流Ion过高，并且高的开态电流Ion在薄膜晶体管的工作过程中也会造成阈值电压的偏移量Δth变大。因此，探究薄膜晶体管的设计边界非常重要。
经过发明人的探究，在本公开实施例提供的薄膜晶体管中，发明人建立了W/L与P×N的关系，在12≤W/L≤400的情况下，满足P×N≥4能够有效降低薄膜晶体管的发热，降低薄膜晶体管的阈值电压的偏移量Δth，提高薄膜晶体管的充电率，保持薄膜晶体管在工作过程中性能的稳定，从而提高采用包括该薄膜晶体管的GOA驱动电路的显示面板的显示效果，并且不会造成过高的开态电流Ion，避免一味地增加源漏单元的个数、源极分支和漏极分支的个数，而导致由此造成源极分支和漏极分支以高聚集形式布置，从而避免这种高聚集布置形式导致的热量聚集。能够针对特定的W/L的区间，寻找到合适的源漏单元的个数P与一个源漏单元中源极分支的个数N的乘积，来达到较好的降低薄膜晶体管发热的技术效果，对晶体管的合理设计具有重要意义。尤其是对于W较大(例如W大于100μm)的晶体管，降低薄膜晶体管的发热程度的效果更加明显。
通过依据W/L与P和N之间的关系，可以控制P和N数量设计上的界限，设计规则更加明确，从而能够实现基于可预见的能够达到改善发热问题的基础上，合理地在采用 多个该薄膜晶体管的显示面板的电路(例如GOA驱动电路)区域排布薄膜晶体管，也利于在显示面板的有限的GOA区域(非显示区域，例如至少部分围绕显示区)中合理地排布多个薄膜晶体管，设置更多的移位寄存器单元来驱动显示面板的显示区中更多行的像素，利于实现驱动高PPI的显示面板，并且，高PPI的显示面板的GOA区域中，GOA驱动电路中的薄膜晶体管的排布更加密集，在这种情况下，特别需要改善薄膜晶体管的散热情况，而根据本申请的W/L与P和N的乘积之间的关系来进行设计，可以有效获得设计边界，解决该问题改善薄膜晶体管发热问题和防止薄膜晶体管的阈值电压的偏移量Δth过大的问题。
例如，多个子沟道区40的长度均相等，均为图1中的一个子沟道区40在第一方向D1上的长度L’，即上述L＝L’。当然，在其他实施例中，多个子沟道区40的长度也可以不都是相等的，总之，上述L为P个源漏单元10的多个子沟道区40在第一方向D1上的宽度的总和为W，P个源漏单元10的多个子沟道区40在与第一方向D1垂直的方向上的平均长度。
为了清楚地交代上述P、M和N的含义，下面以图1所示的薄膜晶体管作为示例对此进行解释。例如，在图1所示的薄膜晶体管中，源漏单元10的个数P＝8，也即源极单元的个数也即漏极单元的个数，一个源漏单元10中的N个源极分支120构成一个源极单元，一个源漏单元10中的M个漏极分支220构成一个漏极单元。例如，在图1所示的薄膜晶体管中，M＝5，N＝4，M＝N+1。当然，在其他实施例中，也可以是M＝N。
需要说明的是，这里的“交替设置”是指按照一个源极分支120、一个漏极分支220、一个源极分支120、一个漏极分支220……的规律排布，或者，按照一个漏极分支220、一个源极分支120、一个漏极分支220、一个源极分支120……的规律排布。
例如，在112≤W/L≤400的情况下，P×N≥6。经过试验研究，进一步地，在112≤W/L≤400的情况下，即对于相对更大的W/L的值(至少为112)，满足P×N≥6能够更加有效降低薄膜晶体管的发热程度，降低薄膜晶体管的阈值电压的偏移量Δth，保持薄膜晶体管在工作过程中性能的稳定，从而提高采用包括该薄膜晶体管的GOA驱动电路的显示面板的显示效果。例如，尤其是对于W较大的晶体管，例如，W≥950μm，在112≤W/L≤400的情况下，且P×N≥6，降低薄膜晶体管的发热程度显著。
例如，在112≤W/L≤400的情况下，P×N≥6，P≥3且N≥2。如图3A所示，图3A示出了薄膜晶体管M13和薄膜晶体管M3的一种结构。在图3A中，薄膜晶体管M13满足112≤W/L≤400，在薄膜晶体管M13中，P＝3且N＝2。
例如，进一步地，在112≤W/L≤400的情况下，P×N≥12，以进一步有效降低薄膜晶体管的发热程度。
例如，进一步地，P≥4且N≥3。如图3A所示，薄膜晶体管M3也满足112≤W/L≤400，在薄膜晶体管M3中，P＝4且N＝3，经过试验验证，薄膜晶体管M3的发热问题得到显著改善，且可以控制P和N数量设计上的界限，设计规则更加明确。
例如，进一步地，P×N≥16，以进一步有效降低薄膜晶体管的发热程度。
例如，进一步地，P≥4且N≥4。如图3B所示，图3B示出了薄膜晶体管M13和薄膜晶体管M3的另一种结构。在图3B中，薄膜晶体管M13满足112≤W/L≤400，在薄膜晶体管M13中，P＝4且N＝4。
例如，进一步地，235≤W/L≤400，P×N≥32。即对于相对更大的W/L的值(至少为235)，经过试验探索，满足235≤W/L≤400，且P×N≥32能够显著降低薄膜晶体管的发热程度，降低薄膜晶体管的阈值电压的偏移量Δth，保持薄膜晶体管在工作过程中性能的稳定，从而提高采用包括该薄膜晶体管的GOA驱动电路的显示面板的显示效果。
例如进一步地，P≥8且N≥4，以进一步有效降低薄膜晶体管的发热程度。在图3B中，薄膜晶体管M3满足112≤W/L≤400，在薄膜晶体管M3中，P＝8且N＝4。
如图5A所示，在沟道区的总宽度W和子沟道区的平均长度L相同的情况下，在一定范围内，阈值电压的偏移量Δth与源/漏分支数呈负相关，并且，提高源/漏分支数也有利于降低薄膜晶体管的发热程度。例如图5A中示出了W分别为1200μm、L为4.5μm，源极分支数N(这里以源极分支数N代表源/漏分支数)分别为9和39的情况、W分别为1200μm、L为6m，源极分支数N分别为9和39的情况、W分别为1200μm、L为8.5μm，源极分支数N分别为9和39的情况。因此，适当提高源/漏分支数有利于减小阈值电压的偏移量Δth和降低薄膜晶体管的发热程度。
如图5B所示，图5B示出了源漏单元数量P分别为2、12、16的情况，由此可见，在一定范围内，阈值电压的偏移量Δth与源漏单元数量P呈负相关，并且，提高源/漏分支数也有利于降低薄膜晶体管的发热程度。
申请的方案中，所探究得到的各个薄膜晶体管的W/L与P和N的关系，是优化后的设计，可以给栅极驱动电路中的薄膜晶体管的设计提供设计边界，获得较好的工作效果。
例如，在至少一实施例提供的薄膜晶体管中，W/L<180，W的范围是10μm～1600μm。经过试验研究得到图4C，参考图4C，图4C展示了薄膜晶体管的W/L的值在50～400之间的情况，根据图4C可知，当W/L<180(在图4C中的两条线的交点处，W/L＝180)时，子沟道区的平均长度L对阈值电压的偏移量Δth的影响较小，而相对于子沟道区的平均长度L，沟道区的总宽度W对阈值电压的偏移量Δth的影响更大。因此，在W/L<180的情况下，调整沟道区的总宽度W能够更加有效地调整阈值电压的偏移量Δth，改善薄膜晶体管的工作性能。经过试验研究，在W/L<180的情况下，W的范围是10μm～1600μm能够较好地减小阈值电压的偏移量Δth，改善薄膜晶体管发热问题，为薄膜晶体管的沟道区尺寸的设计提供了指导。
例如，在至少一实施例提供的薄膜晶体管中，W/L>180，L的范围是4μm～15μm。参考图4C，当W/L>180时，沟道区的总宽度W沟道区对阈值电压的偏移量Δth的影响较小，而相对于沟道区的总宽度W，子沟道区的平均长度L对偏移量Δth的影响更大。因此，在W/L>180的情况下，调整子沟道区的平均长度L能够更加有效地调整阈值电压的 偏移量Δth，改善薄膜晶体管的工作性能。经过试验研究，在W/L>180的情况下，L的范围是4μm～15μm能够较好地减小阈值电压的偏移量Δth，改善薄膜晶体管发热问题，为薄膜晶体管的沟道区尺寸的设计提供了指导。
例如，在本公开至少一实施例提供的薄膜晶体管中，L＝6μm～8.5μm，以使得更加便于控制W/L的值，容易实现合适的晶体管尺寸设计。
例如，多个源漏单元10排列成至少一个单元行1，至少一个单元行1中的每个单元行1包括至少一个源漏单元10；同一单元行1中，相邻的源漏单元10之间的距离为d。参考图5C，图5C示出了在同一单元行1中，相邻的源漏单元10之间的距离d分别为50μm、100μm、150μm、200μm和250μm的情况下的阈值电压的偏移量Δth和开态电流Ion，根据图5C可知，薄膜晶体管的阈值电压的偏移量Δth与相邻的源漏单元10之间的距离d呈负相关，每一单元行1内的相邻单元10之间的距离d越大，散热能力越强，且阈值电压的偏移量Δth越小，有利于提高薄膜晶体管的充电率，薄膜晶体管的性能越好。但是，随着距离d的增大，开态电流Ion提高，我们希望获得较小的阈值电压的偏移量Δth，同时也不希望开态电流Ion过高，高的开态电流Ion在薄膜晶体管的工作过程中也会造成阈值电压的偏移量Δth变大。因此，探究设计边界非常重要。
例如，在至少一实施例提供的薄膜晶体管中，如图1所示，W≥500μm，同一单元行1中相邻的源漏单元10之间的距离d的范围是50μm～500μm。经过试验研究，如此，在12≤W/L≤400且P×N≥4的条件下，使得W≥500μm且d的范围是50μm～500μm这一条件与12≤W/L≤400且P×N≥4的条件结合，能够在薄膜晶体管的沟道区的总宽度W较大时，达到较好的减小薄膜晶体管的阈值电压的偏移量Δth的效果，降低薄膜晶体管的发热程度，对于满足W≥500μm的薄膜晶体管，给以有效减小薄膜晶体管的阈值电压的偏移量Δth以及降低薄膜晶体管的发热程度为目的的薄膜晶体管的设计提供了设计边界。
例如，在另一实施例中，W<500μm，同一单元行1中相邻的源漏单元10之间的距离为d，d的范围是20μm～300μm。经过试验研究，如此，在12≤W/L≤400且P×N≥4的条件下，使得W<500μm且d的范围是20μm～300μm这一条件与12≤W/L≤400且P×N≥4的条件结合，能够在薄膜晶体管的沟道区的总宽度W较大时，达到较好的减小薄膜晶体管的阈值电压的偏移量Δth的效果，降低薄膜晶体管的发热程度，对于满足W<500μm的薄膜晶体管，给以有效减小薄膜晶体管的阈值电压的偏移量Δth以及降低薄膜晶体管的发热程度为目的的薄膜晶体管的设计提供了设计边界。
当然以上仅是一种具体示例，在实际应用中，同一单元行1内的相邻的源漏单元10之间的距离d大小不限于此。
例如，如图1所示，多个源漏单元10排列成至少两个单元行1，至少一个单元行1中的每个单元行1包括至少一个源漏单元10。例如，多个源漏单元10设置在相邻的源极走线110与漏极走线210之间的区域，以将多个源漏单元10排列为至少两个单元行1。例如，第一源极走线110a、第一漏极走线210a和第二漏极走线210b平行且间隔设置； 且第一源极走线110a位于第一漏极走线210a和第二漏极走线210b之间，在第一源极走线110a和第一漏极走线210a之间间隔排布多个源漏单元10，形成第一单元行11；在第一源极走线110a和第二漏极走线210b之间间隔排布多个源漏单元10，而形成第二单元行12。第一单元行11内各单元10的漏极分支220均连接至第一漏极走线210a，第二单元行12内各单元10的漏极分支220均连接至第二漏极走线210b上；即，每个单元行1内至少一个源漏单元10的源极分支120电连接同一条源极走线110，每一单元行1内至少一个源漏单元10的漏极分支220电连接同一条漏极走线210。第一单元行11内各源漏单元10的源极分支120均连接至第一源极走线110a的一侧，第二单元行12内各源漏单元10的源极分支120均连接至第一源极走线110a的另一侧，也就是，第一单元行11内的源极分支120与第二单元行12内的源极分支120共用同一根第一源极走线110a。
当然，在其他实施例中，薄膜晶体管的源漏单元10也可以只排列为一个单元行。
例如，图1所示例的薄膜晶体管中，所述第一单元行11内的源漏单元10数量为4个，所述第二单元行12内的单元10数量q为4个，该薄膜晶体管内单元10数量总共为8个，当然，每个单元行1内的源漏单元10的数量q不限于此，例如，每个所述单元行1内的源漏单元10数量也可以仅2个，这样，薄膜晶体管中两个单元行1的源漏单元10数量总数仍大于3个，以提高薄膜晶体管的散热性能，或者，根据实际需求，该薄膜晶体管内的源漏单元10的数量也可以小于或等于3个。
例如，结合图1和图2，半导体层400包括与多个源漏单元10中的每个源漏单元10交叠的子部，即子部与每个漏极单元10在由第一方向D1和第二方向D2限定出的平面上的正投影存在交叠，每个子部包括Q个半导体分支410，多个子沟道区40包括Q个半导体分支410的位于相邻的源极分支120和漏极分支220之间的子沟道单元401，以如图2所示的一个小的矩形作为一个子沟道单元401的示意，Q为大于或等于1的整数。这种情况下，沟道区的总宽度W为P个源漏单元10的Q个半导体分支410的子沟道单元401在第一方向D1上的宽度的总和，一个子沟道单元401在第一方向D1上的宽度为W1，即，W＝W1×Q×P；L为P个源漏单元10的多个子沟道单元401在与第一方向D1垂直的方向上的平均长度，例如第二方向D2垂直于第一方向D1，L＝P个源漏单元10的多个子沟道单元401在第二方向D2上的长度之和/个子沟道单元401的总个数，例如在多个子沟道区40的长度均相等的情况下，L＝L’。
此外，在图1所示的实施例中，所述栅极300在衬底基板上的正投影与所述源极走线110在所述衬底基板上的正投影不重叠，且所述栅极300在所述衬底基板上的正投影与所述漏极走线210在所述衬底基板上的正投影重叠。
在上述实施例中，所述栅极300在衬底基板上的正投影与所述第一源极走线110a在所述衬底基板上的正投影不重叠，例如，图1中所示例的，所述栅极300在布置所述第一源极走线110a的位置镂空设计，这样，可以减少所述栅极300与所述第一源极走线110a的重叠面积，从而减少CGS电容，即，减少栅极300和第一源极走线110a之间的电容， 以减少信号DELAY(延迟)；而所述栅极300在所述衬底基板上的正投影与所述第一漏极走线210a、所述第二漏极走线210b在所述衬底基板上的正投影重叠，例如，图1中所示的，所述薄膜晶体管的各单元10内的源极分支120和漏极分支220以及第一漏极走线210a、第二漏极走线210b在所述衬底基板上的正投影均落入所述栅极300在所述衬底基板上的正投影上，这样，可以增加CGD电容，即，所述漏极200与所述栅极300之间的电容，以减少信号噪音。
另外，在图1所示的实施例中，薄膜晶体管应用中，例如，应用于GOA电路中时，第一源极走线110a的第一端连接至GOA电路中的时钟脉冲信号走线600上，栅极300在衬底基板上的正投影与时钟脉冲信号走线600在衬底基板上的正投影不重叠，且栅极300上连接有栅极走线310，栅极走线310在衬底基板上的正投影与时钟脉冲信号走线600在衬底基板上的正投影交叉重叠。
在上述实施例中，一方面，减少栅极300与时钟脉冲信号走线600之间的重叠面积，可以进一步减少CGS电容，即，减少栅极300和时钟脉冲信号走线600之间的电容，以减少信号DELAY(延迟)；另一方面，如图1所示，当GOA电路中包括多个薄膜晶体管时，以图1所示的薄膜晶体管为例，该薄膜晶体管与其他的薄膜晶体管的栅极300之间通过栅极走线310连接，栅极走线310设置在栅极300的靠近时钟脉冲信号走线600的一侧，栅极300在时钟脉冲信号走线600所在一侧具有镂空图形，以与时钟脉冲信号走线600之间不重叠，而仅栅极走线310与时钟脉冲信号线600交叉重叠，这样，该镂空图形处可以增大相邻薄膜晶体管的栅极300之间的间距，从而减少栅极300发热问题。
此外，图1所示的实施例中，相邻两个单元10之间设有采用漏极200的金属层所形成的漏极电极块230，漏极电极块230与栅极300在衬底基板上的正投影重叠，这样，可增加CGD电容，即，漏极200的金属层与栅极300之间的电容，以进一步的减少信号噪音。
当然可以理解的是，在其他实施例中，根据实际需求，也可以在相邻两个单元10之间不设置漏极电极块230。
此外，在图1所示的实施例中，漏极走线210的一端连接至信号输出端500，在衬底基板上还设有由栅极300的金属层所形成的第一栅金属图形320，该第一栅金属图形320位于所述信号输出端500的一侧，并与所述栅极300之间相互独立且绝缘；信号输出端500上设多个第一过孔510，第一栅金属图形320上设有多个第二过孔321，且信号输出端500通过第一过孔510连接至一ITO层(氧化铟锡)330，第一栅金属图形320通过第二过孔321连接至所述ITO层330，以实现信号输出端500与第一栅金属图形320之间的电连接，且第一栅金属图形320又通过第二过孔321与显示器件的像素电极电连接。
此外，如图1所示，所述第一源极走线110a的一端与时钟脉冲信号走线600连接，时钟脉冲信号走线600的走线方向为垂直于所述第一源极走线110a设置；信号输出端500连接在第一漏极走线210a和第二漏极走线210b的同一端，并与第一漏极走线210a垂直 设置，且时钟脉冲信号走线600与信号输出端500分别位于该薄膜晶体管的相对两侧。当然，时钟脉冲信号走线和信号输出端500的位置不局限于这种情况。
图6A是本公开至少一实施例提供的另一种薄膜晶体管的结构示意图。图6A所示的薄膜晶体管与图1所示的薄膜晶体管存在以下区别。在图6A所示的实施例中，在每一源漏单元10内，至少一个半导体分支410设计为补偿半导体分支411，该补偿半导体分支411的沟道总长度小于其他半导体分支410的沟道在第二方向D2上的长度。图6A所示的实施例的其他特征和相应的技术效果均与图1的相同，可参考之前的描述，在此不再重复。
图6B是本公开至少一实施例提供的再一种薄膜晶体管的结构示意图。图6B所示的薄膜晶体管与图1所示的薄膜晶体管存在以下区别。在图6B所示的实施例中，半导体层400包括与多个源漏单元10中的每个源漏单元10交叠的子部，即子部与每个漏极单元10在由第一方向D1和第二方向D2限定出的平面上的正投影存在交叠，与多个源漏单元10交叠的子部构成连续的一体化结构。这种情况下，例如，多个子部构成连续的一体化结构，W＝W2×P。只要不矛盾，图6B所示的实施例的其他特征和相应的技术效果均与图1的相同，可参考之前的描述，在此不再重复。
在本公开的实施例中，薄膜晶体管可以为P型薄膜晶体管或者N型薄膜晶体管，结构可以为底栅型、顶栅型或者双栅型，本公开的实施例对薄膜晶体管的具体类型不做限定。
本公开至少一实施例还提供一种移位寄存器单元，该移位寄存器单元包括本公开实施提供的任意一种薄膜晶体管。
图7是本公开至少一实施例提供的一种移位寄存器单元的示例性电路图。图7所示，在该移位寄存器单元01中，栅极行驱动电路包括输入电路101、输出电路102/103和第一节点复位电路104；输入电路101与第一节点PU连接，且配置为响应于输入信号对第一节点PU进行充电；输出电路102/103与第一节点PU连接，且配置为在第一节点PU的电平信号的控制下，将输出信号在输出端Output1输出；第一节点复位电路104与第一节点PU连接，配置为响应于复位信号对第一节点PU进行复位；输出电路102/103、输入电路101和第一节点复位电路104均包括本公开实施提供的任意一种薄膜晶体管。
如图7所示，输出端Output1包括扫描信号输出端即第一输出端Output1和移位输出端即第二输出端Output2；输出电路包括第一输出子电路102和第二输出子电路103。例如移位寄存器单元01还包括监控子电路105。输入电路101被配置为响应于输入信号，通过输入信号对上拉节点PU(即上述第一节点PU)进行预充电；上拉节点PU为输入电路101、第一输出子电路102、第二输出子电路103和复位子电路104之间的连接节点；第一输出子电路102被配置为响应于上拉节点PU的电位，而将时钟信号通过第一输出端Output1进行输出；第二输出子电路103被配置为响应于上拉节点PU的电位，并通过第二输出端Output2输出与第一输出端Output1所输出的同步信号；复位子电路104被配置为响应于复位信号，通过第二电源电压对上拉节点PU的电位进行复位；监控子电路104 被配置为对第二输出端Output2进行监测，并通过第三输出端Output3将监测结果进行输出。
由此，在上述移位寄存单元中，第一输出子电路102可以通过第一输出端Output1输出GOA信号，例如时钟信号，第二输出子电路103可以通过第二输出端Output2输出第一输出端Output1所输出的同步信号，监控子电路104可以对第二输出端Output2进行监控，同时可以通过第三输出端Output3将监测结果进行输出，这样，可以对第二输出端Output2输出的GOA信号进行监控，判断出移位寄存器输出的GOA信号是否发生异常，因此，可以实现GOA信号的实时监控，从而可以在产品信赖性过程中可以对GOA工作状态变化情况进行监控，进而可以在第一时间检测出GOA信号发生异常的点位。
例如，在一些示例中，如图7所示，第一移位寄存器还可以包括至少一个下拉控制子电路106、至少一个下拉子电路107、至少一个第一降噪子电路108、至少一个第二降噪子电路109和至少一个第三降噪子电路110。下拉控制子电路106被配置为响应于第一电源电压，通过第一电源电压控制下拉节点PD的电位；下拉节点PD为下拉控制子电路106和下拉子电路107之间的连接节点；下拉子电路107被配置为响应于上拉节点PU的电位，通过第二电源电压下拉下拉节点PD的电位；第一降噪子电路108被配置为响应于下拉节点PD的电位，通过第二电源电压对第一输出端Output1进行降噪；第二降噪子电路109被配置为响应于下拉节点PD的电位，通过第二电源电压对第二输出端Output2进行降噪；第三降噪子电路110被配置为响应于下拉节点PD的电位，通过第二电源电压对上拉节点PU进行降噪。
例如，在一些实施例中，如图7所示，第一移位寄存单元还可以包括初始化子电路111；初始化子电路111被配置为响应于初始化信号，通过第二电源电压对上拉节点PU的电位进行初始化。
具体地，如图7所示，输入电路101包括第一晶体管M1(输入晶体管)，第一晶体管M1的栅极和源极均连接输入信号端Input，漏极连接上拉节点PU。复位子电路104包括第二晶体管M2(即上述复位晶体管)，第二晶体管M2的栅极连接复位控制信号端Reset，源极连接第二电源电压端VSS，漏极连接上拉节点PU。第一输出子电路102包括第三晶体管M3(即上述输出晶体管)和存储电容C，第三晶体管M3的栅极连接上拉节点PU，源极连接时钟信号端CLK，漏极连接第一输出端Output1；存储电容C的一端连接上拉节点PU，漏极连接第一输出端Output1。第二输出子电路103包括第十三晶体管M13(该晶体管也为输出晶体管)；第十三晶体管M13的栅极连接上拉节点PU，源极连接时钟信号端CLK，漏极连接第二输出端Output2。
在输入阶段，信号输入端Input写入高电平信号，第一晶体管M1被打开，高电平信号可以通过第一晶体管M1给上拉节点PU进行预充电。在输出阶段，由于上拉节点PU的电位被预充电而拉高，且存储在存储电容C中，在该阶段第一晶体管M1截止，存储电容C放电进一步将上拉节点PU的电位拉高，第三晶体管M3和第十三晶体管M13均被 打开，第一输出端Output1则将时钟信号端CLK写入的高电平信号输出，第二输出端Output2则将第一输出端Output1所输出的同步信号输出。在复位阶段，复位控制信号端Reset被写入高电平信号，第二晶体管M2被打开，通过第二电源电压端VSS写入的低电源电压对上拉节点PU的电位进行复位。
例如，监控子电路105包括第四晶体管M4，第四晶体管M4的栅极和源极均连接第二输出端Output2，漏极连接第三输出端Output3。
需要说明的是，第四晶体管M4的栅极和源极连接第二输出端Output2，漏极连接第三输出端Output3，当第二输出端Output2输出的GOA信号为高电平信号时，第四晶体管M4可以在高电平信号的控制下开启，并该高电平信号通过第三输出端Output3输出，通过将第三输出端Output3输出的高电平信号与参考高电平信号进行比较。如果第三输出端Output3输出的信号与参考高电平信号相同，则表示第二输出端Output2输出的GOA信号正常；如果第三输出端Output3输出的信号与参考高电平信号不同或者第三输出端Output3无输出信号，则表示第二输出端Output2输出的GOA信号异常，因此可以实现GOA信号的实时监控，从而可以在产品信赖性过程中可以对GOA工作状态变化情况进行监控，进而可以在第一时间检测出GOA信号发生异常的点位，避免出现AD等不良。
例如，下拉控制子电路106包括第九晶体管M9和第五晶体管M5，第九晶体管M9的栅极和源极均连接第一电源电压端VDD，漏极连接第五晶体管的M5栅极；第五晶体管M5的栅极连接第九晶体管M9的漏极，源极连接第一电源电压端VDD，漏极连接下拉节点PD。下拉子电路107包括第六晶体管M6和第八晶体管M8，第六晶体管M6的栅极连接上拉节点PU，源极连接下拉节点PD，漏极连接第二电源电压端VSS；第八晶体管M8的栅极连接上拉节点PU，源极连接第九晶体管M9的漏极，漏极连接第二电源电压端VSS。第一降噪子电路108包括第十一晶体管M11，第十一晶体管M11的栅极连接下拉节点PD，源极连接第一输出端Output1，漏极连接第二电源电压端VSS。第二降噪子电路109包括第十二晶体管M12，第十二晶体管M12的栅极连接下拉节点PD，源极连接第二输出端Output2，漏极连接第二电源电压端VSS。第三降噪子电路110包括第十晶体管M10，第十晶体管M10的栅极连接下拉节点PD，源极连接上拉节点PU；漏极连接第二电源电压端VSS。
需要说明的是，在图7示出的示例中，以两个下拉控制子电路106、两个下拉子电路107、两个第一降噪子电路108、两个第二降噪子电路109和两个第三降噪子电路110为例进行说明。可以理解的是，上述的各个子电路的数量还可以为一个或其他数量，其实现原理相同，在此不再赘述。
例如，在图7中，第一个和第二个下拉控制子电路106中的第五晶体管分别用M5和M5′表示，第九晶体管分别用M9和M9′表示；第一个和第二个下拉电路5中的第六晶体管分别用M6和M6′表示，第八晶体管M8分别用M8和M8′表示；第一个和第二个第一降噪电路108中的第十一晶体管分别用M11和M11′表示；第一个和第二个第二降噪电路 109中的第十二晶体管M12分别用M12和M12′表示；第一个和第二个第三降噪电路110中的第十晶体管分别用M10和M10′表示；第一个和第二个下拉控制子电路106所连接的第一电源电压端分别用VDD1和VDD2表示。另外，第一个下拉控制子电路106和第一个下拉电路107连接，二者之间的连接节点用下拉节点PD1表示；第二个下拉控制子电路106和第二个下拉电路107连接，二者之间的连接节点用下拉节点PD2表示；第一个第一降噪电路108连接PD1，第二个第一降噪电路108连接PD2；第一个第二降噪电路109连接PD1，第二个第二降噪电路109连接PD2；第一个第三降噪电路110连接PD1，第二个第三降噪电路110连接PD2。
例如，在一帧图像的扫描过程中，第一个下拉控制子电路106、第一个第一下拉电路107、第一个第一降噪电路108、第一个第二降噪电路109、第一个第三降噪电路110进行工作，或者第二个下拉控制子电路106、第二个第一下拉电路107、第二个第一降噪电路108、第二个第二降噪电路109、第二个第三降噪电路110进行工作。也就是，对于下拉控制子电路106、第一下拉电路107、第一降噪电路108、第二降噪电路109、第三降噪电路110数量可以均为多个，相同的功能的子电路在一帧图像扫描时，仅其中一个工作，同时可以在工作预设时间切换为另一个工作，以此可以延长移位寄存器的寿命。在降噪阶段，由于在复位阶段上拉节点PU被下拉至低电平电位；而第五晶体管M5和第九晶体管M9一直被第一电源电压端VDD1写入的第一电源电压控制，此时下拉节点PD1的电位为高电平信号，第十一晶体管M11被打开，第二电源电压端VSS所写入的第二电源电压通过第十一晶体管M11对第一输出端Output1的输出进行降噪。与此同时，第十二晶体管M12和第十晶体管M10也被打开，第二电源电压端VSS所写入的第二电源电压通过第十二晶体管M12和第十晶体管M10分别对第二输出端Output2和上拉节点PU的输出进行降噪。
例如，初始化子电路111包括第七晶体管M7，第七晶体管M7的栅极连接初始化信号端STV，源极连接上拉节点PU，漏极连接第二电源电压端VSS。
需要说明的是，在显示下一帧显示画面时，初始化信号端STV写入高电平信号，第七晶体管M7被打开，通过第二电源电压端VSS写入的低电源电压对上拉节点PU的电位进行初始化，以防止相邻帧的显示画面相互干扰，影响显示效果。
可以理解的是，本公开实施例提供的第一移位寄存单元和第二移位寄存单元除了可以为上述的19T1C的结构外，还可以为其他的电路结构，例如17T1C结构、18T2C结构、21T1C结构等，本公开的实施例对第一移位寄存单元和第二移位寄存单元的具体结构不做限定。例如，当第一移位寄存单元和第二移位寄存单元的结构为17T1C结构时，相比于上述19T1C结构，该17T1C可以没有第九晶体管M9和M9′，但其实现原理与上述19T1C结构的移位寄存单元的实现原理相同，在此不再赘述。
例如，第一输出子电路102包括第一输出晶体管，第三晶体管M3作为第一输出晶体管；第二输出子电路103包括第二输出晶体管，第十三晶体管M13作为第二输出晶体管； 第一输出晶体管的栅极300和第一节点PU连接，第一输出晶体管的第一极和时钟信号端连接以接收时钟信号，第一输出晶体管的第二极和移位输出端Output2连接；第二输出晶体管的栅极300和第一节点PU连接，第二输出晶体管的第一极和时钟信号端连接以接收时钟信号，第二输出晶体管的第二极和扫描信号输出端Output1连接；时钟信号被传输至输出端Output1作为输出信号；第一输出晶体管和第二输出晶体管均为本公开实施例提供的薄膜晶体管。
第三晶体管M3和第十三晶体管M13的沟道区的总宽度W都比较大，阈值电压的偏移量Δth尤其大，发热尤其严重。例如，第三晶体管M3和第十三晶体管M13均满足P≥3且N≥2，即第一输出晶体管和第二输出晶体管均满足P≥3且N≥2；或者，第三晶体管M3和第十三晶体管M13均满足P×N≥12，即第一输出晶体管和第二输出晶体管均满足P×N≥12；或者，第三晶体管M3和第十三晶体管M13均满足P×N≥16，即第一输出晶体管和第二输出晶体管均满足P×N≥16，以较好地减小第三晶体管M3和第十三晶体管M13的阈值电压的偏移量Δth，降低第三晶体管M3和第十三晶体管M13的发热程度，保证移位寄存器单元01具有较好、较稳定的工作性能，保证使用包括该移位寄存器单元01的栅极驱动电路作为扫描驱动电路的显示面板具有更好的显示效果。
例如，在本公开实施例提供的移位寄存器单元01中，第三晶体管M3和第十三晶体管M13分别为图3A所示的晶体管，第十三晶体管M13满足112≤W/L≤400，在薄膜晶体管M13中，P＝3且N＝2。第三晶体管M3满足112≤W/L≤400，在薄膜晶体管M3中，P＝4且N＝3。第三晶体管M3的源极和第十三晶体管M13的源极均与同一条时钟信号线CLK连接；第三晶体管M3的漏极和第十三晶体管M13的漏极分别与第一漏极走线210A和第二漏极走线210B连接。
例如，第三晶体管M3满足235≤W/L≤400，P×N≥32。例如第三晶体管M3和第十三晶体管M13分别为图3B所示的晶体管，第十三晶体管M13满足112≤W/L≤400，在薄膜晶体管M13中，P＝4且N＝4。第三晶体管M3满足112≤W/L≤400，在薄膜晶体管M3中，P＝8且N＝4。第三晶体管M3的源极和第十三晶体管M13的源极分别与第一源极走线110A和第二源极走线110B连接，第一源极走线110A与同一条时钟信号线CLK连接；第三晶体管M3的漏极和第十三晶体管M13的漏极分别与第一漏极走线210A和第二漏极走线210B连接。
例如，第一晶体管M1、第二晶体管M2、第六晶体管M6、第八晶体管M8/M8’、第十晶体管M10/M10’、第十一晶体管M11/M11’均是本公开实施例提供的薄膜晶体管，均满足12≤W/L≤400，P和N均为大于等于1的整数，M为大于等于2的整数，P×N≥4。由此，通过依据W/L与P和N之间的关系，可以控制P和N数量设计上的界限，设计规则更加明确，从而能够实现基于可预见的能够达到改善发热问题的基础上，在使用该移位寄存器单元01的GOA驱动电路的显示面板中，能够合理地在显示面板的有限的GOA区域(非显示区域，例如至少部分围绕显示区)中合理地排布多个薄膜晶体管，设置更多 的移位寄存器单元来驱动显示面板的显示区中更多行的像素，利于实现驱动高PPI的显示面板，并且，高PPI的显示面板的GOA区域中，GOA驱动电路中的薄膜晶体管的排布更加密集，在这种情况下，特别需要改善薄膜晶体管的散热情况，而根据本申请的W/L与P和N的乘积之间的关系来进行设计，可以有效获得设计边界，改善薄膜晶体管发热问题和防止薄膜晶体管的阈值电压的偏移量Δth过大的问题。
例如，在一些实施例提供的图7所示的移位寄存器单元中，除了上述第一晶体管M1、第二晶体管M2、第六晶体管M6/M6’、第八晶体管M8/M8’、第十晶体管M10/M10’、第十一晶体管M11/M11’、第三晶体管M3和第十三晶体管M13之外的其他任何一个晶体管都可以采用本公开实施例提供的薄膜晶体管，根据不同的晶体管的设计需求，依据本公开实施例提供的薄膜晶体管的设计边界进行具体的设计。
例如，图7所示的移位寄存器单元01中的各个薄膜晶体管采用的设计数据如下表1所示。采用该方案可以根据各个薄膜晶体管的功能的需要，兼顾空间与性能，来合理地设计各个薄膜晶体管。
表1一种移位寄存器单元中各个薄膜晶体管(TFT)的数据
Figure PCTCN2022102945-appb-000001
Figure PCTCN2022102945-appb-000002
图8是本公开至少一实施例提供的另一种移位寄存器单元的示例性电路图。图8中的各个薄膜晶体管与图7中对应的薄膜晶体管执行的功能类似，例如第三晶体管M3和第十三晶体管M13分别为第一输出晶体管和第二输出晶体管，第二晶体管M2为复位晶体管等。各个晶体管和电容的连接关系如图8所示，在此不再一一介绍，可参考对图7的描述以本领域常规技术对图8所示的移位寄存器单元的示例性电路进行理解。
例如，在图8所示的移位寄存器单元中，第三晶体管M3和第十三晶体管M13的沟道区的总宽度W都比较大，阈值电压的偏移量Δth尤其大，发热尤其严重。例如，第三晶体管M3和第十三晶体管M13均满足P≥3且N≥2，即第一输出晶体管和第二输出晶体管均满足P≥3且N≥2；或者，第三晶体管M3和第十三晶体管M13均满足P×N≥12，即第一输出晶体管和第二输出晶体管均满足P×N≥12；或者，第三晶体管M3和第十三晶体管M13均满足P×N≥16，即第一输出晶体管和第二输出晶体管均满足P×N≥16，以较好地减小第三晶体管M3和第十三晶体管M13的阈值电压的偏移量Δth，降低第三晶体管M3和第十三晶体管M13的发热程度，保证移位寄存器单元具有较好、较稳定的工作性能，保证使用包括该移位寄存器单元的栅极驱动电路作为扫描驱动电路的显示面板具有更好的显示效果。
例如，在本公开实施例提供的移位寄存器单元中，第三晶体管M3和第十三晶体管M13分别为图3A所示的晶体管，第十三晶体管M13满足112≤W/L≤400，在薄膜晶体管M13中，P＝3且N＝2。第三晶体管M3满足112≤W/L≤400，在薄膜晶体管M3中，P＝4且N＝3。
例如，第三晶体管M3满足235≤W/L≤400，P×N≥32。例如第三晶体管M3和第十三晶体管M13分别为图3B所示的晶体管，第十三晶体管M13满足112≤W/L≤400，在薄膜晶体管M13中，P＝4且N＝4。第三晶体管M3满足112≤W/L≤400，在薄膜晶体管M3中，P＝8且N＝4。
例如，第一晶体管M1、第二晶体管M2、第六晶体管M6/M6’、第十晶体管M10/M10’、第十一晶体管M11/M11’、第十六晶体管M16/M16’、均是本公开实施例提供的薄膜晶体管，均满足12≤W/L≤400，P和N均为大于等于1的整数，M为大于等于2的整数，P×N≥4。由此，通过依据W/L与P和N之间的关系，可以控制P和N数量设计上的界限，设计规则更加明确，从而能够实现基于可预见的能够达到改善发热问题的基础上，在使用该移位寄存器单元的GOA驱动电路的显示面板中，能够合理地在显示面板的有限的GOA区域(非显示区域，例如至少部分围绕显示区)中合理地排布多个薄膜晶体管，设置更多的移位寄存器单元来驱动显示面板的显示区中更多行的像素，利于实现驱动高PPI的显示 面板，并且，高PPI的显示面板的GOA区域中，GOA驱动电路中的薄膜晶体管的排布更加密集，在这种情况下，特别需要改善薄膜晶体管的散热情况，而根据本申请的W/L与P和N的乘积之间的关系来进行设计，可以有效获得设计边界，改善薄膜晶体管发热问题和防止薄膜晶体管的阈值电压的偏移量Δth过大的问题。
例如，图8所示的移位寄存器单元中的各个薄膜晶体管采用的设计数据如下表2所示。采用该方案可以根据各个薄膜晶体管的功能的需要，兼顾空间与性能，来合理地设计各个薄膜晶体管。
表2一种移位寄存器单元中各个薄膜晶体管(TFT)的数据
Figure PCTCN2022102945-appb-000003
本公开至少一实施例还提供一种栅极驱动电路，该栅极驱动电路包括本公开实施例提供的任意一种移位寄存器单元，栅极驱动电路包括多个级联的移位寄存器单元；除第1级至第s级移位寄存器单元外，其余各级移位寄存器单元的预充控制端和与其相隔至少s级的上级移位寄存器单元的输出端连接；除第1级至第s级移位寄存器单元外，其余各级 移位寄存器单元的输入端和与其相隔s-1级的上级移位寄存器单元的输出端连接；除最后s级移位寄存器单元外，其余各级移位寄存器单元的复位端和与其相隔s-1级的下级移位寄存器单元的输出端连接；其中，s为大于2的整数。
本公开至少一实施例还提供一种显示面板，包括本公开任一实施例提供的栅极驱动电路。例如，本公开实施例提供的显示面板可以为有机发光二极管显示面板或液晶显示面板等。
图9是本公开至少一实施例还提供的一种显示面板的示意图。如图9所示，例如，该显示面板1000包括显示区10A和至少部分围绕显示区10A的非显示区。非显示区包括栅极驱动电路区域10B/10C和电路引线区域10D。例如，非显示区包括第一电路区域10B和第二电路区域10C，例如第一电路区域10B和第二电路区域10C均沿纵向延伸，第一电路区域10B和第二电路区域10C均沿纵向延伸中分别设置有多个级联的移位寄存器单元01，多个级联的移位寄存器单元01沿纵向排列；电路引线区域10D，即Fanout区，中设置有电路引线(未示出)，电路引线区域10D沿与纵向相交的横向延伸，与栅极驱动电路区域10B/10C相邻，电路引线包括与栅极驱动电路连接第一引线和连接至显示区10A的第二引线；多个级联的移位寄存器单元01包括位于第一电路区域10B的靠近电路引线区域10D的一端的第一端部移位寄存器单元01a和位于第二电路区域10C的靠近电路引线区域10D的一端的第二端部移位寄存器单元01b；第一端部移位寄存器单元01a中的第一输出晶体管的P×N的值和第一端部移位寄存器单元01a中的第二输出晶体管的P×N的值分别大于位于第一电路区域10B中的多个级联的移位寄存器单元01中的其他移位寄存器单元中的第一输出晶体管的P×N的值和第一端部移位寄存器单元01a中的第二输出晶体管的P×N的值。在显示面板中，第一端部移位寄存器单元01a的位置处以及电路引线区域10D的靠近第一端部移位寄存器单元01a的区域布线较为密集，发热尤其严重，采用该方案可以有效降低该发热严重区域的发热程度，提高栅极驱动电路的性能，提高显示效果，且利于提高该区域的电路的寿命。同理，对于第二端部移位寄存器单元01b也是如此，第二端部移位寄存器单元01b中的第一输出晶体管的P×N的值和第二端部移位寄存器单元01b中的第二输出晶体管的P×N的值分别大于位于第而电路区域10C中多个级联的移位寄存器单元01中的其他移位寄存器单元中的第一输出晶体管的P×N的值和第二端部移位寄存器单元01b中的第二输出晶体管的P×N的值。这里的第一输出晶体管和第二输出晶体管指前面关于移位寄存器单元的实施例中的第一输出晶体管和第二输出晶体管，具体可参考之前的描述。
例如，本公开至少一实施例还提供一种显示装置，该显示装置包括本公开任一实施例提供的显示面板。例如该显示装置可以是液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置还可以包括显示面板等其他常规部件，本公开的实施例对此不作限定。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围根据权利要求书所界定的范围确定。

Claims (21)

  1. 一种薄膜晶体管，包括：
    源极，包括源极走线和与所述源极走线电连接的P个源极单元，其中，所述P个源极单元中的每个包括M个源极分支，所述M个源极分支的每个沿第一方向延伸且在与所述第一方向相交的第二方向上间隔排列；
    漏极，包括漏极走线和与所述漏极走线电连接且与所述P个源极单元一一对应的P个漏极单元，其中，所述P个漏极单元中的每个包括N个漏极分支，所述N个漏极分支的每个沿所述第一方向延伸且在所述第二方向上间隔排列；所述薄膜晶体管包括P个源漏单元，一个所述源极单元与对应的一个所述漏极单元构成一个所述源漏单元，在所述P个源漏单元中的每个源漏单元内，所述M个源极分支与所述N个漏极分支交替设置、彼此间隔且绝缘，M大于等于N；
    栅极，与所述源极和所述漏极绝缘；以及
    半导体层，与每个所述源漏单元的所述M个源极分支和所述N个漏极分支电连接，其中，所述半导体层包括位于所述P个源漏单元中每个源漏单元中的多个子沟道区，所述多个子沟道区的每个位于彼此相邻的所述漏极分支和所述源极分支之间；
    所述P个源漏单元的多个子沟道区在所述第一方向上的宽度的总和为W，所述P个源漏单元的多个子沟道区在与所述第一方向垂直的方向上的平均长度为L；
    12≤W/L≤400，P、M和N均为大于等于1的整数，P×N≥4。
  2. 根据权利要求1所述的薄膜晶体管，其中，112≤W/L≤400，P×N≥6。
  3. 根据权利要求2所述的薄膜晶体管，其中，P≥3且N≥2。
  4. 根据权利要求2或3所述的薄膜晶体管，其中，P×N≥12。
  5. 根据权利要求2-4任一所述的薄膜晶体管，其中，P×N≥16。
  6. 根据权利要求2-5任一所述的薄膜晶体管，其中，235≤W/L≤400，P×N≥32。
  7. 根据权利要求1-6任一所述的薄膜晶体管，其中，
    W/L<180，W的范围是10μm～1600μm。
  8. 根据权利要求1-6任一所述的薄膜晶体管，其中，
    W/L>180，L的范围是4μm～15μm。
  9. 根据权利要求1-8任一所述的薄膜晶体管，其中，
    所述多个源漏单元排列成至少一个单元行，所述至少一个单元行中的每个单元行包括至少一个源漏单元；
    同一所述单元行中，相邻的所述源漏单元之间的距离为d，W≥500μm，d的范围为是50μm～500μm。
  10. 根据权利要求1-8任一所述的薄膜晶体管，其中，
    所述多个源漏单元排列成至少一个单元行，所述至少一个单元行中的每个单元行包括 至少一个源漏单元；
    同一所述单元行中，相邻的所述源漏单元之间的距离为d，W<500μm，d的范围为是20μm～300μm。
  11. 根据权利要求1-8任一所述的薄膜晶体管，其中，所述多个源漏单元排列成至少两个单元行，所述至少一个单元行中的每个单元行包括至少一个源漏单元。
  12. 根据权利要求1-11任一所述的薄膜晶体管，其中，所述半导体层包括与所述多个源漏单元中的每个源漏单元交叠的子部，所述子部包括Q个半导体分支，所述多个子沟道区包括所述Q个半导体分支的位于相邻的所述源极分支和所述漏极分支之间的子沟道单元，Q为大于或等于1的整数；
    W为所述P个源漏单元的Q个半导体分支的子沟道单元在所述第一方向上的宽度的总和，L为所述P个源漏单元的多个所述子沟道单元在与所述第一方向垂直的方向上的平均长度。
  13. 根据权利要求1-11任一所述的薄膜晶体管，其中，所述半导体层包括与所述多个源漏单元中的每个源漏单元交叠的子部，与所述源漏单元交叠的多个所述子部构成连续的一体化结构。
  14. 根据权利要求1-13任一所述的薄膜晶体管，其中，所述多个源漏单元设置在相邻的所述源极走线与所述漏极走线之间的区域，以将所述多个源漏单元排列为至少两个单元行，所述至少两个单元行中的每个单元行包括至少一个所述源漏单元；
    每个所述单元行内所述至少一个源漏单元的所述源极分支电连接同一条所述源极走线，每一所述单元行内所述至少一个源漏单元的所述漏极分支电连接同一条所述漏极走线。
  15. 一种移位寄存器单元，包括根据权利要求1-14任一所述的薄膜晶体管。
  16. 根据权利要求15所述的移位寄存器单元，其中，所述栅极行驱动电路包括输入电路、输出电路和第一节点复位电路；
    所述输入电路与第一节点连接，且配置为响应于输入信号对所述第一节点进行充电；所述输出电路与所述第一节点连接，且配置为在所述第一节点的电平信号的控制下，将输出信号在输出端输出；所述第一节点复位电路与所述第一节点连接，配置为响应于复位信号对所述第一节点进行复位；
    所述输出电路、所述输入电路和所述第一节点复位电路均包括根据权利要求1所述的薄膜晶体管。
  17. 根据权利要求16所述的移位寄存器单元，其中，所述输出端包括移位输出端和扫描信号输出端；所述输出电路包括第一输出晶体管和第二输出晶体管；
    所述第一输出晶体管的栅极和所述第一节点连接，所述第一输出晶体管的第一极和时钟信号端连接以接收时钟信号，所述第一输出晶体管的第二极和所述移位输出端连接；所述第二输出晶体管的栅极和所述第一节点连接，所述第二输出晶体管的第一极和所述时钟 信号端连接以接收所述时钟信号，所述第二输出晶体管的第二极和所述扫描信号输出端连接；所述时钟信号被传输至所述输出端作为所述输出信号；
    所述第一输出晶体管和第二输出晶体管均为根据权利要求1所述的薄膜晶体管；
    所述第一输出晶体管和第二输出晶体管均满足P≥3且N≥2，或者，
    所述第一输出晶体管和第二输出晶体管均满足P×N≥12，或者，
    所述第一输出晶体管和第二输出晶体管均满足P×N≥16。
  18. 根据权利要求17所述的移位寄存器单元，其中，所述第一输出晶体管满足235≤W/L≤400，P×N≥32。
  19. 一种栅极驱动电路，包括根据权利要求15-18任一所述的移位寄存器单元，其中，所述栅极驱动电路包括多个级联的所述移位寄存器单元；
    除第1级至第s级移位寄存器单元外，其余各级移位寄存器单元的预充控制端和与其相隔至少s级的上级移位寄存器单元的输出端连接；
    除第1级至第s级移位寄存器单元外，其余各级移位寄存器单元的输入端和与其相隔s-1级的上级移位寄存器单元的输出端连接；
    除最后s级移位寄存器单元外，其余各级移位寄存器单元的复位端和与其相隔s-1级的下级移位寄存器单元的输出端连接；
    其中，s为大于2的整数。
  20. 一种显示面板，包括权利要求19所述的栅极驱动电路。
  21. 根据权利要求20所述的显示面板，其中，所述显示面板包括显示区和至少部分围绕所述显示区的非显示区；
    所述非显示区包括：
    栅极驱动电路区域，沿纵向延伸，设置有所述栅极驱动电路，其中，所述多个级联的移位寄存器单元沿所述纵向排列；以及
    电路引线区域，设置有电路引线，沿与所述纵向相交的横向延伸，与所述栅极驱动电路区域相邻，其中，所述电路引线包括与所述栅极驱动电路连接第一引线和连接至所述显示区的第二引线；
    所述多个级联的移位寄存器单元包括位于所述电路区域的靠近所述电路引线区域的一端的端部移位寄存器单元；
    每个所述移位寄存器中，所述输出端包括移位输出端和扫描信号输出端；所述输出电路包括第一输出晶体管和第二输出晶体管；
    所述第一输出晶体管的栅极和所述第一节点连接，所述第一输出晶体管的第一极和时钟信号端连接以接收时钟信号，所述第一输出晶体管的第二极和所述移位输出端连接；所述第二输出晶体管的栅极和所述第一节点连接，所述第二输出晶体管的第一极和所述时钟信号端连接以接收所述时钟信号，所述第二输出晶体管的第二极和所述扫描信号输出端连接；所述时钟信号被传输至所述输出端作为所述输出信号；
    所述第一输出晶体管和第二输出晶体管均为根据权利要求1所述的薄膜晶体管；
    所述端部移位寄存器单元中的第一输出晶体管的P×N的值和所述端部移位寄存器单元中的第二输出晶体管的P×N的值分别大于所述多个级联的移位寄存器单元中的其他移位寄存器单元中的第一输出晶体管的P×N的值和所述端部移位寄存器单元中的第二输出晶体管的P×N的值。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010000627A1 (en) * 1996-11-21 2001-05-03 Semiconductor Energy Laboratory Co., Ltd Active matrix display device having multiple gate electrode portions
CN101154713A (zh) * 2006-09-26 2008-04-02 精工爱普生株式会社 薄膜晶体管、电光装置及电子设备
US20090050900A1 (en) * 2007-08-23 2009-02-26 Fujitsu Limited Field-effect transistor
CN104465787A (zh) * 2014-12-31 2015-03-25 京东方科技集团股份有限公司 一种薄膜晶体管及电路结构
CN109309100A (zh) * 2018-09-29 2019-02-05 京东方科技集团股份有限公司 薄膜晶体管、栅极驱动电路和显示面板
CN113851485A (zh) * 2020-06-28 2021-12-28 京东方科技集团股份有限公司 一种薄膜晶体管、栅极行驱动电路及阵列基板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010000627A1 (en) * 1996-11-21 2001-05-03 Semiconductor Energy Laboratory Co., Ltd Active matrix display device having multiple gate electrode portions
CN101154713A (zh) * 2006-09-26 2008-04-02 精工爱普生株式会社 薄膜晶体管、电光装置及电子设备
US20090050900A1 (en) * 2007-08-23 2009-02-26 Fujitsu Limited Field-effect transistor
CN104465787A (zh) * 2014-12-31 2015-03-25 京东方科技集团股份有限公司 一种薄膜晶体管及电路结构
CN109309100A (zh) * 2018-09-29 2019-02-05 京东方科技集团股份有限公司 薄膜晶体管、栅极驱动电路和显示面板
CN113851485A (zh) * 2020-06-28 2021-12-28 京东方科技集团股份有限公司 一种薄膜晶体管、栅极行驱动电路及阵列基板

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