WO2021140771A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2021140771A1
WO2021140771A1 PCT/JP2020/044019 JP2020044019W WO2021140771A1 WO 2021140771 A1 WO2021140771 A1 WO 2021140771A1 JP 2020044019 W JP2020044019 W JP 2020044019W WO 2021140771 A1 WO2021140771 A1 WO 2021140771A1
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Prior art keywords
conductive plate
slit
chip
region
semiconductor device
Prior art date
Application number
PCT/JP2020/044019
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English (en)
French (fr)
Inventor
健史 寺島
Original Assignee
富士電機株式会社
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Publication date
Application filed by 富士電機株式会社 filed Critical 富士電機株式会社
Priority to CN202080047591.1A priority Critical patent/CN114026687A/zh
Priority to DE112020002845.3T priority patent/DE112020002845T5/de
Priority to JP2021569755A priority patent/JP7201106B2/ja
Publication of WO2021140771A1 publication Critical patent/WO2021140771A1/ja
Priority to US17/565,067 priority patent/US20220122920A1/en

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Definitions

  • the present invention relates to a semiconductor device.
  • Semiconductor devices include power devices and are used as power conversion devices.
  • the power device includes, for example, a semiconductor chip of an IGBT (Insulated Gate Bipolar Transistor) and a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
  • IGBT Insulated Gate Bipolar Transistor
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • Such a semiconductor device includes at least a semiconductor chip, wiring terminals, and a ceramic circuit board.
  • a semiconductor chip and wiring terminals are arranged on the ceramic circuit board.
  • the ceramic circuit board includes an insulating plate and a conductive plate provided on the insulating plate.
  • a semiconductor chip and wiring terminals are joined on the conductive plate by soldering.
  • the molten solder spreads.
  • the semiconductor chip and the wiring terminal are arranged on such solder, the semiconductor chip and the wiring terminal may be displaced from the predetermined joining region. Therefore, a slit is formed in the conductive plate around the joint region. With such a slit, it is possible to control the spread of the molten solder when joining the semiconductor chip and the wiring terminal with solder.
  • the slit is also used for alignment when arranging the semiconductor chip and the wiring terminal on the conductive plate.
  • the inductance in the current path of the conductive plate may change. Therefore, the electrical characteristics of the semiconductor device are affected, and the reliability is lowered.
  • the present invention has been made in view of such a point, and an object of the present invention is to provide a semiconductor device capable of preventing a change in inductance while controlling the spread of molten solder.
  • a substrate including an insulating plate and a conductive plate provided on the front surface of the insulating plate, and a first chip region provided on the front surface of the conductive plate. It has one semiconductor chip, a second semiconductor chip provided in the second chip region of the front surface of the conductive plate, and a wiring terminal provided in the terminal region of the front surface of the conductive plate.
  • the conductive plate includes a first slit formed in the gap between the first chip region and the second chip region, and a second slit formed in the gap between the first chip region and the terminal region.
  • a third slit formed in a gap between the first chip region and the terminal region is provided, the first slit is a continuous line penetrating the conductive plate, and the second slit and the third slit are ,
  • a semiconductor device is provided which is either a non-penetrating continuous line of the conductive plate or a broken line partially penetrating the conductive plate.
  • the "front surface” and the “upper surface” represent the surfaces facing upward in the semiconductor device 50 of FIG. Similarly, “upper” represents the upper direction in the semiconductor device 50 of FIG.
  • the “back surface” and the “bottom surface” represent a surface facing downward in the semiconductor device 50 of FIG. Similarly, “bottom” represents the direction of the lower side in the semiconductor device 50 of FIG.
  • other drawings mean the same direction.
  • the "front surface”, “upper surface”, “upper”, “back surface”, “lower surface”, “lower”, and “side surface” are merely convenient expressions for specifying the relative positional relationship, and the present invention It does not limit the technical idea of. For example, “above” and “below” do not necessarily mean vertical to the ground. That is, the “up” and “down” directions are not limited to the direction of gravity.
  • FIG. 1 is a side view of the semiconductor device of the first embodiment
  • FIG. 2 is a plan view of the semiconductor device of the first embodiment
  • the sealing member 45 is represented by a broken line.
  • the sealing member 45 is not shown.
  • the description of the case is omitted.
  • the case houses the ceramic circuit board 10, the first and second semiconductor chips 20, 21, and the like.
  • the plurality of conductive plates 12, the first and second semiconductor chips 20, 21, the plurality of contact parts 30, the plurality of bonding wires 15, and the plurality of external connection pins 40 are respectively. It will be described with the same reference numerals without distinction. It should be noted that the configurations other than these are also described with the same reference numerals and the same reference numerals without distinguishing between the plurality of configurations.
  • the semiconductor device 50 includes a ceramic circuit board 10 (board) and first and second semiconductor chips 20 and 21 bonded to the front surface of the ceramic circuit board 10. doing.
  • the semiconductor device 50 has a contact component 30 (wiring terminal) joined to the front surface of the ceramic circuit board 10.
  • the first and second semiconductor chips 20, 21 and the contact component 30 are joined to the front surface of the ceramic circuit board 10 via a joining material (not shown).
  • the bonding material is, for example, solder. The details of the solder will be described later.
  • the semiconductor device 50 has a bonding wire 15 that electrically connects the front surface of the ceramic circuit board 10 and the main electrodes of the first and second semiconductor chips 20 and 21.
  • an external connection pin 40 is press-fitted and attached to the contact component 30.
  • the semiconductor device 50 is sealed together with the first and second semiconductor chips 20 and 21 on the front surface of the ceramic circuit board 10 so that the tip of the external connection pin 40 attached to the contact component 30 protrudes. It is sealed by a member 45.
  • the ceramic circuit board 10 is an example of a board. Such a ceramic circuit board 10 has a rectangular shape in a plan view.
  • the ceramic circuit board 10 includes an insulating plate 11, a metal plate 13 provided on the back surface of the insulating plate 11, and a plurality of conductive plates 12 provided on the front surface of the insulating plate 11 (including the conductive plate 12a; the same applies hereinafter). And include.
  • the insulating plate 11 and the metal plate 13 have a rectangular shape in a plan view. Further, the corners may be chamfered into an R shape or a C shape.
  • the size of the metal plate 13 is smaller than the size of the insulating plate 11 in a plan view, and is formed inside the insulating plate 11.
  • the insulating plate 11 is made of ceramics having good thermal conductivity. Such ceramics are, for example, aluminum oxide, aluminum nitride, and silicon nitride. The thickness of the insulating plate 11 is 0.5 mm or more and 2.0 mm or less.
  • the metal plate 13 is made of a metal having excellent thermal conductivity. Such metals are, for example, aluminum, iron, silver, copper, or alloys containing at least one of these. The thickness of the metal plate 13 is 0.1 mm or more and 2.0 mm or less. The surface of the metal plate 13 may be plated in order to improve the corrosion resistance. At this time, the plating material used is, for example, nickel, nickel-phosphorus alloy, nickel-boron alloy.
  • the plurality of conductive plates 12 are made of a metal having excellent conductivity. Such metals are, for example, silver, copper, nickel, or alloys containing at least one of these.
  • the thickness of the plurality of conductive plates 12 is 0.5 mm or more and 1.5 mm or less.
  • the surfaces of the plurality of conductive plates 12 may be plated in order to improve the corrosion resistance. At this time, the plating material used is, for example, nickel, nickel-phosphorus alloy, nickel-boron alloy.
  • the plurality of conductive plates 12 with respect to the insulating plate 11 are obtained by forming a metal layer on the front surface of the insulating plate 11 and performing a treatment such as etching on the metal layer.
  • a plurality of conductive plates 12 cut out from the metal layer in advance may be pressure-bonded to the front surface of the insulating plate 11.
  • the plurality of conductive plates 12 shown in FIGS. 1 and 2 are examples. If necessary, the number, shape, size, etc. of the conductive plates 12 can be appropriately selected. Further, a plurality of slits are formed in the broken line region in FIG. 2 of the conductive plate 12a. Details of these slits will be described later.
  • a ceramic circuit board 10 for example, a DCB (Direct Copper Bonding) board or an AMB (Active Metal Brazing) board can be used.
  • a metal base substrate can be used as another example of the substrate.
  • the metal base substrate includes an insulating layer made of resin, a metal plate 13 provided on the back surface of the insulating layer, and a plurality of conductive plates 12 provided on the front surface of the insulating plate 11. Further, in the semiconductor device 50 configured by being sealed by the sealing member 45, the back surface of the metal plate 13 of the ceramic circuit board 10 is exposed.
  • the first semiconductor chip 20 is a switching element made of silicon or silicon carbide.
  • the switching element is, for example, an IGBT or a power MOSFET.
  • a collector electrode is provided as a main electrode on the back surface
  • a gate electrode is provided as a control electrode
  • an emitter electrode is provided as a main electrode on the front surface.
  • a drain electrode is provided as a main electrode on the back surface
  • a gate electrode is provided as a control electrode
  • a source electrode is provided as a main electrode on the front surface.
  • the second semiconductor chip 21 is a diode element made of silicon or silicon carbide.
  • the diode element is, for example, an FWD (Free Wheeling Diode) such as an SBD (Schottky Barrier Diode) or a PiN (P-intrinsic-N) diode.
  • FWD Free Wheeling Diode
  • SBD Schottky Barrier Diode
  • PiN PiN
  • Such a second semiconductor chip 21 is provided with a cathode electrode as a main electrode on the back surface and an anode electrode as a main electrode on the front surface.
  • the back surfaces of the first and second semiconductor chips 20 and 21 are joined to a predetermined conductive plate 12 by a joining material (not shown).
  • the bonding material is, for example, solder. Details of the joining material will be described later.
  • the thicknesses of the first and second semiconductor chips 20 and 21 are, for example, 180 ⁇ m or more and 220 ⁇ m or less, and the average is about 200 ⁇ m.
  • the electronic component 24 can also be arranged on the conductive plate 12.
  • the electronic component 24 is, for example, a thermistor or a current sensor.
  • the bonding wire 15 appropriately electrically connects between the first and second semiconductor chips 20 and 21 and the conductive plate 12, or between a plurality of first and second semiconductor chips 20 and 21.
  • a bonding wire 15 is made of a material having excellent conductivity.
  • the material is composed of, for example, gold, silver, copper, aluminum, or an alloy containing at least one of these.
  • the diameter of the bonding wire 15 is, for example, 100 ⁇ m or more and 500 ⁇ m or less.
  • the contact component 30 is an example of a wiring terminal.
  • Such a contact component 30 includes a main body and a flange.
  • the main body has a cylindrical through hole formed inside.
  • the flange is provided at the open end of the main body.
  • An external connection pin 40 is press-fitted into the through hole of the main body of the contact component 30.
  • the external connection pin 40 has a rod-shaped main body and tapered tip portions formed at both ends of the main body.
  • the main body has a prismatic shape.
  • the diagonal length of the cross section of the external connection pin 40 is several percent longer than the diameter of the main body of the contact component 30.
  • the contact component 30 and the external connection pin 40 are made of a metal having excellent conductivity.
  • Such metals are, for example, silver, copper, nickel, or alloys containing at least one of these.
  • the surfaces of the contact component 30 and the external connection pin 40 may be plated in order to improve corrosion resistance.
  • the plating material used is, for example, nickel, nickel-phosphorus alloy, nickel-boron alloy.
  • wiring terminals include lead frames, busbars and external connection terminals.
  • the lead frame electrically connects the first and second semiconductor chips 20, 21 and the conductive plate 12.
  • the bus bar electrically connects the plurality of conductive plates 12.
  • the external connection terminal electrically connects the conductive plate 12 and the external device.
  • Such a lead frame, a bus bar, and an external connection terminal are made of a metal having excellent conductivity. Such metals are, for example, silver, copper, nickel, or alloys containing at least one of these.
  • the surfaces of the contact component 30 and the external connection pin 40 may be plated in order to improve corrosion resistance. At this time, the plating material used is, for example, nickel, nickel-phosphorus alloy, nickel-boron alloy.
  • the sealing member 45 contains a thermosetting resin and a filler contained in the thermosetting resin as a filler.
  • the thermosetting resin is, for example, an epoxy resin, a phenol resin, or a maleimide resin.
  • the filler is, for example, silicon dioxide, aluminum oxide, boron nitride or aluminum nitride.
  • FIG. 3 is a plan view of a main part of the conductive plate of the ceramic circuit board included in the semiconductor device of the first embodiment.
  • 4 and 5 are cross-sectional views of a main part of a ceramic circuit board included in the semiconductor device of the first embodiment.
  • 4 is a cross-sectional view taken along the alternate long and short dash line YY of FIG. 3
  • FIG. 5 is a sectional view taken along line XX of the alternate long and short dash line of FIG.
  • the first semiconductor chip 20 is provided in the first chip region 12a1 on the front surface of the conductive plate 12a via the solder 20a.
  • the second semiconductor chip 21 is provided in the second chip region 12a2 on the front surface of the conductive plate 12a via the solder 21a.
  • the contact component 30 is provided in the terminal region 12a3 on the front surface of the conductive plate 12a via the solder 30a. Further, the external connection pin 40 is press-fitted into the contact component 30.
  • the solders 20a, 21a, and 30a are composed of lead-free solder as a substrate.
  • the lead-free solder contains, for example, at least one of an alloy composed of tin and silver, an alloy composed of tin and antimony, an alloy composed of tin and zinc, and an alloy composed of tin and copper as a main component.
  • the solders 20a, 21a and 30a may contain additives. Additives are, for example, copper, bismuth, indium, nickel, germanium, cobalt or silicon.
  • the solder compositions of the solders 20a and 21a for joining the first and second semiconductor chips 20 and 21 and the solder 30a for joining the contact component 30 are different. The solders 20a and 21a for joining the first and second semiconductor chips 20 and 21 are less likely to generate voids and have high temperature resistance.
  • the solders 20a and 21a are alloys containing tin and antimony as main components.
  • the solder 30a for joining the wiring terminals of the contact component 30 and the like has a lower elastic modulus than the solders 20a and 21a.
  • the solder 30a is, for example, an alloy containing tin and silver as main components.
  • FIG. 3 shows a state in which the molten solders 20a, 21a, and 30a are spread and solidified.
  • the solders 20a and 21a for joining the first and second semiconductor chips 20 and 21 may be thinner than the solders 30a for joining the contact parts 30.
  • the thicknesses of the solders 20a and 21a are 0.05 mm or more and 0.25 mm or less.
  • the thickness of the solder 30a is 0.10 mm or more and 0.50 mm or less. Since the solder 30a has a lower elastic modulus than the solders 20a and 21a, the thickness of the solder 30a can be made thicker than that of the solders 20a and 21a. Therefore, the heat generated by the semiconductor chips 20 and 21 during the operation of the semiconductor device 10 can be satisfactorily dissipated. Further, the occurrence of cracks and peeling in the solder 30a can be suppressed, and the semiconductor device 10 can be prevented from being damaged.
  • first chip region 12a1 and the second chip region 12a2 are set so that at least a part of the side portions of the conductive plate 12a faces each other and is adjacent to each other.
  • the terminal region 12a3 is set adjacent to the conductive plate 12a so as to face the side portion of the first chip region 12a1 and the side portion of the second chip region 12a2.
  • the terminal region 12a3 is adjacent to the conductive plate 12a in a direction perpendicular to the arrangement direction (vertical direction in FIG. 3) of the first chip region 12a1 and the second chip region 12a2 (horizontal direction in FIG. 3). It is set.
  • the contact component 30 may be arranged in any of the terminal regions 12a3, and the arrangement position in FIG. 3 is an example.
  • the first, second, and third slits 14a, 14b, and 14c are formed on the conductive plate 12a, respectively.
  • the first slit 14a is formed in the gap between the first chip region 12a1 and the second chip region 12a2.
  • the first slit 14a is a continuous line penetrating the conductive plate 12a.
  • the width of the first slit 14a may be larger than the thickness of the solders 20a and 21a and may be equal to or less than the width of the gap between the first chip region 12a1 and the second chip region 12a2.
  • the heights of the first and second semiconductor chips 20 and 21 from the front surface of the conductive plates 12a are substantially the same.
  • the length of the first slit 14a is preferably at least the length corresponding to the side portion where the first chip region 12a1 and the second chip region 12a2 face each other and overlap.
  • the length of the first slit 14a is preferably less than or equal to the length corresponding to any of the opposite side portions of the first chip region 12a1 and the second chip region 12a2.
  • the second slit 14b is formed in the gap between the first chip region 12a1 and the terminal region 12a3.
  • the third slit 14c is formed in the gap between the second chip region 12a2 and the terminal region 12a3.
  • the third slit 14c is a non-penetrating continuous line of the conductive plate 12a.
  • the cross-sectional view of the second slit 14b is omitted, it is a non-penetrating continuous line of the conductive plate 12a like the third slit 14c shown in FIG. That is, the depth of the second and third slits 14b and 14c is less than the thickness of the conductive plate 12a.
  • the thickness of the solder 30a is thicker than the thickness of the solder 21a (and the solder 20a).
  • the widths of the second and third slits 14b and 14c are larger than the thicknesses of the solders 20a and 21a, the width of the gap between the first chip region 12a1 and the terminal region 12a3, and the width between the second chip region 12a2 and the terminals. It may be equal to or less than the width of the gap with the region 12a3.
  • the length of the second and third slits 14b and 14c is preferably at least the length corresponding to the side portion where the terminal region 12a3 and the first and second chip regions 12a1 and 12a2 face each other and overlap. ..
  • the length is preferably equal to or less than the length corresponding to the side portion of the first chip region 12a1 on the terminal region 12a3 side and the side portion of the second chip region 12a2 on the terminal region 12a3 side.
  • the second and third slits 14b and 14c are formed on the side portions of the first and second chip regions 12a1 and 12a2, respectively.
  • the second and third slits 14b and 14c may be continuous slits connected in the middle thereof.
  • Such first, second, and third slits 14a, 14b, and 14c are formed to a predetermined depth according to the formation location by, for example, etching or laser processing.
  • the molten solders 20a and 30a are closed and separated by the opposite ends of the second slit 14b. Therefore, the movement of the molten solders 20a and 30a between the first chip region 12a1 and the terminal region 12a3 is prevented, and the first semiconductor chip 20 and the contact component 30 are displaced from the predetermined joining region. Can be prevented. Further, since the outflow of the solder 20a is suppressed, the solder thickness of the first semiconductor chip 20 is maintained. Therefore, it is possible to prevent solder cracks and heat dissipation defects in the solder 20a.
  • the second chip region 12a2 includes a first side end portion facing the first chip region 12a1 with the first slit 14a interposed therebetween, and a second side end portion perpendicular to the first side end portion. Have. The second side end portion faces the terminal region 12a3 with the third slit 14c interposed therebetween. Further, the first chip region 12a1 has a third side end portion facing the second chip region 12a2 and a fourth side end portion perpendicular to the third side end portion. The fourth side end portion faces the terminal region 12a3 with the second slit 14b interposed therebetween.
  • the distance between the first and second semiconductor chips 20 and 21 may be shorter than the distance between the first semiconductor chip 20 and the contact component 30 and the distance between the second semiconductor chip 21 and the contact component 30. .. Further, the width of the first slit 14a may be narrower than the width of the second and third slits 14b and 14c.
  • the semiconductor device 50 is formed on a ceramic circuit board 10 including an insulating plate 11 and a conductive plate 12a provided on the front surface of the insulating plate 11 and a first chip region 12a1 on the front surface of the conductive plate 12a.
  • the first semiconductor chip 20 provided, the second semiconductor chip 21 provided in the second chip region 12a2 on the front surface of the conductive plate 12a, and the terminal region 12a3 on the front surface of the conductive plate 12a are provided. It has a contact component 30 and a contact component 30.
  • the conductive plate 12a includes a first slit 14a formed in the gap between the first chip region 12a1 and the second chip region 12a2, and a second slit 14b formed in the gap between the first chip region 12a1 and the terminal region 12a3.
  • a third slit 14c formed in the gap between the second chip region 12a2 and the terminal region 12a3 is provided.
  • the first slit 14a is a continuous line penetrating the conductive plate 12a, and the second and third slits 14b and 14c are non-penetrating continuous lines of the conductive plate 12a.
  • the spread of the molten solder 20a, 21a, 30a can be limited by the first, second, and third slits 14a, 14b, and 14c. Therefore, it is possible to prevent different types of solders 20a, 21a, and 30a from being mixed with each other.
  • the first slit 14a is formed in the conductive plate 12a by a continuous line penetrating the first slit 14a. Therefore, the first and second semiconductor chips 20 and 21 can be arranged close to each other by preventing the positions of the first and second semiconductor chips 20 and 21 from being displaced.
  • the second and third slits 14b and 14c are formed in the conductive plate 12a by continuous lines that do not penetrate (non-penetrate) the conductive plate 12a.
  • the current from the contact component 30 can be reliably passed to the main electrode on the back surface of the first semiconductor chip 20 along the broken line arrow in FIG. Further, the current output from the back surface of the second semiconductor chip 21 can be reliably passed through the contact component 30 along the broken line arrow in FIGS. 3 and 5.
  • the first and second semiconductor chips 20 and 21 can be brought close to each other by the first slit 14a of the continuous line penetrating.
  • the second and third slits 14b and 14c of the non-penetrating continuous line do not obstruct the current paths of the first and second semiconductor chips 20 and 21 with respect to the contact component 30, while realizing low inductance wiring.
  • the spread of the solders 20a, 21a, and 30a can be limited. As a result, it is possible to prevent a decrease in reliability while enhancing the electrical characteristics of the semiconductor device 50.
  • FIG. 6 is a plan view of a main part of the conductive plate of the ceramic circuit board included in the semiconductor device of the second embodiment.
  • the same configurations as those in the first embodiment are designated by the same reference numerals, and the description thereof will be simplified or omitted.
  • the first chip region 12a1 is adjacent to the second chip region 12a2 at a position shifted downward in FIG. 6 from the second chip region 12a2 with respect to the second chip region 12a2. Is set. Further, the lower side portion of the first chip region 12a1 in FIG. 6 is close to the end portion of the conductive plate 12a.
  • the first slit 14a is formed in the gap between the first chip region 12a1 and the second chip region 12a2.
  • the first slit 14a is formed corresponding to the length of the side portion of the second chip region 12a2 facing the first chip region 12a1.
  • the first and second semiconductor chips 20 and 21 are provided in the first and second chip regions 12a1 and 12a2, respectively. In FIG. 6, the positions of the first and second chip regions 12a1 and 12a2 may be opposite.
  • the terminal region 12a3 is set in a region surrounded by a side portion of the conductive plate 12a that is displaced from the second chip region 12a2 of the first chip region 12a1 and a lower side portion of the second chip region 12a2 in FIG. There is.
  • a lead frame 41 which is a wiring terminal, is formed in the terminal region 12a3.
  • the lead frame 41 is joined to the conductive plate 12a via the solder 40a.
  • the solder 40a is configured in the same manner as the solder 30a of the first embodiment.
  • the second and third slits 14b and 14c are formed along the side portions of the second and first chip regions 12a2 and 12a1 facing the terminal region 12a3, respectively.
  • the first slit 14a is a continuous line penetrating the conductive plate 12a
  • the second and third slits 14b, 14c are non-penetrating continuous lines of the conductive plate 12a.
  • the second chip region 12a2 has a first side end portion that faces the first chip region 12a1 with the first slit 14a interposed therebetween, and a second side end portion that is perpendicular to the first side end portion.
  • the second side end portion faces the terminal region 12a3 with the third slit 14c interposed therebetween.
  • the first chip region 12a1 has a third side end portion that faces the second chip region 12a2 with the first slit 14a interposed therebetween and faces the terminal region 12a3 with the second slit 14b interposed therebetween.
  • the distance between the first and second semiconductor chips 20 and 21 may be shorter than the distance between the first semiconductor chip 20 and the contact component 30 and the distance between the second semiconductor chip 21 and the contact component 30.
  • the width of the first slit 14a may be narrower than the width of the second and third slits 14b and 14c.
  • the first, second, and third slits 14a, 14b, and 14c are formed, the spread of the molten solder 20a, 21a, and 40a can be limited. Therefore, it is possible to prevent different types of solders 20a, 21a, and 40a from being mixed with each other.
  • the first slit 14a is formed in the conductive plate 12a by a continuous line penetrating the first slit 14a. Therefore, it is possible to prevent misalignment between the first and second semiconductor chips 20 and 21 and arrange them in close proximity to each other.
  • the second and third slits 14b and 14c are formed in the conductive plate 12a by continuous lines that do not penetrate (non-penetrate) the conductive plate 12a. Therefore, the current from the lead frame 41 can be reliably passed to the main electrode on the back surface of the first semiconductor chip 20 along the broken line arrow in FIG. Further, the current output from the back surface of the second semiconductor chip 21 can be reliably passed through the lead frame 41 along the broken line arrow in FIG. In this way, the first and second semiconductor chips 20 and 21 can be brought close to each other by the first slit 14a of the continuous line penetrating.
  • the second and third slits 14b and 14c of the non-penetrating continuous wire do not obstruct the current paths of the first and second semiconductor chips 20 and 21 with respect to the lead frame 41, and realize low inductance wiring.
  • the spread of the solder 20a, 21a, 40a can be limited. As a result, it is possible to prevent a decrease in reliability while enhancing the electrical characteristics of the semiconductor device 50.
  • FIG. 7 is a plan view of a main part of the conductive plate of the ceramic circuit board included in the semiconductor device of the third embodiment.
  • the first chip regions 12a1 and 12a4 are set adjacent to each other with an interval.
  • the first semiconductor chip 23 is also provided in the first chip region 12a4 via the solder 23a.
  • the first semiconductor chip 23 is a switching element similar to the first semiconductor chip 20.
  • the solder 23a has the same composition as the solder 20a.
  • a first slit 14a is formed in the gap between the first chip regions 12a1 and 12a4. The length of the first slit 14a corresponds to the width of the first semiconductor chips 20 and 23.
  • the terminal region 12a3 is set to face the lower side portion in FIG. 7 of the first chip regions 12a1 and 12a4 with respect to the conductive plate 12a.
  • the lead frame 41 is also joined to the terminal region 12a3.
  • the lead frame 41 is joined to the conductive plate 12a via the solder 40a.
  • the second slits 14b and 14d are formed along the side portions of the first chip regions 12a1 and 12a4 facing the terminal regions 12a3, respectively.
  • the second slit 14d is formed continuously and non-penetratingly with respect to the conductive plate 12a, similarly to the second slit 14b.
  • the second slits 14b and 14d are formed in gaps where the side portions of the first chip regions 12a1 and 12a4 overlap with the terminal regions 12a3, respectively.
  • the first slit 14a is a continuous line penetrating the conductive plate 12a
  • the second and third slits 14b, 14c are non-penetrating continuous lines of the conductive plate 12a.
  • the two first chip regions 12a1 and 12a4 face each other with the first slit 14a in between.
  • the side ends perpendicular to the opposite side ends of the two first chip regions 12a1 and 12a4 face the terminal regions 12a3 with the second slits 14b and 14d, respectively.
  • the second slits 14b and 14d may be continuously formed.
  • the distance between the two first semiconductor chips 20 and 23 may be shorter than the distance between the respective first semiconductor chips 20 and 23 and the contact component 30.
  • the width of the first slit 14a may be narrower than the width of the second slits 14b and 14d.
  • the first slit 14a and the second slits 14b, 14d are formed, the spread of the molten solder 20a, 23a, 40a can be restricted. Therefore, it is possible to prevent different types of solders 20a, 23a, and 40a from being mixed with each other.
  • the first slit 14a is formed in the conductive plate 12a by a continuous line penetrating the first slit 14a. Therefore, it is possible to prevent misalignment between the first semiconductor chips 20 and 23 and arrange them in close proximity to each other.
  • the second slits 14b and 14d are formed in the conductive plate 12a by continuous lines that do not penetrate (non-penetrate) the conductive plate 12a.
  • the current from the lead frame 41 can be reliably passed to the main electrodes on the back surfaces of the first semiconductor chips 20 and 23 along the broken line arrow in FIG. 7.
  • the first semiconductor chips 20 and 23 can be brought close to each other by the first slit 14a of the continuous line penetrating.
  • the second slits 14b and 14d of the non-penetrating continuous wire do not obstruct the current path of the first semiconductor chips 20 and 23 with respect to the lead frame 41, and the solders 20a, 23a and 40a are realized while realizing the wiring with low inductance. Can limit the spread of. As a result, it is possible to prevent a decrease in reliability while enhancing the electrical characteristics of the semiconductor device 50.
  • FIG. 8 is a plan view of a main part of the conductive plate of the ceramic circuit board included in the semiconductor device of the fourth embodiment.
  • FIG. 9 is a cross-sectional view of a main part of the conductive plate of the ceramic circuit board included in the semiconductor device of the fourth embodiment. Note that FIG. 9 shows a cross-sectional view taken along the alternate long and short dash line YY of FIG.
  • the conductive plate 12a shown in FIG. 8 has the second and third slits 14b1 formed in a broken line shape in place of the second and third slits 14b and 14c continuously formed in the conductive plate 12a of FIG. Each of 14c1 is formed.
  • the second slit 14b1 partially penetrates the gap between the first chip region 12a1 and the terminal region 12a3 of the conductive plate 12a and is formed in a broken line shape. Therefore, the first chip region 12a1 and the terminal region 12a3 are not completely separated by the second slit 14b1. Since the second slit 14b1 includes the penetrated portion, the spread of the molten solders 20a and 30a can be limited.
  • the current from the contact component 30 can be passed through the non-penetrating portion of the conductive plate 12a of the second slit 14b1 to the main electrode on the back surface of the first semiconductor chip 20 along the broken line arrow in FIG.
  • the third slit 14c1 is also formed in a broken line shape by partially penetrating the gap between the second chip region 12a2 and the terminal region 12a3 of the conductive plate 12a, similarly to the second slit 14b1. Therefore, the second chip region 12a2 and the terminal region 12a3 are not completely separated by the third slit 14c1. Since the third slit 14c1 also includes the penetrated portion, the spread of the molten solders 21a and 30a can be limited. Further, a current from the back surface of the second semiconductor chip 21 can be passed through the contact component 30 along the broken line arrow in FIG. 8 through the non-penetrating portion of the conductive plate 12a of the third slit 14c1.
  • the first, second, and third slits 14a, 14b1, 14c1 are formed, the spread of the molten solder 20a, 21a, 30a can be limited. Therefore, it is possible to prevent different types of solders 20a, 21a, and 30a from being mixed with each other.
  • the first slit 14a is formed in the conductive plate 12a by a continuous line penetrating the first slit 14a. Therefore, it is possible to prevent misalignment between the first and second semiconductor chips 20 and 21 and arrange them in close proximity to each other.
  • the second and third slits 14b1 and 14c1 are partially penetrated and formed in the conductive plate 12a in a broken line shape.
  • the current from the contact component 30 can be reliably passed to the main electrode on the back surface of the first semiconductor chip 20 along the broken line arrow in FIG. Further, the current output from the back surface of the second semiconductor chip 21 can be reliably passed through the contact component 30 along the broken line arrow in FIG. In this way, the first and second semiconductor chips 20 and 21 can be brought close to each other by the first slit 14a of the continuous line penetrating. Further, the second and third slits 14b1 and 14c1 of the non-penetrating continuous line do not obstruct the current paths of the first and second semiconductor chips 20 and 21 with respect to the contact component 30, and realize low inductance wiring. The spread of the solders 20a, 21a, and 30a can be limited. As a result, it is possible to prevent a decrease in reliability while enhancing the electrical characteristics of the semiconductor device 50.
  • Ceramic circuit board 11 Insulation plate 12, 12a Conductive plate 12a1, 12a4 1st chip area 12a2 2nd chip area 12a3 Terminal area 13 Metal plate 14a 1st slit 14b, 14b1, 14d 2nd slit 14c, 14c1 3rd slit 15 Bonding Wires 20, 23 1st semiconductor chip 21 2nd semiconductor chip 20a, 21a, 23a, 30a, 40a Solder 24 Electronic component 30 Contact component 40 External connection pin 41 Lead frame 45 Encapsulating member 50 Semiconductor device

Abstract

溶融したはんだの広がりを制御しつつインダクタンスの変化を防止できる。　導電板（１２ａ）は、第１チップ領域（１２ａ１）と第２チップ領域（１２ａ２）との間隙に形成された第１スリット（１４ａ）と、第１チップ領域（１２ａ１）と端子領域（１２ａ３）との間隙に形成された第２スリット（１４ｂ）と、第２チップ領域（１２ａ２）と端子領域（１２ａ３）との間隙に形成された第３スリット（１４ｃ）とを備える。そして、第１スリット（１４ａ）は、導電板（１２ａ）を貫通した連続線であり、第２，第３スリット（１４ｂ，１４ｃ）は、導電板（１２ａ）の非貫通の連続線である。

Description

半導体装置
　本発明は、半導体装置に関する。
　半導体装置は、パワーデバイスを含み、電力変換装置として利用されている。パワーデバイスは、例えば、ＩＧＢＴ（Insulated Gate Bipolar Transistor）、パワーＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）の半導体チップを含む。このような半導体装置は、少なくとも、半導体チップと配線端子とセラミック回路基板とを含んでいる。セラミック回路基板は、半導体チップ及び配線端子が配置されている。セラミック回路基板は、絶縁板と当該絶縁板上に設けられた導電板とを含んでいる。導電板上には半導体チップ及び配線端子がはんだにより接合される。
　このように導電板に半導体チップ及び配線端子を接合する際に、溶融したはんだが広がってしまう。このようなはんだに半導体チップ及び配線端子を配置すると、半導体チップ及び配線端子が所定の接合領域から位置ずれしてしまう場合がある。そこで、導電板には当該接合領域の周りにスリットが形成される。このようなスリットにより、半導体チップ及び配線端子をはんだにより接合する際に、溶融したはんだの広がりを制御することができる。また、スリットは、半導体チップ及び配線端子を導電板に配置する際の位置合わせとしても用いられる。
特開２００３－１００９８３号公報
　しかしながら、導電板に形成されたスリットのために、導電板の電流経路におけるインダクタンスが変化してしまうおそれがある。このため、半導体装置の電気的特性が影響を受けて、信頼性が低下してしまう。
　本発明は、このような点に鑑みてなされたものであり、溶融したはんだの広がりを制御しつつインダクタンスの変化を防止できる半導体装置を提供することを目的とする。
　本発明の一観点によれば、絶縁板と前記絶縁板のおもて面に設けられた導電板とを含む基板と、前記導電板のおもて面の第１チップ領域に設けられた第１半導体チップと、前記導電板のおもて面の第２チップ領域に設けられた第２半導体チップと、前記導電板のおもて面の端子領域に設けられた配線端子と、を有し、前記導電板は、前記第１チップ領域と前記第２チップ領域との間隙に形成された第１スリットと、前記第１チップ領域と前記端子領域との間隙に形成された第２スリットと、前記第１チップ領域と前記端子領域との間隙に形成された第３スリットとを備え、前記第１スリットは、前記導電板を貫通した連続線であり、前記第２スリット及び前記第３スリットは、前記導電板の非貫通の連続線、または、前記導電板を部分的に貫通した破線のいずれかである半導体装置が提供される。
　開示の技術によれば、溶融したはんだの広がりを制御しつつインダクタンスの変化を防止でき、信頼性の低下が抑制された半導体装置を提供することができる。
　本発明の上記及び他の目的、特徴及び利点は本発明の例として好ましい実施の形態を表す添付の図面と関連した以下の説明により明らかになるであろう。
第１の実施の形態の半導体装置の側面図である。 第１の実施の形態の半導体装置の平面図である。 第１の実施の形態の半導体装置に含まれるセラミック回路基板の導電板の要部の平面図である。 第１の実施の形態の半導体装置に含まれるセラミック回路基板の要部の断面図（その１）である。 第１の実施の形態の半導体装置に含まれるセラミック回路基板の要部の断面図（その２）である。 第２の実施の形態の半導体装置に含まれるセラミック回路基板の導電板の要部の平面図である。 第３の実施の形態の半導体装置に含まれるセラミック回路基板の導電板の要部の平面図である。 第４の実施の形態の半導体装置に含まれるセラミック回路基板の導電板の要部の平面図である。 第４の実施の形態の半導体装置に含まれるセラミック回路基板の導電板の要部の断面図である。
　以下、図面を参照して、実施の形態について説明する。なお、以下の説明において、「おもて面」及び「上面」とは、図１の半導体装置５０において、上側を向いた面を表す。同様に、「上」とは、図１の半導体装置５０において、上側の方向を表す。「裏面」及び「下面」とは、図１の半導体装置５０において、下側を向いた面を表す。同様に、「下」とは、図１の半導体装置５０において、下側の方向を表す。必要に応じて他の図面でも同様の方向性を意味する。「おもて面」、「上面」、「上」、「裏面」、「下面」、「下」、「側面」は、相対的な位置関係を特定する便宜的な表現に過ぎず、本発明の技術的思想を限定するものではない。例えば、「上」及び「下」は、必ずしも地面に対する鉛直方向を意味しない。つまり、「上」及び「下」の方向は、重力方向に限定されない。
　［第１の実施の形態］
　第１の実施の形態の半導体装置について図１及び図２を用いて説明する。図１は、第１の実施の形態の半導体装置の側面図であり、図２は、第１の実施の形態の半導体装置の平面図である。なお、図１は、封止部材４５については破線で表している。図２では、封止部材４５の図示を省略している。また、半導体装置５０は、ケースの記載を省略している。なお、ケースは、セラミック回路基板１０、第１，第２半導体チップ２０，２１等を収納する。また、第１の実施の形態では、複数の導電板１２、第１，第２半導体チップ２０，２１、複数のコンタクト部品３０、複数のボンディングワイヤ１５、複数の外部接続ピン４０に対して、それぞれ区別することなく、同じ符号を付して説明する。なお、これら以外の構成についても、複数あるものはそれぞれ区別することなく、同じ符号を付して同じ符号で説明する。
　半導体装置５０は、図１及び図２に示されるように、セラミック回路基板１０（基板）とセラミック回路基板１０のおもて面に接合された第１，第２半導体チップ２０，２１とを有している。半導体装置５０は、セラミック回路基板１０のおもて面に接合されたコンタクト部品３０（配線端子）を有している。第１，第２半導体チップ２０，２１及びコンタクト部品３０は、セラミック回路基板１０のおもて面に接合材（図示を省略）を介して接合されている。接合材は、例えば、はんだである。はんだの詳細については後述する。また、半導体装置５０は、セラミック回路基板１０のおもて面と第１，第２半導体チップ２０，２１の主電極とを電気的に接続するボンディングワイヤ１５を有している。また、コンタクト部品３０には外部接続ピン４０が圧入されて取り付けられている。さらに、半導体装置５０は、セラミック回路基板１０のおもて面の第１，第２半導体チップ２０，２１と共に、コンタクト部品３０に取り付けられた外部接続ピン４０の先端部が突出するように封止部材４５により封止されている。
　セラミック回路基板１０は、基板の一例である。このようなセラミック回路基板１０は、平面視で矩形状である。セラミック回路基板１０は、絶縁板１１と絶縁板１１の裏面に設けられた金属板１３と絶縁板１１のおもて面に設けられた複数の導電板１２（導電板１２ａを含む。以下同様）とを含んでいる。絶縁板１１及び金属板１３は、平面視で矩形状である。また、角部がＲ形状や、Ｃ形状に面取りされていてもよい。金属板１３のサイズは、平面視で、絶縁板１１のサイズより小さく、絶縁板１１の内側に形成されている。絶縁板１１は、熱伝導性のよいセラミックスにより構成されている。このようなセラミックスは、例えば、酸化アルミニウム、窒化アルミニウム、窒化珪素である。また、絶縁板１１の厚さは、０．５ｍｍ以上、２．０ｍｍ以下である。金属板１３は、熱伝導性に優れた金属により構成されている。このような金属は、例えば、アルミニウム、鉄、銀、銅、または、少なくともこれらの一種を含む合金である。また、金属板１３の厚さは、０．１ｍｍ以上、２．０ｍｍ以下である。金属板１３の表面に対して、耐食性を向上させるために、めっき処理を行ってもよい。この際、用いられるめっき材は、例えば、ニッケル、ニッケル－リン合金、ニッケル－ボロン合金である。
　複数の導電板１２は、導電性に優れた金属により構成されている。このような金属は、例えば、銀、銅、ニッケル、または、少なくともこれらの一種を含む合金である。また、複数の導電板１２の厚さは、０．５ｍｍ以上、１．５ｍｍ以下である。複数の導電板１２の表面に対して、耐食性を向上させるために、めっき処理を行ってもよい。この際、用いられるめっき材は、例えば、ニッケル、ニッケル－リン合金、ニッケル－ボロン合金である。絶縁板１１に対して複数の導電板１２は、絶縁板１１のおもて面に金属層を形成し、この金属層に対してエッチング等の処理を行って得られる。または、あらかじめ金属層から切り出した複数の導電板１２を絶縁板１１のおもて面に圧着させてもよい。なお、図１及び図２に示す複数の導電板１２は一例である。必要に応じて、導電板１２の個数、形状、大きさ等を適宜選択できる。また、導電板１２ａの図２中破線領域内には、複数のスリットが形成されている。これらのスリットの詳細については後述する。
　このようなセラミック回路基板１０として、例えば、ＤＣＢ（Direct Copper Bonding）基板、ＡＭＢ（Active Metal Brazed）基板を用いることができる。なお、基板の別の例として、例えば、金属ベース基板を用いることができる。金属ベース基板は、樹脂からなる絶縁層と絶縁層の裏面に設けられた金属板１３と絶縁板１１のおもて面に設けられた複数の導電板１２とを含んでいる。また、封止部材４５により封止されて構成される半導体装置５０は、セラミック回路基板１０の金属板１３の裏面が表出されている。
　第１半導体チップ２０は、シリコンまたは炭化シリコンにより構成されたスイッチング素子である。スイッチング素子は、例えば、ＩＧＢＴ、パワーＭＯＳＦＥＴである。第１半導体チップ２０がＩＧＢＴである場合には、裏面に主電極としてコレクタ電極を、おもて面に、制御電極としてゲート電極及び主電極としてエミッタ電極をそれぞれ備えている。第１半導体チップ２０がパワーＭＯＳＦＥＴである場合には、裏面に主電極としてドレイン電極を、おもて面に、制御電極としてゲート電極及び主電極としてソース電極をそれぞれ備えている。また、第２半導体チップ２１は、シリコンまたは炭化シリコンにより構成されたダイオード素子である。ダイオード素子は、例えば、ＳＢＤ（Schottky Barrier Diode）、ＰｉＮ（Ｐ-intrinsic-Ｎ）ダイオード等のＦＷＤ（Free Wheeling Diode）である。このような第２半導体チップ２１は、裏面に主電極としてカソード電極を、おもて面に主電極としてアノード電極をそれぞれ備えている。第１，第２半導体チップ２０，２１は、その裏面側が所定の導電板１２上に接合材（図示を省略）により接合されている。接合材は、例えば、はんだである。接合材の詳細については後述する。また、第１，第２半導体チップ２０，２１の厚さは、例えば、１８０μｍ以上、２２０μｍ以下であって、平均は、２００μｍ程度である。なお、導電板１２には、電子部品２４を配置することもできる。電子部品２４は、例えば、サーミスタ、電流センサである。
　ボンディングワイヤ１５は、第１，第２半導体チップ２０，２１と、導電板１２との間、または、複数の第１，第２半導体チップ２０，２１間を適宜電気的に接続する。このようなボンディングワイヤ１５は、導電性に優れた材質により構成されている。当該材質として、例えば、金、銀、銅、アルミニウム、または、少なくともこれらの一種を含む合金により構成されている。また、ボンディングワイヤ１５の径は、例えば、１００μｍ以上、５００μｍ以下である。
　コンタクト部品３０は、配線端子の一例である。このようなコンタクト部品３０は、本体部とフランジとを備えている。本体部は、内部に円筒状の貫通孔が形成されている。フランジは、本体部の開口端部に設けられている。コンタクト部品３０の本体部の貫通孔には、外部接続ピン４０が圧入される。外部接続ピン４０は、棒状の本体部と本体部の両端部にそれぞれ形成された、テーパ状の先端部とを有している。本体部は、角柱状を成す。外部接続ピン４０の断面の対角線の長さは、コンタクト部品３０の本体部の径よりも数％長い。コンタクト部品３０及び外部接続ピン４０は、導電性に優れた金属により構成されている。このような金属は、例えば、銀、銅、ニッケル、または、少なくともこれらの一種を含む合金である。コンタクト部品３０や外部接続ピン４０の表面に対して、耐食性を向上させるために、めっき処理を行ってもよい。この際、用いられるめっき材は、例えば、ニッケル、ニッケル－リン合金、ニッケル－ボロン合金である。
　配線端子は、少なくとも一端が導電板１２と接合部材を介して接合されていればよい。配線端子の別の例として、リードフレーム、バスバー及び外部接続端子がある。リードフレームは、第１，第２半導体チップ２０，２１と導電板１２との間を電気的に接続する。バスバーは、複数の導電板１２間を電気的に接続する。外部接続端子は、導電板１２と外部機器とを電気的に接続する。このようなリードフレーム、バスバー及び外部接続端子は、導電性に優れた金属により構成されている。このような金属は、例えば、銀、銅、ニッケル、または、少なくともこれらの一種を含む合金である。コンタクト部品３０や外部接続ピン４０の表面に対して、耐食性を向上させるために、めっき処理を行ってもよい。この際、用いられるめっき材は、例えば、ニッケル、ニッケル－リン合金、ニッケル－ボロン合金である。
　封止部材４５は、熱硬化性樹脂とフィラーとして熱硬化性樹脂に含有される充填剤とを含んでいる。熱硬化性樹脂は、例えば、エポキシ樹脂、フェノール樹脂、マレイミド樹脂である。充填剤は、例えば、二酸化シリコン、酸化アルミニウム、窒化ホウ素または窒化アルミニウムである。
　次に、セラミック回路基板１０の導電板１２ａの図２中の破線領域の詳細について、図３～図５を用いて説明する。図３は、第１の実施の形態の半導体装置に含まれるセラミック回路基板の導電板の要部の平面図である。図４及び図５は、第１の実施の形態の半導体装置に含まれるセラミック回路基板の要部の断面図である。なお、図４は、図３の一点鎖線Ｙ－Ｙにおける断面図、図５は、図３の一点鎖線Ｘ－Ｘにおける断面図をそれぞれ表している。
　図３によれば、第１半導体チップ２０は、導電板１２ａのおもて面の第１チップ領域１２ａ１にはんだ２０ａを介して設けられている。第２半導体チップ２１は、導電板１２ａのおもて面の第２チップ領域１２ａ２にはんだ２１ａを介して設けられている。コンタクト部品３０は、導電板１２ａのおもて面の端子領域１２ａ３にはんだ３０ａを介して設けられている。さらに、外部接続ピン４０は、コンタクト部品３０に圧入されている。はんだ２０ａ，２１ａ，３０ａは、鉛フリーはんだを基体として構成されている。鉛フリーはんだは、例えば、錫及び銀からなる合金、錫及びアンチモンからなる合金、錫及び亜鉛からなる合金、錫及び銅からなる合金のうち少なくともいずれかの合金を主成分とする。また、はんだ２０ａ，２１ａ，３０ａには、添加物が含まれてもよい。添加物は、例えば、銅、ビスマス、インジウム、ニッケル、ゲルマニウム、コバルトまたはシリコンである。また、第１，第２半導体チップ２０，２１を接合するはんだ２０ａ，２１ａとコンタクト部品３０を接合するはんだ３０ａとは、はんだ組成が異なっている。第１，第２半導体チップ２０，２１を接合するはんだ２０ａ，２１ａは、ボイドが発生しにくく、高温耐性を有する。例えば、はんだ２０ａ，２１ａは、錫及びアンチモンを主成分とする合金である。コンタクト部品３０等の配線端子を接合するはんだ３０ａは、はんだ２０ａ，２１ａよりも低弾性率を有する。はんだ３０ａは、例えば、錫及び銀を主成分とする合金である。なお、図３では、溶融したはんだ２０ａ，２１ａ，３０ａが広がって固化されている状態を示している。また、第１，第２半導体チップ２０，２１を接合するはんだ２０ａ，２１ａは、コンタクト部品３０を接合するはんだ３０ａより、薄くてよい。はんだ２０ａ，２１ａの厚さは、０．０５ｍｍ以上、０．２５ｍｍ以下である。はんだ３０ａの厚さは、０．１０ｍｍ以上、０．５０ｍｍ以下である。はんだ３０ａがはんだ２０ａ，２１ａよりも弾性率が低いために、はんだ３０ａの厚さをはんだ２０ａ，２１ａより厚くすることができる。このため、半導体装置１０の稼働時の半導体チップ２０，２１の発熱を良好に放熱することができる。さらに、はんだ３０ａにおけるクラック並びに剥離等の発生を抑止でき、半導体装置１０の破損を防止できる。
　また、第１チップ領域１２ａ１と第２チップ領域１２ａ２とは、導電板１２ａに対して少なくとも互いの側部の一部が対向して隣り合って設定されている。また、端子領域１２ａ３は、導電板１２ａに対して第１チップ領域１２ａ１の側部及び第２チップ領域１２ａ２の側部と対向して隣り合って設定されている。さらに、端子領域１２ａ３は、導電板１２ａに対して第１チップ領域１２ａ１及び第２チップ領域１２ａ２の配列方向（図３中上下方向）に対して垂直方向（図３中左右方向）に隣接して設定されている。コンタクト部品３０は、当該端子領域１２ａ３内のいずれかに配置されればよく、図３の配置位置は一例である。
　導電板１２ａには、第１，第２，第３スリット１４ａ，１４ｂ，１４ｃがそれぞれ形成されている。第１スリット１４ａは、第１チップ領域１２ａ１と第２チップ領域１２ａ２との間隙に形成されている。第１スリット１４ａは、図３，４に示されるように、導電板１２ａを貫通した連続線である。この際の第１スリット１４ａの幅は、はんだ２０ａ，２１ａの厚さよりも大きく、第１チップ領域１２ａ１と第２チップ領域１２ａ２との間隙の幅以下でよい。なお、第１，第２半導体チップ２０，２１は、それらの導電板１２ａのおもて面からの高さが略等しい。また、第１スリット１４ａの長さは、少なくとも、第１チップ領域１２ａ１と第２チップ領域１２ａ２とが対向して重複する側部に対応する長さ以上であることが好ましい。また、第１スリット１４ａの長さは、好ましくは、第１チップ領域１２ａ１及び第２チップ領域１２ａ２の対向するいずれかの側部に対応する長さ以下である。こうすることで、溶融したはんだ２０ａ，２１ａの端部は、第１スリット１４ａの対向するそれぞれの端辺に接して、分離される。そのため、第１，第２チップ領域１２ａ１，１２ａ２間で溶融したはんだ２０ａ，２１ａの移動が防止され、第１，第２半導体チップ２０，２１が所定の接合領域から位置ずれしてしまうのを防止できる。
　第２スリット１４ｂは、第１チップ領域１２ａ１と端子領域１２ａ３との間隙に形成されている。第３スリット１４ｃは、第２チップ領域１２ａ２と端子領域１２ａ３との間隙に形成されている。第３スリット１４ｃは、図３，５に示されるように、導電板１２ａの非貫通の連続線である。なお、第２スリット１４ｂの断面図は省略するものの、図５に示す第３スリット１４ｃと同様に導電板１２ａの非貫通の連続線である。すなわち、第２，第３スリット１４ｂ，１４ｃの深さは、導電板１２ａの厚さ未満である。また、はんだ３０ａの厚さははんだ２１ａ（並びにはんだ２０ａ）の厚さよりも厚い。この際の第２，第３スリット１４ｂ，１４ｃの幅は、はんだ２０ａ，２１ａの厚さよりも大きく、第１チップ領域１２ａ１と端子領域１２ａ３との間隙の幅、及び、第２チップ領域１２ａ２と端子領域１２ａ３との間隙の幅以下でよい。第２，第３スリット１４ｂ，１４ｃの長さは、少なくとも、端子領域１２ａ３と第１，第２チップ領域１２ａ１，１２ａ２とが対向して重複する側部に対応する長さ以上であることが好ましい。また、第１チップ領域１２ａ１の端子領域１２ａ３側の側部、及び、第２チップ領域１２ａ２の端子領域１２ａ３側の側部に対応する長さ以下であることが好ましい。また、図３では、第２，第３スリット１４ｂ，１４ｃは、第１，第２チップ領域１２ａ１，１２ａ２の側部にそれぞれ形成されている。第２，第３スリット１４ｂ，１４ｃは、その途中が接続されて連続したスリットであってもよい。このような第１，第２，第３スリット１４ａ，１４ｂ，１４ｃは、例えば、エッチング、レーザ加工により形成箇所に応じて所定の深さに形成される。こうすることで、溶融したはんだ２０ａ，３０ａは、第２スリット１４ｂの対向する端辺で塞き止められて、分離される。そのため、第１チップ領域１２ａ１と端子領域１２ａ３との間で溶融したはんだ２０ａ，３０ａの移動が防止され、第１半導体チップ２０、及び、コンタクト部品３０が所定の接合領域から位置ずれしてしまうのを防止できる。また、はんだ２０ａの流出が抑制されるため、第１半導体チップ２０のはんだ厚さが維持される。このため、はんだ２０ａにおけるはんだクラックや放熱不良が発生することも防止できる。
　さらに、上記から、第２チップ領域１２ａ２は、第１チップ領域１２ａ１に対して第１スリット１４ａを挟んで対向する第１側端部と、第１側端部と垂直な第２側端部とを有する。そして、当該第２側端部は端子領域１２ａ３に対して第３スリット１４ｃを挟んで対向している。また、第１チップ領域１２ａ１は、第２チップ領域１２ａ２に対向する第３側端部と当該第３側端部に垂直な第４側端部とを有する。そして、当該第４側端部は端子領域１２ａ３に対して第２スリット１４ｂを挟んで対向している。この際、第１，第２半導体チップ２０，２１間の間隔は、第１半導体チップ２０とコンタクト部品３０との間隔及び、第２半導体チップ２１とコンタクト部品３０との間隔よりも、短くてよい。また、第１スリット１４ａの幅は、第２，第３スリット１４ｂ，１４ｃの幅よりも、狭くてよい。
　上記の半導体装置５０は、絶縁板１１と絶縁板１１のおもて面に設けられた導電板１２ａとを含むセラミック回路基板１０と、導電板１２ａのおもて面の第１チップ領域１２ａ１に設けられた第１半導体チップ２０と、導電板１２ａのおもて面の第２チップ領域１２ａ２に設けられた第２半導体チップ２１と、導電板１２ａのおもて面の端子領域１２ａ３に設けられたコンタクト部品３０と、を有する。導電板１２ａは、第１チップ領域１２ａ１と第２チップ領域１２ａ２との間隙に形成された第１スリット１４ａと、第１チップ領域１２ａ１と端子領域１２ａ３との間隙に形成された第２スリット１４ｂと、第２チップ領域１２ａ２と端子領域１２ａ３との間隙に形成された第３スリット１４ｃとを備える。そして、第１スリット１４ａは、導電板１２ａを貫通した連続線であり、第２，第３スリット１４ｂ，１４ｃは、導電板１２ａの非貫通の連続線である。
　この第１，第２，第３スリット１４ａ，１４ｂ，１４ｃにより、溶融したはんだ２０ａ，２１ａ，３０ａの広がりを制限できる。このため、種類の異なるはんだ２０ａ，２１ａ，３０ａが混ざり合うことを防止できる。また、第１スリット１４ａは、貫通した連続線により、導電板１２ａに形成されている。このため、第１，第２半導体チップ２０，２１の位置ずれを防止して、近接して配置できる。さらに、第２，第３スリット１４ｂ，１４ｃは、導電板１２ａを貫通しない（非貫通の）連続線により、導電板１２ａに形成されている。このため、図３中の破線矢印に沿ってコンタクト部品３０からの電流を第１半導体チップ２０の裏面の主電極に確実に流すことができる。また、図３及び図５中の破線矢印に沿って第２半導体チップ２１の裏面から出力される電流をコンタクト部品３０に確実に流すことができる。このように、貫通した連続線の第１スリット１４ａにより第１，第２半導体チップ２０，２１を近接させることができる。さらに、非貫通の連続線の第２，第３スリット１４ｂ，１４ｃによりコンタクト部品３０に対する第１，第２半導体チップ２０，２１の電流経路が妨げられることなく、低インダクタンスの配線を実現しつつ、はんだ２０ａ，２１ａ，３０ａの広がりを制限できる。これらにより、半導体装置５０の電気的特性を高めつつ、信頼性の低下を防止することができる。
　［第２の実施の形態］
　第２の実施の形態では、第１，第２チップ領域１２ａ１，１２ａ２及び端子領域１２ａ３の配置位置、形状が第１の実施の形態とは異なる場合について、図６を用いて説明する。図６は、第２の実施の形態の半導体装置に含まれるセラミック回路基板の導電板の要部の平面図である。なお、第２の実施の形態では、第１の実施の形態と同じ構成には同じ符号を付して、それらの説明については簡略、または、省略する。
　図６に示す導電板１２ａでは、第１チップ領域１２ａ１は、第２チップ領域１２ａ２に対して、第２チップ領域１２ａ２よりも図６中下方にずれた位置で、第２チップ領域１２ａ２に隣接して設定されている。さらに、第１チップ領域１２ａ１の図６中下方の側部は、導電板１２ａの端部に接近している。第１スリット１４ａが第１チップ領域１２ａ１と第２チップ領域１２ａ２との間隙に形成されている。第１スリット１４ａは、第２チップ領域１２ａ２の第１チップ領域１２ａ１に対向する側部の長さに対応して形成されている。第１，第２チップ領域１２ａ１，１２ａ２には、第１，第２半導体チップ２０，２１がそれぞれ設けられている。なお、図６において、第１，第２チップ領域１２ａ１，１２ａ２の位置は反対であってもよい。
　端子領域１２ａ３は、導電板１２ａにおいて第１チップ領域１２ａ１の第２チップ領域１２ａ２から位置ずれした側部と第２チップ領域１２ａ２の図６中下方の側部とで囲まれた領域に設定されている。この端子領域１２ａ３には、配線端子であるリードフレーム４１が形成されている。リードフレーム４１は、はんだ４０ａを介して導電板１２ａに接合されている。なお、はんだ４０ａは、第１の実施の形態のはんだ３０ａと同様に構成されている。そして、端子領域１２ａ３に対向する第２，第１チップ領域１２ａ２，１２ａ１の側部に沿って、第２，第３スリット１４ｂ，１４ｃがそれぞれ形成されている。第１スリット１４ａは、導電板１２ａを貫通した連続線であり、第２，第３スリット１４ｂ，１４ｃは、導電板１２ａの非貫通の連続線である。
　第２チップ領域１２ａ２は、第１チップ領域１２ａ１に対して第１スリット１４ａを挟んで対向する第１側端部と、第１側端部と垂直な第２側端部とを有する。そして、当該第２側端部は端子領域１２ａ３に対して第３スリット１４ｃを挟んで対向している。また、第１チップ領域１２ａ１は、第２チップ領域１２ａ２に対して第１スリット１４ａを挟んで対向し、端子領域１２ａ３に対して第２スリット１４ｂを挟んで対向する第３側端部を有する。この際、第１，第２半導体チップ２０，２１間の間隔は、第１半導体チップ２０とコンタクト部品３０との間隔及び第２半導体チップ２１とコンタクト部品３０との間隔よりも、短くてよい。また、第１スリット１４ａの幅は、第２，第３スリット１４ｂ，１４ｃの幅よりも、狭くてよい。
　このような導電板１２ａでも、第１，第２，第３スリット１４ａ，１４ｂ，１４ｃが形成されているため、溶融したはんだ２０ａ，２１ａ，４０ａの広がりを制限できる。このため、種類の異なるはんだ２０ａ，２１ａ，４０ａが混ざり合うことを防止できる。また、第１スリット１４ａは、貫通した連続線により、導電板１２ａに形成されている。このため、第１，第２半導体チップ２０，２１間での位置ずれを防止して、近接して配置することができる。さらに、第２，第３スリット１４ｂ，１４ｃは、導電板１２ａを貫通しない（非貫通の）連続線により、導電板１２ａに形成されている。このため、図６中の破線矢印に沿ってリードフレーム４１からの電流を第１半導体チップ２０の裏面の主電極に確実に流すことができる。また、図６の破線矢印に沿って第２半導体チップ２１の裏面から出力される電流をリードフレーム４１に確実に流すことができる。このように、貫通した連続線の第１スリット１４ａにより第１，第２半導体チップ２０，２１を近接させることができる。さらに、非貫通の連続線の第２，第３スリット１４ｂ，１４ｃによりリードフレーム４１に対する第１，第２半導体チップ２０，２１の電流経路が妨げられることなく、低インダクタンスの配線を実現しつつ、はんだ２０ａ，２１ａ，４０ａの広がりを制限できる。これらにより、半導体装置５０の電気的特性を高めつつ、信頼性の低下を防止することができる。
　［第３の実施の形態］
　第３の実施の形態では、第１チップ領域１２ａ１，１２ａ４及び端子領域１２ａ３の配置位置、形状が第１，第２の実施の形態とは異なる場合について、図７を用いて説明する。図７は、第３の実施の形態の半導体装置に含まれるセラミック回路基板の導電板の要部の平面図である。
　図７に示す導電板１２ａでは、第１チップ領域１２ａ１，１２ａ４は、間隔を空けて隣接して設定されている。なお、第１チップ領域１２ａ４にも第１半導体チップ２３がはんだ２３ａを介して設けられる。第１半導体チップ２３は、第１半導体チップ２０と同様のスイッチング素子である。はんだ２３ａは、はんだ２０ａと同様の組成を成している。また、第１チップ領域１２ａ１，１２ａ４の間隙には、第１スリット１４ａが形成されている。第１スリット１４ａの長さは、第１半導体チップ２０，２３の幅に対応している。
　端子領域１２ａ３は、導電板１２ａに対して、第１チップ領域１２ａ１，１２ａ４の図７中下方の側部と対向して設定されている。この端子領域１２ａ３にも、リードフレーム４１が接合される。リードフレーム４１は、はんだ４０ａを介して導電板１２ａに接合されている。そして、端子領域１２ａ３に対向する第１チップ領域１２ａ１，１２ａ４の側部に沿って、第２スリット１４ｂ，１４ｄがそれぞれ形成されている。なお、第２スリット１４ｄは、第２スリット１４ｂと同様に、導電板１２ａに対して非貫通で連続的に形成されている。また、第２スリット１４ｂ，１４ｄは、第１チップ領域１２ａ１，１２ａ４の側部が端子領域１２ａ３に重複する間隙にそれぞれ形成されている。第１スリット１４ａは、導電板１２ａを貫通した連続線であり、第２，第３スリット１４ｂ，１４ｃは、導電板１２ａの非貫通の連続線である。
　２つの第１チップ領域１２ａ１，１２ａ４は、第１スリット１４ａを挟んで対向している。そして、２つの第１チップ領域１２ａ１，１２ａ４の対向する側端部と垂直な側端部は、それぞれ端子領域１２ａ３に対して第２スリット１４ｂ，１４ｄを挟んで対向している。第２スリット１４ｂ，１４ｄは、連続的に形成されていてもよい。この際、２つの第１半導体チップ２０，２３間の間隔は、それぞれの第１半導体チップ２０，２３とコンタクト部品３０との間隔よりも、短くてよい。また、第１スリット１４ａの幅は、第２スリット１４ｂ，１４ｄの幅よりも、狭くてよい。
　このような導電板１２ａでも、第１スリット１４ａ及び第２スリット１４ｂ，１４ｄが形成されているため、溶融したはんだ２０ａ，２３ａ，４０ａの広がりを制限できる。このため、種類の異なるはんだ２０ａ，２３ａ，４０ａが混ざり合うことを防止できる。また、第１スリット１４ａは、貫通した連続線により、導電板１２ａに形成されている。このため、第１半導体チップ２０，２３間での位置ずれを防止して、近接して配置することができる。さらに、第２スリット１４ｂ，１４ｄは、導電板１２ａを貫通しない（非貫通の）連続線により、導電板１２ａに形成されている。このため、図７中の破線矢印に沿ってリードフレーム４１からの電流を第１半導体チップ２０，２３の裏面の主電極に確実に流すことができる。このように、貫通した連続線の第１スリット１４ａにより第１半導体チップ２０，２３を近接させることができる。さらに、非貫通の連続線の第２スリット１４ｂ，１４ｄによりリードフレーム４１に対する第１半導体チップ２０，２３の電流経路が妨げられることなく、低インダクタンスの配線を実現しつつ、はんだ２０ａ，２３ａ，４０ａの広がりを制限できる。これらにより、半導体装置５０の電気的特性を高めつつ、信頼性の低下を防止することができる。
　［第４の実施の形態］
　第４の実施の形態では、第１の実施の形態の導電板１２ａにおいて第２，第３スリット１４ｂ，１４ｃが破線を成して構成されている場合について、図８及び図９を用いて説明する。図８は、第４の実施の形態の半導体装置に含まれるセラミック回路基板の導電板の要部の平面図である。図９は、第４の実施の形態の半導体装置に含まれるセラミック回路基板の導電板の要部の断面図である。なお、図９は、図８の一点鎖線Ｙ－Ｙにおける断面図を表している。
　図８に示す導電板１２ａには、図３の導電板１２ａに連続的に形成された第２，第３スリット１４ｂ，１４ｃに代わって、破線状に形成された第２，第３スリット１４ｂ１，１４ｃ１がそれぞれ形成されている。この第２スリット１４ｂ１は、図８に示されるように、導電板１２ａの第１チップ領域１２ａ１と端子領域１２ａ３との間隙を部分的に貫通して破線状に形成されている。このため、第１チップ領域１２ａ１と端子領域１２ａ３とは第２スリット１４ｂ１で完全に分断されていない。第２スリット１４ｂ１は、貫通された部分を含んでいるために、溶融したはんだ２０ａ，３０ａの広がりを制限できる。さらに、第２スリット１４ｂ１の導電板１２ａの貫通されていない部分を通じて、コンタクト部品３０からの電流を図８中の破線矢印に沿って第１半導体チップ２０の裏面の主電極に流すことができる。また、第３スリット１４ｃ１も、第２スリット１４ｂ１と同様に、導電板１２ａの第２チップ領域１２ａ２と端子領域１２ａ３との間隙を部分的に貫通して破線状に形成されている。このため、第２チップ領域１２ａ２と端子領域１２ａ３とは第３スリット１４ｃ１で完全に分断されていない。第３スリット１４ｃ１もまた、貫通された部分を含んでいるために、溶融したはんだ２１ａ，３０ａの広がりを制限できる。さらに、第３スリット１４ｃ１の導電板１２ａの貫通されていない部分を通じて、第２半導体チップ２１の裏面からの電流を図８中の破線矢印に沿ってコンタクト部品３０に流すことができる。
　このような導電板１２ａでも、第１，第２，第３スリット１４ａ，１４ｂ１，１４ｃ１が形成されているため、溶融したはんだ２０ａ，２１ａ，３０ａの広がりを制限できる。このため、種類の異なるはんだ２０ａ，２１ａ，３０ａが混ざり合うことを防止できる。また、第１スリット１４ａは、貫通した連続線により、導電板１２ａに形成されている。このため、第１，第２半導体チップ２０，２１間での位置ずれを防止して、近接して配置することができる。さらに、第２，第３スリット１４ｂ１，１４ｃ１は、部分的に貫通して破線状に、導電板１２ａに形成されている。このため、図８中の破線矢印に沿ってコンタクト部品３０からの電流を第１半導体チップ２０の裏面の主電極に確実に流すことができる。また、図８の破線矢印に沿って第２半導体チップ２１の裏面から出力される電流をコンタクト部品３０に確実に流すことができる。このように、貫通した連続線の第１スリット１４ａにより第１，第２半導体チップ２０，２１を近接させることができる。さらに、非貫通の連続線の第２，第３スリット１４ｂ１，１４ｃ１によりコンタクト部品３０に対する第１，第２半導体チップ２０，２１の電流経路が妨げられることなく、低インダクタンスの配線を実現しつつ、はんだ２０ａ，２１ａ，３０ａの広がりを制限できる。これらにより、半導体装置５０の電気的特性を高めつつ、信頼性の低下を防止することができる。
　上記については単に本発明の原理を示すものである。さらに、多数の変形、変更が当業者にとって可能であり、本発明は上記に示し、説明した正確な構成及び応用例に限定されるものではなく、対応するすべての変形例及び均等物は、添付の請求項及びその均等物による本発明の範囲とみなされる。
　１０　セラミック回路基板
　１１　絶縁板
　１２，１２ａ　導電板
　１２ａ１，１２ａ４　第１チップ領域
　１２ａ２　第２チップ領域
　１２ａ３　端子領域
　１３　金属板
　１４ａ　第１スリット
　１４ｂ，１４ｂ１，１４ｄ　第２スリット
　１４ｃ，１４ｃ１　第３スリット
　１５　ボンディングワイヤ
　２０，２３　第１半導体チップ
　２１　第２半導体チップ
　２０ａ，２１ａ，２３ａ，３０ａ，４０ａ　はんだ
　２４　電子部品
　３０　コンタクト部品
　４０　外部接続ピン
　４１　リードフレーム
　４５　封止部材
　５０　半導体装置

Claims (14)

  1. 　絶縁板と前記絶縁板のおもて面に設けられた導電板とを含む基板と、
    　前記導電板のおもて面の第１チップ領域に設けられた第１半導体チップと、
    　前記導電板のおもて面の第２チップ領域に設けられた第２半導体チップと、
    　前記導電板のおもて面の端子領域に設けられた配線端子と、
    　を有し、
    　前記導電板は、前記第１チップ領域と前記第２チップ領域との間隙に形成された第１スリットと、前記第１チップ領域と前記端子領域との間隙に形成された第２スリットと、前記第１チップ領域と前記端子領域との間隙に形成された第３スリットとを備え、
    　前記第１スリットは、前記導電板を貫通した連続線であり、前記第２スリット及び前記第３スリットは、前記導電板の非貫通の連続線、または、前記導電板を部分的に貫通した破線のいずれかである半導体装置。
  2. 　前記第２スリット及び前記第３スリットの深さは、前記導電板の厚さ未満である、
    　請求項１に記載の半導体装置。
  3. 　前記第２スリットは、前記導電板の前記第１半導体チップの前記端子領域側の側部に沿って形成されている、
    　請求項１に記載の半導体装置。
  4. 　前記第３スリットは、前記導電板の前記第２半導体チップの前記端子領域側の側部に沿って形成されている、
    　請求項１に記載の半導体装置。
  5. 　前記第２チップ領域は、前記第１チップ領域に対して前記第１スリットを挟んで対向する第１側端部と、前記第１側端部と垂直な第２側端部とを有し、
    　前記第２側端部は前記端子領域に対して前記第３スリットを挟んで対向している、
    　請求項１に記載の半導体装置。
  6. 　前記第１チップ領域は、前記第２チップ領域に対向する第３側端部を有し、
    　前記第３側端部は前記端子領域に対して前記第２スリットを挟んで対向している、
    　請求項５に記載の半導体装置。
  7. 　前記第１チップ領域は、前記第２チップ領域に対向する第３側端部と前記第３側端部に垂直な第４側端部とを有し、
    　前記第４側端部は前記端子領域に対して前記第２スリットを挟んで対向している、
    　請求項５に記載の半導体装置。
  8. 　前記第２スリットは、前記第１半導体チップの前記端子領域側の側部と略等しい長さで形成されている、
    　請求項３に記載の半導体装置。
  9. 　前記第３スリットは、前記第２半導体チップの前記端子領域側の側部と略等しい長さで形成されている、
    　請求項４に記載の半導体装置。
  10. 　前記第１半導体チップ及び前記第２半導体チップは前記導電板に第１接合材により固着され、
    　前記配線端子は前記導電板に前記第１接合材と異なる組成の第２接合材により固着されている、
    　請求項１に記載の半導体装置。
  11. 　前記第１接合材は、錫及びアンチモンを主成分とする合金からなるはんだであり、
    　前記第２接合材は、錫及び銀を主成分とする合金からなるはんだである、
    　請求項１０に記載の半導体装置。
  12. 　前記第１半導体チップ及び前記第２半導体チップは前記導電板に第１接合材により固着され、
    　前記配線端子は前記導電板に第２接合材により固着され、
    　前記第１接合材の厚さは前記第２接合材の厚さより薄い、
    　請求項１に記載の半導体装置。
  13. 　前記第１スリットの幅は、前記第１接合材の高さと略等しい、
    　請求項１０乃至１２のいずれかに記載の半導体装置。
  14. 　前記第１半導体チップは、スイッチング素子であり、
    　前記第２半導体チップは、ダイオード素子である、
    　請求項１乃至１３のいずれかに記載の半導体装置。
PCT/JP2020/044019 2020-01-07 2020-11-26 半導体装置 WO2021140771A1 (ja)

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CN113241325A (zh) * 2020-01-23 2021-08-10 富士电机株式会社 电子装置以及电子装置的制造方法

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