JPWO2021140771A1 - - Google Patents
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- Publication number
- JPWO2021140771A1 JPWO2021140771A1 JP2021569755A JP2021569755A JPWO2021140771A1 JP WO2021140771 A1 JPWO2021140771 A1 JP WO2021140771A1 JP 2021569755 A JP2021569755 A JP 2021569755A JP 2021569755 A JP2021569755 A JP 2021569755A JP WO2021140771 A1 JPWO2021140771 A1 JP WO2021140771A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
- H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
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JP2011054625A (ja) * | 2009-08-31 | 2011-03-17 | Sanyo Electric Co Ltd | 回路装置 |
JP2017011028A (ja) * | 2015-06-18 | 2017-01-12 | 株式会社デンソー | 半導体装置 |
WO2019181198A1 (ja) * | 2018-03-20 | 2019-09-26 | 富士電機株式会社 | 半導体装置 |
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JP2000031358A (ja) | 1998-07-08 | 2000-01-28 | Sansha Electric Mfg Co Ltd | 電力用半導体モジュール |
JP2003100983A (ja) | 2001-09-21 | 2003-04-04 | Kyocera Corp | セラミック回路基板 |
JP5954409B2 (ja) * | 2012-03-22 | 2016-07-20 | 富士電機株式会社 | 放熱フィン付き半導体モジュール |
JP2014093365A (ja) * | 2012-11-01 | 2014-05-19 | Toyota Industries Corp | 半導体装置 |
JP2014216459A (ja) | 2013-04-25 | 2014-11-17 | 三菱電機株式会社 | 半導体装置 |
WO2018105075A1 (ja) * | 2016-12-08 | 2018-06-14 | 三菱電機株式会社 | 半導体装置および電力変換装置 |
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JP2011054625A (ja) * | 2009-08-31 | 2011-03-17 | Sanyo Electric Co Ltd | 回路装置 |
JP2017011028A (ja) * | 2015-06-18 | 2017-01-12 | 株式会社デンソー | 半導体装置 |
WO2019181198A1 (ja) * | 2018-03-20 | 2019-09-26 | 富士電機株式会社 | 半導体装置 |
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