WO2021135101A1 - 谐振器及其形成方法 - Google Patents

谐振器及其形成方法 Download PDF

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Publication number
WO2021135101A1
WO2021135101A1 PCT/CN2020/098840 CN2020098840W WO2021135101A1 WO 2021135101 A1 WO2021135101 A1 WO 2021135101A1 CN 2020098840 W CN2020098840 W CN 2020098840W WO 2021135101 A1 WO2021135101 A1 WO 2021135101A1
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Prior art keywords
layer
substrate
forming
piezoelectric
laminate structure
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PCT/CN2020/098840
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English (en)
French (fr)
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杨国煌
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中芯集成电路（宁波）有限公司上海分公司
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Priority to JP2021504342A priority Critical patent/JP7255910B2/ja
Priority to US17/203,041 priority patent/US20210226600A1/en
Publication of WO2021135101A1 publication Critical patent/WO2021135101A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • H03H9/171—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator implemented with thin-film techniques, i.e. of the film bulk acoustic resonator [FBAR] type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02007—Details of bulk acoustic wave devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • H03H9/171—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator implemented with thin-film techniques, i.e. of the film bulk acoustic resonator [FBAR] type
    • H03H9/172—Means for mounting on a substrate, i.e. means constituting the material interface confining the waves to a volume
    • H03H9/173—Air-gaps
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/46—Filters
    • H03H9/54—Filters comprising resonators of piezoelectric or electrostrictive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/05—Manufacture of multilayered piezoelectric or electrostrictive devices, or parts thereof, e.g. by stacking piezoelectric bodies and electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
    • H10N30/073—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/08—Shaping or machining of piezoelectric or electrostrictive bodies
    • H10N30/085—Shaping or machining of piezoelectric or electrostrictive bodies by machining
    • H10N30/086—Shaping or machining of piezoelectric or electrostrictive bodies by machining by polishing or grinding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/704—Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive films or coatings
    • H10N30/706—Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive films or coatings characterised by the underlying bases, e.g. substrates
    • H10N30/708—Intermediate layers, e.g. barrier, adhesion or growth control buffer layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/87—Electrodes or interconnections, e.g. leads or terminals
    • H10N30/872—Interconnections, e.g. connection electrodes of multilayer piezoelectric or electrostrictive devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H2003/021—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks being of the air-gap type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H2003/023—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks being of the membrane type

Definitions

  • the embodiments of the present invention relate to the field of semiconductors, and in particular to a resonator and a method of forming the same.
  • the high-power filters in wireless base stations and other equipment are mainly cavity filters, whose power can reach hundreds of watts.
  • some devices use dielectric filters with an average power of more than 5 watts.
  • the sizes of these two filters are relatively large, and it is difficult to integrate them into the RF front-end chip.
  • FBAR film bulk acoustic resonator
  • the problem solved by the present invention is to provide a resonator and a method for forming the resonator to improve the performance of the resonator.
  • the present invention provides a method for forming a resonator, including: providing a first substrate; forming a piezoelectric stack structure on the first substrate, the piezoelectric stack structure including a working area, The surface of the piezoelectric laminate structure in contact with the first substrate is the first front surface; a sacrificial layer covering the piezoelectric laminate structure is formed on the working area; a second substrate is provided; An adhesive layer is formed on the second substrate, the surface of the adhesive layer in contact with the second substrate is the second front surface, and the surface of the adhesive layer opposite to the second front surface is the second surface.
  • the second back of the adhesive layer is attached to the sacrificial layer and the piezoelectric laminate structure exposed by the sacrificial layer, so that the adhesive layer covers the sidewalls of the sacrificial layer and fills the first
  • the first substrate is removed to expose the first front surface of the piezoelectric laminate structure; forming a penetrating piezoelectric laminate structure
  • a structural release hole, or a release hole penetrating the second substrate is formed, and the release hole exposes the sacrificial layer; the sacrificial layer is removed through the release hole to form a cavity.
  • the method for forming the resonator further includes: forming the piezoelectric laminate structure in the working area First groove.
  • the piezoelectric laminated structure includes a first electrode layer, a piezoelectric layer on the first electrode layer, and a second electrode layer on the piezoelectric layer, the first electrode layer and
  • the contact surface of the first substrate is the first front surface; in the step of forming the first trench, the bottom of the first trench exposes the first electrode layer; after the cavity is formed, The opening of the first groove communicates with the cavity.
  • the method for forming the resonator further includes: in the piezoelectric laminate structure of the working area A second trench is formed.
  • the piezoelectric laminated structure includes a first electrode layer, a piezoelectric layer on the first electrode layer, and a second electrode layer on the piezoelectric layer; forming the second groove In the step, the bottom of the second trench exposes the second electrode layer; after the cavity is formed, the second trench and the cavity are separated by the second electrode layer.
  • the process of forming the adhesive layer includes a spin coating process.
  • the material of the adhesive layer is a deformable material.
  • the material of the adhesive layer includes a dry film or an adhesive sheet film.
  • a bonding process is used to achieve the bonding.
  • the temperature of the bonding process is 50°C to 300°C.
  • the thickness of the adhesive layer is 0.5 ⁇ m to 40 ⁇ m.
  • the top surface of the sacrificial layer is Part of the thickness of the adhesive layer remains between the second substrates.
  • the adhesive layer is located on the top surface of the sacrificial layer and the second liner.
  • the thickness of the adhesive layer between the bottoms is 0.5 ⁇ m to 35 ⁇ m.
  • the step of removing the first substrate includes: performing a grinding process on the first substrate to remove a part of the thickness of the first substrate; after performing the grinding process on the first substrate, A wet etching process is used to remove the remaining first substrate.
  • the process of polishing the first substrate includes a chemical mechanical polishing process.
  • the method for forming the resonator further includes: forming a buffer layer on the first substrate; In the substrate step, the first substrate is removed by using the buffer layer as a stop layer; after the first substrate is removed, the method for forming the resonator further includes: removing the buffer layer.
  • the step of forming the sacrificial layer includes: forming a sacrificial material layer on the piezoelectric laminate structure; performing a planarization process on the sacrificial material layer; after performing a planarization process on the sacrificial material layer, The sacrificial material layer is patterned, and the sacrificial material layer in the working area is retained as the sacrificial layer.
  • the present invention also provides a resonator, including: a substrate; an adhesive layer located on the substrate; a piezoelectric laminate structure located on the adhesive layer, the piezoelectric laminate structure including Working area, the piezoelectric laminated structure located in the working area and the adhesive layer enclose a cavity, and the side wall of the cavity exposes the adhesive layer; the release of the piezoelectric laminated structure penetrates A hole, or, a release hole that penetrates the substrate, and the release hole communicates with the cavity.
  • the material of the adhesive layer is a deformable material.
  • the material of the adhesive layer includes a dry film or an adhesive sheet film.
  • the piezoelectric laminate structure includes a second electrode layer, a piezoelectric layer located on the second electrode layer, and a first electrode layer located on the piezoelectric layer.
  • the surface facing the second electrode layer is the first front surface, and the surface of the second electrode layer facing away from the first electrode layer is the first back surface; the cavity exposes the first surface of the second electrode layer. back.
  • the resonator further includes: a first trench located in the piezoelectric laminate structure, the opening of the first trench is in communication with the cavity, and the opening of the first trench is in communication with the cavity.
  • the first electrode layer is exposed at the bottom.
  • the resonator further includes: a second trench located in the piezoelectric laminate structure, the bottom of the second trench exposes the second electrode layer, and the second trench The cavity is separated from the cavity by the second electrode layer.
  • the technical solution of the present invention has the following advantages: in the method for forming a resonator provided by the embodiment of the present invention, after the piezoelectric laminated structure is formed on the first substrate, A sacrificial layer covering the piezoelectric laminate structure is formed on the area, and then the second back surface of the adhesive layer is attached to the sacrificial layer and the piezoelectric laminate structure exposed by the sacrificial layer, Make the adhesive layer cover the sidewall of the sacrificial layer and fill it between the second substrate and the piezoelectric laminate structure to achieve bonding, then remove the first substrate, and form the release hole and pass through the The sacrificial layer is removed from the release hole to form a cavity; in the embodiment of the present invention, when the piezoelectric laminate structure is formed, the sacrificial layer is not formed on the surface of the first substrate, and the flatness of the surface of the first substrate is Preferably, it is beneficial to provide a good interface for forming the piezoelectric
  • the thickness uniformity, lattice orientation uniformity, and film continuity of each film layer in the layer structure are correspondingly beneficial to improve the performance of the resonator.
  • the present invention also utilizes the plasticity of the adhesive layer to form a convex
  • the second substrate is attached to the structured first substrate to correspondingly realize the sealing of the sacrificial layer, thereby helping to improve the convenience and operability of forming the cavity, and also helping to save costs.
  • 1 to 13 are schematic diagrams of the structure corresponding to each step in an embodiment of the method for forming a resonator of the present invention.
  • FBAR film bulk acoustic resonator
  • the current preparation process of thin film bulk acoustic resonators is usually to form a groove in the substrate, form a sacrificial layer in the groove, and then sequentially form a piezoelectric laminate structure on the sacrificial layer, and in order to release the groove
  • the sacrificial layer usually needs to form a release hole penetrating the piezoelectric laminate structure, and the sacrificial material layer in the groove is removed by using the release hole to finally form a cavity.
  • the step of forming the sacrificial layer usually includes: forming a sacrificial material layer in the groove, and the sacrificial material layer is also formed on the substrate; grinding and removing the sacrificial material layer higher than the substrate, and the remaining sacrificial material in the groove The layer serves as the sacrificial layer.
  • the material of the sacrificial layer and the material of the substrate have different hardness and mechanical strength.
  • the sacrificial layer is a material that is easy to remove, and the material of the sacrificial layer is softer, which results in high removal during grinding.
  • the top of the sacrificial material layer is polished at a faster rate, and the height of the top of the sacrificial layer and the surface of the substrate is poor.
  • Steps are prone to appear between the surfaces, which leads to poor flatness and height consistency between the sacrificial layer and the substrate surface, which easily affects the film growth quality of the piezoelectric laminate structure, for example, affects the film layers in the piezoelectric laminate structure Consistency of crystal lattice orientation, thickness consistency, film continuity, etc., which can easily reduce the performance of the resonator.
  • the present invention provides a method for forming a resonator, including: providing a first substrate; forming a piezoelectric laminate structure on the first substrate, the piezoelectric laminate structure including working Area, the surface of the piezoelectric laminate structure in contact with the first substrate is a first front surface; a sacrificial layer covering the piezoelectric laminate structure is formed on the working area; a second substrate is provided; An adhesive layer is formed on the second substrate, the surface of the adhesive layer in contact with the second substrate is the second front surface, and the surface of the adhesive layer opposite to the second front surface is Second back; bonding the second back of the adhesive layer to the sacrificial layer and the piezoelectric laminate structure exposed by the sacrificial layer, so that the adhesive layer covers the sidewalls of the sacrificial layer and fills Between the second substrate and the piezoelectric laminate structure; after the bonding is achieved, the first substrate is removed to expose the first front surface of the piezoelectric laminate structure; A release
  • a sacrificial layer covering the piezoelectric laminate structure is formed on the working area, and then Then attach the second back surface of the adhesive layer to the sacrificial layer and the piezoelectric laminate structure exposed by the sacrificial layer, so that the adhesive layer covers the sidewalls of the sacrificial layer and fills the first
  • the two substrates and the piezoelectric laminated structure are bonded together, and then the first substrate is removed, the release hole is formed, and the sacrificial layer is removed through the release hole to form a cavity;
  • the surface of the first substrate is not formed with a sacrificial layer, and the surface of the first substrate has good flatness, which is beneficial for forming the pressure on the first substrate.
  • the electrical laminated structure provides a good interface, thereby improving the formation quality of each film layer in the piezoelectric laminated structure, for example, it is beneficial to improve the thickness uniformity and lattice orientation uniformity of each film layer in the piezoelectric laminated structure , Film continuity, etc., which is beneficial to improve the performance of the resonator.
  • the present invention also utilizes the plasticity of the adhesive layer to bond the second substrate on the first substrate with the convex structure, correspondingly The sealing of the sacrificial layer is realized, thereby helping to improve the convenience and operability of forming the cavity, and also helping to save costs.
  • 1 to 13 are schematic diagrams of the structure corresponding to each step in an embodiment of the method for forming a resonator of the present invention.
  • a first substrate 100 is provided.
  • the first substrate 100 provides a process platform for subsequent processes.
  • the first substrate 100 may be any suitable semiconductor substrate, such as a bulk silicon substrate, which may also be at least one of the following materials: SiGe, SiGe, Sic, SiGeC , TnAs, GaAs, Inp or other group III and group V compound semiconductors, including multilayer structures made of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon germanium-on-insulator (SiGe01), germanium-on-insulator (GeOI), or double-side polished wafers (DSP), or ceramic substrates such as alumina, Quartz or glass substrate, etc.
  • SOI silicon-on-insulator
  • SSOI silicon-on-insulator
  • SiGeOI silicon-germanium-on-insulator
  • SiGe01 silicon germanium-on-insulator
  • GeOI germanium-on-insulator
  • DSP double-side polished wafer
  • the subsequent step further includes forming a piezoelectric laminate structure on the first substrate 100.
  • the method for forming the resonator before forming the piezoelectric laminate structure on the first substrate 100, the method for forming the resonator further includes : A buffer layer 105 is formed on the first substrate 100.
  • the buffer layer 105 is used to improve the interface quality on the surface of the first substrate 100, and serves as a transition layer between the subsequent piezoelectric laminate structure and the first substrate 100, thereby improving the growth of the subsequent piezoelectric laminate structure Consistency, and adhesion between the first substrate 100 and the piezoelectric laminate structure.
  • the method for forming the resonator is also Including: removing the first substrate 100, the buffer layer 105 can also be used as a stop layer in the step of removing the first substrate 100, thereby reducing the difficulty of removing the first substrate 100, and is beneficial to Prevent the subsequent removal of the first substrate 100 from affecting the piezoelectric stack structure.
  • the material of the buffer layer 105 may be one or more of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the material of the buffer layer 105 is silicon oxide.
  • the buffer layer 105 is formed by a deposition process.
  • the deposition process may be a chemical vapor deposition process or an atomic layer deposition process or the like.
  • a piezoelectric stack structure 130 is formed on the first substrate 100, the piezoelectric stack structure 130 includes a working area 100s, and the piezoelectric stack structure 130 and the first substrate
  • the contact surface 100 is the first front surface 130a.
  • the piezoelectric laminated structure 130 is used to realize the mutual conversion between the electrical signal and the acoustic signal, so that the resonator can filter the signal.
  • the piezoelectric laminated structure 130 includes a working area 100s, the working area 100s includes an effective working area of a resonator for implementing a filtering function, and a cavity is subsequently formed in the working area 100s.
  • the piezoelectric laminated structure 130 includes a first electrode layer 110, a piezoelectric layer 115 on the first electrode layer 110, and a second electrode layer 120 on the piezoelectric layer 115,
  • the contact surface of the first electrode layer 110 and the first substrate 100 is the first front surface 130a.
  • the subsequent steps further include: forming a sacrificial layer covering the piezoelectric laminate structure 130 on the working area 100s.
  • the piezoelectric laminated structure 130 is first formed on the first substrate 100.
  • the first substrate 100 is not formed with The sacrificial layer, the surface of the first substrate 100 has good flatness, which is beneficial to provide a good interface for the formation of the piezoelectric laminate structure 130, thereby improving the first electrode layer 110 in the piezoelectric laminate structure 130.
  • the formation quality of the piezoelectric layer 115 and the second electrode layer 120 is beneficial to improve the thickness uniformity, lattice orientation uniformity, and film continuity of each film layer in the piezoelectric laminated structure 130, thereby helping to improve The performance of the resonator.
  • the first electrode layer 110 is used to form a bottom electrode (Bottom Electrode).
  • the material of the first electrode layer 110 is a conductive material or a semiconductor material.
  • the conductive material may be a metal material with conductive properties, for example: one or more of Al, Cu, Pt, Au, Ir, Os, Re, Pd, Rh, Ru, Mo, and W; the semiconductor material It can be Si, Ge, SiGe, SiC or SiGeC.
  • the first electrode layer 110 may be formed by a physical vapor deposition process.
  • the material of the piezoelectric layer 115 is a piezoelectric material.
  • the piezoelectric material has a piezoelectric effect, that is, the piezoelectric material is a crystalline material that generates a voltage between the two end faces when subjected to pressure.
  • the electric effect can realize the mutual conversion of mechanical vibration (sound wave) and alternating current, and then realize the conversion of sound energy and electric energy.
  • the material of the piezoelectric layer 115 may be a piezoelectric material having a wurtzite crystal structure, such as ZnO, AlN, GaN, aluminum zirconate titanate, or lead titanate.
  • the material of the piezoelectric layer 115 is AlN.
  • a deposition process such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process may be used to form the piezoelectric layer 115.
  • the second electrode layer 120 is used to form a top electrode.
  • the material of the second electrode layer 120 is a conductive material or a semiconductor material.
  • the conductive material may be a metal material with conductive properties, for example: one or more of Al, Cu, Pt, Au, Ir, Os, Re, Pd, Rh, Ru, Mo, and W; the semiconductor material It can be Si, Ge, SiGe, SiC or SiGeC.
  • the subsequent steps further include: forming a sacrificial layer on the piezoelectric laminated structure 130 in the working area 100s.
  • the method for forming the resonator further includes: The first trench 10 is formed in the piezoelectric laminated structure 130 in the working area 100s.
  • the first groove 10 is used to laterally reflect the sound wave, thereby helping to increase the residence time of the sound wave in the cavity, thereby reducing energy dissipation, and correspondingly helping to improve the acoustic-electric conversion performance of the resonator.
  • the first trench can also be used to define the edge of the active region of the resonator, that is, the edge of the region where the resonator selects effective resonance; the first trench and the second trench fabricated later together define the effective resonance area.
  • the bottom of the first trench 10 exposes the first electrode layer 110.
  • the method for forming the resonator further includes: The second electrode layer 120 is patterned to expose a part of the piezoelectric layer 115 in the working area 100s.
  • the second electrode layer 120 is patterned to form an upper electrode.
  • the edge of the effective resonance region can also be defined by the pattern of the upper electrode.
  • a dry etching process is used to pattern the second electrode layer 120.
  • the first trench 10 penetrates the piezoelectric layer 115 and the bottom of the first trench 10 exposes the first electrode layer 110 .
  • a sacrificial layer 140 covering the piezoelectric laminate structure 130 is formed on the working area 100s.
  • the sacrificial layer 140 is used to occupy a space for the subsequent formation of a cavity, that is, the sacrificial layer 140 is subsequently removed to form a cavity at the position of the sacrificial layer 140.
  • the material of the sacrificial layer 140 is a material that can be easily removed, and the subsequent process of removing the sacrificial layer 140 will have less influence on the piezoelectric laminate structure 130.
  • the material of the sacrificial layer 140 can ensure that The sacrificial layer 140 has good coverage, so as to completely cover the piezoelectric laminated structure 130 in the working area 100s.
  • the material of the sacrificial layer 140 includes PSG (phosphorus-doped silicon oxide), LTO (Li 2 TiO 3 , lithium titanate), BPSG (boron and phosphorus-doped silicon oxide), Ge, photoresist, polysilicon or amorphous Materials such as carbon.
  • the material of the sacrificial layer 140 is PSG.
  • the sacrificial layer 140 is also filled in the first trench 10.
  • the step of forming the sacrificial layer 140 includes.
  • a sacrificial material layer 125 is formed on the piezoelectric laminated structure 130.
  • the sacrificial material layer 125 is used to form a sacrificial layer.
  • the sacrificial material layer 125 is formed by a chemical vapor deposition (CVD) process.
  • the sacrificial material layer 125 is also filled in the first trench 10.
  • the sacrificial material layer 125 is planarized.
  • the sacrificial material layer 125 is planarized, so that the top surface of the sacrificial material layer 125 is planarized, thereby improving the flatness of the subsequent sacrificial layer surface.
  • CMP chemical mechanical polishing
  • the sacrificial material layer 125 is planarized, the sacrificial material layer 125 is patterned, and the sacrificial material layer in the working area 100s is retained as the sacrificial layer 140.
  • a dry etching process such as an anisotropic dry etching process, is used to pattern the sacrificial material layer 125.
  • a second substrate 200 is provided.
  • the subsequent steps further include: forming an adhesive layer on the second substrate 200; and attaching the adhesive layer to the sacrificial layer 140 and the piezoelectric laminate structure 130 exposed by the sacrificial layer 140.
  • the second substrate 200 is used to provide a process platform for the subsequent formation of the adhesive layer and the bonding of the adhesive layer and the sacrificial layer 140.
  • the second substrate 200 may be any suitable semiconductor substrate, such as a bulk silicon substrate, which may also be at least one of the following materials: SiGe, SiGe, Sic, SiGeC , TnAs, GaAs, Inp or other group III and group V compound semiconductors, including multilayer structures made of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), or silicon-germanium-on-insulator (S-SiGeOI), silicon germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), or double-side polished wafers (DSP), or ceramic substrates such as alumina, Quartz or glass substrate, etc.
  • SOI silicon-on-insulator
  • SSOI silicon-on-insulator
  • S-SiGeOI silicon-germanium-on-insulator
  • SiGeOI silicon germanium-on-insulator
  • GeOI germanium-on-insulator
  • DSP double
  • an adhesive layer 210 is formed on the second substrate 200, the surface of the adhesive layer 210 in contact with the second substrate 200 is the second front surface 201a, and the adhesive layer 210 The surface opposite to the second front surface 210a is the second back surface 210b.
  • the subsequent steps further include: attaching the second back surface 210b of the adhesive layer 210 to the sacrificial layer 140 and the piezoelectric laminate structure 130 exposed by the sacrificial layer 140, so that the adhesive layer 210 covers the The sidewall of the sacrificial layer 140 is filled between the second substrate 200 and the piezoelectric laminate structure 130, so that the sacrificial layer 140 is sealed by the adhesive layer 210, and then after the sacrificial layer 140 is subsequently removed, it can be A cavity is formed at the position of the sacrificial layer 140.
  • the adhesive layer 210 is a deformable material.
  • the material of the adhesive layer 210 may be an organic material with strong adhesion, so that the bonding can be achieved through the adhesive layer 210.
  • the adhesive layer 210 is a heat-deformable material, and the heat-deformable adhesive layer 210 becomes soft after being heated, so that the adhesive layer 210 has strong plasticity.
  • the adhesive layer 210 can be squeezed and deformed and filled Between the second substrate 200 and the piezoelectric stacked structure 130, so that the second substrate 200 can be attached to the first substrate 100 formed with the convex structure through the adhesive layer 210, and the sacrificial layer 140 can be aligned accordingly. Seal.
  • the material of the adhesive layer 210 is dry film.
  • Dry film is a viscous photoresist film used in semiconductor chip packaging or printed circuit board manufacturing.
  • the dry film photoresist is made of solvent-free photoresist. Coat the polyester film base, and then cover the polyethylene film; when using, remove the polyethylene film, press the solvent-free photoresist on the base plate, after exposure and development, the dry film can be photoetched Patterns are formed in the glue.
  • the material of the adhesive layer may also be other organic materials with strong viscosity such as die attach film (DAF).
  • DAF die attach film
  • the process of forming the adhesive layer 210 includes a spin coating process.
  • the subsequent steps further include: bonding the second back surface 210b of the adhesive layer 210 to the sacrificial layer 140 and the piezoelectric laminate structure 130 exposed by the sacrificial layer 140, and the adhesive
  • the adhesive layer 210 needs to be able to seal the sacrificial layer 140. Therefore, in the step of forming the adhesive layer 210, the thickness of the adhesive layer 210 needs to be determined according to the thickness of the sacrificial layer 140. In this embodiment, the thickness of the adhesive layer 210 needs to be greater than the thickness of the subsequent sacrificial layer 140.
  • the thickness of the adhesive layer 210 is 0.5 ⁇ m to 40 ⁇ m, such as 15 ⁇ m or 20 ⁇ m.
  • the second back surface 210b of the adhesive layer 210 is attached to the sacrificial layer 140 and the piezoelectric laminate structure 130 exposed by the sacrificial layer 140, so that the adhesive layer 210 covers the sacrificial layer.
  • the sidewall of the layer 140 is filled between the second substrate 200 and the piezoelectric laminated structure 130.
  • the adhesive layer 210 covers the top and sidewalls of the sacrificial layer 140, and on the piezoelectric laminate structure 130 exposed by the sacrificial layer 140 to achieve bonding, so that the adhesive layer 210 connects the sacrificial layer 140 seal.
  • a release hole exposing the sacrificial layer 140 is formed, and the sacrificial layer 140 is removed through the release hole, a cavity can be formed.
  • the second substrate 200 is attached to the first substrate 100 formed with the protruding structure, that is, the second substrate 200 is attached after the sacrificial layer is formed.
  • the second substrate 200 is attached to the first substrate 100 of 140, and the sacrificial layer 140 is sealed accordingly, which is beneficial to improve the convenience and operability of forming the cavity, and is also beneficial to cost saving.
  • a bonding process is adopted to realize the bonding.
  • the bonding is achieved by bonding, so that the process of sealing the sacrificial layer 140 is compatible with the existing bonding process, which is beneficial to improve process integration and process compatibility.
  • the adhesive layer 210 is made of a material that is softer and deformable when heated. During the bonding process, the second back surface 210b of the adhesive layer 210 is pressed to the The adhesive layer 210 is heated on the sacrificial layer 140, and the adhesive layer 210 becomes soft after being heated, so that the adhesive layer 210 fills the sidewalls of the sacrificial layer 140 and the piezoelectric laminated structure 130 In the space enclosed by the space, the top and sidewalls of the sacrificial layer 140 are further sealed.
  • the adhesive layer 210 in order to ensure that the adhesive layer 210 can be sufficiently soft, so that the adhesive layer 210 can attach the second substrate 200 to the first substrate 100 formed with the convex structure, and seal it.
  • the top and side walls of the sacrificial layer 140 need to be prevented from causing damage to the piezoelectric laminate structure 130 or other film structures due to excessive temperature, or from affecting the viscosity of the adhesive layer 210 due to excessive temperature.
  • the temperature of the bonding process is 50°C to 300°C.
  • the thickness of the adhesive layer 210 is relatively large.
  • the thickness of the adhesive layer 210 is greater than the thickness of the sacrificial layer 140 to be formed.
  • the top surface of the sacrificial layer 140 and the second A part of the thickness of the adhesive layer 210 remains between the two substrates 200, which helps prevent the problem that part of the adhesive layer 210 and the piezoelectric laminate structure 130 are not completely bonded, and is correspondingly helpful to prevent the occurrence of
  • a part of the thickness of the adhesive layer 210 remains between the top surface of the sacrificial layer 140 and the second substrate 200, which also helps reduce the difficulty of bonding.
  • the thickness of the adhesive layer 210 located between the top surface of the sacrificial layer 140 and the second substrate 200 is 0.5 ⁇ m to 35 ⁇ m, for example, 15 ⁇ m.
  • a part of the thickness of the adhesive layer may not remain between the top surface of the sacrificial layer and the second substrate, that is, The top surface of the sacrificial layer is in direct contact with the second substrate. Accordingly, the adhesive layer is filled between the second substrate and the piezoelectric laminate structure, so as to pass through the second substrate And the adhesive layer seals the top surface and sidewalls of the sacrificial layer.
  • the first substrate 100 is removed, and the first front surface 130a of the piezoelectric laminated structure 130 is exposed.
  • the first substrate 100 is removed to expose the first front surface 130a of the piezoelectric stacked structure 130, which is prepared for subsequent processes.
  • the first front surface 130a of the piezoelectric laminate structure 130 is exposed, and preparations are also made for the subsequent formation of a release hole penetrating the piezoelectric laminate structure 130.
  • the step of removing the first substrate 100 includes: grinding the first substrate 100 to remove a part of the thickness of the first substrate 100; After the grinding process, a wet etching process is used to remove the remaining first substrate 100.
  • the thickness of the first substrate 100 is realized, thereby reducing the difficulty of the subsequent wet etching process.
  • a chemical mechanical polishing process is used to perform polishing processing on the first substrate 100.
  • the etching solution of the wet etching process includes TMAH (tetramethylammonium hydroxide) solution and the like.
  • the buffer layer 105 is used as a stop layer to remove the first substrate 100, which is beneficial to reduce the removal of the first substrate 100. It is difficult and helps to prevent the process of removing the first substrate 100 from damaging the piezoelectric stacked structure 130.
  • the method for forming the resonator further includes: removing the buffer layer 105.
  • a wet etching process is used to remove the buffer layer 105.
  • the wet etching process is performed by using a hydrofluoric acid solution.
  • the method for forming the resonator further includes: patterning the first electrode layer 110 After processing, a part of the piezoelectric layer 115 in the working area 100s is exposed.
  • the first electrode layer 110 is patterned to form a bottom electrode.
  • a dry etching process is used to pattern the first electrode layer 110.
  • the method for forming the resonator further includes: A second trench 20 is formed in the piezoelectric laminated structure 130 in the effective working area 100s.
  • the second groove 20 is used to laterally reflect the sound wave, thereby increasing the residence time of the sound wave in the cavity, thereby reducing energy dissipation, and correspondingly beneficial to improving the acoustic-electric conversion performance of the resonator.
  • the second trench can also be used to define the edge of the active region of the resonator, that is, the edge of the region where the resonator selects effective resonance; the second trench and the first trench jointly enclose the effective resonance region.
  • the first surface 130a of the piezoelectric laminate structure 130 is exposed after the first substrate 100 is removed, it is easy to form the second trench 20 in the piezoelectric laminate structure 130, thereby further improving The performance of the resonator.
  • the second electrode layer 120 is exposed at the bottom of the second trench 20.
  • the piezoelectric layer 115 is also patterned to define an effective working area.
  • a release hole 30 is formed through the piezoelectric laminate structure 130, or a release hole 30 is formed through the second substrate 200, and the release hole 30 exposes the sacrificial layer 140.
  • the release hole 30 exposes the sacrificial layer 140, so that the sacrificial layer 140 can be removed later through the release hole 30.
  • the number of the release holes 30 is multiple, so as to improve the subsequent removal efficiency of the sacrificial layer 140 through the release holes 30.
  • the release hole 30 penetrates the piezoelectric laminate structure 130.
  • the release hole may also penetrate the second substrate.
  • the release hole may penetrate the second substrate. Bottom and the adhesive layer to expose the sacrificial layer.
  • a dry etching process is used to etch the piezoelectric laminate structure 130 to form the release hole 30.
  • the sacrificial layer 140 is removed through the release hole 30 to form a cavity 40.
  • the piezoelectric laminated structure 130 is in contact with the air, so that sound waves are reflected at the interface between the cavity 40 and the piezoelectric laminated structure 130, so that the resonator can vibrate normally during operation.
  • the resonator can work normally; moreover, the piezoelectric laminated structure 130 is in contact with the air, which can effectively reflect the leakage wave of the resonator from the interface between the air and the piezoelectric laminated structure 130 back to the surface of the substrate, thereby Improve the conversion efficiency of electrical and mechanical energy, that is, increase the quality factor (Q value).
  • a wet etching process is used to remove the sacrificial layer 140.
  • the etching solution of the wet etching process includes BOE (Buffered Oxide Etch) solution or HF solution.
  • BOE Borered Oxide Etch
  • the BOE solution is made by mixing hydrofluoric acid and water, or ammonium fluoride and water.
  • the opening of the first groove 10 communicates with the cavity 40, so that the first groove 10 can reflect the sound waves laterally, thereby reducing The dissipation of energy improves the acoustic-electric conversion capability of the resonator.
  • the second trench 20 and the cavity 40 are separated by the second electrode layer 120.
  • the second groove 20 can also have a lateral reflection effect on sound waves, and correspondingly improve the acoustic-electric conversion capability of the resonator.
  • the present invention also provides a resonator.
  • FIG. 13 there is shown a schematic structural diagram of an embodiment of the resonator of the present invention.
  • the resonator includes: a substrate 200; an adhesive layer 210 located on the substrate 200; a piezoelectric laminate structure 130 located on the adhesive layer 210, the piezoelectric laminate structure 130 including a working area 100s, the piezoelectric laminated structure 130 located in the working area 100s and the adhesive layer 210 enclose a cavity 40, and the sidewall of the cavity 40 exposes the adhesive layer 210; The release hole 30 of the laminated structure 130 or the release hole 30 passing through the substrate 200 is communicated with the cavity 40.
  • the substrate 200 is a second substrate 200.
  • the resonator provided by the embodiment of the present invention further includes an adhesive layer 210 located on the second substrate 200; the piezoelectric laminated structure 130 is also located on the adhesive layer 210, and is located in the effective working area 100s.
  • the piezoelectric laminated structure 130 and the adhesive layer 210 enclose a cavity 40.
  • the cavity 40 is not located in the second substrate 200.
  • the formation of the cavity 40 usually includes first forming a sacrificial layer and then removing the sacrificial layer through a release hole 30. Step, the cavity 40 is surrounded by the piezoelectric laminate structure 130 and the adhesive layer 210.
  • the piezoelectric laminate structure 130 Since the piezoelectric laminate structure 130 is formed first, then a sacrificial layer is formed on the piezoelectric laminate structure 130, and then the adhesive layer 210 is attached. Is combined on the sacrificial layer to form a release hole 30 and then the sacrificial layer is removed through the release hole 30.
  • the piezoelectric laminated structure 130 can be directly formed on another substrate, thereby providing a good effect for the formation of the piezoelectric laminated structure 130.
  • the interface and the flat surface are further conducive to improving the film quality of the piezoelectric laminated structure 130, for example: the thickness uniformity of each film layer in the piezoelectric laminated structure 130, the uniformity of crystal lattice orientation, and the continuity of the film, etc. In turn, the performance of the resonator is improved.
  • the second substrate 200 is used to provide a process platform for the process. Specifically, the second substrate 200 is used to provide a process platform for the formation of the adhesive layer 210 and the bonding of the adhesive layer 210 and the piezoelectric laminated structure 130.
  • the second substrate 200 may be any suitable semiconductor substrate, such as a bulk silicon substrate, which may also be at least one of the following materials: SiGe, SiGe, Sic, SiGeC , TnAs, GaAs, Inp or other group III and group V compound semiconductors, including multilayer structures made of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), or silicon-germanium-on-insulator (S-SiGeOI), silicon germanium-on-insulator (SiGe01), germanium-on-insulator (GeOI), or double-side polished silicon wafers (DSP), or ceramic substrates such as alumina, Quartz or glass substrate, etc.
  • SOI silicon-on-insulator
  • SSOI silicon-on-insulator
  • SiGeOI silicon-germanium-on-insulator
  • SiGe01 silicon germanium-on-insulator
  • GeOI germanium-on-insulator
  • DSP double-side polished
  • the adhesive layer 210 is used to seal the sacrificial layer, so that the cavity 40 can be formed after the sacrificial layer is removed by the release hole 30.
  • the material of the adhesive layer 210 is a deformable material.
  • the material of the adhesive layer 210 may be an organic material with strong adhesion, so that the bonding can be achieved through the adhesive layer 210.
  • the adhesive layer 210 is a heat-deformable material, and the heat-deformable adhesive layer 210 becomes soft after being heated, so that the adhesive layer 210 has strong plasticity.
  • the adhesive layer 210 can be squeezed It is deformed and filled between the second substrate 200 and the piezoelectric laminate structure 130, so that the second substrate 200 can be attached to the first substrate formed with the convex structure through the adhesive layer 210, and the alignment is achieved accordingly.
  • the sacrificial layer is sealed, and the cavity 40 can be formed after the sacrificial layer is removed.
  • the material of the adhesive layer 210 is dry film.
  • Dry film is a viscous photoresist film used in semiconductor chip packaging or printed circuit board manufacturing.
  • the dry film photoresist is made of solvent-free photoresist. Coat the polyester film base, and then cover the polyethylene film; when using, remove the polyethylene film, press the solvent-free photoresist on the base plate, after exposure and development, the dry film can be photoetched Patterns are formed in the glue.
  • the material of the adhesive layer may also be other organic materials with strong viscosity such as die attach film (DAF).
  • DAF die attach film
  • the thickness of the adhesive layer 210 remains between the bottom of the cavity 40 and the second substrate 200, that is, the bottom of the cavity 40 also exposes the adhesive layer 210. This is beneficial to ensure that during the process of forming the cavity 40, the adhesive layer 210 can seal the top and sidewalls of the sacrificial layer.
  • the thickness of the adhesive layer 210 located between the bottom of the cavity 40 and the second substrate 200 is 0.5 ⁇ m to 35 ⁇ m, for example, 15 ⁇ m.
  • the piezoelectric laminated structure 130 is used to realize the mutual conversion between the electrical signal and the acoustic signal, so that the resonator can filter the signal.
  • the piezoelectric laminate structure 130 includes a working area 100s, and the working area 100s includes an effective working area for a resonator to implement a filtering function.
  • the piezoelectric laminated structure 130 includes a second electrode layer 120, a piezoelectric layer 115 on the second electrode layer 120, and a first electrode layer 115 on the piezoelectric layer 115.
  • the first electrode The surface of the layer facing away from the second electrode layer is the first front surface, and the surface of the second electrode layer facing away from the first electrode layer is the first back surface; the cavity 40 exposes the second electrode layer The first back of 120.
  • the second electrode layer 120 is a top electrode (Top Electrode).
  • the material of the second electrode layer 120 is a conductive material or a semiconductor material.
  • the conductive material may be a metal material with conductive properties, for example: one or more of Al, Cu, Pt, Au, Ir, Os, Re, Pd, Rh, Ru, Mo, and W; the semiconductor material It can be Si, Ge, SiGe, SiC or SiGeC.
  • the material of the piezoelectric layer 115 is a piezoelectric material.
  • the piezoelectric material has a piezoelectric effect, that is, the piezoelectric material is a crystalline material that generates a voltage between the two end faces when subjected to pressure.
  • the electric effect can realize the mutual conversion of mechanical vibration (sound wave) and alternating current, and then realize the conversion of sound energy and electric energy.
  • the material of the piezoelectric layer 115 may be a piezoelectric material having a wurtzite crystal structure, such as ZnO, AlN, GaN, aluminum zirconate titanate, or lead titanate.
  • the material of the piezoelectric layer 115 is AlN.
  • the first electrode layer 110 is a bottom electrode (Bottom Electrode).
  • the material of the first electrode layer 110 is a conductive material or a semiconductor material.
  • the conductive material may be a metal material with conductive properties, for example: one or more of Al, Cu, Pt, Au, Ir, Os, Re, Pd, Rh, Ru, Mo, and W; the semiconductor material It can be Si, Ge, SiGe, SiC or SiGeC.
  • the piezoelectric laminated structure 130 is in contact with the air, so that sound waves are reflected at the interface between the cavity 40 and the piezoelectric laminated structure 130, so that the resonator can vibrate normally during operation.
  • the resonator can work normally; moreover, the piezoelectric laminated structure 130 is in contact with the air, which can effectively reflect the leakage wave of the resonator from the interface between the air and the piezoelectric laminated structure 130 back to the surface of the substrate, thereby Improve the conversion efficiency of electrical and mechanical energy, that is, increase the quality factor (Q value).
  • the cavity 40 also exposes a part of the piezoelectric layer 115 in the working area 100s.
  • the resonator further includes: a first trench 10 located in the piezoelectric laminate structure 130, the opening of the first trench 10 communicates with the cavity 40, and the first trench 10 The first electrode layer 110 is exposed at the bottom.
  • the opening of the first groove 10 is communicated with the cavity 40, so that the first groove 10 can reflect the sound waves laterally, which is beneficial to reduce energy dissipation and improve the resonator's performance. Acousto-electric conversion capability.
  • the first trench can also be used to define the edge of the active region of the resonator, that is, the edge of the region where the resonator selects effective resonance; the first trench and the second trench jointly enclose the effective resonance region.
  • the first trench 10 penetrates the piezoelectric layer 115 and the bottom of the first trench 10 exposes the first electrode layer 110.
  • the resonator further includes: a second trench 20 located in the piezoelectric laminate structure 130, the bottom of the second trench 20 exposes the second electrode layer 120, and the second trench 20 and the cavity 40 are separated by the second electrode layer 120.
  • the second trench 20 and the cavity 40 are separated by the second electrode layer 120.
  • the second groove 20 can also have a lateral reflection effect on sound waves, and correspondingly improve the acoustic-electric conversion capability of the resonator.
  • the release hole 30 communicates with the cavity 40.
  • the release hole 30 is used to release the sacrificial layer, thereby forming the cavity 40.
  • the number of the release holes 30 is multiple, so as to improve the efficiency of removing the sacrificial layer.
  • the release hole 30 penetrates the piezoelectric laminate structure 130.
  • the release hole may also penetrate the second substrate.
  • the release hole may also penetrate the second substrate.
  • an adhesive layer remains between the top of the cavity and the second substrate, the release hole penetrates the second substrate.
  • an adhesive layer located between the top of the cavity and the second substrate.
  • the resonator may be formed by the method for forming the resonator described in the foregoing embodiment, or may be formed by other methods for forming the resonator. In this embodiment, for the specific description of the resonator, reference may be made to the corresponding description in the foregoing embodiment, and this embodiment will not be repeated here.

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Abstract

一种谐振器及其形成方法，谐振器的形成方法包括：在第一衬底（100）上形成压电叠层结构（130），包括工作区（100s），压电叠层结构（130）与第一衬底（100）相接触的面为第一正面（130a）；在工作区（100s）上形成覆盖压电叠层结构（130）的牺牲层（140）；提供第二衬底（200）；在第二衬底（200）上形成粘合层（210），粘合层（210）与第二衬底（200）相接触的面为第二正面（210a），与第二正面（210a）相背的面为第二背面（210b）；将粘合层（210）的第二背面（210b）贴合于牺牲层（140）和牺牲层（140）暴露出的压电叠层结构（130）上，使粘合层（210）覆盖牺牲层（140）的侧壁且填充于第二衬底（200）与压电叠层结构（130）之间；去除第一衬底（100），暴露出压电叠层结构（130）的第一正面（130a）；形成贯穿压电叠层结构（130）的释放孔（30）或者形成贯穿第二衬底（200）的释放孔（30），释放孔（30）暴露出牺牲层（140）；通过释放孔（30）去除牺牲层（140），形成空腔（40）；有利于提升谐振器的性能。

Description

谐振器及其形成方法 技术领域
本发明实施例涉及半导体领域，尤其涉及一种谐振器及其形成方法。
 背景技术
随着移动通信技术的发展，移动数据传输量也迅速上升。因此，在频率资源有限以及应当使用尽可能少的移动通信设备的前提下，提高无线基站、微基站或直放站等无线功率发射设备的发射功率成了必须考虑的问题，同时，对移动通信设备前端电路中滤波器功率的要求也越来越高。
目前，无线基站等设备中的大功率滤波器主要是以腔体滤波器为主，其功率可达上百瓦，另外，还有些设备中使用介质滤波器，其平均功率可达5瓦以上。但是，这两种滤波器的尺寸均较大，难以集成到射频前端芯片中。
目前，基于半导体微加工工艺技术的薄膜体声波谐振器（Film Bulk Acoustic Resonator，FBAR）能够很好地克服上述两种滤波器存在的缺陷。FBAR的工作频率高，所承受功率高和品质因数(Q值)高，体积小，有利于集成化，且FBAR还具有与硅片工艺兼容性好以及可靠性好等优点。
 技术问题
本发明解决的问题是提供一种谐振器及其形成方法，提升谐振器的性能。
 技术解决方案
为解决上述问题，本发明提供一种谐振器的形成方法，包括：提供第一衬底；在所述第一衬底上形成压电叠层结构，所述压电叠层结构包括工作区，所述压电叠层结构与所述第一衬底相接触的面为第一正面；在所述工作区上形成覆盖所述压电叠层结构的牺牲层；提供第二衬底；在所述第二衬底上形成粘合层，所述粘合层与所述第二衬底相接触的面为第二正面，所述粘合层与所述第二正面相背的面为第二背面；将所述粘合层的第二背面贴合于所述牺牲层以及所述牺牲层暴露出的压电叠层结构上，使粘合层覆盖所述牺牲层的侧壁且填充于第二衬底与压电叠层结构之间；在实现所述贴合后，去除所述第一衬底，暴露出所述压电叠层结构的第一正面；形成贯穿所述压电叠层结构的释放孔，或者，形成贯穿所述第二衬底的释放孔，所述释放孔暴露出所述牺牲层；通过所述释放孔去除所述牺牲层，形成空腔。
可选的，在所述第一衬底上形成压电叠层结构之后，形成所述牺牲层之前，所述谐振器的形成方法还包括：在所述工作区的压电叠层结构中形成第一沟槽。
可选的，所述压电叠层结构包括第一电极层、位于所述第一电极层上的压电层以及位于所述压电层上的第二电极层，所述第一电极层与所述第一衬底相接触的面为所述第一正面；形成所述第一沟槽的步骤中，所述第一沟槽的底部暴露出所述第一电极层；形成空腔后，所述第一沟槽的开口与所述空腔相连通。
可选的，在去除所述第一衬底，暴露出所述压电叠层结构的第一正面之后，所述谐振器的形成方法还包括：在所述工作区的压电叠层结构中形成第二沟槽。
可选的，所述压电叠层结构包括第一电极层、位于所述第一电极层上的压电层以及位于所述压电层上的第二电极层；形成所述第二沟槽的步骤中，所述第二沟槽的底部暴露出所述第二电极层；在形成所述空腔后，所述第二沟槽与所述空腔由所述第二电极层相隔离。
可选的，形成所述粘合层的工艺包括旋涂工艺。
可选的，所述粘合层的材料为可形变材料。
可选的，所述粘合层的材料包括干膜或粘片膜。
可选的，采用键合工艺，实现所述贴合。
可选的，所述键合工艺的温度为50℃至300℃。
可选的，形成所述粘合层的步骤中，所述粘合层的厚度为0.5μm至40μm。
可选的，在将所述粘合层的第二背面贴合于所述牺牲层以及所述牺牲层所暴露出的压电叠层结构上的步骤中，所述牺牲层的顶面与所述第二衬底之间还保留有部分厚度的所述粘合层。
可选的，在将所述粘合层贴合于所述牺牲层以及所述牺牲层所暴露出的压电叠层结构上的步骤中，位于所述牺牲层顶面与所述第二衬底之间的所述粘合层的厚度为0.5μm至35μm。
可选的，去除所述第一衬底的步骤包括：对所述第一衬底进行研磨处理，去除部分厚度的所述第一衬底；在对所述第一衬底进行研磨处理后，采用湿法刻蚀工艺，去除剩余的所述第一衬底。
可选的，对所述第一衬底进行研磨处理的工艺包括化学机械研磨工艺。
可选的，在所述第一衬底上形成所述压电叠层结构之前，所述谐振器的形成方法还包括：在所述第一衬底上形成缓冲层；在去除所述第一衬底的步骤中，以所述缓冲层作为停止层，去除所述第一衬底；在去除所述第一衬底后，所述谐振器的形成方法还包括：去除所述缓冲层。
可选的，形成所述牺牲层的步骤包括：在所述压电叠层结构上形成牺牲材料层；对所述牺牲材料层进行平坦化处理；对所述牺牲材料层进行平坦化处理之后，图形化所述牺牲材料层，保留位于所述工作区的牺牲材料层作为所述牺牲层。
相应的，本发明还提供一种谐振器，包括：衬底；粘合层，位于所述衬底上；压电叠层结构，位于所述粘合层上，所述压电叠层结构包括工作区，位于所述工作区的压电叠层结构与所述粘合层围成空腔，所述空腔的侧壁暴露出所述粘合层；贯穿所述压电叠层结构的释放孔，或者，贯穿所述衬底的释放孔，所述释放孔与所述空腔相连通。
可选的，所述粘合层的材料为可形变材料。
可选的，所述粘合层的材料包括干膜或粘片膜。
可选的，所述压电叠层结构包括第二电极层、位于所述第二电极层上的压电层以及位于所述压电层上的第一电极层，所述第一电极层背向所述第二电极层的面为第一正面，所述第二电极层背向所述第一电极层的面为第一背面；所述空腔暴露出所述第二电极层的第一背面。
可选的，所述谐振器还包括：第一沟槽，位于所述压电叠层结构中，所述第一沟槽的开口与所述空腔相连通，且所述第一沟槽的底部暴露出所述第一电极层。
可选的，所述谐振器还包括：第二沟槽，位于所述压电叠层结构中，所述第二沟槽的底部暴露出所述第二电极层，且所述第二沟槽与所述空腔由所述第二电极层相隔离。
 有益效果
与现有技术相比，本发明的技术方案具有以下优点：本发明实施例提供的谐振器的形成方法中，在所述第一衬底上形成压电叠层结构之后，再在所述工作区上形成覆盖所述压电叠层结构的牺牲层，之后再将所述粘合层的第二背面贴合于所述牺牲层以及所述牺牲层所暴露出的压电叠层结构上，使粘合层覆盖所述牺牲层的侧壁且填充于第二衬底与压电叠层结构之间，实现贴合，然后去除所述第一衬底、以及形成所述释放孔并通过所述释放孔去除牺牲层，形成空腔；本发明实施例在形成所述压电叠层结构时，所述第一衬底的表面未形成有牺牲层，所述第一衬底表面的平坦度较好，有利于为在第一衬底上形成所述压电叠层结构提供良好的界面，进而提高所述压电叠层结构中各个膜层的形成质量，例如：有利于提高压电叠层结构中各个膜层的厚度一致性、晶格取向一致性、薄膜连续性等，相应有利于提升谐振器的性能，此外，本发明还利用了所述粘合层的可塑性，在形成有凸起结构的第一衬底上贴合第二衬底，相应实现对所述牺牲层的密封，从而有利于提高形成空腔的便捷性和可操作性，还有利于节约成本。
 附图说明
图1至图13是本发明谐振器的形成方法一实施例中各步骤对应的结构示意图。
 本发明的实施方式
由背景技术可知，目前薄膜体声波谐振器（Film Bulk Acoustic Resonator，FBAR）得到广泛应用。但是目前形成的谐振器的性能不佳。
具体地，目前薄膜体声波谐振器的制备工艺通常是在衬底中形成凹槽，在凹槽中形成牺牲层，随后在牺牲层上依次形成压电叠层结构，而为了释放凹槽中的牺牲层，通常需要形成贯穿所述压电叠层结构的释放孔，利用该释放孔，将凹槽中的牺牲材料层去除，最终形成空腔。
其中，形成牺牲层的步骤通常包括：在凹槽中形成牺牲材料层，牺牲材料层还形成在所述衬底上；研磨去除高于衬底的牺牲材料层，位于凹槽中的剩余牺牲材料层作为所述牺牲层。
然而由于牺牲层与衬底的材料不同，牺牲层的材料与衬底的材料的硬度和机械强度不同，例如：牺牲层为易于去除的材料，牺牲层的材料较软，这导致在研磨去除高于衬底的牺牲材料层时，牺牲材料层顶部被研磨的速率较快，牺牲层顶部与衬底表面的高度一致性较差，例如：牺牲层顶部容易出现凹陷、牺牲层顶部与衬底顶面之间容易出现台阶，这导致牺牲层和衬底表面的平坦度和高度一致性较差，进而容易影响压电叠层结构的薄膜生长质量，例如：影响压电叠层结构中各膜层的晶格取向一致性、厚度一致性、薄膜连续性等，进而易降低谐振器的性能。
为了解决所述技术问题，本发明提供一种谐振器的形成方法，包括：提供第一衬底；在所述第一衬底上形成压电叠层结构，所述压电叠层结构包括工作区，所述压电叠层结构与所述第一衬底相接触的面为第一正面；在所述工作区上形成覆盖所述压电叠层结构的牺牲层；提供第二衬底；在所述第二衬底上形成粘合层，所述粘合层与所述第二衬底相接触的面为第二正面，所述粘合层与所述第二正面相背的面为第二背面；将所述粘合层的第二背面贴合于所述牺牲层以及所述牺牲层暴露出的压电叠层结构上，使粘合层覆盖所述牺牲层的侧壁且填充于第二衬底与压电叠层结构之间；在实现所述贴合后，去除所述第一衬底，暴露出所述压电叠层结构的第一正面；形成贯穿所述压电叠层结构的释放孔，或者，形成贯穿所述第二衬底的释放孔，所述释放孔暴露出所述牺牲层；通过所述释放孔去除所述牺牲层，形成空腔。
本发明实施例提供的谐振器的形成方法中，在所述第一衬底上形成压电叠层结构之后，再在所述工作区上形成覆盖所述压电叠层结构的牺牲层，之后再将所述粘合层的第二背面贴合于所述牺牲层以及所述牺牲层所暴露出的压电叠层结构上，使粘合层覆盖所述牺牲层的侧壁且填充于第二衬底与压电叠层结构之间，实现贴合，然后去除所述第一衬底、以及形成所述释放孔并通过所述释放孔去除牺牲层，形成空腔；本发明实施例在形成所述压电叠层结构时，所述第一衬底的表面未形成有牺牲层，所述第一衬底表面的平坦度较好，有利于为在第一衬底上形成所述压电叠层结构提供良好的界面，进而提高所述压电叠层结构中各个膜层的形成质量，例如：有利于提高压电叠层结构中各个膜层的厚度一致性、晶格取向一致性、薄膜连续性等，进而有利于提升谐振器的性能，此外，本发明还利用了所述粘合层的可塑性，在形成有凸起结构的第一衬底上贴合第二衬底，相应实现对所述牺牲层的密封，从而有利于提高形成空腔的便捷性和可操作性，还有利于节约成本。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1至图13是本发明谐振器的形成方法一实施例中各步骤对应的结构示意图。
参考图1，提供第一衬底100。
所述第一衬底100为后续工艺制程提供工艺平台。
本实施例中，所述第一衬底100可以为任意合适的半导体衬底，例如体硅衬底，其还可以是以下所提到的材料中的至少一种：SiGe、SiGe、Sic、SiGeC、TnAs、GaAs、Inp或者其它Ⅲ族和Ⅴ族化合物半导体，还包括这些半导体成的多层结构等，或者为绝缘体上硅（SOI）、绝缘体上层叠硅（SSOI）、绝缘体上层叠锗化硅（S- SiGeOI）、绝缘体上锗化硅（SiGe01）以及绝缘体上锗（GeOI），或者还可以为双面抛光硅片（Double Side Polished Wafers，DSP），也可为氧化铝等的陶瓷基底、石英或玻璃基底等。
后续还包括在第一衬底100上形成压电叠层结构，本实施例中，在所述第一衬底100上形成所述压电叠层结构之前，所述谐振器的形成方法还包括：在所述第一衬底100上形成缓冲层105。
所述缓冲层105用于改善所述第一衬底100表面的界面质量，并作为后续压电叠层结构与第一衬底100之间的过渡层，从而提高后续压电叠层结构的生长一致性，以及第一衬底100和压电叠层结构之间的粘附性。而且，后续在第二衬底上形成粘合层，并将粘合层贴合于所述牺牲层以及所述牺牲层暴露出的压电叠层结构上后，所述谐振器的形成方法还包括：去除所述第一衬底100，所述缓冲层105还能够在去除所述第一衬底100的步骤中用于作为停止层，从而降低去除第一衬底100的难度，并有利于防止后续去除第一衬底100的工艺对压电叠层结构产生影响。
所述缓冲层105的材料可以为氧化硅、氮化硅和氮氧化硅中的一种或多种。本实施例中，所述缓冲层105的材料为氧化硅。
本实施例中，采用沉积工艺形成所述缓冲层105。具体地，所述沉积工艺可以为化学气相沉积工艺或原子层沉积工艺等。
继续参考图1，在所述第一衬底100上形成压电叠层结构130，所述压电叠层结构130包括工作区100s，所述压电叠层结构130与所述第一衬底100相接触的面为第一正面130a。
所述压电叠层结构130用于实现电信号与声信号之间的相互转换，从而使谐振器对信号进行滤波处理。
本实施例中，所述压电叠层结构130包括工作区100s，所述工作区100s包括谐振器用于实现滤波功能的有效工作区，后续在所述工作区100s形成空腔。
本实施例中，所述压电叠层结构130包括第一电极层110、位于所述第一电极层110上的压电层115以及位于所述压电层115上的第二电极层120，所述第一电极层110与所述第一衬底100相接触的面为所述第一正面130a。
后续步骤还包括：在所述工作区100s上形成覆盖所述压电叠层结构130的牺牲层。本实施例中，先在所述第一衬底100上形成所述压电叠层结构130，在形成所述压电叠层结构130的过程中，所述第一衬底100上未形成有牺牲层，所述第一衬底100的表面平坦度较好，有利于为压电叠层结构130的形成提供良好的界面，进而提高所述压电叠层结构130中的第一电极层110、压电层115以及第二电极层120的形成质量，例如：有利于提高压电叠层结构130中各个膜层的厚度一致性、晶格取向一致性和薄膜连续性等，进而有利于提升谐振器的性能。
本实施例中，所述第一电极层110用于形成下电极（Bottom Electrode）。
所述第一电极层110的材料为导电材料或半导体材料。其中，导电材料可以为具有导电性能的金属材料，例如：Al、Cu、Pt、Au、Ir、Os、Re、Pd、Rh、Ru、Mo和W中的一种或多种；所述半导体材料可以为Si、Ge、SiGe、SiC或SiGeC等。
本实施例中，可以采用物理气相沉积工艺形成所述第一电极层110。
所述压电层115的材料为压电材料，压电材料具有压电效应，也就是说，压电材料是受到压力作用时会在两端面间出现电压的晶体材料，利用压电材料的压电效应可实现机械振动（声波）和交流电的互相转换，进而实现声能与电能的转换。
所述压电层115的材料可以为ZnO、AlN、GaN、锆钛酸铝或钛酸铅等具有纤锌矿型结晶结构的压电材料。本实施例中，所述压电层115的材料为AlN。
本实施例中，可以采用化学气相沉积工艺、物理气相沉积工艺或原子层沉积工艺等沉积工艺，形成所述压电层115。
本实施例中，所述第二电极层120用于形成上电极（Top Electrode）。
所述第二电极层120的材料为导电材料或半导体材料。其中，导电材料可以为具有导电性能的金属材料，例如：Al、Cu、Pt、Au、Ir、Os、Re、Pd、Rh、Ru、Mo和W中的一种或多种；所述半导体材料可以为Si、Ge、SiGe、SiC或SiGeC等。
后续步骤还包括：在所述工作区100s的压电叠层结构130上形成牺牲层。
结合参考图2和图3，本实施例中，在所述第一衬底100上形成压电叠层结构130之后，形成所述牺牲层之前，所述谐振器的形成方法还包括：在所述工作区100s的压电叠层结构130中形成第一沟槽10。
所述第一沟槽10用于对声波进行横向反射，从而有利于提高声波在空腔中的驻留时间，进而减小能量的耗散，相应有利于提高谐振器的声电转换性能。在其他实施例中，第一沟槽还能够用于限定谐振器有源区的边缘，即谐振器选择有效谐振的区域边缘；第一沟槽与后续制作的第二沟槽共同圈定有效谐振的区域。
本实施例中，形成所述第一沟槽10的步骤中，所述第一沟槽10的底部暴露出所述第一电极层110。
需要说明的是，结合参考图2，本实施例中，形成所述压电叠层结构130后，形成所述第一沟槽10之前，所述谐振器的形成方法还包括：对所述第二电极层120进行图形化处理，暴露出部分位于所述工作区100s的压电层115。
通过对所述第二电极层120进行图形化处理，从而形成上电极。本实施例也可以通过上电极的图案来定义有效谐振的区域边缘。
本实施例中，采用干法刻蚀工艺，图形化所述第二电极层120。
因此，本实施例中，形成所述第一沟槽10的步骤中，所述第一沟槽10贯穿所述压电层115且第一沟槽10的底部暴露出所述第一电极层110。
参考图4至图6，在所述工作区100s上形成覆盖所述压电叠层结构130的牺牲层140。
所述牺牲层140用于为后续形成空腔占据空间位置，也就是说，后续通过去除所述牺牲层140，从而在所述牺牲层140的位置处形成空腔。
因此，所述牺牲层140的材料为易于被去除的材料，且后续去除牺牲层140的工艺对所述压电叠层结构130的影响较小，此外，所述牺牲层140的材料能够保证使所述牺牲层140具有较好的覆盖性，从而完全覆盖所述工作区100s的压电叠层结构130。
所述牺牲层140的材料包括PSG（掺磷的氧化硅）、LTO（Li 2TiO 3，钛酸锂）、BPSG（掺硼和磷的氧化硅）、Ge、光刻胶、多晶硅或非晶碳等材料。本实施例中，所述牺牲层140的材料为PSG。
本实施例中，形成所述牺牲层140的步骤中，所述牺牲层140还填充于所述第一沟槽10中。
本实施例中，形成所述牺牲层140的步骤包括。
如图4所示，在所述压电叠层结构130上形成牺牲材料层125。
所述牺牲材料层125用于形成牺牲层。
本实施例中，采用化学气相沉积（CVD）工艺形成所述牺牲材料层125。
本实施例中，牺牲材料层125还填充于所述第一沟槽10中。
如图5所示，对所述牺牲材料层125进行平坦化处理。
通过对牺牲材料层125进行平坦化处理，从而实现牺牲材料层125的顶面平坦化，进而提高后续牺牲层表面的平坦度。
本实施例中，采用化学机械研磨（CMP）工艺，对所述牺牲材料层125进行平坦化处理。
如图6所示，对所述牺牲材料层125进行平坦化处理之后，图形化所述牺牲材料层125，保留位于所述工作区100s的牺牲材料层作为所述牺牲层140。
本实施例中，采用干法刻蚀工艺，例如：各向异性的干法刻蚀工艺，图形化所述牺牲材料层125。
参考图7，提供第二衬底200。
后续步骤还包括：在第二衬底200上形成粘合层；将所述粘合层贴合于所述牺牲层140以及所述牺牲层140暴露出的压电叠层结构130上。
所述第二衬底200用于为后续粘合层的形成、以及实现所述粘合层与牺牲层140的贴合提供工艺平台。
本实施例中，所述第二衬底200可以为任意合适的半导体衬底，例如体硅衬底，其还可以是以下所提到的材料中的至少一种：SiGe、SiGe、Sic、SiGeC、TnAs、GaAs、Inp或者其它Ⅲ族和Ⅴ族化合物半导体，还包括这些半导体成的多层结构等，或者为绝缘体上硅（SOI）、绝缘体上层叠硅（SSOI）、绝缘体上层叠锗化硅（S- SiGeOI）、绝缘体上锗化硅（SiGeOI）以及绝缘体上锗（GeOI），或者还可以为双面抛光硅片（Double Side Polished Wafers，DSP），也可为氧化铝等的陶瓷基底、石英或玻璃基底等。
继续参考图7，在所述第二衬底200上形成粘合层210，所述粘合层210与所述第二衬底200相接触的面为第二正面201a，所述粘合层210与所述第二正面210a相背的面为第二背面210b。
后续步骤还包括：将所述粘合层210的第二背面210b贴合于所述牺牲层140以及所述牺牲层140暴露出的压电叠层结构130上，使粘合层210覆盖所述牺牲层140的侧壁且填充于第二衬底200与压电叠层结构130之间，从而通过所述粘合层210将所述牺牲层140密封，进而在后续去除牺牲层140后，能够在牺牲层140的位置处形成空腔。
本实施例中，所述粘合层210为可形变材料。具体地，所述粘合层210的材料可以为具有较强粘性的有机材料，从而使得通过所述粘合层210能够实现所述贴合。
具体地，所述粘合层210为受热可形变的材料，受热可形变的所述粘合层210在受热后会变软，从而使得所述粘合层210具有较强的可塑性，在后续将所述粘合层210的第二背面210b贴合于所述牺牲层140以及所述牺牲层140暴露出的压电叠层结构130上时，所述粘合层210能够被挤压变形并填充到第二衬底200与压电叠层结构130之间，从而通过粘合层210能够在形成有凸起结构的第一衬底100上贴合第二衬底200，相应实现对牺牲层140的密封。
本实施例中，所述粘合层210的材料为干膜（Dry film）。
干膜是一种用于半导体芯片封装或印刷电路板制造时所采用的具有粘性的光致抗蚀膜，在一实施例中，干膜光刻胶的制造是将无溶剂型光致抗蚀剂涂在涤纶片基上，再覆上聚乙烯薄膜；使用时揭去聚乙烯薄膜，把无溶剂型光致抗蚀剂压于基版上，经曝光显影处理，即可在干膜光刻胶内形成图形。
在其他实施例中，所述粘合层的材料还可以为粘片膜（Die attach film，DAF）等其他具有较强粘性的有机材料。
本实施例中，形成所述粘合层210的工艺包括旋涂工艺。
需要说明的是，后续步骤还包括：将所述粘合层210的第二背面210b贴合于所述牺牲层140以及所述牺牲层140暴露出的压电叠层结构130上，所述粘合层210需要能够将所述牺牲层140密封，因此，形成所述粘合层210的步骤中，所述粘合层210的厚度需要根据所述牺牲层140的厚度而定。本实施例中，所述粘合层210的厚度需大于后续牺牲层140的厚度。
本实施例中，形成所述粘合层210的步骤中，所述粘合层210的厚度为0.5μm至40μm，例如：15μm或20μm等。
参考图8，将所述粘合层210的第二背面210b贴合于所述牺牲层140以及所述牺牲层140暴露出的压电叠层结构130上，使粘合层210覆盖所述牺牲层140的侧壁且填充于第二衬底200与压电叠层结构130之间。
具体地，粘合层210覆盖所述牺牲层140的顶部和侧壁、以及牺牲层140所暴露出的压电叠层结构130上，以实现贴合，进而使粘合层210将牺牲层140密封。
因此，在后续去除所述第一衬底100、以及形成暴露出牺牲层140的释放孔并通过所述释放孔去除牺牲层140后，即可形成空腔。
本实施例中，利用了所述粘合层210的可形变特性和可塑性，在形成有凸起结构的第一衬底100上贴合第二衬底200，也就是说，在形成有牺牲层140的第一衬底100上贴合第二衬底200，相应实现对所述牺牲层140的密封，从而有利于提高形成空腔的便捷性和可操作性，还有利于节约成本。
本实施例中，采用键合（bonding）工艺，实现所述贴合。通过键合的方式实现所述贴合，从而将密封牺牲层140的工艺与现有的键合工艺相兼容，有利于提高工艺整合度和工艺兼容性。
具体地，本实施例中，所述粘合层210为材质较软、受热可形变的材料，在进行键合的过程中，将所述粘合层210的第二背面210b压合到所述牺牲层140上，并对粘合层210进行升温处理，所述粘合层210在受热后会变软，从而使粘合层210填充到所述牺牲层140侧壁与压电叠层结构130之间围成的空隙中，进而将所述牺牲层140的顶部和侧壁密封。
本实施例中，为保证所述粘合层210能够变的足够软，以使粘合层210能够将第二衬底200贴合到形成有凸起结构的第一衬底100上，并密封所述牺牲层140的顶部和侧壁，同时，还需防止温度过高会对压电叠层结构130或其他膜层结构造成损伤，或者防止温度过高对粘合层210的粘性造成影响，本实施例中，所述键合工艺的温度为50℃至300℃。
需要说明的是，为保证粘合层210能够将牺牲层140的顶部和侧壁密封，本实施例中，在形成所述粘合层210的步骤中，所述粘合层210的厚度较大，所述粘合层210的厚度大于需形成的牺牲层140的厚度。
因此，在将所述粘合层210贴合于所述牺牲层140以及所述牺牲层140暴露出的压电叠层结构130上的步骤中，所述牺牲层140的顶面与所述第二衬底200之间还保留有部分厚度的所述粘合层210，有利于防止出现部分的粘合层210和所述压电叠层结构130未完全贴合的问题，相应有利于防止出现粘合层210与压电叠层结构130之间出现空隙的问题，从而保证粘合层210将牺牲层140的顶部和侧壁密封，有利于提高工艺稳定性、降低工艺风险，而且，通过使牺牲层140的顶面与第二衬底200之间还保留有部分厚度的粘合层210，还有利于降低贴合的难度。
具体地，本实施例中，位于所述牺牲层140顶面与第二衬底200之间的所述粘合层210的厚度为0.5μm至35μm，例如：15μm。
在其他实施例中，根据实际的工艺，在实现贴合的步骤中，所述牺牲层的顶面与第二衬底之间还可以不保留有部分厚度的粘合层，也就是说，所述牺牲层的顶面直接与第二衬底相接触，相应地，所述粘合层填充于所述第二衬底与所述压电叠层结构之间，从而通过所述第二衬底和粘合层将所述牺牲层的顶面和侧壁密封。
参考图9，在实现所述贴合后，去除所述第一衬底100，暴露出所述压电叠层结构130的第一正面130a。
去除第一衬底100，暴露出压电叠层结构130的第一正面130a，为后续工艺做准备。
本实施例中，暴露出压电叠层结构130的第一正面130a，还为后续形成贯穿压电叠层结构130的释放孔做准备。
本实施例中，去除所述第一衬底100的步骤包括：对所述第一衬底100进行研磨处理，去除部分厚度的所述第一衬底100；在对所述第一衬底100进行研磨处理后，采用湿法刻蚀工艺，去除剩余的所述第一衬底100。
通过对第一衬底100进行研磨处理，从而实现对第一衬底100的减薄，进而减小后续湿法刻蚀工艺的难度。
本实施例中，采用化学机械研磨工艺，对第一衬底100进行研磨处理。
本实施例中，所述湿法刻蚀工艺的刻蚀溶液包括TMAH（四甲基氢氧化铵）溶液等。
需要说明的是，本实施例中，在去除所述第一衬底100的步骤中，以所述缓冲层105作为停止层，去除第一衬底100，有利于降低去除第一衬底100的难度，并有利于防止去除第一衬底100的工艺对压电叠层结构130造成损伤。
本实施例中，在去除所述第一衬底100后，所述谐振器的形成方法还包括：去除所述缓冲层105。
具体地，采用湿法刻蚀工艺，去除所述缓冲层105。本实施例中，通过氢氟酸溶液，进行所述湿法刻蚀工艺。
需要说明的是，本实施例中，结合参考图10，本实施例中，在去除第一衬底100后，所述谐振器的形成方法还包括：对所述第一电极层110进行图形化处理，暴露出部分位于所述工作区100s的压电层115。
通过对所述第一电极层110进行图形化处理，从而形成下电极。
本实施例中，采用干法刻蚀工艺，图形化所述第一电极层110。
结合参考图11，本实施例中，在去除所述第一衬底100，暴露出所述压电叠层结构130的第一正面130a之后，所述谐振器的形成方法还包括：在所述有效工作区100s的压电叠层结构130中形成第二沟槽20。
所述第二沟槽20用于对声波进行横向反射，从而提高声波在空腔中的驻留时间，进而减小能量的耗散，相应有利于提高谐振器的声电转换性能。在其他实施例中，第二沟槽还能够用于限定谐振器有源区的边缘，即谐振器选择有效谐振的区域边缘；第二沟槽与第一沟槽共同圈定有效谐振的区域。
本实施例中，由于去除第一衬底100后，暴露出了压电叠层结构130的第一正面130a，因此，易于在压电叠层结构130中形成第二沟槽20，从而进一步提升谐振器的性能。
本实施例中，形成所述第二沟槽20的步骤中，所述第二沟槽20的底部暴露出所述第二电极层120。
本实施例中，在形成所述第二沟槽20的步骤中，还图形化所述压电层115，从而定义有效工作区。
参考图12，形成贯穿所述压电叠层结构130的释放孔30，或者，形成贯穿所述第二衬底200的释放孔30，所述释放孔30暴露出所述牺牲层140。
所述释放孔30暴露出所述牺牲层140，从而后续能够通过释放孔30去除所述牺牲层140。
本实施例中，所述释放孔30的数量为多个，从而提高后续通过释放孔30去除牺牲层140的效率。
作为一种示例，本实施例中，所述释放孔30贯穿所述压电叠层结构130。
在其他实施例中，所述释放孔还可以贯穿所述第二衬底，相应的，当牺牲层的顶部与第二衬底之间还保留有粘合层时，释放孔相应贯穿第二衬底和所述粘合层，以暴露出所述牺牲层。通过使释放孔贯穿第二衬底，有利于防止对压电叠层结构造成损伤。
本实施例中，采用干法刻蚀工艺，刻蚀所述压电叠层结构130，形成所述释放孔30。
参考图13，通过所述释放孔30去除所述牺牲层140，形成空腔40。
通过形成空腔40，使压电叠层结构130与空气相接触，使声波在空腔40与压电叠层结构130的交界面处发生反射，从而使谐振器在工作时能够正常产生振动，进而使谐振器能够正常工作；而且，压电叠层结构130与空气相接触，能有效地将谐振器的漏波从空气与压电叠层结构130的交界面处反射回衬底表面，从而提高电能与机械能的转换效率，也即提高了品质因子（Q值）。
本实施例中，采用湿法刻蚀工艺，去除所述牺牲层140。所述湿法刻蚀工艺的刻蚀溶液包括BOE（Buffered Oxide Etch，缓冲氧化物刻蚀液）溶液或HF溶液。其中，BOE溶液由氢氟酸与水，或由氟化铵与水混合而成。
本实施例中，形成空腔40后，所述第一沟槽10的开口与所述空腔40相连通，从而使得所述第一沟槽10能够对声波起到横向反射作用，进而减小能量的耗散，提高谐振器的声电转换能力。
本实施例中，在形成所述空腔40后，所述第二沟槽20与所述空腔40由所述第二电极层120相隔离。所述第二沟槽20也能够对声波起到横向反射作用，相应提高谐振器的声电转换能力。
相应的，本发明还提供一种谐振器。继续参考图13，示出了本发明谐振器一实施例的结构示意图。
所述谐振器包括：衬底200；粘合层210，位于所述衬底200上；压电叠层结构130，位于所述粘合层210上，所述压电叠层结构130包括工作区100s，位于所述工作区100s的压电叠层结构130与所述粘合层210围成空腔40，所述空腔40的侧壁暴露出所述粘合层210；贯穿所述压电叠层结构130的释放孔30，或者，贯穿所述衬底200的释放孔30，所述释放孔30与所述空腔40相连通。
本实施例中，所述衬底200为第二衬底200。
本发明实施例提供的谐振器中，还包括粘合层210，位于第二衬底200上；压电叠层结构130还位于所述粘合层210上，且位于所述有效工作区100s的压电叠层结构130与所述粘合层210围成空腔40，空腔40不位于第二衬底200中，形成空腔40通常包括先形成牺牲层再通过释放孔30去除牺牲层的步骤，空腔40由压电叠层结构130与粘合层210围成，由于先形成压电叠层结构130、再在压电叠层结构130上形成牺牲层，随后将粘合层210贴合于牺牲层上并形成释放孔30再通过释放孔30去除所述牺牲层，压电叠层结构130可直接形成于另一衬底上，从而为压电叠层结构130的形成提供良好的界面和平坦的表面，进而有利于提高所述压电叠层结构130的薄膜质量，例如：压电叠层结构130中各个膜层的厚度一致性、晶格取向一致性以及薄膜连续性等，进而提高谐振器的性能。
第二衬底200用于为工艺制程提供工艺平台。具体的，第二衬底200用于为粘合层210的形成、以及粘合层210和压电叠层结构130的贴合提供工艺平台。
本实施例中，所述第二衬底200可以为任意合适的半导体衬底，例如体硅衬底，其还可以是以下所提到的材料中的至少一种：SiGe、SiGe、Sic、SiGeC、TnAs、GaAs、Inp或者其它Ⅲ族和Ⅴ族化合物半导体，还包括这些半导体成的多层结构等，或者为绝缘体上硅（SOI）、绝缘体上层叠硅（SSOI）、绝缘体上层叠锗化硅（S- SiGeOI）、绝缘体上锗化硅（SiGe01）以及绝缘体上锗（GeOI），或者还可以为双面抛光硅片（Double Side Polished Wafers，DSP），也可为氧化铝等的陶瓷基底、石英或玻璃基底等。
在空腔40的形成过程中，所述粘合层210用于将牺牲层密封，从而在利用释放孔30去除牺牲层后，即可形成空腔40。
本实施例中，所述粘合层210的材料为可形变材料。具体地，所述粘合层210的材料可以为具有较强粘性的有机材料，从而使得通过所述粘合层210能够实现所述贴合。
具体地，所述粘合层210为受热可形变的材料，受热可形变的所述粘合层210在受热后会变软，从而使得所述粘合层210具有较强的可塑性，在所述空腔40的形成过程中，在将所述粘合层210的第二背面210b贴合于牺牲层以及牺牲层暴露出的压电叠层结构130上时，所述粘合层210能够被挤压变形并填充到第二衬底200与压电叠层结构130之间，从而通过粘合层210能够在形成有凸起结构的第一衬底上贴合第二衬底200，相应实现对牺牲层的密封，进而在去除牺牲层后即可形成所述空腔40。
本实施例中，所述粘合层210的材料为干膜（Dry film）。
干膜是一种用于半导体芯片封装或印刷电路板制造时所采用的具有粘性的光致抗蚀膜，在一实施例中，干膜光刻胶的制造是将无溶剂型光致抗蚀剂涂在涤纶片基上，再覆上聚乙烯薄膜；使用时揭去聚乙烯薄膜，把无溶剂型光致抗蚀剂压于基版上，经曝光显影处理，即可在干膜光刻胶内形成图形。
在其他实施例中，所述粘合层的材料还可以为粘片膜（Die attach film，DAF）等其他具有较强粘性的有机材料。
本实施例中，空腔40的底部与第二衬底200之间还保留有部分厚度的所述粘合层210，也就是说，空腔40的底部还暴露出所述粘合层210，从而有利于保证在形成空腔40的过程中，粘合层210能够将牺牲层的顶部和侧壁密封。具体地，本实施例中，位于空腔40的底部与第二衬底200之间的所述粘合层210的厚度为0.5μm至35μm，例如：15μm。
在其他实施例中，根据实际形成空腔的工艺，所述空腔的底部与第二衬底之间还可以不保留有粘合层，也就是说，所述空腔的底部暴露出所述第二衬底。
所述压电叠层结构130用于实现电信号与声信号之间的相互转换，从而使谐振器对信号进行滤波处理。
本实施例中，所述压电叠层结构130包括工作区100s，所述工作区100s包括谐振器用于实现滤波功能的有效工作区。
所述压电叠层结构130包括第二电极层120、位于所述第二电极层120上的压电层115以及位于所述压电层115上的第一电极层115，所述第一电极层背向所述第二电极层的面为第一正面，所述第二电极层背向所述第一电极层的面为第一背面；所述空腔40暴露出所述第二电极层120的第一背面。
本实施例中，所述第二电极层120为上电极（Top Electrode）。
所述第二电极层120的材料为导电材料或半导体材料。其中，导电材料可以为具有导电性能的金属材料，例如：Al、Cu、Pt、Au、Ir、Os、Re、Pd、Rh、Ru、Mo和W中的一种或多种；所述半导体材料可以为Si、Ge、SiGe、SiC或SiGeC等。
所述压电层115的材料为压电材料，压电材料具有压电效应，也就是说，压电材料是受到压力作用时会在两端面间出现电压的晶体材料，利用压电材料的压电效应可实现机械振动（声波）和交流电的互相转换，进而实现声能与电能的转换。
所述压电层115的材料可以为ZnO、AlN、GaN、锆钛酸铝或钛酸铅等具有纤锌矿型结晶结构的压电材料。本实施例中，所述压电层115的材料为AlN。
本实施例中，所述第一电极层110为下电极（Bottom Electrode）。
所述第一电极层110的材料为导电材料或半导体材料。其中，导电材料可以为具有导电性能的金属材料，例如：Al、Cu、Pt、Au、Ir、Os、Re、Pd、Rh、Ru、Mo和W中的一种或多种；所述半导体材料可以为Si、Ge、SiGe、SiC或SiGeC等。
通过设置空腔40，使压电叠层结构130与空气相接触，使声波在空腔40与压电叠层结构130的交界面处发生反射，从而使谐振器在工作时能够正常产生振动，进而使谐振器能够正常工作；而且，压电叠层结构130与空气相接触，能有效地将谐振器的漏波从空气与压电叠层结构130的交界面处反射回衬底表面，从而提高电能与机械能的转换效率，也即提高了品质因子（Q值）。
本实施例中，所述空腔40还暴露出部分位于工作区100s的压电层115。
所述谐振器还包括：第一沟槽10，位于所述压电叠层结构130中，所述第一沟槽10的开口与所述空腔40相连通，且所述第一沟槽10的底部暴露出所述第一电极层110。
所述第一沟槽10的开口与所述空腔40相连通，从而使得所述第一沟槽10能够对声波起到横向反射作用，有利于减小能量的耗散，进而提高谐振器的声电转换能力。在其他实施例中，第一沟槽还能够用于限定谐振器有源区的边缘，即谐振器选择有效谐振的区域边缘；第一沟槽与第二沟槽共同圈定有效谐振的区域。
本实施例中，所述第一沟槽10贯穿所述压电层115且第一沟槽10的底部暴露出所述第一电极层110。
所述谐振器还包括：第二沟槽20，位于所述压电叠层结构130中，所述第二沟槽20的底部暴露出所述第二电极层120，且所述第二沟槽20与所述空腔40由所述第二电极层120相隔离。
所述第二沟槽20与所述空腔40由所述第二电极层120相隔离。所述第二沟槽20也能够对声波起到横向反射作用，相应提高谐振器的声电转换能力。
释放孔30与空腔40相连通。释放孔30用于释放牺牲层，从而形成所述空腔40。
本实施例中，所述释放孔30的数量为多个，从而提高去除牺牲层的效率。
作为一种示例，本实施例中，所述释放孔30贯穿所述压电叠层结构130。
在其他实施例中，所述释放孔还可以贯穿第二衬底，相应的，当空腔的顶部与所述第二衬底之间还保留有粘合层时，释放孔相应贯穿第二衬底、以及位于空腔顶部与第二衬底之间的粘合层。通过使释放孔贯穿第二衬底，有利于防止对压电叠层结构造成损伤，进而有利于提高谐振器的性能。
所述谐振器可以采用前述实施例所述谐振器的形成方法所形成，也可以采用其他谐振器的形成方法所形成。本实施例中，对所述谐振器的具体描述，可参考前述实施例中的相应描述，本实施例在此不再赘述。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (23)

  1. 一种谐振器的形成方法，其特征在于，包括：
    提供第一衬底；
    在所述第一衬底上形成压电叠层结构，所述压电叠层结构包括工作区，所述压电叠层结构与所述第一衬底相接触的面为第一正面；
    在所述工作区上形成覆盖所述压电叠层结构的牺牲层；
    提供第二衬底；
    在所述第二衬底上形成粘合层，所述粘合层与所述第二衬底相接触的面为第二正面，所述粘合层与所述第二正面相背的面为第二背面；
    将所述粘合层的第二背面贴合于所述牺牲层以及所述牺牲层暴露出的压电叠层结构上，使粘合层覆盖所述牺牲层的侧壁且填充于第二衬底与压电叠层结构之间；
    在实现所述贴合后，去除所述第一衬底，暴露出所述压电叠层结构的第一正面；
    形成贯穿所述压电叠层结构的释放孔，或者，形成贯穿所述第二衬底的释放孔，所述释放孔暴露出所述牺牲层；
    通过所述释放孔去除所述牺牲层，形成空腔。
  2. 如权利要求1所述的谐振器的形成方法，其特征在于，在所述第一衬底上形成压电叠层结构之后，形成所述牺牲层之前，所述谐振器的形成方法还包括：在所述工作区的压电叠层结构中形成第一沟槽。
  3. 如权利要求2所述的谐振器的形成方法，其特征在于，所述压电叠层结构包括第一电极层、位于所述第一电极层上的压电层以及位于所述压电层上的第二电极层，所述第一电极层与所述第一衬底相接触的面为所述第一正面；
    形成所述第一沟槽的步骤中，所述第一沟槽的底部暴露出所述第一电极层；
    形成空腔后，所述第一沟槽的开口与所述空腔相连通。
  4. 如权利要求1所述的谐振器的形成方法，其特征在于，在去除所述第一衬底，暴露出所述压电叠层结构的第一正面之后，所述谐振器的形成方法还包括：在所述工作区的压电叠层结构中形成第二沟槽。
  5. 如权利要求4所述的谐振器的形成方法，其特征在于，所述压电叠层结构包括第一电极层、位于所述第一电极层上的压电层以及位于所述压电层上的第二电极层；
    形成所述第二沟槽的步骤中，所述第二沟槽的底部暴露出所述第二电极层；
    在形成所述空腔后，所述第二沟槽与所述空腔由所述第二电极层相隔离。
  6. 如权利要求1所述的谐振器的形成方法，其特征在于，形成所述粘合层的工艺包括旋涂工艺。
  7. 如权利要求1所述的谐振器的形成方法，其特征在于，所述粘合层的材料为可形变材料。
  8. 如权利要求1所述的谐振器的形成方法，其特征在于，所述粘合层的材料包括干膜或粘片膜。
  9. 如权利要求1所述的谐振器的形成方法，其特征在于，采用键合工艺，实现所述贴合。
  10. 如权利要求9所述的谐振器的形成方法，其特征在于，所述键合工艺的温度为50℃至300℃。
  11. 如权利要求1所述的谐振器的形成方法，其特征在于，形成所述粘合层的步骤中，所述粘合层的厚度为0.5μm至40μm。
  12. 如权利要求1所述的谐振器的形成方法，其特征在于，在将所述粘合层的第二背面贴合于所述牺牲层以及所述牺牲层所暴露出的压电叠层结构上的步骤中，所述牺牲层的顶面与所述第二衬底之间还保留有部分厚度的所述粘合层。
  13. 如权利要求12所述的谐振器的形成方法，其特征在于，在将所述粘合层贴合于所述牺牲层以及所述牺牲层所暴露出的压电叠层结构上的步骤中，位于所述牺牲层顶面与所述第二衬底之间的所述粘合层的厚度为0.5μm至35μm。
  14. 如权利要求1所述的谐振器的形成方法，其特征在于，去除所述第一衬底的步骤包括：对所述第一衬底进行研磨处理，去除部分厚度的所述第一衬底；
    在对所述第一衬底进行研磨处理后，采用湿法刻蚀工艺，去除剩余的所述第一衬底。
  15. 如权利要求14所述的谐振器的形成方法，其特征在于，对所述第一衬底进行研磨处理的工艺包括化学机械研磨工艺。
  16. 如权利要求1所述的谐振器的形成方法，其特征在于，在所述第一衬底上形成所述压电叠层结构之前，所述谐振器的形成方法还包括：在所述第一衬底上形成缓冲层；
    在去除所述第一衬底的步骤中，以所述缓冲层作为停止层，去除所述第一衬底；
    在去除所述第一衬底后，所述谐振器的形成方法还包括：去除所述缓冲层。
  17. 如权利要求1或2所述的谐振器的形成方法，其特征在于，形成所述牺牲层的步骤包括：在所述压电叠层结构上形成牺牲材料层；
    对所述牺牲材料层进行平坦化处理；
    对所述牺牲材料层进行平坦化处理之后，图形化所述牺牲材料层，保留位于所述工作区的牺牲材料层作为所述牺牲层。
  18. 一种谐振器，其特征在于，包括：
    衬底；
    粘合层，位于所述衬底上；
    压电叠层结构，位于所述粘合层上，所述压电叠层结构包括工作区，位于所述工作区的压电叠层结构与所述粘合层围成空腔，所述空腔的侧壁暴露出所述粘合层；
    贯穿所述压电叠层结构的释放孔，或者，贯穿所述衬底的释放孔，所述释放孔与所述空腔相连通。
  19. 如权利要求18所述的谐振器，其特征在于，所述粘合层的材料为可形变材料。
  20. 如权利要求18所述的谐振器，其特征在于，所述粘合层的材料包括干膜或粘片膜。
  21. 如权利要求18所述的谐振器，其特征在于，所述压电叠层结构包括第二电极层、位于所述第二电极层上的压电层以及位于所述压电层上的第一电极层，所述第一电极层背向所述第二电极层的面为第一正面，所述第二电极层背向所述第一电极层的面为第一背面；
    所述空腔暴露出所述第二电极层的第一背面。
  22. 如权利要求21所述的谐振器，其特征在于，所述谐振器还包括：第一沟槽，位于所述压电叠层结构中，所述第一沟槽的开口与所述空腔相连通，且所述第一沟槽的底部暴露出所述第一电极层。
  23. 如权利要求21所述的谐振器，其特征在于，所述谐振器还包括：第二沟槽，位于所述压电叠层结构中，所述第二沟槽的底部暴露出所述第二电极层，且所述第二沟槽与所述空腔由所述第二电极层相隔离。
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