WO2022063053A1 - 谐振器制造方法及谐振器 - Google Patents

谐振器制造方法及谐振器 Download PDF

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Publication number
WO2022063053A1
WO2022063053A1 PCT/CN2021/119027 CN2021119027W WO2022063053A1 WO 2022063053 A1 WO2022063053 A1 WO 2022063053A1 CN 2021119027 W CN2021119027 W CN 2021119027W WO 2022063053 A1 WO2022063053 A1 WO 2022063053A1
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Prior art keywords
sacrificial layer
layer pattern
lower electrode
resonator
air gap
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PCT/CN2021/119027
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English (en)
French (fr)
Inventor
唐兆云
唐滨
王家友
赖志国
杨清华
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苏州汉天下电子有限公司
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Priority claimed from CN202011029021.8A external-priority patent/CN112117986B/zh
Priority claimed from CN202011028944.1A external-priority patent/CN112087209B/zh
Application filed by 苏州汉天下电子有限公司 filed Critical 苏州汉天下电子有限公司
Publication of WO2022063053A1 publication Critical patent/WO2022063053A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator

Definitions

  • the present invention relates to a method of manufacturing a resonator, in particular to a method of manufacturing a resonator with at least one air gap.
  • the invention also relates to a resonator, in particular a resonator having at least one air gap.
  • RF filters are used as an intermediary to filter specific frequency signals to reduce signal interference in different frequency bands, and to implement functions such as image cancellation, spurious filtering, and channel selection in wireless transceivers.
  • the design of RF front-end is developing towards miniaturization, low power consumption and integration, and the market has higher and higher requirements for filtering performance. Due to the small size, high operating frequency, low power consumption, high quality factor (Q value), direct With the characteristics of output frequency signal and compatibility with CMOS process, it has become an important device in the field of radio frequency communication and is widely used.
  • FBAR is a thin film device with an electrode-piezoelectric film-electrode sandwich structure fabricated on a substrate material.
  • the structure of FBAR has cavity type, Bragg reflection type (SMR) and backside etching type.
  • SMR Bragg reflection type
  • the cavity type FBAR has higher Q value, lower loss and higher electromechanical coupling coefficient; compared with the backside etching type FBAR, it does not need to remove a large area of the substrate and has higher mechanical strength. Therefore, cavity-type FBAR is the first choice for integration on CMOS devices.
  • the performance of the device is adjusted by controlling the topography size of the air gap.
  • the top electrode is usually fabricated as an arch with an overhanging portion above the substrate, which requires the use of multiple masks. Die and multiple lithography-etching processes are difficult to process, low in machining precision, complex in process, and high in cost, which are not conducive to the overall improvement of device performance.
  • a ring-shaped protrusion (Outie, OT) structure is further formed above the top electrode, and the performance of the device can be adjusted by controlling the topography size of the air gap or protrusion. For this reason, multiple masks and multiple photolithography-etching processes are required, which is difficult to process and has low processing accuracy, which is not conducive to the overall improvement of device performance.
  • the purpose of the present invention is to overcome the above technical obstacles and provide a method for producing a resonator having an air gap and various microstructures with high efficiency and low cost.
  • a method for manufacturing a resonator comprising:
  • the first sacrificial layer pattern and the second sacrificial layer pattern are removed, leaving an air gap between the piezoelectric layer and the lower electrode and a resonant cavity between the lower electrode and the substrate.
  • the step of forming the sacrificial layer pattern includes:
  • a sacrificial layer pattern is formed by etching using the photoresist pattern as a mask.
  • the photoresist pattern after forming the photoresist pattern, it further includes modifying the photoresist pattern to reduce the size.
  • the sacrificial layer pattern includes a central portion, an annular protruding portion outside the central portion is used to form a concave structure, and an annular edge portion outside the annular protruding portion is used to form a frame structure.
  • the thickness of the annular protruding portion is greater than that of the central portion, the thickness of the central portion is greater than that of the annular edge portion, and optionally the thickness of the underground electrode is greater than that of the annular edge portion and smaller than that of the annular protruding portion.
  • the step of forming the second sacrificial layer pattern further includes:
  • the second sacrificial layer is planarized until the central portion of the lower electrode is exposed.
  • the sacrificial layer pattern and the second sacrificial layer pattern are removed by isotropic wet etching.
  • the size of the upper electrode is larger than the size of the sacrificial layer pattern.
  • the lower electrode before forming the lower electrode, it further includes forming a seed layer on the substrate.
  • the resonator cavity and the electrode air gap are simultaneously formed by using the patterned sacrificial layer, and thereby various microstructures such as OT and Innie structures that improve device characteristics are formed, with high efficiency and low cost.
  • the cost increases the performance and reliability of the device.
  • another object of the present invention is to overcome the above technical obstacles and provide a method for manufacturing a resonator with multiple air gaps with high efficiency and low cost.
  • the present invention provides a method for manufacturing a resonator, comprising:
  • the sacrificial layer pattern, the second sacrificial layer pattern, and the third sacrificial layer pattern are removed, leaving a plurality of air gaps.
  • the step of forming the sacrificial layer pattern includes:
  • a sacrificial layer pattern is formed by etching using the photoresist pattern as a mask.
  • the sacrificial layer pattern includes a central portion, an annular protruding portion outside the central portion, and an annular edge portion outside the annular protruding portion; preferably, the thickness of the annular protruding portion is greater than that of the central portion, and the thickness of the central portion is greater than that of the annular edge
  • the thickness of the portion optionally the thickness of the subsurface electrode, is greater than the thickness of the annular edge portion and less than the thickness of the annular protrusion portion.
  • the step of forming the second sacrificial layer pattern further includes:
  • the second sacrificial layer is planarized until the central portion of the lower electrode is exposed.
  • the step of forming the third sacrificial layer pattern further includes:
  • the sacrificial material is planarized until the top of the upper electrode is exposed.
  • the step of removing the sacrificial layer pattern, the second sacrificial layer pattern, and the third sacrificial layer pattern further includes:
  • the sacrificial layer pattern, the second sacrificial layer pattern and the third sacrificial layer pattern are removed by isotropic wet etching, leaving the second air gap and the third air gap.
  • the first air gap is above the edge of the sacrificial layer pattern
  • the second air gap is between the lower electrode and the substrate
  • the third air gap has a first portion between the piezoelectric layer and the lower electrode, A second portion extending vertically outside the first portion and laterally of the piezoelectric layer and the lower electrode, and a third portion extending horizontally between the piezoelectric layer and the lower electrode outside the second portion.
  • the lower electrode before forming the lower electrode, it further includes forming a seed layer on the substrate.
  • the step of forming the through hole exposing the substrate further includes:
  • the upper electrode, the piezoelectric layer, the second sacrificial layer pattern, and the lower electrode are sequentially etched until the substrate is exposed.
  • the size of the upper electrode is larger than the size of the sacrificial layer pattern.
  • a resonator and a plurality of air gaps are simultaneously formed by using a plurality of patterned sacrificial layers to completely surround the resonator, thereby maximizing the suppression of acoustic wave energy loss and effectively improving the Q value.
  • the material of the first sacrificial layer pattern and/or the second sacrificial layer pattern and/or the third sacrificial layer pattern is oxide, preferably a low temperature process such as LPCVD, APCVD, PECVD (deposition temperature is lower than 700 degrees Celsius) , preferably 300 to 600 degrees Celsius) or silicon oxide-based materials manufactured by thermal oxidation processes, such as boron-doped silicon oxide (BSG), phosphorus-doped silicon oxide (PSG), undoped silicon oxide (USG), porous silicon oxide.
  • the sacrificial layer pattern is a buried oxide layer remaining after the semiconductor-on-insulator substrate is etched to remove the top semiconductor layer.
  • the material of the seed layer is metal nitride such as AlN, HfN, HfAlN, TiN, TaN.
  • the material of the lower electrode, the upper electrode, the second electrode and/or the upper electrode is a metal selected from Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg Elements or metal alloys, or conductive oxides, conductive nitrides of these metals, and any combination of the foregoing.
  • the piezoelectric layer is formed by the processes of LPCVD, PECVD, UHVCVD, HDPCVD, MOCVD, MBE, ALD, magnetron sputtering and thermal evaporation, and the material is selected from ZnO, AlN, BST (barium strontium titanate), BT (titanium titanate) Barium oxide), PZT (lead zirconate titanate), PBLN (lead barium lithium niobate), PT (lead titanate) piezoelectric ceramic materials; and preferably, the piezoelectric layer is doped with rare earth elements, such as scandium ( Sc), yttrium (Y), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium ( Any one of Tb),
  • the object according to the invention is also achieved by a resonator.
  • the resonator according to the present invention can preferably be produced by means of the method for producing a resonator according to the present invention.
  • the resonator of the present invention includes: a substrate; a lower electrode above the substrate; a piezoelectric layer and an upper electrode above the lower electrode; wherein a second air gap exists between the substrate and the lower electrode, and the second air gap passes through A first sacrificial layer pattern is formed between the substrate and the lower electrode and the first sacrificial layer pattern is removed; in addition, a part of a third air gap exists between the lower electrode and the piezoelectric layer, and this third air gap is formed by removing the first sacrificial layer pattern.
  • the second sacrificial layer pattern is on the edge portion of the lower electrode (paragraph 53 of specification 209) and the second air gap on the edge portion of the lower electrode; and wherein the second air gap comprises a central portion, an annular protruding portion outside the central portion for forming a recessed structure, and an annular rim portion outside the annular protruding portion; preferably, the annular protruding portion
  • the thickness of the electrode is greater than that of the central portion, the thickness of the central portion is greater than that of the annular edge portion, and the thickness of the optional underground electrode is greater than that of the annular edge portion and smaller than that of the annular protrusion portion.
  • the resonator further comprises at least one additional air gap passing through the upper electrode, the piezoelectric layer and the lower electrode and exposing the substrate, wherein the at least one additional air gap is located at the second outside the annular edge portion of the air gap, and the at least one further air gap constitutes another portion of the third air gap.
  • the resonator further includes a second upper electrode formed on the upper electrode and a dielectric layer formed on the second upper electrode.
  • the first air gap is formed by etching the dielectric layer, the second upper electrode, and the upper electrode to expose the piezoelectric layer, wherein the first air gap serves as a periphery of the upper electrode structure.
  • the size of the upper electrode is larger than that of the second air gap.
  • the resonator includes a seed layer between the substrate and the lower electrode.
  • Figures 1-14 show cross-sectional views of various stages of a resonator fabrication process in accordance with embodiments of the present invention.
  • Figure 15 shows a flow diagram of a resonator fabrication process according to an embodiment of the first aspect of the invention.
  • Figure 16 shows a flow diagram of a resonator fabrication process according to an embodiment of the second aspect of the invention. .
  • a (first) sacrificial layer 11 is formed on the substrate 10 .
  • Substrate 10 is provided, and the material can be bulk Si or silicon-on-insulator (SOI) or bulk Ge, GeOI to be compatible with CMOS process and integrated with other digital and analog circuits, and can also be a compound for MEMS, optoelectronic devices, power devices Semiconductors such as GaN, GaAs, SiC, InP, GaP, etc., further preferably, the substrate 10 is a single crystal material, and most preferably, the substrate 10 has a low concentration of doping or is not doped so as to have high resistance.
  • the deposition process of the sacrificial layer 11 can be a low temperature process such as LPCVD, APCVD, PECVD (deposition temperature is lower than 700 degrees Celsius, preferably 300 to 600 degrees Celsius), and the material is a silicon oxide-based material, such as boron-doped silicon oxide (BSG), phosphorus-doped oxide Silicon (PSG), Undoped Silicon Oxide (USG), Porous Silicon Oxide, etc.
  • LPCVD low temperature
  • APCVD APCVD
  • PECVD deposition temperature is lower than 700 degrees Celsius, preferably 300 to 600 degrees Celsius
  • the material is a silicon oxide-based material, such as boron-doped silicon oxide (BSG), phosphorus-doped oxide Silicon (PSG), Undoped Silicon Oxide (USG), Porous Silicon Oxide, etc.
  • the sacrificial 11 is manufactured by a thermal oxidation process, or is a buried oxide layer exposed after the semiconductor-on-insulator substrate such as SOI and GeOI is stripped of the top semiconductor thin layer.
  • the initial (first) thickness of the sacrificial layer 11 is a, eg, 50-5000 nm, which determines the height of the annular protrusion of the resonant cavity to be formed in the future.
  • the sacrificial layer 11 is etched to form a sacrificial layer pattern.
  • a photoresist is coated on the sacrificial layer 11 and exposed and developed to obtain a photoresist pattern 12 , and the sacrificial layer 11 is anisotropically etched using the photoresist pattern 12 as a mask to obtain a sacrificial layer pattern , which includes a (first) central portion 11A with a thickness a covered by the photoresist pattern 12 , and a (second) edge portion 11B not covered by the photoresist pattern 12 with a (second) thickness b.
  • the thickness b is smaller than a, for example, the thickness b is 10-2000 nm, which determines the height of the annular periphery of the resonator in the future.
  • Anisotropic etching processes such as plasma dry etching or reactive ion etching, etching gases such as fluorocarbon-based etching gases, such as CF4, CHF3, CH2F2, CH3F, etc., Cl2, HCl, Br2, Other halogen-based gases such as HBr, and may further include oxidizing gases to adjust the etching rate and remove residues.
  • the photoresist pattern 12 is modified, eg, reduced in size, by using a process such as exposure development or laser ablation to obtain a second photoresist pattern 12 ′, and the second photoresist pattern 12 is modified with the second photoresist pattern 12 .
  • the pattern of the sacrificial layer is anisotropically etched again for the mask, and the obtained pattern includes a central portion 11A' and an edge portion 11B', the thicknesses of which are a and b' respectively, and b' is less than or equal to b, eg, 5-1000 nm.
  • the process shown in FIG. 3 is used to indent the sacrificial layer pattern toward the center of the device to leave sufficient dicing area between adjacent device cells.
  • the pattern includes a central portion 11C, an annular protruding portion 11A' at the periphery of the central portion for forming a concave (inner protruding) structure, and an outermost annular edge portion 11B' for forming an outtie (outtie) structure.
  • the central part 11C corresponds to the main part of the future resonant cavity to control the resonant performance of the device, and its thickness is c, preferably a>c>b', c for example 8-1500 nm.
  • the annular protruding portion 11A' corresponds to the arched portion of the future resonant cavity to reduce edge scattering of acoustic waves and condense the energy of acoustic waves, and its thickness maintains the original thickness a of the sacrificial layer.
  • the annular edge portion 11B' corresponds to the edge of the future resonant cavity to reduce the fringing electric field and avoid energy overflow, and its thickness is b'.
  • the photoresist pattern 12" is removed by a process such as wet etching or dry ashing.
  • a lower electrode 13 is formed on the substrate 10 and the sacrificial layer pattern.
  • magnetron sputtering, thermal evaporation, MOCVD, etc. are used to form the lower electrode 13 on the substrate 10 and the sacrificial layer pattern, and its material is such as Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr , Fe, Mg and other metal elements or metal alloys, or conductive oxides, conductive nitrides of these metals, and any combination of the above materials.
  • the portion of the lower electrode in the center is labeled 13A.
  • a pad layer or seed layer (not shown) may be further formed on the sacrificial layer pattern and the substrate, and its material is the same or similar to the lower electrode or piezoelectric layer to be formed in the future.
  • Deposition processes such as magnetron sputtering, thermal evaporation, MOCVD, etc.
  • the material of the liner layer or the seed layer is metal nitride, such as AlN, HfN, HfAlN, TiN, TaN, etc., and preferably can be used as a barrier to prevent the downward migration of the lower electrode metal material at the same time Floor.
  • the lower electrode has a thickness d, which is greater than b and less than a.
  • a second sacrificial layer pattern is formed on the lower electrode.
  • a second sacrificial layer 14 is formed on the lower electrode 13 , and its material and process are the same as those of the sacrificial layer 11 .
  • the second sacrificial layer 14 is planarized, eg, using etch-back or CMP, until the top of the central portion 13A of the lower electrode is exposed.
  • the second sacrificial layer has a reserved pattern 14' on the edge portion of the lower electrode, which corresponds to the air gap under the piezoelectric layer of the upper electrode of the future resonant cavity, so the height difference between the protruding portion 11A' of the sacrificial layer pattern and the peripheral portion 11B' affects the The thickness of the air gap.
  • a piezoelectric layer 15 and an upper electrode 16 are formed on the lower electrode 13 and the second sacrificial layer pattern 14'.
  • the piezoelectric layer 15 is formed by processes such as LPCVD, PECVD, UHVCVD, HDPCVD, MOCVD, MBE, ALD, magnetron sputtering, thermal evaporation, etc., and materials such as ZnO, AlN, BST (barium strontium titanate), BT (barium titanate) ), PZT (lead zirconate titanate), PBLN (lead barium lithium niobate), PT (lead titanate) and other piezoelectric ceramic materials; and preferably, the piezoelectric layer 15 is doped with rare earth elements, such as scandium (Sc ), yttrium (Y), lanthanum (La), cerium (Ce), praseodymium (Pr), neodym
  • the upper electrode 16 is formed on the piezoelectric layer 15 , and its material and process are the same as or similar to those of the lower electrode 13 .
  • the upper electrode layer is etched so that the size of the upper electrode pattern is larger than that of the sacrificial layer pattern, so that a second sacrificial layer pattern (corresponding to the future air gap) is sandwiched between the upper electrode and the lower electrode, thereby accurately adjusting The frequency response characteristics of the device.
  • the air gap includes a first portion 17A between the upper electrode piezoelectric layer 15 and the lower electrode 13, and is used to adjust the acoustic wave reflection performance at the edge of the device, reduce energy consumption, and improve the Q value.
  • the air gap also includes a resonant cavity in front of the lower electrode 13 and the substrate 10, and the resonant cavity includes a central portion 17B3, a central annular protrusion 17B1 (ie, the final recessed structure), and an outermost annular edge 17B2 (ie, the final frame structure) ), the heights of which are respectively the aforementioned c, a, and b', and what needs to be ensured here is the thickness of the second electrode 13A.
  • Removal process such as isotropic wet etching process, such as sacrificial layer and second sacrificial layer for silicon oxide based materials, using HF based etching solutions such as dHF (diluted HF), dBOE (slow release etchant, HF and NH4F) mixture).
  • HF based etching solutions such as dHF (diluted HF), dBOE (slow release etchant, HF and NH4F) mixture).
  • the patterned sacrificial layer is used to form the resonator cavity and the electrode air gap at the same time, thereby forming a variety of microstructures such as OT and Innie structures that improve device characteristics, with high efficiency and low cost. device performance and reliability.
  • a (first) sacrificial layer 11 is formed on the substrate 10 .
  • Substrate 10 is provided, and the material can be bulk Si or silicon-on-insulator (SOI) or bulk Ge, GeOI to be compatible with CMOS process and integrated with other digital and analog circuits, and can also be a compound for MEMS, optoelectronic devices, power devices Semiconductors such as GaN, GaAs, SiC, InP, GaP, etc., further preferably, the substrate 10 is a single crystal material, and most preferably, the substrate 10 has a low concentration of doping or is not doped so as to have high resistance.
  • the deposition process of the sacrificial layer 11 can be a low temperature process such as LPCVD, APCVD, PECVD (deposition temperature is lower than 700 degrees Celsius, preferably 300 to 600 degrees Celsius), and the material is a silicon oxide-based material, such as boron-doped silicon oxide (BSG), phosphorus-doped oxide Silicon (PSG), Undoped Silicon Oxide (USG), Porous Silicon Oxide, etc.
  • LPCVD low temperature
  • APCVD APCVD
  • PECVD deposition temperature is lower than 700 degrees Celsius, preferably 300 to 600 degrees Celsius
  • the material is a silicon oxide-based material, such as boron-doped silicon oxide (BSG), phosphorus-doped oxide Silicon (PSG), Undoped Silicon Oxide (USG), Porous Silicon Oxide, etc.
  • the sacrificial 11 is manufactured by a thermal oxidation process, or is a buried oxide layer exposed after the semiconductor-on-insulator substrate such as SOI and GeOI is stripped of the top semiconductor thin layer.
  • the initial (first) thickness of the sacrificial layer 11 is a, eg, 50-5000 nm, which determines the height of the annular protrusion of the resonant cavity to be formed in the future.
  • the sacrificial layer 11 is etched to form a sacrificial layer pattern.
  • a photoresist is coated on the sacrificial layer 11 and exposed and developed to obtain a photoresist pattern 12 , and the sacrificial layer 11 is anisotropically etched using the photoresist pattern 12 as a mask to obtain a sacrificial layer pattern , which includes a (first) central portion 11A with a thickness a covered by the photoresist pattern 12 , and a (second) edge portion 11B not covered by the photoresist pattern 12 with a (second) thickness b.
  • the thickness b is smaller than a, for example, the thickness b is 10-2000 nm, which determines the height of the annular periphery of the resonator in the future.
  • Anisotropic etching processes such as plasma dry etching or reactive ion etching, etching gases such as fluorocarbon-based etching gases, such as CF4, CHF3, CH2F2, CH3F, etc., Cl2, HCl, Br2, Other halogen-based gases such as HBr, and may further include oxidizing gases to adjust the etching rate and remove residues.
  • the photoresist pattern 12 is modified, eg, reduced in size, by using a process such as exposure development or laser ablation to obtain a second photoresist pattern 12 ′, and the second photoresist pattern 12 is modified with the second photoresist pattern 12 .
  • the pattern of the sacrificial layer is anisotropically etched again for the mask, and the obtained pattern includes a central portion 11A' and an edge portion 11B', the thicknesses of which are a and b' respectively, and b' is less than or equal to b, eg, 5-1000 nm.
  • the process shown in FIG. 3 is used to indent the sacrificial layer pattern toward the center of the device to leave sufficient dicing area between adjacent device cells.
  • a part of the photoresist pattern is removed to leave a third photoresist pattern 12", and the third photoresist pattern 12" is used as a mask to etch the central part of the sacrificial layer pattern, and finally the sacrificial layer is obtained.
  • the pattern includes a central portion 11C, an annular protruding portion 11A' at the periphery of the central portion, and an outermost annular edge portion 11B'.
  • the central part 11C corresponds to the main part of the future resonant cavity to control the resonant performance of the device, and its thickness is c, preferably a>c>b', c for example 8-1500 nm.
  • the annular protruding portion 11A' corresponds to the arched portion of the future resonant cavity to reduce edge scattering of acoustic waves and condense the energy of acoustic waves, and its thickness maintains the original thickness a of the sacrificial layer.
  • the annular edge portion 11B' corresponds to the edge of the future resonant cavity to reduce the fringing electric field and avoid energy overflow, and its thickness is b'.
  • the photoresist pattern 12" is removed by a process such as wet etching or dry ashing. In this way, the traditional annular protrusion structure located on the top of the upper electrode is formed at the lower electrode, and fewer photoresists can be used to form the required device. OT (outie) structure, OT structure is very helpful for improving the Q value of the device.
  • a lower electrode 13 is formed on the substrate 10 and the sacrificial layer pattern.
  • magnetron sputtering, thermal evaporation, MOCVD, etc. are used to form the lower electrode 13 on the substrate 10 and the sacrificial layer pattern, and its material is such as Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr , Fe, Mg and other metal elements or metal alloys, or conductive oxides, conductive nitrides of these metals, and any combination of the above materials.
  • the portion of the lower electrode in the center is labeled 13A.
  • a pad layer or seed layer (not shown) may be further formed on the sacrificial layer pattern and the substrate, and its material is the same or similar to the lower electrode or piezoelectric layer to be formed in the future.
  • Deposition processes such as magnetron sputtering, thermal evaporation, MOCVD, etc.
  • the material of the liner layer or the seed layer is metal nitride, such as AlN, HfN, HfAlN, TiN, TaN, etc., and preferably can be used as a barrier to prevent the downward migration of the lower electrode metal material at the same time Floor.
  • the lower electrode has a thickness d, which is greater than b and less than a.
  • a second sacrificial layer pattern is formed on the lower electrode.
  • a second sacrificial layer 14 is formed on the lower electrode 13 , and its material and process are the same as those of the sacrificial layer 11 .
  • the second sacrificial layer 14 is planarized, eg, using etch-back or CMP, until the top of the central portion 13A of the lower electrode is exposed.
  • the second sacrificial layer has a reserved pattern 14' on the edge portion of the lower electrode, which corresponds to the air gap below the upper electrode of the resonant cavity in the future, so the height difference between the protruding portion 11A' of the sacrificial layer pattern and the peripheral portion 11B' affects the air gap. thickness.
  • the piezoelectric layer 15 and the upper electrode 16 are formed on the lower electrode 13 and the second sacrificial layer pattern 14'.
  • the piezoelectric layer 15 is formed by processes such as LPCVD, PECVD, UHVCVD, HDPCVD, MOCVD, MBE, ALD, magnetron sputtering, thermal evaporation, etc., and materials such as ZnO, AlN, BST (barium strontium titanate), BT (barium titanate) ), PZT (lead zirconate titanate), PBLN (lead barium lithium niobate), PT (lead titanate) and other piezoelectric ceramic materials; and preferably, the piezoelectric layer 15 is doped with rare earth elements, such as scandium (Sc ), yttrium (Y), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (N
  • the upper electrode 16 , the piezoelectric layer 15 , the second sacrificial layer pattern 14 ′, and the lower electrode 13 are etched to form through holes exposing the substrate 10 .
  • a hard mask 17 is preferably deposited on the upper electrode 16 first, and its material is such as silicon oxide, silicon nitride or silicon oxynitride, and the deposition process is such as PECVD, HDPCVD, MBE, ALD and so on.
  • a photoresist pattern (not shown), use the photoresist pattern as a mask to etch the hard mask 17 to form a hard mask pattern, and then use the hard mask pattern as a mask to use various Anisotropic etching process, such as plasma dry etching or reactive ion etching, sequentially etches the upper electrode 16, the piezoelectric layer 15, the second sacrificial layer pattern 14', and the lower electrode 13 downward until the substrate 10 is exposed surface, the through hole 17A is formed outside the annular edge portion 11B' of the first sacrificial layer pattern.
  • various Anisotropic etching process such as plasma dry etching or reactive ion etching
  • the third sacrificial layer pattern 18 is formed in the through hole 17A.
  • Sacrificial materials such as silicon oxide, silicon nitride, silicon oxynitride, etc.
  • the sacrificial layer material is processed by a planarization process such as etch back or CMP until the top of the upper electrode 16 is exposed, so that the top of the third sacrificial layer pattern 18 is flush with the top of the upper electrode 16 .
  • the third sacrificial layer pattern 18 is shown as a solid structure in FIG. 10 , due to the low filling rate of the through hole 17A with a large aspect ratio due to the deposition process, the third sacrificial layer pattern 18 may be premature due to the material of the sacrificial layer. closed with air bubbles or gaps (not shown) inside.
  • the sacrificial layer pattern 11, the second sacrificial layer pattern 14', and the third sacrificial layer pattern 18 are removed, leaving a plurality of air gaps to completely surround the resonator.
  • a second upper electrode 16B is further preferably formed on the upper electrode 16 and the third sacrificial layer pattern 18, and its process and material can be the same as or similar to the upper electrode 16, so that the conductive material is formed in the first
  • the top surface of the three sacrificial layer pattern 18 is completely surrounded by its top surface and a part of the side surface, that is, surrounded by three sides, which is used as the electrode lead-out area of the final device, and the thickened upper electrode stack can effectively reduce the contact resistance and improve the performance of the resonator.
  • a dielectric layer 15B is formed on the second upper electrode 16B, and the deposition process is such as PECVD, HDPCVD, MBE, ALD, etc., and the material is such as oxide, nitride, oxynitride, etc., such as silicon oxide, nitride Silicon, aluminum nitride, etc., for passivation to protect the upper electrode stack.
  • the deposition process is such as PECVD, HDPCVD, MBE, ALD, etc.
  • the material is such as oxide, nitride, oxynitride, etc., such as silicon oxide, nitride Silicon, aluminum nitride, etc., for passivation to protect the upper electrode stack.
  • photoresist is spin-coated on the entire device, exposed and developed to form a photoresist pattern 19 , and the dielectric layer 15B, the second upper electrode 16B and the upper electrode 16 are sequentially etched using the photoresist pattern 19 as a mask.
  • the second through hole 19A formed above near the edge of the sacrificial layer pattern serves as a first air gap around the upper electrode structure, while also separating the body structure of the resonator from the pad lead-out area, Effectively avoid the leakage of sonic energy.
  • the photoresist pattern 19 may then be removed by wet etching or dry ashing.
  • an isotropic wet etching process is used, such as using an HF-based etching solution for silicon oxide-based materials such as dHF (diluted HF), dBOE (slow release etchant, a mixture of HF and NH4F), and at the same time
  • dHF diluted HF
  • dBOE slow release etchant
  • a mixture of HF and NH4F silicon oxide-based materials
  • the sacrificial layer pattern 11, the second sacrificial layer pattern 14' and the third sacrificial layer pattern 18 are removed, leaving the second air gap and the third air gap, which are used to adjust the acoustic wave reflection performance at the edge of the device, reduce energy consumption, and improve the Q value .
  • the second air gap is located between the lower electrode 13 and the substrate 10, and serves as a resonant cavity of the device, including a central portion 19B3, a central annular protrusion 19B1, and an outermost annular edge 19B2, the heights of which are respectively the aforementioned c, a, and b. '.
  • the third air gap 19C corresponds to the space occupied by the second sacrificial layer pattern 14 ′ and the third sacrificial layer pattern 18 , and has a first portion recessed inward between the piezoelectric layer 15 and the lower electrode 13 as shown in FIG.
  • the second part extending vertically outside the first part, the sides of the piezoelectric layer 15 and the lower electrode 13 is used to reduce the leakage of sound waves at the end faces of the piezoelectric layer and the lower electrode, and at the second part.
  • a third portion extending outwardly from a portion outside between the piezoelectric layer 15 and the lower electrode 13 is used to reduce crosstalk between adjacent resonator units or reduce scribe area stress to avoid damage.
  • multiple patterned sacrificial layers are used to simultaneously form a resonator cavity and multiple air gaps to completely surround the resonator cavity, thereby maximizing the suppression of acoustic wave energy loss and effectively improving the Q value.

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Abstract

一种谐振器制造方法，包括：在衬底上形成牺牲层图形；在牺牲层图形上形成下电极；在下电极上形成第二牺牲层图形；在第二牺牲层图形和下电极上形成压电层和上电极；可选地形成第三牺牲层图形；去除牺牲层图形，留下气隙并形成谐振腔。本发明还涉及一种谐振器。

Description

谐振器制造方法及谐振器 技术领域
本发明涉及一种谐振器制造方法，特别是一种具有至少一个气隙的谐振器的制造方法。本发明还涉及一种谐振器，特别是一种具有至少一个气隙的谐振器。
背景技术
在无线通讯中，射频滤波器作为过滤特定频率信号的中介，用于减少不同频段的信号干扰，在无线收发器中实现镜像消除、寄生滤波和信道选择等功能。随着4GLTE网络的部署和市场的增长，射频前端的设计朝着小型化、低功耗和集成化的方向发展，市场对滤波性能的要求也越来越高。由于薄膜体声波谐振器(FilmBulkAcousticResonator，简称“FBAR”，也称“体声波”，BulkAcousticWave，简称“BAW”，)具有尺寸小、工作频率高、功耗低、品质因数(Q值)高、直接输出频率信号、与CMOS工艺兼容等特点，目前已经成为射频通讯领域重要的器件被广泛应用。
FBAR是制作在衬底材料上的电极——压电膜——电极的三明治结构的薄膜器件。FBAR的结构有空腔型、布拉格反射型(SMR)和背面刻蚀型。其中空腔型FBAR相对SMR型Q值要高，损耗要小，机电耦合系数要高；相对于背面刻蚀型FBAR不需要去掉大面积的衬底，机械强度较高。因此，空腔型FBAR是集成于CMOS器件上的首选。
在传统的制造工艺中，为了改善谐振器的性能例如提高Q值，在一些实施方式中，需要在顶部电极与压电层之间留下气隙，形成各种微结构(诸如框架结构(OT，outie)，凹陷结构(Innie)，通过控制气隙的形貌尺寸而调节器件的性能。为此，通常将顶电极制造为具有在衬底之上悬垂部分的拱形，这需要采用多重掩模和多次光刻-刻蚀处理，加工难度大，加工精度低，工艺复杂，成本高，不利于器件性能的整体提高。
而在另一些实施方式中，为了改善谐振器的性能例如提高Q值，需要将谐振器单元结构在顶部和底部形成空气腔隔离，例如在顶部电极与压电层之间留下气隙、而在顶电极上方进一步形成环形突起(Outie，OT)结构，通过控制气隙或突起的形貌尺寸而调节器件的性能。为此，需要采用多重掩模而多次光刻-刻蚀处理，加工难度大，加工精度低，不利于器 件性能的整体提高。另一方面，传统的器件和工艺仅能在顶部电极上方形成气隙，而声波能量同样可以顺着压电层或下电极在水平面上从侧面泄漏，或者在谐振腔与衬底之间的边界处泄漏，因此无法最大化抑制声波能量损失，Q值提升有限。
发明内容
因此，在本发明的第一方面中，本发明的目的在于克服以上技术障碍而提供一种高效低成本制造具有气隙和各种微结构的的谐振器的方法。
在本发明的第一方面中，提供了一种谐振器制造方法，包括：
在衬底上形成第一牺牲层图形；
在第一牺牲层图形上形成下电极；
在下电极上形成第二牺牲层图形；
在第二牺牲层图形和下电极上形成压电层和上电极；
去除第一牺牲层图形和第二牺牲层图形，在压电层和下电极之间留下气隙并在下电极和衬底之间留下谐振腔。
其中，形成牺牲层图形的步骤包括：
在衬底上形成牺牲层；
在牺牲层上形成光刻胶图形；
以光刻胶图形为掩模刻蚀形成牺牲层图形。
其中，形成光刻胶图形之后进一步包括修饰光刻胶图形以缩减尺寸。
其中，牺牲层图形包括中心部分，在中心部分外侧的环形突起部分用于形成凹陷结构，以及在环形突起部分外侧的环形边缘部分用于形成框架结构。
其中，环形突起部分的厚度大于中心部分的厚度，中心部分的厚度大于环形边缘部分的厚度，任选地下电极的厚度大于环形边缘部分的厚度且小于环形突起部分的厚度。
其中，形成第二牺牲层图形的步骤进一步包括：
在下电极上形成第二牺牲层；
平坦化第二牺牲层直至暴露下电极的中心部分。
其中，采用各向同性的湿法腐蚀去除牺牲层图形和第二牺牲层图形。
其中，上电极的尺寸大于牺牲层图形的尺寸。
其中，形成下电极之前进一步包括在衬底上形成种子层。
依照本发明的第一方面的谐振器制造方法，利用图形化的牺牲层同时形成谐振腔和电极气隙，并以此形成了多种改善器件特性的微结构如OT和Innie结构，高效且低成本了提高了器件的性能和可靠性。
在本发明的第二方面中，在本发明的另一目的在于克服以上技术障碍而提供一种高效低成本制造具有多个气隙的谐振器的方法。
在本发明的第二方面中，本发明提供了一种谐振器制造方法，包括：
在衬底上形成牺牲层图形；
在牺牲层图形上形成下电极；
在下电极上形成第二牺牲层图形；
在第二牺牲层图形和下电极上形成压电层和上电极；
刻蚀上电极、压电层、第二牺牲层图形、下电极形成暴露衬底的通孔；
在通孔中形成第三牺牲层图形；
去除牺牲层图形、第二牺牲层图形、第三牺牲层图形，留下多个气隙。
其中，形成牺牲层图形的步骤包括：
在衬底上形成牺牲层；
在牺牲层上形成光刻胶图形；
修饰光刻胶图形以缩减尺寸；
以光刻胶图形为掩模刻蚀形成牺牲层图形。
其中，牺牲层图形包括中心部分，在中心部分外侧的环形突起部分，以及在环形突起部分外侧的环形边缘部分；优选地，环形突起部分的厚度大于中心部分的厚度，中心部分的厚度大于环形边缘部分的厚度，任选地下电极的厚度大于环形边缘部分的厚度且小于环形突起部分的厚度。
其中，形成第二牺牲层图形的步骤进一步包括：
在下电极上形成第二牺牲层；
平坦化第二牺牲层直至暴露下电极的中心部分。
其中，形成第三牺牲层图形的步骤进一步包括：
在通孔和上电极上形成牺牲材料；
平坦化牺牲材料直至暴露上电极顶部。
其中，去除牺牲层图形、第二牺牲层图形、第三牺牲层图形的步骤进一步包括：
在上电极上形成第二上电极；
在第二上电极上形成介质层；
刻蚀介质层、第二上电极、上电极直至暴露压电层，留下第一气隙；
采用各向同性湿法腐蚀去除牺牲层图形、第二牺牲层图形、第三牺牲层图形，留下第二气隙和第三气隙。
其中，第一气隙在牺牲层图形的边缘上方，任选地第二气隙在下电极和衬底之间，任选地第三气隙具有在压电层和下电极之间的第一部分、在第一部分外在压电层和下电极侧面垂直延伸的第二部分、以及在第二部分外在压电层和下电极之间水平延伸的第三部分。
其中，形成下电极之前进一步包括在衬底上形成种子层。
其中，形成暴露衬底的通孔的步骤进一步包括：
在上电极上形成硬掩模图形；
以硬掩模图形为掩模依次刻蚀上电极、压电层、第二牺牲层图形、下电极直至暴露衬底。
其中，上电极的尺寸大于牺牲层图形的尺寸。
依照本发明的第二方面的谐振器制造方法，利用图形化的多个牺牲层同时形成谐振腔和多个气隙以完全包围谐振腔，最大化抑制了声波能量损失，有效提高了Q值。
在本发明中，第一牺牲层图形和/或第二牺牲层图形和/或第三牺牲层图形的材质为氧化物，优选地为LPCVD、APCVD、PECVD等低温工艺(沉积温度低于700摄氏度，优选300至600摄氏度)或热氧化工艺制造的氧化硅基材料，诸如掺硼氧化硅(BSG)、掺磷氧化硅(PSG)、未掺杂氧化硅(USG)、多孔氧化硅。任选地，牺牲层图形为对绝缘体上半导体衬底刻蚀去除顶部半导体层之后剩余的埋氧层。
此外，在本发明中，种子层的材质为金属氮化物例如AlN、HfN、 HfAlN、TiN、TaN。
其中，在本发明中，下电极、上电极、第二和/或上电极的材料为选自Mo、W、Ru、Al、Cu、Ti、Ta、In、Zn、Zr、Fe、Mg的金属单质或金属合金，或者这些金属的导电氧化物、导电氮化物，以及上述材料的任意组合。
其中，采用LPCVD、PECVD、UHVCVD、HDPCVD、MOCVD、MBE、ALD、磁控溅射、热蒸发的工艺形成压电层，材质为选自ZnO、AlN、BST(钛酸锶钡)、BT(钛酸钡)、PZT(锆钛酸铅)、PBLN(铌酸铅钡锂)、PT(钛酸铅)的压电陶瓷材料；且优选地，压电层中掺杂稀土元素，例如包含钪(Sc)、钇(Y)、镧(La)、铈(Ce)、镨(Pr)、钕(Nd)、钷(Pm)、钐(Sm)、铕(Eu)、钆(Gd)、铽(Tb)、镝(Dy)、钬(Ho)、铒(Er)、铥(Tm)、镱(Yb)及镥(Lu)的任一种及其组合，以提高压电系数。
在本发明的第三方面中，根据本发明的目的还通过一种谐振器来实现。优选的是，根据本发明的谐振器优选地可以借助于根据本发明的谐振器的制造方法来制造。本发明的谐振器包括：衬底；衬底上方的下电极；下电极上方的压电层和上电极；其中在衬底和下电极之间存在第二气隙，所述第二气隙通过在衬底和下电极之间构成第一牺牲层图形并去除第一牺牲层图形来构成；此外，在下电极和压电层之间存在第三气隙的一部分，所述第三气隙的该部分通过在下电极和压电层之间构成第二牺牲层图形并去除第二牺牲层图形来构成，其中第二牺牲层图形处于下电极边缘部分上(说明书209的53段)进而第二气隙处于下电极边缘部分上；并且其中所述第二气隙包括中心部分，在中心部分外侧的环形突起部分用于形成凹陷结构，以及在环形突起部分外侧的环形边缘部分；优选地，环形突起部分的厚度大于中心部分的厚度，中心部分的厚度大于环形边缘部分的厚度，任选地下电极的厚度大于环形边缘部分的厚度且小于环形突起部分的厚度。
优选地，谐振器还包括至少一个另外的气隙，所述至少一个另外的气隙穿过上电极、压电层和下电极并暴露衬底，其中所述至少一个另外的气隙位于第二气隙的环形边缘部分的外侧，并且所述至少一个另外的气隙构成第三气隙的另一部分。
优选地，谐振器还包括在上电极上形成的第二上电极和在第二上电极上形成的介质层。
优选地，通过刻蚀介质层、第二上电极、上电极至暴露压电层构成第 一气隙，其中，第一气隙用作上电极结构周围。
优选地，上电极的尺寸大于第二气隙的尺寸。
还优选的是，谐振器包括处于衬底和下电极之间的种子层。
需要说明的是，对于本领域技术人员而言，在本发明的方法方面所提出的技术特征、实施方式和优点可以容易地转移到根据本发明的设备，并且反之亦然。
本发明所述目的，以及在此未列出的其他目的，在本申请独立权利要求的范围内得以满足。本发明的实施例限定在独立权利要求中，具体特征限定在其从属权利要求中。
附图说明
以下参照附图来详细说明本发明的技术方案，其中：
图1至图14显示了根据本发明实施例的谐振器制造工艺各个阶段的剖视图；以及
图15显示了根据本发明的第一方面的实施例的谐振器制造工艺的流程图。
图16显示了根据本发明的第二方面的实施例的谐振器制造工艺的流程图。。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果，公开了高效低成本制造具有一个或多个气隙的谐振器的方法。需要指出的是，类似的附图标记表示类似的结构，本申请中所用的术语“第一”、“第二”、“上”、“下”等等可用于修饰各种器件结构。这些修饰除非特别说明并非暗示所修饰器件结构的空间、次序或层级关系。。
本发明的第一方面的实施例
如图1、图15所示，在衬底10上形成(第一)牺牲层11。提供衬底10，材质可以是体Si或绝缘体上硅(SOI)或者体Ge、GeOI以与CMOS工艺兼容并与其他数字、模拟电路集成，也可以是用于MEMS、光电器件、功率器件的化合物半导体例如GaN、GaAs、SiC、InP、GaP等，进一步优选地，衬底10 是单晶材料，且最佳地，衬底10具有低浓度掺杂或者不掺杂从而具有高电阻。与传统的谐振器制造工艺不同，本发明的制造工艺中不必在衬底10中刻蚀谐振腔，因而避免了刻蚀工艺增多衬底表面缺陷。牺牲层11的沉积工艺可以为LPCVD、APCVD、PECVD等低温工艺(沉积温度低于700摄氏度，优选300至600摄氏度)，材质为氧化硅基材料，诸如掺硼氧化硅(BSG)、掺磷氧化硅(PSG)、未掺杂氧化硅(USG)、多孔氧化硅等等。在本发明其他实施例中，牺牲11为热氧化工艺制造，或者是SOI、GeOI等绝缘体上半导体衬底剥离了顶部半导体薄层之后暴露的埋氧层。牺牲层11的初始(第一)厚度为a，例如50-5000nm，其决定了未来要形成的谐振腔的环形突起的高度。
如图2至图4、图15所示，刻蚀牺牲层11形成牺牲层图形。首先，如图2所示，在牺牲层11上涂覆光刻胶并曝光显影得到光刻胶图形12，以光刻胶图形12为掩模各向异性刻蚀牺牲层11而得到牺牲层图形，其包括被光刻胶图形12所覆盖的具有厚度a的(第一)中心部分11A，以及未被光刻胶图形12覆盖的具有(第二)厚度b的(第二)边缘部分11B。厚度b小于a，例如厚度b为10-2000nm，其决定了未来谐振腔环形周缘的高度。各向异性刻蚀工艺例如等离子体干法刻蚀或反应离子刻蚀，刻蚀气体例如碳氟基刻蚀气体，诸如CF4、CHF3、CH2F2、CH3F等等，也可以采用Cl2、HCl、Br2、HBr等其他卤素基气体，并可以进一步包括氧化性气体以调节刻蚀速度、去除残渣。
随后任选地，如图3所示，采用曝光显影或激光烧蚀等工艺，修饰光刻胶图形12例如缩减尺寸以获得第二光刻胶图形12’，并以第二光刻胶图形12’为掩模再次各向异性刻蚀牺牲层图形，得到的图形包括中心部分11A’和边缘部分11B’，两者厚度分别是a和b’，b’小于等于b例如为5-1000nm。图3所示工艺用于使得牺牲层图形向器件中心缩进，以在相邻器件单元之间留下足够的划片分割区域。
如图4所示，去除一部分光刻胶图形而留下第三光刻胶图形12”，以第三光刻胶图形12”为掩模刻蚀牺牲层图形的中心部分，最终得到的牺牲层图形包括中心部分11C、在中心部分外围的环形突起部分11A’用于形成凹陷(内侧突起)结构、以及在最外侧的环形边缘部分11B’用于形成框架(outtie，最外侧突出)结构。中心部分11C对应于未来谐振腔的主体部分以控制器件谐振性能，其厚度为c，优选地a>c>b’,c例如为8-1500nm。环形突起部分11A’对应于未来谐振腔的拱起部分以降低声波边缘散射、会聚声波能量，其厚度保持牺牲层原始厚度a。环形边缘部分11B’对应于未来谐振腔的边缘以减小边缘电场、避免能量外溢，其厚度为b’。通过湿法腐蚀或干法灰化等工艺，去除光 刻胶图形12”。
如图5、图15所示，在衬底10和牺牲层图形上形成下电极13。例如采用磁控溅射、热蒸发、MOCVD等，在衬底10和牺牲层图形之上形成下电极13，其材质例如Mo、W、Ru、Al、Cu、Ti、Ta、In、Zn、Zr、Fe、Mg等金属单质或金属合金，或者这些金属的导电氧化物、导电氮化物，以及上述材料的任意组合。下电极在中心的部分标记为13A。优选地，在形成下电极13之前可以进一步在牺牲层图形和衬底上形成衬垫层或种子层(未示出)，其材质与未来将要形成的下电极或压电层相同或相近，用于提高下电极边缘处的外延生长质量且提高与下电极之间的粘附力。沉积工艺例如磁控溅射、热蒸发、MOCVD等。在本发明一个优选实施例中，衬垫层或种子层材质为金属氮化物，例如AlN、HfN、HfAlN、TiN、TaN等，且优选地同时可以用作防止下电极金属材料向下迁移的阻挡层。如图5中所示，下电极具有厚度d，d大于b且小于a。
如图6、图7、图15所示，在下电极上形成第二牺牲层图形。如图6所示，在下电极13上形成第二牺牲层14，其材质和工艺与牺牲层11相同。接着如图7中所示，对第二牺牲层14进行平坦化，例如采用回刻蚀或CMP，直至暴露下电极的中心部分13A的顶部。第二牺牲层在下电极边缘部分上具有保留图形14’，其对应于未来谐振腔上电极压电层下方的空气隙，因此牺牲层图形的突起部分11A’与外围部分11B’的高度差影响了气隙的厚度。
如图8A、图15所示，在下电极13和第二牺牲层图形14’上形成压电层15和上电极16。例如采用LPCVD、PECVD、UHVCVD、HDPCVD、MOCVD、MBE、ALD、磁控溅射、热蒸发等工艺形成压电层15，材质例如ZnO、AlN、BST(钛酸锶钡)、BT(钛酸钡)、PZT(锆钛酸铅)、PBLN(铌酸铅钡锂)、PT(钛酸铅)等压电陶瓷材料；且优选地，压电层15中掺杂稀土元素，例如包含钪(Sc)、钇(Y)、镧(La)、铈(Ce)、镨(Pr)、钕(Nd)、钷(Pm)、钐(Sm)、铕(Eu)、钆(Gd)、铽(Tb)、镝(Dy)、钬(Ho)、铒(Er)、铥(Tm)、镱(Yb)及镥(Lu)的任一种及其组合，以提高压电系数。在压电层15上形成上电极16，其材质和工艺与下电极13相同或相近。优选地，刻蚀上电极层使得上电极图形的尺寸大于牺牲层图形，由此使得上电极与下电极之间夹设了第二牺牲层图形(对应于未来的气隙)，由此精确调节器件的频率响应特性。
如图9A、图15所示，去除牺牲层图形和第二牺牲层图形，留下气隙。气隙包括在上电极压电层15和下电极13之间的第一部分17A，用于调节器件边缘的声波反射性能，降低能耗、提高Q值。气隙还包括在下电极13与衬底10之前的谐振腔，谐振腔包括中心部分17B3、中部环形突起17B1(也即最终的 凹陷结构)、以及最外侧的环形边缘17B2(也即最终的框架结构)，其高度分别为前述c、a、b’，其中在此需要确保的是，第二电极13A的厚度。去除工艺例如各向同性的湿法腐蚀工艺，诸如针对氧化硅基材料的牺牲层和第二牺牲层，采用HF基腐蚀液例如dHF(稀释HF)、dBOE(缓释刻蚀剂，HF与NH4F的混合物)。
依照本发明的谐振器制造方法，利用图形化的牺牲层同时形成谐振腔和电极气隙，并以此形成了多种改善器件特性的微结构如OT和Innie结构，高效且低成本了提高了器件的性能和可靠性。
本发明的第二方面的实施例
如图1、图16所示，在衬底10上形成(第一)牺牲层11。提供衬底10，材质可以是体Si或绝缘体上硅(SOI)或者体Ge、GeOI以与CMOS工艺兼容并与其他数字、模拟电路集成，也可以是用于MEMS、光电器件、功率器件的化合物半导体例如GaN、GaAs、SiC、InP、GaP等，进一步优选地，衬底10是单晶材料，且最佳地，衬底10具有低浓度掺杂或者不掺杂从而具有高电阻。与传统的谐振器制造工艺不同，本发明的制造工艺中不必在衬底10中刻蚀谐振腔，因而避免了刻蚀工艺增多衬底表面缺陷。牺牲层11的沉积工艺可以为LPCVD、APCVD、PECVD等低温工艺(沉积温度低于700摄氏度，优选300至600摄氏度)，材质为氧化硅基材料，诸如掺硼氧化硅(BSG)、掺磷氧化硅(PSG)、未掺杂氧化硅(USG)、多孔氧化硅等等。在本发明其他实施例中，牺牲11为热氧化工艺制造，或者是SOI、GeOI等绝缘体上半导体衬底剥离了顶部半导体薄层之后暴露的埋氧层。牺牲层11的初始(第一)厚度为a，例如50-5000nm，其决定了未来要形成的谐振腔的环形突起的高度。
如图2至图4、图16所示，刻蚀牺牲层11形成牺牲层图形。首先，如图2所示，在牺牲层11上涂覆光刻胶并曝光显影得到光刻胶图形12，以光刻胶图形12为掩模各向异性刻蚀牺牲层11而得到牺牲层图形，其包括被光刻胶图形12所覆盖的具有厚度a的(第一)中心部分11A，以及未被光刻胶图形12覆盖的具有(第二)厚度b的(第二)边缘部分11B。厚度b小于a，例如厚度b为10-2000nm，其决定了未来谐振腔环形周缘的高度。各向异性刻蚀工艺例如等离子体干法刻蚀或反应离子刻蚀，刻蚀气体例如碳氟基刻蚀气体，诸如CF4、CHF3、CH2F2、CH3F等等，也可以采用Cl2、HCl、Br2、HBr等其他卤素基气体，并可以进一步包括氧化性气体以调节刻蚀速度、去除残渣。
随后任选地，如图3所示，采用曝光显影或激光烧蚀等工艺，修饰光刻胶图形12例如缩减尺寸以获得第二光刻胶图形12’，并以第二光刻胶图形12’为 掩模再次各向异性刻蚀牺牲层图形，得到的图形包括中心部分11A’和边缘部分11B’，两者厚度分别是a和b’，b’小于等于b例如为5-1000nm。图3所示工艺用于使得牺牲层图形向器件中心缩进，以在相邻器件单元之间留下足够的划片分割区域。
如图4所示，去除一部分光刻胶图形而留下第三光刻胶图形12”，以第三光刻胶图形12”为掩模刻蚀牺牲层图形的中心部分，最终得到的牺牲层图形包括中心部分11C、在中心部分外围的环形突起部分11A’、以及在最外侧的环形边缘部分11B’。中心部分11C对应于未来谐振腔的主体部分以控制器件谐振性能，其厚度为c，优选地a>c>b’,c例如为8-1500nm。环形突起部分11A’对应于未来谐振腔的拱起部分以降低声波边缘散射、会聚声波能量，其厚度保持牺牲层原始厚度a。环形边缘部分11B’对应于未来谐振腔的边缘以减小边缘电场、避免能量外溢，其厚度为b’。通过湿法腐蚀或干法灰化等工艺，去除光刻胶图形12”。如此将传统的位于上电极顶部的环形突起结构形成在下电极处，可以用较少的光刻版形成器件所需要的OT(outie)结构，OT结构对于提升器件的Q值有很大的帮助。
如图5、图16所示，在衬底10和牺牲层图形上形成下电极13。例如采用磁控溅射、热蒸发、MOCVD等，在衬底10和牺牲层图形之上形成下电极13，其材质例如Mo、W、Ru、Al、Cu、Ti、Ta、In、Zn、Zr、Fe、Mg等金属单质或金属合金，或者这些金属的导电氧化物、导电氮化物，以及上述材料的任意组合。下电极在中心的部分标记为13A。优选地，在形成下电极13之前可以进一步在牺牲层图形和衬底上形成衬垫层或种子层(未示出)，其材质与未来将要形成的下电极或压电层相同或相近，用于提高下电极边缘处的外延生长质量且提高与下电极之间的粘附力。沉积工艺例如磁控溅射、热蒸发、MOCVD等。在本发明一个优选实施例中，衬垫层或种子层材质为金属氮化物，例如AlN、HfN、HfAlN、TiN、TaN等，且优选地同时可以用作防止下电极金属材料向下迁移的阻挡层。如图5中所示，下电极具有厚度d，d大于b且小于a。
如图6、图7、图16所示，在下电极上形成第二牺牲层图形。如图6所示，在下电极13上形成第二牺牲层14，其材质和工艺与牺牲层11相同。接着如图7中所示，对第二牺牲层14进行平坦化，例如采用回刻蚀或CMP，直至暴露下电极的中心部分13A的顶部。第二牺牲层在下电极边缘部分上具有保留图形14’，其对应于未来谐振腔上电极下方的空气隙，因此牺牲层图形的突起部分11A’与外围部分11B’的高度差影响了气隙的厚度。
如图8B、图16所示，在下电极13和第二牺牲层图形14’上形成压电层15 和上电极16。例如采用LPCVD、PECVD、UHVCVD、HDPCVD、MOCVD、MBE、ALD、磁控溅射、热蒸发等工艺形成压电层15，材质例如ZnO、AlN、BST(钛酸锶钡)、BT(钛酸钡)、PZT(锆钛酸铅)、PBLN(铌酸铅钡锂)、PT(钛酸铅)等压电陶瓷材料；且优选地，压电层15中掺杂稀土元素，例如包含钪(Sc)、钇(Y)、镧(La)、铈(Ce)、镨(Pr)、钕(Nd)、钷(Pm)、钐(Sm)、铕(Eu)、钆(Gd)、铽(Tb)、镝(Dy)、钬(Ho)、铒(Er)、铥(Tm)、镱(Yb)及镥(Lu)的任一种及其组合，以提高压电系数。在压电层15上形成上电极16，其材质和工艺与下电极13相同或相近。
如图9B、图16所示，刻蚀上电极16、压电层15、第二牺牲层图形14’、下电极13，形成暴露衬底10的通孔。如图所示，优选地先在上电极16上沉积硬掩模17，其材质例如氧化硅、氮化硅或氮氧化硅，沉积工艺例如PECVD、HDPCVD、MBE、ALD等等。旋涂、曝光、显影形成光刻胶图形(未示出)，以光刻胶图形为掩模刻蚀硬掩模17形成硬掩模图形，然后以该硬掩模图形为掩模，采用各向异性的刻蚀工艺例如等离子体干法刻蚀或反应离子刻蚀，依次向下刻蚀上电极16、压电层15、第二牺牲层图形14’、下电极13，直至暴露衬底10表面，形成的通孔17A位于第一牺牲层图形的环形边缘部分11B’的外侧。
如图10、图16所示，在通孔17A中形成第三牺牲层图形18。例如采用PECVD、HDPCVD、MBE、ALD等工艺在整个器件上沉积牺牲材料，诸如氧化硅、氮化硅、氮氧化硅等等，完全填充通孔17A并优选地进一步沉积在上电极16上。随后采用回刻蚀或CMP等平坦化工艺处理牺牲层材料，直至暴露上电极16顶部，使得第三牺牲层图形18顶部与上电极16顶部齐平。虽然图10中示出第三牺牲层图形18为实心结构，但是受限于沉积工艺在深宽比大的通孔17A中填充率较低，第三牺牲层图形18可能因为牺牲层材料过早闭合而内部留有气泡或间隙(未示出)。
如图11-14、图16所示，去除牺牲层图形11、第二牺牲层图形14’、第三牺牲层图形18，留下多个气隙完全包围了谐振器。
具体地，如图11所示，在上电极16和第三牺牲层图形18上进一步优选地形成第二上电极16B，其工艺和材质可以与上电极16相同或相近，由此导电材料在第三牺牲层图形18的顶部附近完全包围了其顶表面和一部分侧面也即三面包围，用作最终器件的电极引出区，且增厚的上电极堆叠可以有效降低接触电阻，提高谐振器性能。
如图12所示，在第二上电极16B上形成介质层15B，沉积工艺例如PECVD、HDPCVD、MBE、ALD等，材料例如氧化物、氮化物、氮氧化物等 等，诸如氧化硅、氮化硅、氮化铝等等，用于钝化保护上电极堆叠。
如图13所示，在整个器件上旋涂光刻胶并曝光显影形成光刻胶图形19，以光刻胶图形19为掩模依次刻蚀介质层15B、第二上电极16B、上电极16直至暴露压电层15，形成在牺牲层图形边缘附近上方的第二通孔19A用作上电极结构周围的第一气隙，同时也将谐振器的主体结构与焊垫引出区域分隔开，有效避免了声波能量的泄漏。随后可以通过湿法腐蚀或干法灰化去除光刻胶图形19。
如图14所示，采用各向同性的湿法腐蚀工艺，诸如针对氧化硅基材料采用HF基腐蚀液例如dHF(稀释HF)、dBOE(缓释刻蚀剂，HF与NH4F的混合物)，同时去除牺牲层图形11、第二牺牲层图形14’和第三牺牲层图形18，留下第二气隙和第三气隙，用于调节器件边缘的声波反射性能，降低能耗、提高Q值。第二气隙位于下电极13与衬底10之间，用作器件的谐振腔，包括中心部分19B3、中部环形突起19B1、以及最外侧的环形边缘19B2，其高度分别为前述c、a、b’。第三气隙19C对应于第二牺牲层图形14’和第三牺牲层图形18占据的空间，如图14所示具有在压电层15与下电极13之间向内凹陷的第一部分用于减少声波在谐振腔边界处的泄漏，在第一部分外侧、压电层15和下电极13侧面垂直延伸的第二部分用于减少声波在压电层和下电极侧端面的泄漏，以及在第二部分外侧位于压电层15和下电极13之间向外延伸的第三部分用于减少相邻谐振器单元之间的串扰或者减小划片区域应力以避免损伤。
依照本发明的谐振器制造方法，利用图形化的多个牺牲层同时形成谐振腔和多个气隙以完全包围谐振腔，最大化抑制了声波能量损失，有效提高了Q值。
尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可以知晓无需脱离本发明范围而对器件结构做出各种合适的改变和等价方式。此外，由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此，本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例，而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims (20)

  1. 一种谐振器制造方法，包括：
    在衬底上形成第一牺牲层图形；
    在第一牺牲层图形上形成下电极；
    在下电极上形成第二牺牲层图形；
    在第二牺牲层图形和下电极上形成压电层和上电极；
    去除第一牺牲层图形和第二牺牲层图形，留下至少一个气隙。
  2. 根据权利要求1的谐振器制造方法，在第二牺牲层图形和下电极上形成压电层和上电极之后，所述谐振器制造方法还包括如下步骤：
    刻蚀上电极、压电层、第二牺牲层图形、下电极形成暴露衬底的通孔；
    在通孔中形成第三牺牲层图形，
    由此在去除第一牺牲层图形、第二牺牲层图形和第三牺牲层图形后，留下多个气隙，
    其中通孔位于第一牺牲层图形的外侧。
  3. 根据权利要求1或2的谐振器制造方法，形成第一牺牲层图形包括：
    在衬底上形成第一牺牲层；
    在第一牺牲层上形成光刻胶图形；
    修饰光刻胶图形以缩减尺寸；
    以光刻胶图形为掩模刻蚀形成第一牺牲层图形。
  4. 根据权利要求1或2的谐振器制造方法，其中，第一牺牲层图形包括中心部分，在中心部分外侧的环形突起部分，以及在环形突起部分外侧的环形边缘部分；优选地，环形突起部分的厚度大于中心部分的厚度，中心部分的厚度大于环形边缘部分的厚度；任选地，下电极的厚度大于环 形边缘部分的厚度且小于环形突起部分的厚度。
  5. 根据权利要求1或2的谐振器制造方法，形成第二牺牲层图形进一步包括：
    在下电极上形成第二牺牲层；
    平坦化第二牺牲层直至暴露下电极的中心部分
  6. 根据权利要求1或2的谐振器制造方法，其中，第一牺牲层图形和/或第二牺牲层图形和/第三牺牲层图形的材质为氧化物。
  7. 根据权利要求1或2的谐振器制造方法，其中，采用各向同性的湿法腐蚀去除牺牲层图形。
  8. 根据权利要求1的谐振器制造方法，其中，上电极的尺寸大于第一牺牲层图形的尺寸。
  9. 根据权利要求1或2的谐振器制造方法，形成下电极之前进一步包括在衬底上形成种子层。
  10. 根据权利要求2的谐振器制造方法，形成第三牺牲层图形进一步包括：
    在通孔和上电极上形成牺牲材料；
    平坦化牺牲材料直至暴露上电极顶部。
  11. 根据权利要求2的谐振器制造方法，去除第一牺牲层图形、第二牺牲层图形和第三牺牲层图形之前，还包括：
    在上电极上形成第二上电极；
    在第二上电极上形成介质层；
    刻蚀介质层、第二上电极、上电极直至暴露压电层，留下第一气隙；
    采用各向同性湿法腐蚀去除第一牺牲层图形、第二牺牲层图形、第三牺牲层图形，留下第二气隙和第三气隙。
  12. 根据权利要求11的谐振器制造方法，其中，第一气隙在第一牺牲层图形的边缘上方，任选地第二气隙在下电极和衬底之间，任选地第三气隙具有在压电层和下电极之间的第一部分、在第一部分外在压电层和下电极侧面垂直延伸的第二部分、以及在第二部分外在压电层和下电极之间水平延伸的第三部分。
  13. 根据权利要求2的谐振器制造方法，形成暴露衬底的通孔进一步包括：
    在上电极上形成硬掩模图形；
    以硬掩模图形为掩模依次刻蚀上电极、压电层、第二牺牲层图形、下电极直至暴露衬底。
  14. 根据权利要求2的谐振器制造方法，其中，第一牺牲层图形、第二牺牲层图形或第三牺牲层图形的材质为氧化物，优选地为LPCVD、APCVD、PECVD等低温工艺(沉积温度低于700摄氏度，优选300至600摄氏度)或热氧化工艺制造的氧化硅基材料，诸如掺硼氧化硅(BSG)、掺磷氧化硅(PSG)、未掺杂氧化硅(USG)、多孔氧化硅；任选地，第一牺牲层图形为对绝缘体上半导体衬底刻蚀去除顶部半导体层之后剩余的埋氧层。
  15. 一种谐振器，其包括
    衬底；
    衬底上方的下电极；
    下电极上方的压电层和上电极；
    其中在衬底和下电极之间存在第二气隙，所述第二气隙通过在衬底和下电极之间构成第一牺牲层图形并去除第一牺牲层图形来构成；此外，在 下电极和压电层之间存在第三气隙的一部分，所述第三气隙的该部分通过在下电极和压电层之间构成第二牺牲层图形并去除第二牺牲层图形来构成，其中第二牺牲层图形处于下电极边缘部分上(说明书209的53段)进而第二气隙处于下电极边缘部分上；并且
    其中所述第二气隙包括中心部分，在中心部分外侧的环形突起部分用于形成凹陷结构，以及在环形突起部分外侧的环形边缘部分；优选地，环形突起部分的厚度大于中心部分的厚度，中心部分的厚度大于环形边缘部分的厚度，任选地下电极的厚度大于环形边缘部分的厚度且小于环形突起部分的厚度。
  16. 根据权利要求15的谐振器，其中，所述谐振器还包括至少一个另外的气隙，所述至少一个另外的气隙穿过上电极、压电层和下电极并暴露衬底，其中所述至少一个另外的气隙位于第二气隙的环形边缘部分的外侧，并且所述至少一个另外的气隙构成第三气隙的另一部分。
  17. 根据权利要求16的谐振器，其中，所述谐振器还包括在上电极上形成的第二上电极和在第二上电极上形成的介质层。
  18. 根据权利要求17的谐振器，其中，通过刻蚀介质层、第二上电极、上电极至暴露压电层构成第一气隙，其中，第一气隙用作上电极结构周围。
  19. 根据权利要求15的谐振器，其中，上电极的尺寸大于第二气隙的尺寸。
  20. 根据权利要求15或16的谐振器，其中，所述谐振器包括处于衬底和下电极之间的种子层。
PCT/CN2021/119027 2020-09-27 2021-09-17 谐振器制造方法及谐振器 WO2022063053A1 (zh)

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