WO2022063149A1 - Fbar谐振器制造方法 - Google Patents

Fbar谐振器制造方法 Download PDF

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Publication number
WO2022063149A1
WO2022063149A1 PCT/CN2021/119758 CN2021119758W WO2022063149A1 WO 2022063149 A1 WO2022063149 A1 WO 2022063149A1 CN 2021119758 W CN2021119758 W CN 2021119758W WO 2022063149 A1 WO2022063149 A1 WO 2022063149A1
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lower electrode
piezoelectric layer
thickness
forming
etching
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PCT/CN2021/119758
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English (en)
French (fr)
Inventor
唐兆云
王家友
唐滨
赖志国
杨清华
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苏州汉天下电子有限公司
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Priority claimed from CN202011028970.4A external-priority patent/CN112071975B/zh
Priority claimed from CN202011029054.2A external-priority patent/CN112087217B/zh
Application filed by 苏州汉天下电子有限公司 filed Critical 苏州汉天下电子有限公司
Publication of WO2022063149A1 publication Critical patent/WO2022063149A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/08—Shaping or machining of piezoelectric or electrostrictive bodies
    • H10N30/082—Shaping or machining of piezoelectric or electrostrictive bodies by etching, e.g. lithography

Definitions

  • the present invention relates to a method for manufacturing an FBAR resonator, in particular an FBAR resonator with improved Q value or a planarized FBAR resonator, and in particular, the present invention relates to a method for manufacturing a resonator with a flat surface.
  • RF filters are used as an intermediary to filter specific frequency signals to reduce signal interference in different frequency bands, and to implement functions such as image cancellation, spurious filtering, and channel selection in wireless transceivers.
  • the design of RF front-end is developing towards miniaturization, low power consumption and integration, and the market has higher and higher requirements for filtering performance. Due to the small size, high operating frequency, low power consumption, high quality factor (Q value), direct With the characteristics of output frequency signal and compatibility with CMOS process, it has become an important device in the field of radio frequency communication and is widely used.
  • FBAR is a thin film device with an electrode-piezoelectric film-electrode sandwich structure fabricated on a substrate material.
  • the structure of FBAR has cavity type, Bragg reflection type (SMR) and backside etching type.
  • SMR Bragg reflection type
  • the cavity type FBAR has higher Q value, lower loss and higher electromechanical coupling coefficient; compared with the backside etching type FBAR, it does not need to remove a large area of the substrate and has higher mechanical strength. Therefore, cavity-type FBAR is the first choice for integration on CMOS devices.
  • the lower electrode 2 formed on the cavity 1A in the substrate 1 is usually limited by the deposition process and it is difficult to have vertical sidewalls, and the piezoelectric further deposited above the lower electrode 2 Layer 3 also has a correspondingly inclined slope due to the inclined sidewall at the end of the lower electrode 2, where the piezoelectric film grows in poor quality, and defects such as fracture and collapse are prone to occur at the dotted oval frame in the figure, resulting in the final product.
  • the upper electrode stack structure 4/5 formed on the piezoelectric layer 3 is not only formed on the flat top of the piezoelectric layer 3, but also formed on the above-mentioned slope, so it is difficult for the lower electrode and the upper electrode to be completely parallel, such as
  • the electric field shown by the arrow in Fig. 1 includes two components, longitudinal and horizontal, which easily causes the leakage of acoustic energy in the horizontal direction, which further reduces the Q value.
  • the purpose of the present invention is to overcome the above technical obstacles and provide a method for fabricating a resonator with a flat surface.
  • the present invention provides a method for preparing a planarized FBAR resonator, comprising:
  • An upper electrode is formed on the piezoelectric layer.
  • the first thickness is 0.05-10 microns, and optionally the second thickness is 100-2000 angstroms.
  • the second thickness is measured after the dielectric layer is planarized, and the process parameters for etching the dielectric layer are adjusted according to the second thickness.
  • the lower electrode has inclined sidewalls after the lower electrode is formed on the substrate.
  • the forming of the first piezoelectric layer further includes etching the inclined sidewalls of the lower electrode so that the lower electrode has vertical sidewalls.
  • an etching process is inserted between the plurality of deposition processes during formation of the lower electrode so that the lower electrode has vertical sidewalls.
  • the size of the upper electrode is larger than the size of the lower electrode.
  • a piezoelectric layer with a flat surface is formed on the lower electrode by successive deposition, flattening and etching processes, which reduces defects and avoids acoustic energy leakage.
  • a method for manufacturing an FBAR resonator with improved Q value comprising:
  • An upper electrode is formed on the second piezoelectric layer.
  • the step of etching the piezoelectric layer until the lower electrode is exposed, and forming a second piezoelectric layer on the lower electrode and the piezoelectric layer further includes:
  • a third piezoelectric layer is formed on the second lower electrode and the second piezoelectric layer.
  • the first thickness is 0.05-10 microns, optionally the fifth thickness is 0-2000 angstroms, the third thickness is optionally 0.1-5 microns, the fourth thickness is optionally 0-2000 angstroms, optionally The thickness of the second lower electrode is 10-100 nm.
  • the fifth thickness is measured after the piezoelectric layer is planarized and the process parameters for etching the piezoelectric layer are adjusted according to the fifth thickness, or the fourth thickness is measured after the second piezoelectric layer is planarized and the second thickness is adjusted and etched according to the fourth thickness. Process parameters of the piezoelectric layer.
  • the lower electrode has sloped sidewalls after the lower electrode is formed on the substrate, or the second lower electrode has sloped sidewalls after the second lower electrode is formed on the piezoelectric layer.
  • the piezoelectric layer Before forming the piezoelectric layer, it further comprises etching the inclined sidewall of the lower electrode, so that the lower electrode has vertical sidewalls; or before forming the second piezoelectric layer, it further comprises etching the inclined sidewall of the second lower electrode, so that the second lower electrode has vertical sidewalls. Has vertical side walls.
  • the process of forming the lower electrode or the second lower electrode includes alternating multiple deposition sub-cycles and multiple etching sub-cycles, and adjusting the working gas so that the electrode sides formed by the multiple deposition sub-cycles before etching during the multiple etching sub-cycles are used. It has vertical side walls.
  • the size of the upper electrode is larger than that of the lower electrode or the second lower electrode.
  • the bottom electrode and the first piezoelectric layer are formed coplanar before depositing the second piezoelectric layer by successively adopting deposition, planarization, and etching processes step by step.
  • the complete flat surface reduces defects and avoids leakage of sonic energy.
  • the material of the substrate is Si, SOI, Ge, GeOI, compound semiconductor;
  • the material of the dielectric layer is oxide, nitride or oxynitride, preferably The lattice constant of the ground dielectric layer is the same as or similar to that of the piezoelectric layer;
  • the material of the piezoelectric layer is ZnO, AlN, BST (barium strontium titanate), BT (barium titanate), PZT (lead zirconate titanate) , PBLN (lead barium lithium niobate), PT (lead titanate), further preferably doped with rare earth elements in the piezoelectric material;
  • the material of the lower electrode or the upper electrode is selected from Mo, W, Ru, Al , Cu, Ti, Ta, In, Zn, Zr, Fe, Mg metal elements or metal alloys, or conductive oxides or conductive nitrides of these
  • the method before forming the lower electrode, the method further includes, forming a pad layer on the substrate.
  • the material of the backing layer is metal nitride, preferably AlN, HfN, HfAlN, TiN, TaN.
  • the resonator manufacturing method of the first aspect and the second aspect of the present invention before forming the lower electrode, it further includes etching the substrate to form a cavity and filling the cavity with a sacrificial layer, and after forming the upper electrode, further including a wet method Etching away the sacrificial layer leaves a resonant cavity in the substrate.
  • Figure 1 shows a cross-sectional view of a resonator according to the prior art
  • FIGS. 2 to 7 show cross-sectional views of various stages of a resonator manufacturing process according to an embodiment of the first design solution of the present invention
  • FIG. 8 shows a flow chart of a resonator manufacturing process according to an embodiment of the first design solution of the present invention
  • 17A and 17B respectively show flowcharts of different embodiments of a resonator manufacturing process according to an embodiment of the second design solution of the present invention.
  • the lower electrode 12 is formed on the substrate 10 .
  • Substrate 10 is provided, and the material can be bulk Si or silicon-on-insulator (SOI) or bulk Ge, GeOI to be compatible with CMOS process and integrated with other digital and analog circuits, and can also be a compound for MEMS, optoelectronic devices, power devices Semiconductors such as GaN, GaAs, SiC, InP, GaP, etc., further preferably, the substrate 10 is a single crystal material.
  • the substrate 10 is etched to form a plurality of cavities, and a sacrificial layer 10A is deposited to fill it.
  • the etching process is preferably anisotropic dry etching or wet etching, such as reactive ion etching using a fluorocarbon-based etching gas, or wet etching using TMAH.
  • the deposition process is a low temperature process such as LPCVD, APCVD, PECVD (deposition temperature is lower than 500 degrees Celsius, preferably 100 to 400 degrees Celsius), and the sacrificial layer 10A is made of silicon oxide-based materials, such as boron-doped silicon oxide (BSG), phosphorus-doped silicon oxide ( PSG), undoped silicon oxide (USG), porous silicon oxide, etc., so that the residual thermal stress in the substrate 10 can be reduced, and it is beneficial to improve the speed of subsequent etching and removal to save time and cost.
  • BSG boron-doped silicon oxide
  • PSG phosphorus-doped silicon oxide
  • USG undoped silicon oxide
  • porous silicon oxide etc.
  • a liner layer or seed layer 11 may be further formed on the sacrificial layer 10A, the material of which is the same as or similar to the piezoelectric layer to be formed in the future, for improving the epitaxial growth at the edge of the lower electrode quality.
  • Deposition processes such as magnetron sputtering, thermal evaporation, MOCVD, etc.
  • the material of the backing layer or the seed layer 11 is metal nitride, such as AlN, HfN, HfAlN, TiN, TaN, etc., and preferably can be used as a material to prevent the downward migration of the metal material of the lower electrode at the same time.
  • the barrier layer avoids affecting the state of the interface between the top of the resonator and the film below.
  • a lower electrode 12 is formed on the substrate 10 and the sacrificial layer 10A, and its material is, for example, Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn , Zr, Fe, Mg and other metal elements or metal alloys, or conductive oxides, conductive nitrides of these metals, and any combination of the above materials.
  • the end of the lower electrode 12 due to the limitation of the deposition process, the end of the lower electrode 12 usually has sloped sidewalls.
  • an anisotropic etching process is used to remove the inclined sidewall at the end of the lower electrode 12 so that the lower electrode 12 has vertical sidewalls.
  • one or more sub-cycles of the etch process may also be inserted between sub-cycles of the deposition process during formation of the lower electrode, such that the resulting lower electrode has vertical sidewalls.
  • a dielectric layer 13 is formed on the lower electrode 12 and the substrate 10 .
  • the dielectric layer 13 is deposited by processes such as PECVD, UHCVD, HDPCVD, MOCVD, MBE, ALD, magnetron sputtering, thermal evaporation, etc.
  • the material of the dielectric layer 13 can be oxide, nitride or oxynitride.
  • the dielectric layer 13 is a material whose lattice constant is the same as or similar to that of the piezoelectric layer to be formed in the future, such as AlN, SiOx, SiON, and the like.
  • a high height also has a step difference.
  • the original thickness H0 is, for example, 0.05 to 10 microns, preferably 0.1 to 5 microns, and optimally 1 to 3 microns.
  • a planarization process is performed on the dielectric layer 13 , for example, a CMP process is used to reduce its thickness H0 to H1 .
  • the thickness H1 is, for example, 100 to 2000 angstroms, preferably 300 to 1000 angstroms, so that the poor quality part of the top film can be removed by a faster CMP process.
  • the polishing speed is adjusted by adjusting the ratio of the polishing liquid and the polishing time, so that the thickness H1 can be adjusted by selecting the termination node time of the CMP process.
  • the first piezoelectric layer 13 is thinned into a piezoelectric film 13'.
  • the remaining thickness H1 of the piezoelectric film 13' is measured by methods such as SEM, laser interference, etc., so as to precisely adjust the parameters of the subsequent etching process.
  • the remaining dielectric film 13' is etched until the lower electrode 12 is exposed.
  • an anisotropic dry etching process is used.
  • a piezoelectric layer 13B is formed on the lower electrode 12 and the seed region 13 ′′ having a flat surface to serve as an acoustic-electric conversion element of the final device.
  • PECVD PECVD, UHVCVD, HDPCVD, MOCVD are used.
  • the piezoelectric layer 13B is doped with rare earth elements, such as scandium (Sc), yttrium (Y), lanthanum (La ), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho) ), erbium (Er), thulium (Tm
  • the upper electrode 14 is formed on the piezoelectric layer 13B, and its process and material are the same as or similar to those of the lower electrode 12 .
  • the size of the upper electrode 14 eg, the width in the figure
  • the size of the upper electrode 14 is larger than that of the lower electrode 11 to completely cover the sacrificial layer 10A, so as to reduce the possibility that the electric field distortion at the edge affects the Q value of the resonator.
  • a wet etchant is applied to remove the sacrificial layer pattern through release holes (not shown) provided at the periphery of the device.
  • HF-based etching solutions such as dHF (diluted HF), dBOE (slow release etchant, a mixture of HF and NH4F) are used to remove the sacrificial layer pattern 10A, leaving multiple resonant cavities.
  • a piezoelectric layer with a flat surface is formed on the lower electrode by successively adopting deposition, flattening and etching processes, which reduces defects and avoids the leakage of acoustic wave energy.
  • a lower electrode is formed on the substrate.
  • Substrate 10 is provided, and the material can be bulk Si or silicon-on-insulator (SOI) or bulk Ge, GeOI to be compatible with CMOS process and integrated with other digital and analog circuits, and can also be a compound for MEMS, optoelectronic devices, power devices Semiconductors such as GaN, GaAs, SiC, InP, GaP, etc., further preferably, the substrate 10 is a single crystal material.
  • the substrate 10 is etched to form a plurality of cavities, and a sacrificial layer 10A is deposited to fill it.
  • the etching process is preferably anisotropic dry etching or wet etching, such as reactive ion etching using a fluorocarbon-based etching gas, or wet etching using TMAH.
  • the deposition process is a low temperature process such as LPCVD, APCVD, PECVD (deposition temperature is lower than 500 degrees Celsius, preferably 100 to 400 degrees Celsius), and the sacrificial layer 10A is made of silicon oxide-based materials, such as boron-doped silicon oxide (BSG), phosphorus-doped silicon oxide ( PSG), undoped silicon oxide (USG), porous silicon oxide, etc., so that the residual thermal stress in the substrate 10 can be reduced, and it is beneficial to improve the speed of subsequent etching and removal to save time and cost.
  • BSG boron-doped silicon oxide
  • PSG phosphorus-doped silicon oxide
  • USG undoped silicon oxide
  • porous silicon oxide etc.
  • a liner layer or seed layer 11 may be further formed on the sacrificial layer 10A, the material of which is the same as or similar to the piezoelectric layer to be formed in the future, for improving the epitaxial growth at the edge of the lower electrode quality.
  • Deposition processes such as magnetron sputtering, thermal evaporation, MOCVD, etc.
  • the material of the backing layer or the seed layer 11 is metal nitride, such as AlN, HfN, HfAlN, TiN, TaN, etc., and preferably can be used as a material to prevent the downward migration of the metal material of the lower electrode at the same time.
  • the barrier layer avoids affecting the state of the interface between the top of the resonator and the film below.
  • a lower electrode 12A is formed on the substrate 10 and the sacrificial layer 10A by, for example, magnetron sputtering, thermal evaporation, MOCVD, etc., and its material is, for example, Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn , Zr, Fe, Mg and other metal elements or metal alloys, or conductive oxides, conductive nitrides of these metals, and any combination of the above materials. As shown in FIG. 9, due to the limitation of the deposition process, the end of the lower electrode 12A typically has sloped sidewalls.
  • an anisotropic etching process is used to remove the inclined sidewall at the end of the lower electrode 12 so that the lower electrode 12 has vertical sidewalls.
  • the process of forming the lower electrode may include alternating multiple deposition sub-cycles and multiple etching sub-cycles, and adjusting the working gas so that the electrode sides formed by the multiple deposition sub-cycles before etching during the multiple etching sub-cycles have vertical side walls.
  • the piezoelectric layer 13A is formed on the lower electrode 12A and the substrate 10 .
  • LPCVD PECVD, UHVCVD, HDPCVD, MOCVD, MBE, ALD, magnetron sputtering, thermal evaporation, etc.
  • the piezoelectric layer 13A is doped with rare earth elements, such as scandium (Sc), yttrium (Y) , Lanthanum (La), Cerium (Ce), Praseodymium (Pr), Neodymium (Nd), Promethium (Pm), Samarium (Sm), Europium (Eu), Gadolinium (Gd), Terbium (Tb), Dysprosium (Dy) , any one of holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu) and combinations thereof to improve the piezoelectric coefficient.
  • rare earth elements such as scandium (Sc), yttrium (Y) , Lanthanum (La), Cerium (Ce), Praseodymium (Pr), Neodymium (Nd), Promethium (Pm), Samarium (Sm), Europium (Eu), Gadolinium (Gd), Terbium
  • the piezoelectric layer 13A has an original thickness H0, and due to the deposition process with good conformality, it also has a conformal slope on the end slope of the lower electrode 12A, so it has a contrast above the sacrificial layer 10A
  • the higher height above the bottom 10 also has a step difference.
  • the original thickness H0 is, for example, 0.05 to 10 microns, preferably 0.1 to 5 microns, and optimally 1 to 3 microns.
  • a planarization process such as a CMP process, is performed on the piezoelectric layer 13A to reduce its thickness H0 to H1.
  • the thickness H1 is, for example, 0 to 2000 angstroms, preferably 100 to 1500 angstroms, and most preferably 800 to 1000 angstroms, so that the poor quality part of the top film can be removed by a faster CMP process.
  • the polishing speed is adjusted by adjusting the ratio of the polishing liquid and the polishing time, so that the thickness H1 can be adjusted by selecting the termination node time of the CMP process.
  • the piezoelectric layer 13A is thinned into a dielectric film 13A'.
  • the remaining thickness H1 of the film 13A' is measured by methods such as SEM, laser interference, etc., in order to precisely adjust the parameters of the subsequent etching process.
  • etching is not performed immediately to expose the lower electrode 12A, but a first electrode is formed on the piezoelectric layer 13A'.
  • the two lower electrodes 12B are used to further improve the flatness of the structure under the second piezoelectric layer and at the same time improve the accuracy of controlling the electric field distribution at the bottom of the resonator.
  • the deposition process and material selection of the second lower electrode 12B are the same as or similar to those of the lower electrode 12A.
  • the slope at the end thereof is removed by etching, so that the second lower electrode 12B also has vertical sidewalls.
  • the thickness of the second lower electrode 12B is 10-100 nm, more preferably 20-50 nm, and optimally 30 nm, so as to avoid the formation of steps at the end and also to take into account the controllability of the resonant cavity.
  • a second piezoelectric layer 13B is formed on the piezoelectric layer 13A' and the second lower electrode 12B, and its process and material are preferably the same as or similar to those of the piezoelectric layer 13A'.
  • the materials of the second piezoelectric layer 13B and the piezoelectric layer 13A are completely the same, so as to better improve the bonding strength between the upper and lower layers in the stacked structure.
  • the second piezoelectric layer 13B has an original thickness H0', such as 0.1-5 microns, preferably 1-3 microns, and optimally 2 microns, which is beneficial to reduce the thickness on the piezoelectric layer 13A' to save subsequent process time, and at the same time The effect of the underlying defects on the top flat surface can be mitigated with sufficient thickness.
  • a planarization process is performed on the second piezoelectric layer 13B to reduce its original thickness H0 ′ to a remaining thickness H1 ′, for example, 0 to 2000 angstroms, preferably 100 to 1500 angstroms, the best 800 to 1000 Angstroms in order to use a faster CMP process to remove the poor quality parts of the top film.
  • an etching process is performed on the remaining second piezoelectric layer 13B until the lower electrode 12 is exposed.
  • an anisotropic dry etching process such as plasma dry etching, reactive ion etching, etc.
  • Etching process gas such as fluorine-based etching gas, such as CF4, CHF3, CH2F2, CH3F, etc., can also use Cl2, HCl, Br2, HBr and other halogen-based gases, and can further include oxidizing gases to adjust etching speed, removal of residues.
  • the second piezoelectric layer is thinned to a layer 13B', the thickness of which is equal to the thickness of the second lower electrode 12B.
  • FIG. 17A the processes of FIGS. 11-13 are omitted, and immediately after the piezoelectric layer 13A on the lower electrode 12A is planarized, the etching process shown in FIG. 14 is used immediately , etching the piezoelectric layer 13A until the lower electrode 12A is exposed, so that the top surface of the remaining piezoelectric film 13A' is flush with the top surface of the lower electrode 12A, and the top surface is directly used as the starting plane for subsequent deposition of the second piezoelectric layer.
  • the third piezoelectric layer 14 is formed on the second lower electrode 12B or the lower electrode 12A, for example, by LPCVD, PECVD, UHVCVD, HDPCVD, MOCVD, MBE, ALD, magnetron sputtering Radiation, thermal evaporation, etc., materials such as ZnO, AlN, BST (barium strontium titanate), BT (barium titanate), PZT (lead zirconate titanate), PBLN (lead barium lithium niobate), PT (lead titanate) isopiezoelectric ceramic material; and preferably, the third piezoelectric layer 14 is doped with rare earth elements, such as scandium (Sc), yttrium (Y), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), Promethium (Pm), Samarium (Sc), scandium (Sc), yttrium (Y),
  • the upper electrode 15 is formed on the third piezoelectric layer 14 .
  • the process and material of the upper electrode 15 are the same as or similar to those of the lower electrode 12A/the second lower electrode 12B.
  • the size of the upper electrode 15 eg, the width in the figure
  • the size of the upper electrode 15 is larger than that of the lower electrode/second lower electrode to completely cover the sacrificial layer 10A, so as to reduce the possibility that the electric field distortion at the edge affects the Q value of the resonator.
  • a wet etchant is applied to remove the sacrificial layer pattern through release holes (not shown) provided at the periphery of the device.
  • HF-based etching solutions such as dHF (diluted HF), dBOE (slow release etchant, a mixture of HF and NH4F) are used to remove the sacrificial layer pattern 10A, leaving multiple resonant cavities.
  • dHF diluted HF
  • dBOE slow release etchant
  • a mixture of HF and NH4F low release etchant
  • a second piezoelectric layer is formed after a piezoelectric layer with a flat surface is formed on the lower electrode step by step using deposition, planarization, and etching processes in sequence. , reducing defects and avoiding sonic energy leakage.

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Abstract

一种FBAR谐振器制造方法，在衬底上形成下电极；在下电极和衬底上形成介质层或压电层，具有第一厚度；平坦化介质层或压电层以将第一厚度减小为第二厚度；刻蚀介质层或压电层直至暴露下电极；在下电极和衬底上形成压电层或另一压电层；在该压电层或另一压电层上形成上电极。依照本发明的谐振器制造方法，依次采用沉积、平坦化、刻蚀工艺分步形成具有平坦表面的平面，减少了缺陷，避免了声波能量泄漏。

Description

FBAR谐振器制造方法 技术领域
本发明涉及一种FBAR谐振器、特别是Q值提升的FBAR谐振器或平坦化FBAR谐振器的制造方法，本发明尤其涉及一种具有平坦表面的谐振器的制造方法。
背景技术
在无线通讯中，射频滤波器作为过滤特定频率信号的中介，用于减少不同频段的信号干扰，在无线收发器中实现镜像消除、寄生滤波和信道选择等功能。随着4GLTE网络的部署和市场的增长，射频前端的设计朝着小型化、低功耗和集成化的方向发展，市场对滤波性能的要求也越来越高。由于薄膜体声波谐振器(FilmBulkAcousticResonator，简称“FBAR”，也称“体声波”，BulkAcousticWave，简称“BAW”，)具有尺寸小、工作频率高、功耗低、品质因数(Q值)高、直接输出频率信号、与CMOS工艺兼容等特点，目前已经成为射频通讯领域重要的器件被广泛应用。
FBAR是制作在衬底材料上的电极——压电膜——电极的三明治结构的薄膜器件。FBAR的结构有空腔型、布拉格反射型(SMR)和背面刻蚀型。其中空腔型FBAR相对SMR型Q值要高，损耗要小，机电耦合系数要高；相对于背面刻蚀型FBAR不需要去掉大面积的衬底，机械强度较高。因此，空腔型FBAR是集成于CMOS器件上的首选。
在传统的制造工艺中，如图1中所示，衬底1中的空腔1A上形成的下电极2通常受限于沉积工艺而难以具有垂直侧壁，下电极2上方进一步沉积的压电层3则由于下电极2尾端倾斜侧壁而相应地也具有倾斜坡面，在该处压电薄膜生长质量不佳，在图中虚线椭圆框处容易出现断裂、塌陷等缺陷，导致产品最终Q值下降。
另一方面，压电层3上形成的上电极堆叠结构4/5不仅形成在压电层3平坦的顶部上，同时也形成在上述坡面上，因此下电极和上电极难以完全平行，如图1中箭头所示产生的电场包括纵向和水平两个分量，容易引起声波能量在水平方向的泄漏，进一步降低了Q值。
发明内容
因此，本发明的目的在于克服以上技术障碍而提供一种具有平坦表面的谐振器制备方法。
在本发明的第一方面中，本发明提供一种平坦化FBAR谐振器制备方法，包括：
在衬底上形成下电极；
在下电极和衬底上形成介质层，具有第一厚度；
平坦化介质层以将第一厚度减小为第二厚度；
刻蚀介质层直至暴露下电极；
在下电极和衬底上形成压电层；
在压电层上形成上电极。
其中，第一厚度为0.05-10微米，任选地第二厚度为100-2000埃。
其中，平坦化介质层之后测量第二厚度，并根据第二厚度调节刻蚀介质层的工艺参数。
其中，在衬底上形成下电极之后下电极具有倾斜侧壁。形成第一压电层之前进一步包括刻蚀下电极的倾斜侧壁，使得下电极具有垂直侧壁。任选地，形成下电极期间在多个沉积工艺之间插入刻蚀工艺使得下电极具有垂直侧壁。
其中，上电极尺寸大于下电极尺寸。
依照本发明的第一方面的平坦化FBAR谐振器制备方法，依次采用沉积、平坦化、刻蚀工艺分步在下电极上形成具有平坦表面的压电层，减少了缺陷，避免了声波能量泄漏。
在本发明的第二方面中，提供了一种Q值提升的FBAR谐振器制造方法，包括：
在衬底上形成下电极；
在下电极和衬底上形成压电层，具有第一厚度；
平坦化压电层以将第一厚度减小为第五厚度；
刻蚀压电层直至暴露下电极；
在下电极和压电层上形成第二压电层；
在第二压电层上形成上电极。
刻蚀压电层直至暴露下电极、在下电极和压电层上形成第二压电层的步骤进一步包括：
在压电层上形成第二下电极；
在第二下电极上形成第二压电层，具有第三厚度；
平坦化第二压电层以将第三厚度减小为第四厚度；
刻蚀第二压电层直至暴露第二下电极；以及
在第二下电极和第二压电层上形成第三压电层。
其中，第一厚度为0.05-10微米，任选地第五厚度为0-2000埃，任选地第三厚度为0.1-5微米，任选地第四厚度为0-2000埃，任选地第二下电极的厚度为10-100nm。
其中，平坦化压电层之后测量第五厚度并根据第五厚度调节刻蚀压电层的工艺参数，或者平坦化第二压电层之后测量第四厚度并根据第四厚度调节刻蚀第二压电层的工艺参数。
其中，在衬底上形成下电极之后下电极具有倾斜侧壁，或者在压电层上形成第二下电极之后第二下电极具有倾斜侧壁。
形成压电层之前进一步包括刻蚀下电极的倾斜侧壁，使得下电极具有垂直侧壁；或者形成第二压电层之前进一步包括刻蚀第二下电极的倾斜侧壁，使得第二下电极具有垂直侧壁。
形成下电极或第二下电极的过程包含交替的多个沉积子循环和多个刻蚀子循环，调节工作气体使得多个刻蚀子循环期间刻蚀之前多个沉积子循环形成的电极侧面使其具有垂直侧壁。
其中，上电极的尺寸大于下电极或第二下电极的尺寸。
依照本发明的第二方面的Q值提升的FBAR谐振器制造方法，依次采用沉积、平坦化、刻蚀工艺分步在沉积第二压电层前形成了底电极和第一压电层共面的完整平坦平面，减少了缺陷，避免了声波能量泄漏。
在本发明的第一方面和第二方面的谐振器制备方法中，衬底的材料为Si、SOI、Ge、GeOI、化合物半导体；介质层的材料为氧化物、氮化物或氮氧化物，优选地介质层与压电层晶格常数相同或相近；任选地，压电层的材料为ZnO、AlN、BST(钛酸锶钡)、BT(钛酸钡)、PZT(锆钛酸铅)、 PBLN(铌酸铅钡锂)、PT(钛酸铅)，进一步优选地压电材料中掺杂稀土元素；任选地，下电极或上电极的材料为选自Mo、W、Ru、Al、Cu、Ti、Ta、In、Zn、Zr、Fe、Mg的金属单质或金属合金、或者这些金属的导电氧化物、或导电氮化物，以及上述材料的任意组合。
此外，在本发明的第一方面和第二方面的谐振器制备方法中，形成下电极之前进一步包括，在衬底上形成衬垫层。其中，衬垫层材质为金属氮化物，优选地为AlN、HfN、HfAlN、TiN、TaN。
其中，在本发明的第一方面和第二方面的谐振器制备方法中，形成下电极之前进一步包括刻蚀衬底形成空腔并在空腔中填充牺牲层，形成上电极之后进一步包括湿法腐蚀去除牺牲层在衬底中留下谐振腔。
本发明所述目的，以及在此未列出的其他目的，在本申请独立权利要求的范围内得以满足。本发明的实施例限定在独立权利要求中，具体特征限定在其从属权利要求中。
附图说明
以下参照附图来详细说明本发明的技术方案，其中：
图1显示了根据现有技术的谐振器的剖视图；
图2至图7显示了根据本发明第一设计方案的实施例的谐振器制造工艺各个阶段的剖视图；
图8显示了根据本发明第一设计方案的实施例的谐振器制造工艺的流程图；
图9至图16显示了根据本发明第二设计方案的实施例的谐振器制造工艺各个阶段的剖视图；以及
图17A和图17B分别显示了根据本发明第二设计方案的实施例的谐振器制造工艺的不同实施例的流程图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果，公开了具有平坦表面的谐振器的制备方法。需要指出的是，类似的附图标记表示类似的结构，本申请中所用的术语“第一”、 “第二”、“上”、“下”等等可用于修饰各种器件结构。这些修饰除非特别说明并非暗示所修饰器件结构的空间、次序或层级关系。
第一设计方案的实施例
如图2、图8所示，在衬底10上形成下电极12。提供衬底10，材质可以是体Si或绝缘体上硅(SOI)或者体Ge、GeOI以与CMOS工艺兼容并与其他数字、模拟电路集成，也可以是用于MEMS、光电器件、功率器件的化合物半导体例如GaN、GaAs、SiC、InP、GaP等，进一步优选地，衬底10是单晶材料。刻蚀衬底10形成多个空腔，并沉积牺牲层10A填充。刻蚀工艺优选各向异性的干法刻蚀或湿法刻蚀，例如碳氟基刻蚀气体的反应离子刻蚀，或者TMAH的湿法腐蚀。沉积工艺为LPCVD、APCVD、PECVD等低温工艺(沉积温度低于500摄氏度，优选100至400摄氏度)，牺牲层10A材质为氧化硅基材料，诸如掺硼氧化硅(BSG)、掺磷氧化硅(PSG)、未掺杂氧化硅(USG)、多孔氧化硅等等，如此可以降低衬底10中残留热应力，并有利于提高后续刻蚀去除的速度以节省时间成本。
任选地，在形成下电极12之前可以进一步在牺牲层10A上形成衬垫层或种子层11，其材质与未来将要形成的压电层相同或相近，用于提高下电极边缘处的外延生长质量。沉积工艺例如磁控溅射、热蒸发、MOCVD等。在本发明一个优选实施例中，衬垫层或种子层11材质为金属氮化物，例如AlN、HfN、HfAlN、TiN、TaN等，且优选地同时可以用作防止下电极金属材料向下迁移的阻挡层以避免影响谐振腔顶部以及与下方膜层之间的界面状态。
随后，例如采用磁控溅射、热蒸发、MOCVD等，在衬底10和牺牲层10A之上形成下电极12，其材质例如Mo、W、Ru、Al、Cu、Ti、Ta、In、Zn、Zr、Fe、Mg等金属单质或金属合金，或者这些金属的导电氧化物、导电氮化物，以及上述材料的任意组合。如图2中所示，由于沉积工艺的限制，下电极12末端通常具有倾斜侧壁。优选地，形成下电极12之后采用各向异性刻蚀工艺去除下电极12末端的倾斜侧壁，使其具有垂直侧壁。此外，任选地，也可以在形成下电极期间在多个沉积工艺的子循环之间插入一个或多个刻蚀工艺子循环，使得最终得到的下电极具有垂直侧壁。
接着，如图3、图8所示，在下电极12和衬底10上形成介质层13。例如采用PECVD、UHCVD、HDPCVD、MOCVD、MBE、ALD、磁控溅射、热蒸发等工艺沉积介质层13，其材质可以是氧化物、氮化物或氮氧化物。在一个优选实施例中，介质层13为晶格常数与未来要形成的压电层晶格常数相同或相近的材料，例如AlN或SiOx、SiON等等。介质层13的初始厚度H0，由于采用 共形性良好的沉积工艺，介质层13在其在下电极12末端斜坡上也同样具有共形的斜坡，因此在牺牲层10A上方具有比衬底10上方更高的高度也即具有台阶差。原始厚度H0例如为0.05至10微米，优选0.1至5微米，最佳1至3微米，通过控制厚度H0可以控制薄膜质量，降低斜坡处的缺陷向上传播的几率或比例。
随后，如图4、图8所示，对介质层13执行平坦化工艺，例如采用CMP工艺，将其厚度H0减小为H1。厚度H1例如为100至2000埃，优选300至1000埃，以便利用较快的CMP工艺去除顶部薄膜质量不佳的部分。通过调节研磨液配比、研磨时间而调节研磨速度以便通过选择CMP工艺的终止节点时间而调整厚度H1。平坦化工艺之后，第一压电层13减薄为压电膜13’。优选地，通过SEM、激光干涉等方法测量压电膜13’的剩余厚度H1，以便精确地调节后续刻蚀工艺参数。
如图5、图8所示，按照剩余膜厚H1，对剩余的介质膜13’进行刻蚀，直至暴露下电极12。优选采用各向异性的干法刻蚀工艺。
如图6、图8所示，在具有平坦表面的下电极12和晶种区13”上形成压电层13B，用作最终器件的声-电转换元件。例如采用PECVD、UHVCVD、HDPCVD、MOCVD、MBE、ALD、磁控溅射、热蒸发等工艺沉积压电层13B，其材质例如ZnO、AlN、BST(钛酸锶钡)、BT(钛酸钡)、PZT(锆钛酸铅)、PBLN(铌酸铅钡锂)、PT(钛酸铅)等压电陶瓷材料；且优选地，压电层13B中掺杂稀土元素，例如包含钪(Sc)、钇(Y)、镧(La)、铈(Ce)、镨(Pr)、钕(Nd)、钷(Pm)、钐(Sm)、铕(Eu)、钆(Gd)、铽(Tb)、镝(Dy)、钬(Ho)、铒(Er)、铥(Tm)、镱(Yb)及镥(Lu)的任一种及其组合，以提高压电系数。
最后，如图7、图8所示，在压电层13B上形成上电极14，其工艺、材料与下电极12相同或相近。优选地，上电极14尺寸(例如图中宽度)大于下电极11以完全覆盖牺牲层10A，以便减小边缘处电场畸变影响谐振器Q值的可能性。随后，通过设置在器件外围的释放孔(未示出)，施加湿法腐蚀剂去除牺牲层图形。针对氧化硅基材料，采用HF基腐蚀液例如dHF(稀释HF)、dBOE(缓释刻蚀剂，HF与NH4F的混合物)去除牺牲层图形10A，留下多个谐振腔。
依照本发明的第一设计方案的平坦化FBAR谐振器制备方法，依次采用沉积、平坦化、刻蚀工艺分步在下电极上形成具有平坦表面的压电层，减少了缺陷，避免了声波能量泄漏。
第二设计方案的实施例
如图9、图17A、图17B所示，在衬底上形成下电极。提供衬底10，材质可以是体Si或绝缘体上硅(SOI)或者体Ge、GeOI以与CMOS工艺兼容并与其他数字、模拟电路集成，也可以是用于MEMS、光电器件、功率器件的化合物半导体例如GaN、GaAs、SiC、InP、GaP等，进一步优选地，衬底10是单晶材料。刻蚀衬底10形成多个空腔，并沉积牺牲层10A填充。刻蚀工艺优选各向异性的干法刻蚀或湿法刻蚀，例如碳氟基刻蚀气体的反应离子刻蚀，或者TMAH的湿法腐蚀。沉积工艺为LPCVD、APCVD、PECVD等低温工艺(沉积温度低于500摄氏度，优选100至400摄氏度)，牺牲层10A材质为氧化硅基材料，诸如掺硼氧化硅(BSG)、掺磷氧化硅(PSG)、未掺杂氧化硅(USG)、多孔氧化硅等等，如此可以降低衬底10中残留热应力，并有利于提高后续刻蚀去除的速度以节省时间成本。
任选地，在形成下电极12A之前可以进一步在牺牲层10A上形成衬垫层或种子层11，其材质与未来将要形成的压电层相同或相近，用于提高下电极边缘处的外延生长质量。沉积工艺例如磁控溅射、热蒸发、MOCVD等。在本发明一个优选实施例中，衬垫层或种子层11材质为金属氮化物，例如AlN、HfN、HfAlN、TiN、TaN等，且优选地同时可以用作防止下电极金属材料向下迁移的阻挡层以避免影响谐振腔顶部以及与下方膜层之间的界面状态。
随后，例如采用磁控溅射、热蒸发、MOCVD等，在衬底10和牺牲层10A之上形成下电极12A，其材质例如Mo、W、Ru、Al、Cu、Ti、Ta、In、Zn、Zr、Fe、Mg等金属单质或金属合金，或者这些金属的导电氧化物、导电氮化物，以及上述材料的任意组合。如图9中所示，由于沉积工艺的限制，下电极12A末端通常具有倾斜侧壁。优选地，形成下电极12A之后采用各向异性刻蚀工艺去除下电极12末端的倾斜侧壁，使其具有垂直侧壁。此外，形成下电极的过程可以包含交替的多个沉积子循环和多个刻蚀子循环，调节工作气体使得多个刻蚀子循环期间刻蚀之前多个沉积子循环形成的电极侧面使其具有垂直侧壁。
接着，在下电极12A和衬底10上形成压电层13A。例如采用LPCVD、PECVD、UHVCVD、HDPCVD、MOCVD、MBE、ALD、磁控溅射、热蒸发等，材质例如ZnO、AlN、BST(钛酸锶钡)、BT(钛酸钡)、PZT(锆钛酸铅)、PBLN(铌酸铅钡锂)、PT(钛酸铅)等压电陶瓷材料；且优选地，压电层13A中掺杂稀土元素，例如包含钪(Sc)、钇(Y)、镧(La)、铈(Ce)、镨(Pr)、钕(Nd)、钷(Pm)、钐(Sm)、铕(Eu)、钆(Gd)、铽(Tb)、镝(Dy)、钬(Ho)、铒(Er)、铥(Tm)、镱(Yb)及镥(Lu)的任一种及其组合，以提高压电系数。如图9所示，压电层13A 具有原始厚度H0，且由于采用共形性良好的沉积工艺，其在下电极12A末端斜坡上也同样具有共形的斜坡，因此在牺牲层10A上方具有比衬底10上方更高的高度也即具有台阶差。原始厚度H0例如为0.05至10微米，优选0.1至5微米，最佳1至3微米，通过控制厚度H0可以控制薄膜质量，降低斜坡处的缺陷向上传播的几率或比例。
随后，如图10、图17A、图17B所示，对压电层13A执行平坦化工艺，例如采用CMP工艺，将其厚度H0减小为H1。厚度H1例如为0至2000埃，优选100至1500埃，最佳800至1000埃，以便利用较快的CMP工艺去除顶部薄膜质量不佳的部分。通过调节研磨液配比、研磨时间而调节研磨速度以便通过选择CMP工艺的终止节点时间而调整厚度H1。平坦化工艺之后，压电层13A减薄为介质膜13A’。优选地，通过SEM、激光干涉等方法测量膜13A’的剩余厚度H1，以便精确地调节后续刻蚀工艺参数。
在本发明一个优选实施例中，参照图11、图17B所示，平坦化压电层13A之后，并未立即进行刻蚀暴露至下电极12A，而是进一步在压电层13A’上形成第二下电极12B，用于进一步提高第二压电层下方结构的平坦性并同时提高对于谐振器底部电场分布控制的精确度。第二下电极12B的沉积工艺和材料选择与下电极12A相同或相近。优选地，形成第二下电极12B之后刻蚀去除其端部的斜坡，使得第二下电极12B也同样具有垂直侧壁。优选地，第二下电极12B的厚度为10-100nm、进一步优选20-50nm、最佳30nm，以避免末端处台阶的形成同时也能兼顾对谐振腔的控制能力。
接着，如图12、图17B所示，在压电层13A’和第二下电极12B上形成第二压电层13B，其工艺和材质优选地与压电层13A’相同或相近。在优选实施例中，第二压电层13B与压电层13A材料完全相同，以便更好地提高堆叠结构之中上下层之间的结合强度。第二压电层13B具有原始厚度H0’，例如0.1-5微米、优选1-3微米、最佳2微米，有利于减薄在压电层13A’上的厚度从而节省后续工艺时间，且同时能够通过足够的厚度缓解下方缺陷对于顶部平坦表面的影响。
随后，如图13、图17B所示，对第二压电层13B执行平坦化工艺，将其原始厚度H0’减少为剩余厚度H1’，例如0至2000埃，优选100至1500埃，最佳800至1000埃，以便利用较快的CMP工艺去除顶部薄膜质量不佳的部分。
接着，如图14、图17B所示，按照剩余膜厚H1’，对剩余的第二压电层13B执行刻蚀工艺，直至暴露下电极12。优选采用各向异性的干法刻蚀工艺，例如等离子体干法刻蚀、反应离子刻蚀等。刻蚀工艺气体例如碳氟基刻蚀气体， 诸如CF4、CHF3、CH2F2、CH3F等等，也可以采用Cl2、HCl、Br2、HBr等其他卤素基气体，并可以进一步包括氧化性气体以调节刻蚀速度、去除残渣。最终第二压电层减薄为层13B’，其厚度等同于第二下电极12B的厚度。
在本发明另一个优选实施例中，如图17A所示，省略了图11-13的工艺，在平坦化了下电极12A上的压电层13A之后，立即采用图14所示的刻蚀工艺，刻蚀压电层13A直至暴露下电极12A，使得剩余压电膜13A’顶面与下电极12A顶面齐平，并以该顶面直接作为后续第二压电层沉积的起始平面。
如图15、图17A、图17B所示，在第二下电极12B或下电极12A上形成第三压电层14，例如采用LPCVD、PECVD、UHVCVD、HDPCVD、MOCVD、MBE、ALD、磁控溅射、热蒸发等，材质例如ZnO、AlN、BST(钛酸锶钡)、BT(钛酸钡)、PZT(锆钛酸铅)、PBLN(铌酸铅钡锂)、PT(钛酸铅)等压电陶瓷材料；且优选地，第三压电层14中掺杂稀土元素，例如包含钪(Sc)、钇(Y)、镧(La)、铈(Ce)、镨(Pr)、钕(Nd)、钷(Pm)、钐(Sm)、铕(Eu)、钆(Gd)、铽(Tb)、镝(Dy)、钬(Ho)、铒(Er)、铥(Tm)、镱(Yb)及镥(Lu)的任一种及其组合，以提高压电系数。
最后，如图16、图17A、图17B所示，在第三压电层14上形成上电极15。上电极15的工艺、材料与下电极12A/第二下电极12B相同或相近。优选地，上电极15尺寸(例如图中宽度)大于下电极/第二下电极以完全覆盖牺牲层10A，以便减小边缘处电场畸变影响谐振器Q值的可能性。随后，通过设置在器件外围的释放孔(未示出)，施加湿法腐蚀剂去除牺牲层图形。针对氧化硅基材料，采用HF基腐蚀液例如dHF(稀释HF)、dBOE(缓释刻蚀剂，HF与NH4F的混合物)去除牺牲层图形10A，留下多个谐振腔。此外，也可以形成了下电极12A并沉积压电层13A之后立即去除牺牲层图形10A而留下谐振腔。
依照本发明的第二设计方案的Q值提升的FBAR谐振器制造方法，依次采用沉积、平坦化、刻蚀工艺分步在下电极上形成具有平坦表面的压电层之后再形成第二压电层，减少了缺陷，避免了声波能量泄漏。
尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可以知晓无需脱离本发明范围而对器件结构做出各种合适的改变和等价方式。此外，由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此，本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例，而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims (17)

  1. 一种FBAR谐振器制备方法，包括：
    在衬底上形成下电极；
    在下电极和衬底上形成介质层，具有第一厚度；
    平坦化介质层以将第一厚度减小为第二厚度；
    刻蚀介质层直至暴露下电极；
    在下电极和衬底上形成压电层；
    在压电层上形成上电极。
  2. 一种FBAR谐振器制造方法，包括：
    在衬底上形成下电极；
    在下电极和衬底上形成压电层，具有第一厚度；
    平坦化压电层以将第一厚度减小为第五厚度；
    刻蚀压电层直至暴露下电极；
    在下电极和压电层上形成第二压电层；
    在第二压电层上形成上电极。
  3. 根据权利要求1或2所述的FBAR谐振器制造方法，形成下电极之前进一步包括，在衬底上形成衬垫层。
  4. 根据权利要求1或2所述的FBAR谐振器制造方法，其中，衬垫层材质为金属氮化物，优选地为AlN、HfN、HfAlN、TiN、TaN。
  5. 根据权利要求2所述的FBAR谐振器制造方法，刻蚀压电层直至暴露下电极、在下电极和压电层上形成第二压电层的步骤进一步包括：
    在压电层上形成第二下电极；
    在第二下电极上形成第二压电层，具有第三厚度；
    平坦化第二压电层以将第三厚度减小为第四厚度；
    刻蚀第二压电层直至暴露第二下电极；以及
    在第二下电极和第二压电层上形成第三压电层。
  6. 根据权利要求1所述的FBAR谐振器制造方法，其中，第一厚度为0.05-10微米，任选地第二厚度为100-2000埃。
  7. 根据权利要求2或5所述的FBAR谐振器制造方法，其中，第一厚度为0.05-10微米，任选地第五厚度为0-2000埃，任选地第三厚度为0.1-5微米，任选地第四厚度为0-2000埃，任选地第二下电极的厚度为10-100nm。
  8. 根据权利要求1所述的FBAR谐振器制造方法，其中，平坦化介质层之后测量第二厚度，并根据第二厚度调节刻蚀介质层的工艺参数。
  9. 根据权利要求2或5所述的FBAR谐振器制造方法，其中，平坦化压电层之后测量第五厚度并根据第五厚度调节刻蚀压电层的工艺参数，或者平坦化第二压电层之后测量第四厚度并根据第四厚度调节刻蚀第二压电层的工艺参数。
  10. 根据权利要求1、2或5所述的FBAR谐振器制造方法，其中，衬底的材料为Si、SOI、Ge、GeOI、化合物半导体；任选地，全部压电层的材料为ZnO、AlN、BST(钛酸锶钡)、BT(钛酸钡)、PZT(锆钛酸铅)、PBLN(铌酸铅钡锂)、PT(钛酸铅)，进一步优选地压电材料中掺杂稀土元素；任选地，下电极或上电极的材料为选自Mo、W、Ru、Al、Cu、Ti、Ta、In、Zn、Zr、Fe、Mg的金属单质或金属合金、或者这些金属的导电氧化物、或导电氮化物，以及上述材料的任意组合。
  11. 根据权利要求1或10所述的FBAR谐振器制造方法，其中，介质层的材料为氧化物、氮化物或氮氧化物，优选地介质层与压电层晶格常 数相同或相近。
  12. 根据权利要求1所述的FBAR谐振器制造方法，其中，在衬底上形成下电极之后下电极具有倾斜侧壁；优选地，形成介质层之前进一步包括刻蚀下电极的倾斜侧壁，使得下电极具有垂直侧壁。
  13. 根据权利要求2或5所述的FBAR谐振器制造方法，其中，在衬底上形成下电极之后下电极具有倾斜侧壁，或者在压电层上形成第二下电极之后第二下电极具有倾斜侧壁；优选地，形成压电层之前进一步包括刻蚀下电极的倾斜侧壁，使得下电极具有垂直侧壁；或者形成第二压电层之前进一步包括刻蚀第二下电极的倾斜侧壁，使得第二下电极具有垂直侧壁。
  14. 根据权利要求1所述的FBAR谐振器制造方法，其中，形成下电极期间在多个沉积工艺之间插入刻蚀工艺使得下电极具有垂直侧壁。
  15. 根据权利要求2所述的FBAR谐振器制造方法，其中，形成下电极或第二下电极的过程包含交替的多个沉积子循环和多个刻蚀子循环，调节工作气体使得多个刻蚀子循环期间刻蚀之前多个沉积子循环形成的电极侧面使其具有垂直侧壁。
  16. 根据权利要求1或2所述的FBAR谐振器制造方法，其中，形成下电极之前进一步包括刻蚀衬底形成空腔并在空腔中填充牺牲层，形成上电极之后进一步包括湿法腐蚀去除牺牲层在衬底中留下谐振腔。
  17. 根据权利要求1所述的FBAR谐振器制造方法，其中，上电极尺寸大于下电极尺寸。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116346067A (zh) * 2023-04-07 2023-06-27 中国科学院宁波材料技术与工程研究所 空腔型体声波谐振器及其制作方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050006984A1 (en) * 2003-07-09 2005-01-13 Tdk Corporation Thin-film bulk acoustic oscillator and method of manufacturing same
US20100107389A1 (en) * 2002-01-11 2010-05-06 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Method of fabricating an electrode for a bulk acoustic resonator
US20130106534A1 (en) * 2011-10-31 2013-05-02 Avago Technologies Wireless IP (Singapore) Ltd. Pte. Planarized electrode for improved performance in bulk acoustic resonators
US20150280679A1 (en) * 2014-03-26 2015-10-01 Avago Technologies General Ip (Singapore) Pte. Ltd Acoustic resonator with planarization layer and method of fabricating the same
CN112071975A (zh) * 2020-09-27 2020-12-11 苏州汉天下电子有限公司 平坦化fbar谐振器制备方法
CN112087217A (zh) * 2020-09-27 2020-12-15 苏州汉天下电子有限公司 Q值提升的fbar谐振器制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100107389A1 (en) * 2002-01-11 2010-05-06 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Method of fabricating an electrode for a bulk acoustic resonator
US20050006984A1 (en) * 2003-07-09 2005-01-13 Tdk Corporation Thin-film bulk acoustic oscillator and method of manufacturing same
US20130106534A1 (en) * 2011-10-31 2013-05-02 Avago Technologies Wireless IP (Singapore) Ltd. Pte. Planarized electrode for improved performance in bulk acoustic resonators
US20150280679A1 (en) * 2014-03-26 2015-10-01 Avago Technologies General Ip (Singapore) Pte. Ltd Acoustic resonator with planarization layer and method of fabricating the same
CN112071975A (zh) * 2020-09-27 2020-12-11 苏州汉天下电子有限公司 平坦化fbar谐振器制备方法
CN112087217A (zh) * 2020-09-27 2020-12-15 苏州汉天下电子有限公司 Q值提升的fbar谐振器制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116346067A (zh) * 2023-04-07 2023-06-27 中国科学院宁波材料技术与工程研究所 空腔型体声波谐振器及其制作方法

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