WO2021128490A1 - 无源噪声整形的逐次逼近型模数转换器 - Google Patents

无源噪声整形的逐次逼近型模数转换器 Download PDF

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WO2021128490A1
WO2021128490A1 PCT/CN2020/071166 CN2020071166W WO2021128490A1 WO 2021128490 A1 WO2021128490 A1 WO 2021128490A1 CN 2020071166 W CN2020071166 W CN 2020071166W WO 2021128490 A1 WO2021128490 A1 WO 2021128490A1
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passive
switched capacitor
output
noise shaping
circuit
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PCT/CN2020/071166
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English (en)
French (fr)
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孙楠
刘佳欣
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清华大学
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Publication of WO2021128490A1 publication Critical patent/WO2021128490A1/zh
Priority to US17/385,605 priority Critical patent/US11705920B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M3/424—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one
    • H03M3/426—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one the quantiser being a successive approximation type analogue/digital converter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H03M1/0854—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of quantisation noise
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array

Definitions

  • This application belongs to the technical field of integrated circuit design, and in particular relates to a successive approximation analog-to-digital converter for passive noise shaping.
  • An analog-to-digital converter is an electronic device that can convert an analog signal in the real world into a digital signal in an electronic system.
  • the Noise Shaping Successive Approximation Register (SAR) ADC is a high-precision ADC structure, which has a wide range of applications in the Internet of Things, wearable devices, implantable medical electronics and other fields.
  • the core of the noise shaping SAR ADC is the noise shaping circuit.
  • the function of the noise shaping circuit is to integrate and store the conversion residual of the ADC, provide the necessary gain, and add it to the signal on the switched capacitor array. According to whether the circuit contains active circuits such as operational amplifiers, noise shaping SAR ADCs can be divided into two categories: active and passive.
  • the existing passive noise shaping SAR ADC mainly implements the following two schemes.
  • the noise shaping circuit part includes two passive integrators, two gain stages and two adders.
  • the function of each module is described as follows: the passive integrator obtains the conversion residual on the switched capacitor array, integrates it and stores it, the integrated signal stored on the passive integrator is Vint; because the passive integrator uses the capacitance between the capacitors The principle of charge free exchange realizes integration.
  • the signal Vint obtained by integration is attenuated, so it needs to be amplified by the gain stage.
  • the amplified integral signal is G*Vint, where G is the gain of the gain stage; finally, the switch capacitor is switched through the adder
  • the signal Vin on the array and the amplified integrated signal are added together, and the result of the addition is Vin+G*Vint, which is sent to both ends of the comparator.
  • the disadvantage of the above-mentioned scheme is that the implementation complexity of the noise shaping circuit is relatively high, the stability is poor or the power consumption is high, because the gain stage and the adder both consume additional hardware overhead. If a dynamic amplifier is used to realize the gain stage, the circuit structure of the dynamic amplifier is more complicated and the stability is poor. If a multi-input comparator is used to realize the gain stage and adder, the power consumption of the multi-input comparator is very high.
  • the noise shaping circuit part includes a residual acquisition circuit and two passive integrators.
  • the function description of each module is as follows:
  • the residual error acquisition circuit acquires the conversion residual on the switched capacitor array, and then transmits the acquired residual signal to the passive integrator;
  • the passive integrator integrates and stores the residual difference signal, and stores it in
  • scheme 2 has a simpler circuit structure than scheme 1, but scheme 2 can only achieve twice the gain of the integrated signal, and the noise shaping effect is poor, because the noise shaping effect depends on the gain. The larger the gain, the stronger the realistic shaping ability. In addition, the residual acquisition circuit will introduce greater circuit noise, which will reduce the accuracy of the ADC.
  • This application aims to solve one of the technical problems in the related technology at least to a certain extent.
  • the purpose of this application is to propose a passive noise shaping successive approximation analog-to-digital converter, which can realize the amplification of the integrated signal without using an operational amplifier and a multiple-input comparator. , Simple structure, low power consumption.
  • an embodiment of the present application proposes a passive noise shaping successive approximation analog-to-digital converter, including: two switched capacitor arrays, a noise shaping circuit, a comparator, and a logic circuit;
  • the noise shaping circuit is a passive integration network, and the input ends of the passive integration network are respectively connected to the output ends of the two switched capacitor arrays, and are used to obtain the output signals of the two switched capacitor arrays.
  • the passive integration network is composed of a plurality of sub-passive integrators, and different circuit forms are realized by reconstructing the structure of the plurality of sub-passive integrators;
  • the two input terminals of the comparator are respectively connected to the output terminal of the passive integration network, and the output terminal is connected to the input terminal of the logic circuit.
  • the comparator is used to compare the magnitude of the output signal of the noise shaping circuit and compare Output the result to the logic circuit;
  • the two output terminals of the logic circuit are respectively connected to the input terminals of the two switched capacitor arrays, the other output terminal outputs a digital output signal, and the logic circuit is used to output the digital output signal and process the comparison result to obtain
  • the control signal controls the output voltage of the two switched capacitor arrays according to the control signal.
  • the successive approximation analog-to-digital converter of passive noise shaping in the embodiment of the present application reconstructs the noise shaping circuit, efficiently utilizes the hardware resources of the circuit, and realizes the passive noise shaping SAR ADC with extremely low hardware cost.
  • this solution can also achieve arbitrarily large gains, which in turn can achieve strong noise shaping capabilities.
  • successive approximation analog-to-digital converter of passive noise shaping may also have the following additional technical features:
  • the analog-to-digital converter includes a residual processing stage, a sampling stage, and a conversion stage;
  • the passive integration network structure is deformed in the margin processing stage and the conversion stage.
  • the multiple sub-passive integrators of the passive integration network are connected in parallel with each other, and after the multiple sub-passive integrators are connected in parallel with each other
  • the two input terminals of are respectively connected to the output terminals of the two switched capacitor arrays, and the output terminals are disconnected from the comparator;
  • the passive integration network obtains the residual signal Vres of the last cycle of the switched capacitor array, and after the integration is completed, the integrated signal on each passive integrator is Vint.
  • the switched capacitor array collects the analog input signal Vin, and the passive integration network is in any circuit form.
  • the passive integrator network in the conversion stage, is split into two groups of multiple sub-passive integrators in series with each other, and the input end of each group of sub-passive integrators
  • the output terminal of the switched capacitor array is connected, and the output terminal is connected to an input terminal of the comparator.
  • the output signal of the switched capacitor array enters the noise shaping circuit, and after being integrated with the residual signal in the noise shaping circuit, two output signals are output. Path signal to the comparator;
  • the magnitude of the signal is compared by the comparator, and the comparison result is output to the logic circuit.
  • the logic circuit processes the comparison result to obtain the control signal, and controls the control signal through two signals respectively. Two switched capacitor arrays, the switched capacitor arrays adjust the output voltage according to the control signal, and cycle sequentially;
  • the conversion phase ends, and the logic circuit outputs a digital output signal.
  • the passive integration network is implemented by capacitors and switching devices.
  • Figure 1 is the first existing passive noise shaping SAR ADC structure block diagram
  • FIG. 2 is a block diagram of the existing second passive noise shaping SAR ADC
  • Fig. 3 is a schematic structural diagram of a noise SAR ADC according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of the circuit structure of the successive approximation analog-to-digital converter of passive noise shaping according to an embodiment of the present application in the residual processing stage;
  • FIG. 5 is a schematic diagram of the circuit structure of the successive approximation analog-to-digital converter of passive noise shaping according to an embodiment of the present application at the sampling stage;
  • FIG. 6 is a schematic diagram of the circuit structure of a successive approximation analog-to-digital converter of passive noise shaping according to an embodiment of the present application at the conversion stage;
  • FIG. 7 is a schematic diagram of an implementation scheme of a successive approximation analog-to-digital converter of passive noise shaping according to an embodiment of the present application
  • Fig. 8 is a schematic diagram of an equivalent circuit of a residual acquisition phase according to an embodiment of the present application.
  • Fig. 9 is a schematic diagram of an equivalent circuit of a sampling stage according to an embodiment of the present application.
  • Fig. 10 is a schematic diagram of an equivalent circuit of a conversion stage according to an embodiment of the present application.
  • the structure of the noisy SAR ADC is shown in Figure 3(a). It mainly consists of two switched capacitor arrays, a noise shaping circuit, a comparator, and a logic circuit.
  • One operation cycle of a noisy SAR ADC consists of three stages: sampling, conversion, and residual processing.
  • the conversion stage includes multiple comparison processes.
  • Margin processing stage The noise shaping circuit processes the residual signal remaining on the switched capacitor array, and the processing result is stored in the noise shaping circuit.
  • the embodiment of the present application reconstructs the noise shaping circuit, and designs a reconfigurable noise shaping SAR ADC, which can realize the amplification of the integrated signal without using an operational amplifier and multiple input comparators, thereby greatly Reduce circuit complexity and power consumption.
  • FIG. 4 is a schematic diagram of the circuit structure of the successive approximation analog-to-digital converter of passive noise shaping according to an embodiment of the present application in the residual processing stage.
  • the successive approximation analog-to-digital converter of passive noise shaping includes: two switched capacitor arrays, a noise shaping circuit, a comparator, and a logic circuit.
  • the input terminal of the switched capacitor array collects analog input signals
  • the noise shaping circuit is a passive integration network.
  • the input terminals of the passive integration network are respectively connected to the output terminals of the two switched capacitor arrays to obtain the output signals of the two switched capacitor arrays.
  • the passive integration network is integrated by multiple sub-passives The structure of multiple sub-passive integrators can be reconstructed to realize different circuit forms;
  • the two input terminals of the comparator are respectively connected to the output terminal of the passive integrator network, and the output terminal is connected to the input terminal of the logic circuit.
  • the comparator is used to compare the size of the output signal of the noise shaping circuit and output the comparison result to the logic circuit;
  • the two output terminals of the logic circuit are respectively connected to the input terminals of the two switched capacitor arrays, and the other output terminal outputs a digital output signal.
  • the logic circuit is used to output the digital output signal and process the comparison result to obtain the control signal, and control the two according to the control signal.
  • the output voltage of a switched capacitor array is used to output the digital output signal and process the comparison result to obtain the control signal, and control the two according to the control signal.
  • the passive integrator network is a form of multiple sub-passive integrators in parallel with each other.
  • the passive integration network is disconnected from the comparator, and at the same time, the two input ends of the passive integration network are connected to the output ends of the two switched capacitor arrays to obtain the residual signal Vres of the last cycle of the switched capacitor array.
  • the final The integrated signal stored in each sub-passive integrator is Vint.
  • the switched capacitor array collects the analog input signal Vin.
  • the passive integrator network can be configured into any circuit form, and each sub-passive integrator still retains the integral signal Vint obtained in the previous stage.
  • the passive integrator network is split into two sets of structures connected in series, and each set is connected to the output of the switched capacitor array. Between the terminal and an input terminal of the comparator. At this time, each sub-passive integrator still retains the integrated signal of Vint. Assuming that the total number of sub-passive integrators is G, the signal at both ends of the comparator is Vin+G*Vint, which realizes the function of gain and addition of G times, and no additional hardware overhead is required to realize the gain stage and adder.
  • the output signal of the switched capacitor array enters the noise shaping circuit, and after integrating with the residual signal in the noise shaping circuit, two signals are output to the comparator;
  • the signal size is compared by the comparator, and the comparison result is output to the logic circuit.
  • the logic circuit processes the comparison result to obtain the control signal, and controls the two switched capacitor arrays respectively through the two signals, and the switched capacitor array adjusts the output according to the control signal Voltage, cycle in turn;
  • the conversion phase ends, and the logic circuit outputs a digital output signal.
  • the passive integration network can be implemented by capacitors and switching devices.
  • FIG. 7 it is a schematic diagram of an implementation scheme of a successive approximation analog-to-digital converter with passive noise shaping.
  • Fig. 7(a) is a circuit structure diagram, and the circuit structure in Fig. 7 can realize a noise transfer function of (1-0.8z -1 ).
  • the logic circuit part is omitted in the figure.
  • the sub-passive integrators are realized by capacitors, and the connection and disconnection between devices are realized by switches.
  • the total capacitance value in each switched capacitor circuit is C
  • the sub-capacitance value in the passive integration network is C/2.
  • the control sequence of the switch is shown in Figure 7(b).
  • the control signal is high to indicate that the switch is closed, and the signal is low to indicate that the switch is off.
  • Vres(n-1) Vin(n-1)-Dout(n-1) (1)
  • the signal on the integrating capacitor is:
  • Vint(n) 0.8*Vint(n-1)+0.2*Vres(n-1) (2)
  • ⁇ cnv is high
  • ⁇ s and ⁇ int are low
  • ⁇ cmp is a continuous pulse signal.
  • the comparator is activated and the comparison operation is performed.
  • the passive integrator network is configured in the form of two sets of capacitors connected in series, and they are respectively connected between the output terminal of a switched capacitor array and an input terminal of the comparator. At this time, the signals at both ends of the comparator are:
  • Vcmp(n) Vin(n)+4Vint(n) (3)
  • the ADC converts Vcmp(n) into the digital output signal of the current cycle, which is:
  • Q(n) is the quantization noise introduced in the conversion stage of the nth cycle.
  • the passive noise shaping successive approximation analog-to-digital converter proposed in the embodiment of the present application, by reconstructing the noise shaping circuit, the hardware resources of the circuit are efficiently used, and the passive noise shaping SAR is realized at a very low hardware cost.
  • ADC Analog to digital converter
  • dynamic amplifiers or multi-input comparators to realize the functions of gain and adder, and it has the advantages of simple circuit structure, good stability and low power consumption.
  • this solution can also achieve arbitrarily large gains, which in turn can achieve strong noise shaping capabilities.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include at least one of the features. In the description of the present application, "a plurality of” means at least two, such as two, three, etc., unless specifically defined otherwise.
  • the terms “installed”, “connected”, “connected”, “fixed” and other terms should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection , Or integrated; it can be mechanically connected or electrically connected; it can be directly connected or indirectly connected through an intermediary, it can be the internal connection of two components or the interaction relationship between two components, unless otherwise specified The limit.
  • installed can be a fixed connection or a detachable connection , Or integrated; it can be mechanically connected or electrically connected; it can be directly connected or indirectly connected through an intermediary, it can be the internal connection of two components or the interaction relationship between two components, unless otherwise specified The limit.
  • the first feature “on” or “under” the second feature may be in direct contact with the first and second features, or the first and second features may be indirectly through an intermediary. contact.
  • the "above”, “above” and “above” of the first feature on the second feature may mean that the first feature is directly above or diagonally above the second feature, or it simply means that the level of the first feature is higher than the second feature.
  • the “below”, “below” and “below” of the second feature of the first feature may mean that the first feature is directly below or obliquely below the second feature, or it simply means that the level of the first feature is smaller than the second feature.

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Abstract

本申请公开了一种无源噪声整形的逐次逼近型模数转换器，包括：开关电容阵列采集模拟输入信号；噪声整形电路为一个无源积分网络，输入端分别连接两个开关电容阵列的输出端，用于获取两个开关电容阵列的输出信号，无源积分网络由多个子无源积分器组成，通过对多个子无源积分器结构进行重构实现不同的电路形式；比较器的两个输入端分别连接无源积分网络的输出端，输出端连接逻辑电路输入端，用于比较噪声整形电路输出信号的大小；逻辑电路的两个输出端分别连接两个开关电容阵列的输入端，另一个输出端输出数字输出信号。该模数转换器可以在不采用运算放大器和多路输入比较器的情况下实现对积分信号的放大，结构简单、功耗低。

Description

无源噪声整形的逐次逼近型模数转换器
相关申请的交叉引用
本申请要求清华大学于2019年12月27日提交的、发明名称为“无源噪声整形的逐次逼近型模数转换器”的、中国专利申请号“201911382808.X”的优先权。
技术领域
本申请属于集成电路设计技术领域，特别涉及一种无源噪声整形的逐次逼近型模数转换器。
背景技术
模数转换器(Analog-to-digital converter，ADC)是一种能将现实世界中的模拟信号转换成在电子系统中的数字信号的电子器件。噪声整形逐次逼近型(Successive Approximation Register，SAR)ADC是一种高精度的ADC结构，在物联网、可穿戴设备、可植入医疗电子等领域有着广泛的应用。
噪声整形SAR ADC的核心是噪声整形电路，噪声整形电路的功能是对ADC的转换余差进行积分、存储，提供必要的增益，并将其与开关电容阵列上的信号相加起来。根据电路中是否包含运算放大器等有源电路，可将噪声整形SAR ADC分为有源和无源两大类。现有的无源噪声整形SAR ADC主要以下两种实现方案。
第一种方案如图1所示，噪声整形电路部分包含两个无源积分器、两个增益级和两个加法器。各模块功能描述如下：无源积分器获取开关电容阵列上的转换余差，将其积分并存储起来，存储在无源积分器上的积分信号为Vint；由于无源积分器采用电容之间的电荷自由交换原理实现积分，积分得到的信号Vint有衰减，因此需要通过增益级将其放大，放大后的积分信号为G*Vint，其中G为增益级的增益；最后，通过加法器将开关电容阵列上的信号Vin和放大后的积分信号加起来，相加结果为Vin+G*Vint，并输送到比较器的两端。
上述方案的缺点是噪声整形电路的实现复杂度较高，稳定性差或功耗高，因为增益级和加法器都要消耗额外的硬件开销。若采用动态放大器来实现增益级，但动态放大器的电路结构较为复杂，而且稳定性较差。若采用多路输入的比较器来实现增益级和加法器，但多路输入比较器的功耗非常高。
第二种方案如图2所示，噪声整形电路部分包含一个余差获取电路和两个无源积分器。 各模块功能描述如下：余差获取电路获取开关电容阵列上的转换余差，然后将获取到的余差信号输送到无源积分器；无源积分器将其余差信号积分并存储起来，存储在无源积分器上的积分信号为Vint；由于无源积分器堆叠在开关电容阵列和比较器之间，因此比较器两端的信号为Vin+2*Vint，即通过这种堆叠的方式获得了G＝2的增益。
上述方案2比方案1电路结构简单，但方案2仅能实现对积分信号的两倍增益，噪声整形效果较差，因为噪声整形效果取决于增益，增益越大，可现实的整形能力越强。此外，余差获取电路会引入较大的电路噪声，进而会降低ADC的精度。
发明内容
本申请旨在至少在一定程度上解决相关技术中的技术问题之一。
为此，本申请的目的在于提出一种无源噪声整形的逐次逼近型模数转换器，该模数转换器可以在不采用运算放大器和多路输入比较器的情况下实现对积分信号的放大，结构简单、功耗低。
为达到上述目的，本申请实施例提出了一种无源噪声整形的逐次逼近型模数转换器，包括：两个开关电容阵列、噪声整形电路、比较器、逻辑电路；
所述开关电容阵列的输入端采集模拟输入信号；
所述噪声整形电路为一个无源积分网络，所述无源积分网络的输入端分别连接所述两个开关电容阵列的输出端，用于获取所述两个开关电容阵列的输出信号，所述无源积分网络由多个子无源积分器组成，通过对所述多个子无源积分器结构进行重构实现不同的电路形式；
所述比较器的两个输入端分别连接所述无源积分网络的输出端，输出端连接所述逻辑电路输入端，所述比较器用于比较所述噪声整形电路输出信号的大小，并将比较结果输出到所述逻辑电路；
所述逻辑电路的两个输出端分别连接所述两个开关电容阵列的输入端，另一个输出端输出数字输出信号，所述逻辑电路用于输出数字输出信号以及对所述比较结果进行处理得到控制信号，根据所述控制信号控制所述两个开关电容阵列的输出电压。
本申请实施例的无源噪声整形的逐次逼近型模数转换器，通过对噪声整形电路进行重构，高效利用了电路的硬件资源，以极低的硬件成本实现了无源噪声整形SAR ADC。不需要动态放大器或多路输入的比较器来实现增益和加法器的功能，具有电路结构简单、稳定性好、功耗低的优势。此外，本方案还可以实现任意大的增益，进而可实现较强的噪声整形能力。
另外，根据本申请上述实施例的无源噪声整形的逐次逼近型模数转换器还可以具有以 下附加的技术特征：
进一步地，在本申请的一个实施例中，所述模数转换器包括余差处理阶段、采样阶段和转换阶段；
在所述余量处理阶段和所述转换阶段对所述无源积分网络结构进行变形。
进一步地，在本申请的一个实施例中，在所述余差处理阶段，将所述无源积分网络的所述多个子无源积分器相互并联，所述多个子无源积分器相互并联后的两个输入端分别连接所述两个开关电容阵列的输出端，输出端与所述比较器断开；
所述无源积分网络获取所述开关电容阵列的上一个周期的余差信号Vres，完成积分后，每个无源积分器上的积分信号均为Vint。
进一步地，在本申请的一个实施例中，在所述采样阶段，所述开关电容阵列采集模拟输入信号Vin，所述无源积分网络为任意电路形式。
进一步地，在本申请的一个实施例中，在所述转换阶段，将所述无源积分网络分裂成两组多个子无源积分器相互串联的结构，每组子无源积分器的输入端连接所述开关电容阵列的输出端，输出端连接所述比较器的一个输入端。
进一步地，在本申请的一个实施例中，在所述转换阶段，所述开关电容阵列的输出信号进入所述噪声整形电路，与所述噪声整形电路中已有余差信号进行整合后，输出两路信号到所述比较器；
通过所述比较器对信号大小进行比较，并将所述比较结果输出到所述逻辑电路，所述逻辑电路对所述比较结果进行处理得到所述控制信号，并通过两路信号分别控制所述两个开关电容阵列，所述开关电容阵列根据所述控制信号调节输出电压，依次循环；
当循环次数达到所述开关电容阵列的位数后，转换阶段结束，所述逻辑电路输出数字输出信号。
进一步地，在本申请的一个实施例中，所述无源积分网络通过电容和开关器件实现。
本申请附加的方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本申请的实践了解到。
附图说明
本申请上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1为现有的第一种无源噪声整形SAR ADC结构框图；
图2为现有的第二种无源噪声整形SAR ADC结构框图；
图3为根据本申请一个实施例的噪声SAR ADC的结构示意图；
图4为根据本申请一个实施例的无源噪声整形的逐次逼近型模数转换器在余差处理阶段的电路结构示意图；
图5为根据本申请一个实施例的无源噪声整形的逐次逼近型模数转换器在采样阶段的电路结构示意图；
图6为根据本申请一个实施例的无源噪声整形的逐次逼近型模数转换器在转换阶段的电路结构示意图；
图7为根据本申请一个实施例的无源噪声整形的逐次逼近型模数转换器的一种实现方案示意图；
图8为根据本申请一个实施例的余差采集阶段的等效电路示意图；
图9为根据本申请一个实施例的采样阶段的等效电路示意图；
图10为根据本申请一个实施例的转换阶段的等效电路示意图。
具体实施方式
下面详细描述本申请的实施例，实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本申请，而不能理解为对本申请的限制。
下面参照附图描述根据本申请实施例提出的无源噪声整形的逐次逼近型模数转换器。
如图3所示，噪声SAR ADC的结构如图3(a)所示，主要有两个开关电容阵列、噪声整形电路、比较器和逻辑电路构成。噪声SAR ADC的一次操作周期由采样、转换和余差处理三个阶段构成，其中转换阶段包含多次比较过程。结合图3(b)，其工作流程描述如下：
(1)余量处理阶段：噪声整形电路对开关电容阵列上残留的余差信号进行处理，处理结果存储在噪声整形电路中。
(2)采样阶段：开关电容阵列采集模拟输入信号。
(3)转换阶段：开关电容阵列的输出信号进入噪声整形电路，与噪声整形电路中已有的信号进行整合后，输出两路信号到比较器，比较器对信号大小进行比较，比较结果进入逻辑电路，逻辑电路对比较结果进行处理，并输出两路信号分别控制两个开关电容阵列，开关电容阵列根据控制信号调节其输出电压，依次循环；当循环次数达到开关电容阵列的位数后，转换阶段结束。
本申请的实施例对噪声整形电路进行重构，设计一种可重构的噪声整形SAR ADC，可以在不采用运算放大器和多路输入比较器的情况下实现对积分信号的放大，从而可 以大幅降低电路复杂度和功耗。
图4为根据本申请一个实施例的无源噪声整形的逐次逼近型模数转换器在余差处理阶段的电路结构示意图。
如图4所示，无源噪声整形的逐次逼近型模数转换器包括：两个开关电容阵列、噪声整形电路、比较器、逻辑电路。
其中，开关电容阵列的输入端采集模拟输入信号；
噪声整形电路为一个无源积分网络，无源积分网络的输入端分别连接两个开关电容阵列的输出端，用于获取两个开关电容阵列的输出信号，无源积分网络由多个子无源积分器组成，通过对多个子无源积分器结构进行重构实现不同的电路形式；
比较器的两个输入端分别连接无源积分网络的输出端，输出端连接逻辑电路输入端，比较器用于比较噪声整形电路输出信号的大小，并将比较结果输出到逻辑电路；
逻辑电路的两个输出端分别连接两个开关电容阵列的输入端，另一个输出端输出数字输出信号，逻辑电路用于输出数字输出信号以及对比较结果进行处理得到控制信号，根据控制信号控制两个开关电容阵列的输出电压。
可以理解的是，在模数转换器的不同阶段对噪声整形电路中的无源积分网络进行重构，可以实现不同的电路功能，结构简单，功耗低。
如图4所示，为无源噪声整形的逐次逼近型模数转换器的余差处理阶段，在此阶段，无源积分网络为多个子无源积分器相互并联的形式。无源积分网络与比较器断开连接，同时无源积分网络的两个输入端与两个开关电容阵列的输出端相连，获取开关电容阵列上一周期的余差信号Vres，完成积分后，最终存储在每个子无源积分器上的积分信号均为Vint。
如图5所示，为无源噪声整形的逐次逼近型模数转换器的采样阶段，开关电容阵列采集模拟输入信号Vin。在此阶段，无源积分网络可配置成任意电路形式，每个子无源积分器上仍保留上一阶段得到的积分信号Vint。
如图6所示，为无源噪声整形的逐次逼近型模数转换器的转换阶段，在此阶段，无源积分网络分裂成两组相互串联的结构，每组分别连接在开关电容阵列的输出端和比较器的一个输入端之间。此时，每个子无源积分器上仍保留上Vint的积分信号。假设子无源积分器的总数为G，则比较器两端的信号为Vin+G*Vint，实现了G倍的增益和加法的功能，同时不需要额外的硬件开销来实现增益级和加法器。
进一步地，在转换阶段，开关电容阵列的输出信号进入噪声整形电路，与噪声整形电路中已有余差信号进行整合后，输出两路信号到比较器；
通过比较器对信号大小进行比较，并将比较结果输出到逻辑电路，逻辑电路对比较结果进行处理得到控制信号，并通过两路信号分别控制两个开关电容阵列，开关电容阵列根 据控制信号调节输出电压，依次循环；
当循环次数达到开关电容阵列的位数后，转换阶段结束，逻辑电路输出数字输出信号。
进一步地，在本申请的一个实施例中，无源积分网络可通过电容和开关器件实现。
如图7所示，为无源噪声整形的逐次逼近型模数转换器的一种实现方案示意图。图7(a)为电路结构图，图7中的电路结构可以实现噪声传递函数为(1-0.8z -1)。为简便起见，图中省略了逻辑电路部分。图中的无源积分网络中共有4个子无源积分器，子无源积分器采用电容来实现，器件之间的连接与断开采用开关实现。每个开关电容电路中的总电容值为C，无源积分网络中的子电容值为C/2。开关的控制时序如图7(b)所示，控制信号为高电平表示开关闭合，信号为低电平表示开关断开。
如图8所示，在第(n-1周期)余差处理阶段，Φint为高，Φs、Φcnv和Φcmp为低。此时，比较器处于待机状态(图中已省略)，4个子积分电容相互并联从开关电容电路上获取第(n-1)周期的余差信号Vres(n-1)，该余差信号为模拟输入信号与数字输出信号之间的差值，即：
Vres(n-1)＝Vin(n-1)-Dout(n-1)                                (1)
余差采集阶段结束后，在第n个转换周期过程中，积分电容上的信号为：
Vint(n)＝0.8*Vint(n-1)+0.2*Vres(n-1)                      (2)
如图9所示，在第n周期的采样阶段，Φs为高，Φint、Φcnv和Φcmp为低。此时，比较器依然处于待机状态(图中已省略)，无源积分网络与开关电容阵列断开连接关系，每个子积分电容上依然保留积分信号Vint(n)。同时，开关电容阵列采集到第n周期的输入信号Vin(n)，该信号保存在开关电容阵列上。
如图10所示，在第n周期的转换阶段，Φcnv为高，Φs、Φint为低，Φcmp为连续脉冲信号。此时，比较器被激活，执行比较操作。无源积分网络被配置成两组电容相串联的形式，并分别连接在一个开关电容阵列的输出端和比较器的一个输入端之间。此时比较器两端的信号为：
Vcmp(n)＝Vin(n)+4Vint(n)                    (3)
经过数个循环的比较，转换阶段结束时，ADC将Vcmp(n)转换为当前周期的数字输出信号，其为：
Dout(n)＝Vcmp(n)+Q(n)                      (4)
其中，Q(n)为在第n周期的转换阶段引入的量化噪声。
将公式(1-4)结合起来，可以得到：
Dout(n)＝Vin(n)+Q(n)-0.8*Q(n-1)               (5)
将公式(5)从时域转化到z域，可以得到：
Dout(z)＝Vin(z)+(1-0.8z -1)Q(z)                (6)
即实现了对量化噪声的(1-0.8z -1)整形。
根据本申请实施例提出的无源噪声整形的逐次逼近型模数转换器，通过对噪声整形电 路进行重构，高效利用了电路的硬件资源，以极低的硬件成本实现了无源噪声整形SAR ADC。不需要动态放大器或多路输入的比较器来实现增益和加法器的功能，具有电路结构简单、稳定性好、功耗低的优势。此外，本方案还可以实现任意大的增益，进而可实现较强的噪声整形能力。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”、“顺时针”、“逆时针”、“轴向”、“径向”、“周向”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本申请的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
在本申请中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系，除非另有明确的限定。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征“上”或“下”可以是第一和第二特征直接接触，或第一和第二特征通过中间媒介间接接触。而且，第一特征在第二特征“之上”、“上方”和“上面”可是第一特征在第二特征正上方或斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”可以是第一特征在第二特征正下方或斜下方，或仅仅表示第一特征水平高度小于第二特征。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本申请的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本申请的限制，本领域的普通技术人员在本申请的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (7)

  1. 一种无源噪声整形的逐次逼近型模数转换器，其特征在于，包括：
    两个开关电容阵列、噪声整形电路、比较器、逻辑电路；
    所述开关电容阵列的输入端采集模拟输入信号；
    所述噪声整形电路为一个无源积分网络，所述无源积分网络的输入端分别连接所述两个开关电容阵列的输出端，用于获取所述两个开关电容阵列的输出信号，所述无源积分网络由多个子无源积分器组成，通过对所述多个子无源积分器结构进行重构实现不同的电路形式；
    所述比较器的两个输入端分别连接所述无源积分网络的输出端，输出端连接所述逻辑电路输入端，所述比较器用于比较所述噪声整形电路输出信号的大小，并将比较结果输出到所述逻辑电路；
    所述逻辑电路的两个输出端分别连接所述两个开关电容阵列的输入端，另一个输出端输出数字输出信号，所述逻辑电路用于输出数字输出信号以及对所述比较结果进行处理得到控制信号，根据所述控制信号控制所述两个开关电容阵列的输出电压。
  2. 根据权利要求1所述的一种无源噪声整形的逐次逼近型模数转换器，其特征在于，所述模数转换器包括余差处理阶段、采样阶段和转换阶段；
    在所述余量处理阶段和所述转换阶段对所述无源积分网络结构进行变形。
  3. 根据权利要求2所述的一种无源噪声的整形逐次逼近型模数转换器，其特征在于，
    在所述余差处理阶段，将所述无源积分网络的所述多个子无源积分器相互并联，所述多个子无源积分器相互并联后的两个输入端分别连接所述两个开关电容阵列的输出端，输出端与所述比较器断开；
    所述无源积分网络获取所述开关电容阵列的上一个周期的余差信号Vres，完成积分后，每个无源积分器上的积分信号均为Vint。
  4. 根据权利要求2所述的一种无源噪声整形的逐次逼近型模数转换器，其特征在于，
    在所述采样阶段，所述开关电容阵列采集模拟输入信号Vin，所述无源积分网络为任意电路形式。
  5. 根据权利要求2所述的一种无源噪声整形的逐次逼近型模数转换器，其特征在于，
    在所述转换阶段，将所述无源积分网络分裂成两组多个子无源积分器相互串联的结构，每组子无源积分器的输入端连接所述开关电容阵列的输出端，输出端连接所述比较器的一个输入端。
  6. 根据权利要求5所述的一种无源噪声整形的逐次逼近型模数转换器，其特征在于，
    在所述转换阶段，所述开关电容阵列的输出信号进入所述噪声整形电路，与所述噪声整形电路中已有余差信号进行整合后，输出两路信号到所述比较器；
    通过所述比较器对信号大小进行比较，并将所述比较结果输出到所述逻辑电路，所述逻辑电路对所述比较结果进行处理得到所述控制信号，并通过两路信号分别控制所述两个开关电容阵列，所述开关电容阵列根据所述控制信号调节输出电压，依次循环；
    当循环次数达到所述开关电容阵列的位数后，转换阶段结束，所述逻辑电路输出数字输出信号。
  7. 根据权利要求1所述的一种无源噪声整形的逐次逼近型模数转换器，其特征在于，所述无源积分网络通过电容和开关器件实现。
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