WO2021111243A1 - 半導体装置および電子機器 - Google Patents

半導体装置および電子機器 Download PDF

Info

Publication number
WO2021111243A1
WO2021111243A1 PCT/IB2020/061059 IB2020061059W WO2021111243A1 WO 2021111243 A1 WO2021111243 A1 WO 2021111243A1 IB 2020061059 W IB2020061059 W IB 2020061059W WO 2021111243 A1 WO2021111243 A1 WO 2021111243A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor
insulator
transistor
conductor
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2020/061059
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
津田一樹
郷戸宏充
大下智
國武寛司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2021562199A priority Critical patent/JP7714471B2/ja
Priority to KR1020227018560A priority patent/KR20220110201A/ko
Priority to US17/776,342 priority patent/US12207462B2/en
Priority to CN202080084468.7A priority patent/CN114787998A/zh
Publication of WO2021111243A1 publication Critical patent/WO2021111243A1/ja
Anticipated expiration legal-status Critical
Priority to US19/004,719 priority patent/US20260122891A1/en
Priority to JP2025119962A priority patent/JP2025157403A/ja
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/693—Vertical IGFETs having charge trapping gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices

Definitions

  • One aspect of the present invention relates to semiconductor devices and electronic devices.
  • One aspect of the present invention is not limited to the above technical fields.
  • the technical field of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method.
  • one aspect of the invention relates to a process, machine, manufacture, or composition of matter. Therefore, more specifically, the technical fields of one aspect of the present invention disclosed in the present specification include semiconductor devices, display devices, liquid crystal display devices, light emitting devices, power storage devices, image pickup devices, storage devices, signal processing devices, and processors.
  • Electronic devices, systems, their driving methods, their manufacturing methods, or their inspection methods can be mentioned as examples.
  • CPUs central processing units
  • GPUs graphics processing units
  • storage devices and sensors
  • sensors have been used in various electronic devices such as personal computers, smartphones, and digital cameras. Improvements are progressing in various aspects such as miniaturization and low power consumption.
  • Patent Document 1 and Patent Document 2 disclose a NAND memory device having a three-dimensional structure using a metal oxide as a channel forming region.
  • One aspect of the present invention is to provide a highly reliable storage device. Alternatively, one aspect of the present invention is to provide a storage device having a large storage capacity. Alternatively, one aspect of the present invention is to provide a new storage device. Alternatively, one aspect of the present invention is to provide a highly reliable semiconductor device. Alternatively, one aspect of the present invention is to provide a semiconductor device having a large storage capacity. Alternatively, one aspect of the present invention is to provide a novel semiconductor device.
  • the problems of one aspect of the present invention are not limited to the problems listed above.
  • the issues listed above do not preclude the existence of other issues.
  • Other issues are issues not mentioned in this item, which are described below. Issues not mentioned in this item can be derived from descriptions in the description, drawings, etc. by those skilled in the art, and can be appropriately extracted from these descriptions.
  • one aspect of the present invention solves at least one of the above-listed problems and other problems. It should be noted that one aspect of the present invention does not need to solve all of the above-listed problems and other problems.
  • One aspect of the present invention includes a structure extending in the first direction, a first conductor extending in the second direction, and a second conductor extending in the second direction. Is a third conductor extending in the first direction, a first insulator adjacent to the third conductor, a first semiconductor adjacent to the first semiconductor, and a second semiconductor adjacent to the first semiconductor.
  • the structure includes a second semiconductor adjacent to the second semiconductor, a third semiconductor adjacent to the second semiconductor, and the like.
  • the structure is a second insulator.
  • It has a fourth conductor adjacent to the fourth semiconductor, a second semiconductor adjacent to the fourth semiconductor, and a third insulator adjacent to the second semiconductor, and at the first intersection, the first insulator, the first The semiconductor, the second insulator, the second semiconductor, the third insulator, the functional body, and the fourth insulator are concentrically provided on the outside of the third conductor when viewed from the first direction, and at the second intersection. , The first insulator, the first semiconductor, the second insulator, the fourth conductor, the second semiconductor, and the third insulator are concentrically provided outside the third conductor when viewed from the first direction. It is a semiconductor device.
  • the first direction is a direction orthogonal to the second direction. Further, the first intersection functions as a first transistor, and the second intersection functions as a second transistor and a capacitive element. At least one of the first semiconductor and the second semiconductor may be silicon.
  • An insulator or a semiconductor can be used as the functional body.
  • the first transistor can be made into a MONOS type transistor.
  • the first transistor can be made into an FG type transistor.
  • the threshold voltage of the first transistor can be increased, and the first transistor can be made into a normally-off type transistor. Therefore, the first transistor can be a normally-off type transistor, and the second transistor can be a normally-on type transistor.
  • At least one of the first semiconductor and the second semiconductor may be an oxide semiconductor.
  • the oxide semiconductor preferably contains at least one of indium and zinc.
  • Another aspect of the present invention is an electronic device having the above-mentioned semiconductor device and at least one of an operation switch, a battery, and a display unit.
  • a highly reliable storage device can be provided.
  • a storage device having a large storage capacity can be provided.
  • a new storage device can be provided.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device having a large storage capacity can be provided.
  • a new semiconductor device can be provided.
  • the effects of one aspect of the present invention are not limited to the effects listed above.
  • the effects listed above do not preclude the existence of other effects.
  • the other effects are the effects not mentioned in this item, which are described below. Effects not mentioned in this item can be derived from those described in the description, drawings, etc. by those skilled in the art, and can be appropriately extracted from these descriptions.
  • one aspect of the present invention has at least one of the above-listed effects and other effects. Therefore, one aspect of the present invention may not have the effects listed above in some cases.
  • FIG. 1A is a perspective view of a memory cell.
  • FIG. 1B is a cross-sectional view of the memory cell.
  • 2A and 2B are cross-sectional views of the memory cell.
  • FIG. 3 is a perspective view of the structure.
  • 4A to 4C are equivalent circuit diagrams of memory cells.
  • 5A and 5B are equivalent circuit diagrams of memory cells.
  • FIG. 6 is a cross-sectional view of the memory string.
  • FIG. 7 is an equivalent circuit diagram of the memory string.
  • FIG. 8 is an equivalent circuit diagram of the memory string.
  • FIG. 9 is an equivalent circuit diagram of the memory string.
  • FIG. 10 is an equivalent circuit diagram of a memory string.
  • 11A and 11B are top views of the memory string.
  • 12A and 12B are cross-sectional views of the memory cell.
  • FIG. 13 is a cross-sectional view of the memory cell.
  • FIG. 14A is a diagram illustrating the classification of crystal structures.
  • FIG. 14B is a diagram illustrating an XRD spectrum of the CAAC-IGZO film.
  • FIG. 14C is a diagram illustrating a microelectron diffraction pattern of the CAAC-IGZO film.
  • 15A and 15B are cross-sectional views illustrating a method of manufacturing a memory cell.
  • 16A and 16B are cross-sectional views illustrating a method of manufacturing a memory cell.
  • 17A and 17B are cross-sectional views illustrating a method of manufacturing a memory cell.
  • 18A and 18B are cross-sectional views illustrating a method of manufacturing a memory cell.
  • 19A and 19B are cross-sectional views illustrating a method of manufacturing a memory cell.
  • 20A and 20B are cross-sectional views illustrating a method of manufacturing a memory cell.
  • 21A and 21B are cross-sectional views illustrating a method of manufacturing a memory cell.
  • 22A and 22B are cross-sectional views illustrating a method of manufacturing a memory cell.
  • FIG. 23 is a circuit diagram of the semiconductor device.
  • FIG. 24 is a timing chart illustrating an operation example of the semiconductor device.
  • 25A and 25B are timing charts for explaining an operation example of the semiconductor device.
  • FIG. 26A is a perspective view illustrating a configuration example of the semiconductor device.
  • FIG. 26B is a top view illustrating a configuration example of the semiconductor device.
  • FIG. 26C is a cross-sectional view illustrating a configuration example of the semiconductor device.
  • FIG. 27A is a perspective view illustrating a configuration example of the semiconductor device.
  • FIG. 27B is a top view illustrating a configuration example of the semiconductor device.
  • FIG. 27C is a cross-sectional view illustrating a configuration example of the semiconductor device.
  • 28A and 28B are cross-sectional views illustrating the semiconductor device.
  • 29A and 29B are cross-sectional views illustrating the semiconductor device.
  • FIG. 30 is a block diagram illustrating a configuration example of the semiconductor device.
  • FIG. 31 is a diagram illustrating a configuration example of the semiconductor device.
  • FIG. 32 is a diagram illustrating an example of constructing an information processing system using a plurality of storage devices.
  • FIG. 33 is a block diagram illustrating a CPU.
  • 34A and 34B are perspective views of the semiconductor device.
  • 35A and 35B are perspective views of the semiconductor device.
  • 36A and 36B are perspective views of the semiconductor device.
  • 37A is a perspective view showing an example of a semiconductor wafer
  • FIG. 37B is a perspective view showing an example of a chip
  • FIGS. 37C and 37D are perspective views showing an example of an electronic component.
  • 38A and 38B are diagrams showing various storage devices layer by layer.
  • 39A to 39J are perspective views or schematic views illustrating an example of an electronic device.
  • 40A to 40E are perspective views or schematic views illustrating an example of an electronic device.
  • 41A to 41C are diagrams illustrating an example of an electronic device.
  • FIG. 42 is a diagram illustrating a configuration example of a computer system.
  • FIG. 43 is a diagram showing the hierarchical structure of the IoT network and the tendency of the required specifications.
  • FIG. 44 is an image diagram of factory automation.
  • FIG. 45A is a perspective conceptual diagram of the semiconductor device.
  • FIG. 45B is an equivalent circuit diagram of a memory cell.
  • FIG. 46 is a timing chart illustrating the operation of the 3DOSN AND string.
  • FIG. 47A is a diagram showing the Id-Vwg characteristics of the transistor WTr.
  • FIG. 47B is a diagram showing the relationship between the threshold voltage of the transistor WTr and Vpre.
  • 48A and 48B are diagrams showing the holding characteristics of the 3DOS NAND string.
  • 49A and 49B are diagrams showing simulation results of memory cell holding characteristics.
  • FIG. 50 is a diagram showing simulation results of memory cell holding data and read current Irbl.
  • the semiconductor device is a device utilizing semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having the same circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip having an integrated circuit, and an electronic component in which the chip is housed in a package are examples of semiconductor devices. Further, the storage device, the display device, the light emitting device, the lighting device, the electronic device, and the like are themselves semiconductor devices, and may have the semiconductor device.
  • an element for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display
  • One or more devices, light emitting devices, loads, etc. can be connected between X and Y.
  • the switch has a function of controlling the on state and the off state. That is, the switch is in a conducting state (on state) or a non-conducting state (off state), and has a function of controlling whether or not a current flows.
  • a circuit that enables functional connection between X and Y for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), signal conversion, etc.) Circuits (digital-to-analog conversion circuit, analog-to-digital conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes the signal potential level, etc.), voltage source, current source , Switching circuit, amplification circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplification circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, storage circuit, control circuit, etc.) It is possible to connect one or more to and from. As an example, even if another circuit is sandwiched between X and Y, if the signal output from X is transmitted to Y, it is assumed that X and Y are functionally connected. To do.
  • X and Y are electrically connected, it means that X and Y are electrically connected (that is, another element between X and Y). Or when they are connected with another circuit in between) and when X and Y are directly connected (that is, they are connected without another element or another circuit between X and Y). If there is) and.
  • X and Y, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and the X, the source (or the second terminal, etc.) of the transistor are connected to each other. (1 terminal, etc.), the drain of the transistor (or the 2nd terminal, etc.), and Y are electrically connected in this order.
  • the source of the transistor (or the first terminal, etc.) is electrically connected to X
  • the drain of the transistor (or the second terminal, etc.) is electrically connected to Y
  • the X, the source of the transistor (such as the second terminal).
  • the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order.
  • X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor. (Terminals, etc.), transistor drains (or second terminals, etc.), and Y are provided in this connection order.
  • the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor can be separated. Separately, the technical scope can be determined. Note that these expression methods are examples, and are not limited to these expression methods.
  • X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
  • circuit diagram shows that the independent components are electrically connected to each other, one component has the functions of a plurality of components.
  • one component has the functions of a plurality of components.
  • the term "electrically connected” as used herein includes the case where one conductive film has the functions of a plurality of components in combination.
  • the “resistance element” can be, for example, a circuit element having a resistance value higher than 0 ⁇ , wiring, or the like. Therefore, in the present specification and the like, the “resistive element” includes a wiring having a resistance value, a transistor in which a current flows between a source and a drain, a diode, a coil, and the like. Therefore, the term “resistance element” can be paraphrased into terms such as “resistance”, “load”, and “region having resistance value”, and conversely, the terms “resistance”, “load”, and “region having resistance value” are used. , “Resistance element” and so on.
  • the resistance value can be, for example, preferably 1 m ⁇ or more and 10 ⁇ or less, more preferably 5 m ⁇ or more and 5 ⁇ or less, and further preferably 10 m ⁇ or more and 1 ⁇ or less. Further, for example, it may be 1 ⁇ or more and 1 ⁇ 10 9 ⁇ or less.
  • the “capacitance element” means, for example, a circuit element having a capacitance value higher than 0F, a wiring region having a capacitance value, a parasitic capacitance, a transistor gate capacitance, and the like. Can be. Therefore, in the present specification and the like, the “capacitive element” is not only a circuit element containing a pair of electrodes and a dielectric contained between the electrodes, but also a parasitic element appearing between the wirings. It shall include the capacitance, the gate capacitance that appears between the gate and one of the source or drain of the transistor, and so on.
  • capacitor element in addition, terms such as “capacitive element”, “parasitic capacitance”, and “gate capacitance” can be paraphrased into terms such as “capacity”, and conversely, the term “capacity” refers to “capacitive element”, “parasitic capacitance”, and “capacity”. It can be paraphrased into terms such as “gate capacitance”.
  • the term “pair of electrodes” of “capacity” can be paraphrased as “pair of conductors", “pair of conductive regions", “pair of regions” and the like.
  • the value of the capacitance can be, for example, 0.05 fF or more and 10 pF or less. Further, for example, it may be 1 pF or more and 10 ⁇ F or less.
  • the transistor has three terminals called a gate, a source, and a drain.
  • the gate is a control terminal that controls the conduction state of the transistor.
  • the two terminals that function as sources or drains are the input and output terminals of the transistor.
  • One of the two input / output terminals becomes a source and the other becomes a drain depending on the high and low potentials given to the conductive type (n-channel type, p-channel type) of the transistor and the three terminals of the transistor. Therefore, in the present specification and the like, the terms of source and drain can be paraphrased.
  • the transistor when explaining the connection relationship of transistors, "one of the source or drain” (or the first electrode or the first terminal), “the other of the source or drain” (or the second electrode, or The notation (second terminal) is used.
  • it may have a back gate in addition to the above-mentioned three terminals.
  • one of the gate or the back gate of the transistor may be referred to as a first gate
  • the other of the gate or the back gate of the transistor may be referred to as a second gate.
  • the terms “gate” and “backgate” may be interchangeable.
  • the respective gates When the transistor has three or more gates, the respective gates may be referred to as a first gate, a second gate, a third gate, and the like in the present specification and the like.
  • a node can be paraphrased as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, or the like, depending on a circuit configuration, a device structure, or the like.
  • terminals, wiring, etc. can be paraphrased as nodes.
  • ground potential ground potential
  • the potentials are relative, and when the reference potential changes, the potential given to the wiring, the potential applied to the circuit or the like, the potential output from the circuit or the like also changes.
  • high level potential also referred to as” high level potential ",” H potential “, or” H
  • low level potential low level potential
  • L low level potential
  • the "current” is a charge transfer phenomenon (electrical conduction).
  • the description “electrical conduction of a positively charged body is occurring” means “electrical conduction of a negatively charged body in the opposite direction”. Is happening. " Therefore, in the present specification and the like, “current” refers to a charge transfer phenomenon (electrical conduction) accompanying the movement of carriers, unless otherwise specified.
  • the carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system in which the current flows (for example, semiconductor, metal, electrolyte, vacuum, etc.).
  • the "current direction” in the wiring or the like is the direction in which the positive carrier moves, and the amount of current is described as a positive value.
  • the direction in which the negative carrier moves is opposite to the direction of the current, and the amount of current is described as a negative value. Therefore, in the present specification and the like, if there is no notice about the positive or negative of the current (or the direction of the current), the description such as “current flows from element A to element B” means “current flows from element B to element A” or the like. It can be paraphrased as. Further, the description such as “a current is input to the element A” can be rephrased as "a current is output from the element A” or the like.
  • the ordinal numbers “first”, “second”, and “third” are added to avoid confusion of the components. Therefore, the number of components is not limited. Moreover, the order of the components is not limited. For example, the component referred to in “first” in one of the embodiments of the present specification and the like may be the component referred to in “second” in another embodiment or in the claims. There can also be. Further, for example, the component mentioned in “first” in one of the embodiments of the present specification and the like may be omitted in another embodiment or in the claims.
  • the terms “upper” and “lower” do not limit the positional relationship of the components to be directly above or directly below and to be in direct contact with each other.
  • the terms “electrode B on the insulating layer A” it is not necessary that the electrode B is formed in direct contact with the insulating layer A, and another configuration is formed between the insulating layer A and the electrode B. Do not exclude those that contain elements.
  • the positional relationship of the constituent elements changes as appropriate according to the direction in which each configuration is depicted. Therefore, it is not limited to the words and phrases explained in the specification and the like, and can be appropriately paraphrased according to the situation.
  • terms indicating the arrangement such as “above” and “below” may be used for convenience in order to explain the positional relationship of the components with reference to the drawings. Therefore, in the expression of "insulator located on the upper surface of the conductor”, it can be rephrased as “insulator located on the lower surface of the conductor” by rotating the direction of the drawing shown by 180 degrees. Further, in the expression of "insulator located on the upper surface of the conductor”, it can be paraphrased as "insulator located on the left side (or right side) of the conductor” by rotating the direction of the drawing shown by 90 degrees. it can.
  • electrode B overlapping the insulating layer A is not limited to the state of "the electrode B is formed on the insulating layer A", but “the electrode B is formed under the insulating layer A”. It does not exclude the state of "being” or the state of "the electrode B is formed on the right side (or left side) of the insulating layer A”.
  • the terms “adjacent” and “proximity” do not limit that the components are in direct contact with each other.
  • electrode B adjacent to the insulating layer A it is not necessary that the insulating layer A and the electrode B are formed in direct contact with each other, and another component is formed between the insulating layer A and the electrode B. Do not exclude those that include.
  • membrane and layer can be interchanged with each other depending on the situation.
  • Electrode may be used as part of a “wiring” and vice versa.
  • the terms “electrode” and “wiring” include the case where a plurality of “electrodes” and “wiring” are integrally formed.
  • a “terminal” may be used as part of a “wiring” or “electrode” and vice versa.
  • the term “terminal” includes a case where a plurality of "electrodes", “wiring”, “terminals” and the like are integrally formed.
  • the "electrode” can be a part of the “wiring” or the “terminal”, and for example, the “terminal” can be a part of the “wiring” or the “electrode”.
  • terms such as “electrode”, “wiring”, and “terminal” may be replaced with terms such as "area” in some cases.
  • terms such as “wiring”, “signal line”, and “power supply line” can be interchanged with each other in some cases or depending on the situation.
  • the reverse is also true, and it may be possible to change terms such as “signal line” and “power supply line” to the term “wiring”.
  • a term such as “power line” may be changed to a term such as "signal line”.
  • terms such as “signal line” may be changed to terms such as "power line”.
  • the term “potential” applied to the wiring may be changed to a term such as “signal” in some cases or depending on the situation.
  • the reverse is also true, and terms such as “signal” may be changed to the term “potential”.
  • the semiconductor impurities refer to, for example, other than the main components constituting the semiconductor layer.
  • an element having a concentration of less than 0.1 atomic% is an impurity.
  • the inclusion of impurities may result in, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, a decrease in crystallinity, and the like.
  • the impurities that change the characteristics of the semiconductor include, for example, group 1 element, group 2 element, group 13 element, group 14 element, group 15 element, and other than the main component.
  • transition metals and the like and in particular, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like.
  • impurities that change the characteristics of the semiconductor include, for example, Group 1 elements other than oxygen and hydrogen, Group 2 elements, Group 13 elements, Group 15 elements, and the like. There is.
  • the switch means a switch that is in a conductive state (on state) or a non-conducting state (off state) and has a function of controlling whether or not a current flows.
  • the switch means a switch having a function of selecting and switching a path through which a current flows.
  • an electric switch, a mechanical switch, or the like can be used. That is, the switch is not limited to a specific switch as long as it can control the current.
  • Examples of electrical switches include transistors (for example, bipolar transistors, MOS transistors, etc.), diodes (for example, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, and MIS (Metal Insulator Semiconductor) diodes. , Diode-connected transistors, etc.), or logic circuits that combine these.
  • transistors for example, bipolar transistors, MOS transistors, etc.
  • diodes for example, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, and MIS (Metal Insulator Semiconductor) diodes. , Diode-connected transistors, etc.
  • the "conducting state" of the transistor means a state in which the source electrode and the drain electrode of the transistor can be regarded as being electrically short-circuited.
  • the "non-conducting state" of the transistor means a state in which the source electrode and the drain electrode of the transistor can be regarded as being electrically cut off.
  • the polarity (conductive type) of the transistor is not particularly limited.
  • a mechanical switch is a switch using MEMS (Micro Electro Mechanical System) technology.
  • the switch has an electrode that can be moved mechanically, and by moving the electrode, it operates by controlling conduction and non-conduction.
  • the “on current” may mean a current flowing between the source and the drain when the transistor is in the on state.
  • the “off current” may mean a current flowing between the source and the drain when the transistor is in the off state.
  • parallel means a state in which two straight lines are arranged at an angle of ⁇ 10 ° or more and 10 ° or less. Therefore, the case of ⁇ 5 ° or more and 5 ° or less is also included.
  • substantially parallel or approximately parallel means a state in which two straight lines are arranged at an angle of ⁇ 30 ° or more and 30 ° or less.
  • vertical means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 ° or more and 95 ° or less is also included.
  • substantially vertical or “approximately vertical” means a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.
  • a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS) and the like. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel forming region of a transistor having at least one of an amplification action, a rectifying action, and a switching action, the metal oxide is referred to as a metal oxide semiconductor. be able to. Further, when describing as an OS transistor, it can be paraphrased as a transistor having a metal oxide or an oxide semiconductor.
  • a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.
  • the configuration shown in each embodiment can be appropriately combined with the configuration shown in other embodiments to form one aspect of the present invention. Further, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.
  • the content (may be a part of the content) described in one embodiment is the other content (may be a part of the content) described in the embodiment and one or more other implementations. It is possible to apply, combine, or replace at least one content with the content described in the form of (may be a part of the content).
  • figure (which may be a part) described in one embodiment is different from another part of the figure, another figure (which may be a part) described in the embodiment, and one or more other figures.
  • the figure (which may be a part) described in the embodiment is different from another part of the figure, another figure (which may be a part) described in the embodiment, and one or more other figures.
  • more figures can be formed.
  • the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to its size and aspect ratio.
  • the drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in the signal, voltage, or current due to noise, or variations in the signal, voltage, or current due to timing lag.
  • the code is used for identification such as "_1", “[n]", “[m, n]”. May be added and described.
  • one of the two wiring GLs may be described as wiring GL [1], and the other may be described as wiring GL [2].
  • FIG. 1A shows a perspective view of the memory cell 100 according to one aspect of the present invention.
  • the memory cell 100 is a storage device having a three-dimensional laminated structure.
  • a part of the memory cell 100 is omitted in order to show the internal structure of the memory cell 100.
  • arrows indicating the X direction, the Y direction, and the Z direction may be added.
  • the X, Y, and Z directions are directions that are orthogonal to each other. In the present specification and the like, one of the X direction, the Y direction, and the Z direction may be referred to as a "first direction" or a "first direction".
  • the other one may be referred to as a "second direction” or a "second direction”. Further, the remaining one may be referred to as a "third direction” or a “third direction”. In the present embodiment and the like, the direction in which the structure 130, which will be described later, extends is the Z direction.
  • FIG. 1B is a cross-sectional view showing a part of the memory cell 100 shown in FIG. 1A. Further, FIG. 1B is a cross-sectional view of a part of the memory cell 100 as viewed from the Y direction. Further, FIG. 1B is a cross-sectional view of an XZ plane passing through the central axis 108.
  • FIG. 2A is a cross-sectional view of the portions A1-A2 shown by the alternate long and short dash line in FIG. 1B as viewed from the Z direction.
  • FIG. 2B is a cross-sectional view of the portions B1-B2 shown by the alternate long and short dash line in FIG. 1B as viewed from the Z direction.
  • the memory cell 100 has a plurality of insulators 101 arranged above the substrate (not shown).
  • the plurality of insulators 101 are laminated in order from the substrate side.
  • the i-th insulator 101 (i is an integer of 1 or more) is referred to as an insulator 101 [i].
  • FIG. 1B shows an insulator 101 [i + 1] arranged above the insulator 101 [i] and an insulator 101 [i + 2] arranged above the insulator 101 [i + 1].
  • the conductor 102 is provided between the insulator 101 [i] and the insulator 101 [i + 1]
  • the conductor 103 is provided between the insulator 101 [i + 1] and the insulator 101 [i + 2].
  • the insulator 101, the conductor 102, and the conductor 103 extend along the Y direction. Further, the memory cell 100 has an insulator 121 so as to cover the side surfaces of the insulator 101, the conductor 102, and the conductor 103.
  • the memory cell 100 has a structure 130.
  • the structure 130 extends in the Z direction along the central axis 108.
  • FIG. 3 shows a perspective view of the structure 130.
  • the structure 130 has a columnar shape. In FIG. 3, a part of the structure 130 is omitted in order to show the internal structure of the structure 130. A part of the structure 130 functions as a part of the memory cell 100. Further, as shown in FIGS. 1 and 3, the structure 130 has irregularities on the side surfaces extending in the Z direction.
  • the outer peripheral shape of the structure 130 is circular when the structure 130 is viewed from the Z direction is shown, but the outer peripheral shape of the structure 130 does not have to be circular.
  • it may be a polygon such as a triangle or a quadrangle.
  • the outer peripheral shape of the structure 130 may be formed of a curved line, or may be formed by combining a curved line and a straight line.
  • the structure 130 has a region that intersects the conductor 102 (also referred to as “intersection R”) and a region that intersects the conductor 103 (also referred to as “intersection W”). Further, the structure 130 includes an insulator 111, a functional body 112, an insulator 113, a semiconductor 114, a conductor 115, an insulator 116, a semiconductor 117, an insulator 118, and a conductor 119.
  • the conductor 119 extends in the Z direction along the central axis 108, and the insulator 118 is provided adjacent to the conductor 119. Further, the semiconductor 117 is provided adjacent to the insulator 118. Further, an insulator 116 is provided adjacent to the semiconductor 117.
  • a semiconductor 114 is provided adjacent to the insulator 116, an insulator 113 is provided adjacent to the semiconductor 114, and a functional body 112 is provided adjacent to the insulator 113 at the intersection W.
  • An insulator 111 is provided adjacent to the functional body 112.
  • FIG. 2A is a cross-sectional view of the intersection W in the direction perpendicular to the Z direction. At the intersection W, the insulator 111, the functional body 112, the insulator 113, the semiconductor 114, the insulator 116, the semiconductor 117, and the insulator 118 are concentrically provided on the outside of the conductor 119.
  • FIG. 2B is a cross-sectional view of the intersection R in the direction perpendicular to the Z direction.
  • the insulator 113, the semiconductor 114, the conductor 115, the insulator 116, the semiconductor 117, and the insulator 118 are concentrically provided on the outside of the conductor 119.
  • the transistor WTr is formed at the intersection W.
  • the conductor 103 functions as a gate electrode of the transistor WTr. Therefore, the insulator 111, the functional body 112, and the insulator 113 function as the gate insulator of the transistor WTr.
  • the semiconductor 114 functions as a semiconductor in which the channel of the transistor WTr is formed.
  • FIG. 2A is also a cross-sectional view of the transistor WTr seen from the Z direction.
  • the conductor 119, the insulator 118, the semiconductor 117, the insulator 116, and the conductor 115 function as the transistor RTr. Further, the conductor 115, the semiconductor 114, the insulator 113, and the conductor 102 function as capacitive elements Cs. Therefore, it can be said that the transistor RTr and the capacitive element Cs are formed at the intersection R.
  • FIG. 2B is also a cross-sectional view of the transistor RTr as viewed from the Z direction.
  • the functional body 112 included in the transistor WTr can function as a charge storage layer. By accumulating an electric charge in the functional body 112, the threshold voltage of the transistor WTr can be controlled. For example, by increasing the threshold voltage of the transistor WTr, the transistor WTr can be made into a normally-off type transistor.
  • the charge can be injected into the functional body 112 from the conductor 103 via the insulator 111.
  • the insulator 111 functions as an injection layer
  • the insulator 113 functions as a block layer.
  • the charge can be injected into the functional body 112 from the semiconductor 114 via the insulator 113.
  • the insulator 113 functions as an injection layer
  • the insulator 111 functions as a block layer.
  • the thickness of the injection layer when viewed from the direction perpendicular to the Z direction is preferably thinner than that of the block layer.
  • the transistor WTr can be called a MONOS (Metal Oxide Nitride Semiconductor) type transistor.
  • MONOS Metal Organic Semiconductor
  • n-type silicon or p-type silicon when n-type silicon or p-type silicon is used for the gate electrode, it can be called a SONOS (Silicon Oxide Nitride Semiconductor) type transistor.
  • SONOS Silicon Oxide Nitride Semiconductor
  • tantalum nitride when tantalum nitride is used for the gate electrode and aluminum oxide is used for the block layer, it can be called a TANOS (Tantalum nitride Oxide Nitride Semiconductor) type transistor.
  • TANOS Tetantalum nitride Oxide Nitride Semiconductor
  • tantalum nitride When tantalum nitride is used for the gate electrode and hafnium oxide is used for the block layer, it can be called a THNOS (Tantalum nitride Hafnium oxide Semiconductor) type transistor.
  • THNOS Tetantalum nitride Hafnium oxide Semiconductor
  • the functional body 112 that functions as the charge storage layer it is preferable to use a material having a bandgap smaller than that of the insulator 111 and the insulator 113.
  • silicon oxide may be used for the insulator 111 and the insulator 113
  • an insulator such as silicon nitride may be used for the functional body 112.
  • silicon nitride it is preferable to use silicon-rich silicon nitride.
  • silicon nitride when silicon nitride is used for the insulator 111 and the insulator 113, silicon nitride having a higher silicon content than the silicon nitride used for the insulator 111 and the insulator 113 may be used for the functional body 112.
  • the functional body 112 that functions as the charge storage layer may be a semiconductor.
  • a semiconductor such as silicon may be used as the functional body 112.
  • a transistor WTr using a semiconductor for the functional body 112 can be called an FG (Floating Gate) type transistor.
  • the insulator 111, the functional body 112, and the insulator 113 may each have a plurality of layers.
  • the insulator that functions as a block layer may be a laminate of silicon oxide and aluminum oxide.
  • FIG. 4A shows an equivalent circuit diagram of the memory cell 100.
  • one of the source or drain of the transistor WTr is electrically connected to the semiconductor 114 and the other of the source or drain is electrically connected to the gate of the transistor RTr.
  • the gate of the transistor WTr is electrically connected to the conductor 103.
  • the transistor WTr is a transistor having a charge storage layer between the gate and the semiconductor layer.
  • a part of the semiconductor 114 functions as a channel forming region of the transistor WTr.
  • the other part of the semiconductor 114 also functions as a source or drain of the transistor WTr.
  • the semiconductor 114 can also function as an electrode or wiring.
  • a part of the conductor 103 functions as a gate of the transistor WTr.
  • the transistor RTr shown in FIG. 4A is a transistor having a back gate.
  • a part of the conductor 119 functions as a back gate of the transistor RTr.
  • the other part of the semiconductor 114 and the conductor 115 function as a gate of the transistor RTr.
  • a part of the conductor 102 functions as the other electrode of the capacitive element Cs.
  • a part of the semiconductor 117 functions as one of the source and the drain of the transistor RTr.
  • the other part of the semiconductor 117 also functions as the source or drain of the transistor RTr.
  • the semiconductor 117 can also function as an electrode or wiring.
  • FIG. 4B corresponds to an equivalent circuit diagram of the memory cells 100B and the memory cells 100C described later.
  • a back gate may be provided in the transistor WTr.
  • FIG. 4C shows a circuit configuration example in which the back gate of the transistor WTr is electrically connected to the conductor 119, a conductor electrically connected to the back gate of the transistor WTr may be provided in addition to the conductor 119. ..
  • the circuit configuration may be as shown in FIG. 5A or FIG. 5B.
  • the conductor 102 functions as one electrode of the capacitive element Cs.
  • a part of the conductor 115 and the semiconductor 114 functions as the other electrode of the capacitive element Cs.
  • a node at which the gate of the transistor RTr, the other of the source or drain of the transistor WTr, and the other electrode of the capacitive element Cs are electrically connected is referred to as a node ND.
  • FIG. 6 shows a cross-sectional view of a memory string 200 including four memory cells 100 (memory cells 100 [1] to memory cells 100 [4]).
  • the memory string 200 shown in FIG. 6 includes a nine-layer insulator 101 (insulator 101 [1] to insulator 101 [9]) and a four-layer conductor 102 (conductor 102 [1] to conductor 102 [9]. 4]) and a four-layer conductor 103 (conductor 103 [1] to conductor 103 [4]).
  • FIG. 7 shows an equivalent circuit diagram of the memory string 200.
  • the memory string 200 has a configuration in which four memory cells 100 are connected in series. Therefore, the memory string 200 is a NAND type storage device.
  • OS may be added to the circuit symbol of the transistor in order to clearly indicate that the transistor is an OS transistor.
  • Si a transistor using silicon in the semiconductor layer on which the channel is formed
  • Si Si may be added to the circuit symbol of the transistor.
  • FIG. 7 shows that the transistor WTr and the transistor RTr are OS transistors.
  • the transistor WTr, the transistor RTr, and the capacitive element Cs included in the memory cell 100 [1] are shown as the transistor WTr [1], the transistor RTr [1], and the capacitive element Cs [1], respectively.
  • the transistor WTr, the transistor RTr, and the capacitive element Cs included in the memory cells 100 [2] to the memory cells 100 [4] are also shown.
  • the number of memory cells 100 included in the memory string 200 is not limited to 4. Assuming that the number of memory cells 100 included in the memory string 200 is n, n may be an integer of 2 or more.
  • the drain (or source) of the transistor WTr [k] included in the memory cell 100 [k] (k is an integer of 1 or more and n or less) is used.
  • the drain (or source) of the transistor RTr [k] included in the memory cell 100 [k] is electrically connected to the source (or drain) of the transistor WTr [k + 1] included in the memory cell 100 [k + 1]. It refers to a configuration electrically connected to the source (or drain) of the transistor RTr [k + 1] included in the memory cell 100 [k + 1].
  • a single crystal semiconductor, a polycrystalline semiconductor, a microcrystal semiconductor, an amorphous semiconductor, or the like can be used alone or in combination.
  • the semiconductor material for example, silicon, germanium, or the like can be used.
  • compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may be used.
  • the semiconductor used for the transistor may be a laminate of semiconductors.
  • semiconductors having different crystal states may be used, or different semiconductor materials may be used.
  • both the semiconductor 114 and the semiconductor 117 may be oxide semiconductors. Further, both the semiconductor 114 and the semiconductor 117 may be silicon. Further, the semiconductor 114 may be an oxide semiconductor and the semiconductor 117 may be silicon. Further, the semiconductor 114 may be silicon and the semiconductor 117 may be an oxide semiconductor.
  • the transistor WTr is preferably a transistor in which an oxide semiconductor, which is a kind of metal oxide, is used in the semiconductor layer on which a channel is formed. Since the oxide semiconductor has a band gap of 2 eV or more, the off-current is remarkably small.
  • an OS transistor is used as the transistor WTr, the electric charge written in the node ND (also referred to as “storage node”) can be retained for a long period of time.
  • the memory cell 100 can be referred to as an "OS memory”. Further, the memory string 200 including the memory cell 100 can also be called an “OS memory”.
  • a NAND type storage device including an OS memory is also referred to as an "OS NAND type” or an “OS NAND type storage device”. Further, an OS NAND type storage device having a configuration in which a plurality of OS memories are stacked in the Z direction is also referred to as a "3D OS NAND type” or a “3D OS NAND type storage device”.
  • the transistor RTr may be a transistor (also referred to as “Si transistor”) in which silicon is used in the semiconductor layer on which the channel is formed.
  • the transistor RTr may be formed of a Si transistor, and the transistor WTr may be formed of an OS transistor.
  • FIG. 8 shows an equivalent circuit diagram of the memory string 200 when an OS transistor is used as the transistor WTr and a Si transistor is used as the transistor RTr.
  • the OS memory can retain the written information for a period of one year or more, or even ten years or more, even if the power supply is stopped. Therefore, the OS memory can be regarded as a non-volatile memory.
  • the OS memory can hold not only binary information (1 bit) but also multi-value (multi-bit) information.
  • the OS memory is a method of writing an electric charge to a node via an OS transistor, a high voltage required for a conventional flash memory is not required, and a high-speed writing operation can be realized. Further, the erasing operation before data rewriting performed in the flash memory is unnecessary in the OS memory. Also, since no charge is injected or withdrawn into the floating gate or charge capture layer, the OS memory can write and read data virtually unlimited times. The OS memory has less deterioration than the conventional flash memory, and high reliability can be obtained.
  • OS memory does not undergo structural changes at the atomic level when data is rewritten. Therefore, the OS memory is superior in rewrite resistance to the magnetoresistive memory and the resistance change type memory.
  • the off-current of the OS transistor hardly increases even in a high temperature environment. Specifically, the off-current hardly increases even at an environmental temperature of room temperature or higher and 200 ° C. or lower. In addition, the on-current does not easily decrease even in a high temperature environment.
  • the storage device including the OS memory has stable operation even in a high temperature environment, and high reliability can be obtained. Further, the OS transistor has a high dielectric strength between the source and the drain. By using an OS transistor as a transistor constituting a semiconductor device, operation is stable even in a high temperature environment, and a semiconductor device with good reliability can be realized.
  • a Si transistor may be used as the transistor WTr and an OS transistor may be used as the transistor RTr depending on the purpose or application. Further, as shown in FIG. 10, a Si transistor may be used for both the transistor WTr and the transistor RTr depending on the purpose or application.
  • the storage capacity per unit area can be increased.
  • the plurality of memory cells 100 or the plurality of memory strings 200 are arranged in a staggered grid pattern (see FIG. 11A) or in a grid pattern (FIG. 11A). 11B) may be provided.
  • FIG. 11 is a top view of the memory string.
  • Table 1 shows a comparison table of a 3D NAND type storage device made of a Si transistor and a 3D OS NAND type storage device.
  • FIG. 12A shows a cross-sectional view of the memory cell 100A.
  • the memory cell 100A is a modification of the memory cell 100. Therefore, in the present embodiment and the like, the points different from the memory cell 100 of the memory cell 100A will be mainly described.
  • a semiconductor 114 is provided adjacent to the insulator 116 and a conductor 115 is provided adjacent to the semiconductor 114 at the intersection R.
  • the insulator 113 may be provided adjacent to the conductor 115.
  • the conductor 119, the insulator 118, the semiconductor 117, the insulator 116, the semiconductor 114, and the conductor 115 function as the transistor RTr.
  • the semiconductor 114 may function as a gate electrode. Further, the semiconductor 114 may function as a gate insulator. Further, the conductor 115, the insulator 113, and the conductor 102 function as capacitive elements Cs.
  • FIG. 12B shows a cross-sectional view of the memory cell 100B.
  • the memory cell 100B is a modification of the memory cell 100.
  • the formation of the conductor 119 that functions as a back gate may be omitted, and the conductor 118 may be filled.
  • the manufacturing process can be simplified and the productivity of the storage device can be increased.
  • FIG. 13 shows a cross-sectional view of the memory cell 100C.
  • the memory cell 100C is a modification of the memory cell 100, and is also a modification of the memory cell 100B.
  • the formation of the conductor 119 that functions as a back gate may be omitted, and the cavity 120 may be formed without filling the area where the conductor 119 is to be formed.
  • the memory cell 100 and the memory string 200 can be provided on the substrate.
  • the substrate for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used.
  • the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria-stabilized zirconia substrate, etc.), a resin substrate, and the like.
  • the semiconductor substrate includes, for example, a semiconductor substrate made of silicon or germanium, or a compound semiconductor made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, gallium nitride (GaN), or the like. There is a board.
  • the conductor substrate includes a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • a substrate having a metal nitride a substrate having a metal oxide, and the like.
  • a substrate in which a conductor or a semiconductor is provided in an insulator substrate a substrate in which a conductor or an insulator is provided in a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided in a conductor substrate, and the like.
  • those on which an element is provided may be used.
  • Elements provided on the substrate include a capacitance element, a resistance element, a switch element, a light emitting element, a storage element, and the like.
  • Insulator examples include oxides, nitrides, oxide nitrides, nitride oxides, metal oxides, metal oxide nitrides, metal nitride oxides and the like having insulating properties.
  • the material may be selected according to the function of the insulator.
  • Examples of the insulator having a high specific dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, nitrides having aluminum and hafnium, oxides having silicon and hafnium, silicon and hafnium. There are nitrides having oxides, or nitrides having silicon and hafnium.
  • Examples of insulators having a low specific dielectric constant include silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and empty. There are silicon oxide having holes, resin, and the like.
  • the OS transistor can stabilize the electrical characteristics of the transistor by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen.
  • the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, gallium, germanium, yttrium, zirconium, and lanthanum. Insulations containing, neodymium, hafnium, or tantalum may be used in single layers or in layers.
  • an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen
  • Metal oxides such as tantalum oxide and metal nitrides such as aluminum nitride, silicon nitride and silicon nitride can be used.
  • the “nitride oxide” refers to a material having a higher oxygen content than nitrogen as a main component.
  • silicon oxide nitride refers to a material containing silicon, nitrogen, and oxygen, which has a higher oxygen content than nitrogen.
  • the “nitride oxide” refers to a material having a higher nitrogen content than oxygen as a main component.
  • aluminum nitride oxide refers to a material containing aluminum, nitrogen, and oxygen, which has a higher nitrogen content than oxygen.
  • the insulator that functions as a gate insulator is preferably an insulator having a region containing oxygen that is desorbed by heating.
  • the oxygen deficiency of the semiconductor 114 and / or the semiconductor 117 can be compensated. Can be done.
  • the insulating layer formed of the above material may be used as a single layer as the insulator, but a plurality of insulating layers formed of the above material may be laminated and used.
  • an insulator when an insulator is provided in contact with a conductor, it is preferable to use an insulator having a function of suppressing oxygen permeation as the insulator in order to prevent oxidation of the conductor.
  • an insulator having a function of suppressing oxygen permeation for example, it is preferable to use hafnium oxide, aluminum oxide, silicon nitride or the like as the insulator.
  • an insulator when an insulator is laminated adjacent to the conductor, it is preferable to use an insulator having a function of suppressing oxygen permeation as the insulator in contact with the conductor.
  • hafnium oxide may be used to form an insulator in contact with a conductor
  • silicon oxide may be used to form an insulator in contact with the insulator.
  • Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum. It is preferable to use a metal element selected from the above, an alloy containing the above-mentioned metal element as a component, an alloy in which the above-mentioned metal element is combined, or the like.
  • tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. are used. Is preferable.
  • tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize.
  • the conductive layer formed of the above material may be used as a single layer, but a plurality of conductive layers formed of the above material may be laminated and used.
  • a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined.
  • a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing nitrogen are combined.
  • a laminated structure may be formed in which the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.
  • the conductor functioning as the gate electrode includes the above-mentioned material containing a metal element, a conductive material containing oxygen, and the like. It is preferable to use a laminated structure in which the above is combined. In this case, a conductive material containing oxygen may be provided on the channel forming region side. By providing the conductive material containing oxygen on the channel forming region side, oxygen separated from the conductive material can be easily supplied to the channel forming region.
  • a conductor that functions as a gate electrode it is preferable to use a conductive material containing a metal element contained in an oxide semiconductor in which a channel is formed and oxygen.
  • the above-mentioned conductive material containing a metal element and nitrogen may be used.
  • a conductive material containing nitrogen such as titanium nitride and tantalum nitride may be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added.
  • Indium tin oxide may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • Oxide semiconductor As the semiconductor 114 and / or the semiconductor 117, it is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor. In particular, it is preferable to use an oxide semiconductor for the semiconductor 114.
  • oxide semiconductor for the semiconductor 114.
  • the oxide semiconductor applicable to the memory cell 100 will be described.
  • the oxide semiconductor preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to them, it is preferable that aluminum, gallium, yttrium, tin and the like are contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt and the like may be contained.
  • the oxide semiconductor is an In—M—Zn oxide having indium, the element M, and zinc.
  • the element M may be one or more selected from aluminum, gallium, yttrium, and tin.
  • Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt and the like.
  • the element M a plurality of the above-mentioned elements may be combined in some cases.
  • FIG. 14A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (metal oxides containing In, Ga, and Zn).
  • IGZO metal oxides containing In, Ga, and Zn
  • oxide semiconductors are roughly classified into “Amorphous”, “Crystalline”, and “Crystal”.
  • Amorphous includes complete amorphous.
  • Crystalline includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite).
  • single crystal, poly crystal, and single crystal amorphous are excluded from the classification of "Crystalline”.
  • “Crystal” includes single crystal and poly crystal.
  • the structure in the thick frame shown in FIG. 14A is an intermediate state between "Amorphous” and “Crystal", and belongs to a new boundary region (New crystal line phase). .. That is, the structure can be rephrased as a structure completely different from the energetically unstable "Amorphous” and "Crystal".
  • the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD: X-Ray Diffraction) spectrum.
  • XRD X-ray diffraction
  • FIG. 14B the XRD spectrum obtained by GIXD (Glazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline" is shown in FIG. 14B.
  • the GIXD method is also referred to as a thin film method or a Seemann-Bohlin method.
  • the XRD spectrum obtained by the GIXD measurement shown in FIG. 14B will be simply referred to as an XRD spectrum.
  • the thickness of the CAAC-IGZO film shown in FIG. 14B is 500 nm.
  • a peak showing clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film.
  • the crystal structure of the film or substrate can be evaluated by a diffraction pattern (also referred to as a microelectron diffraction pattern) observed by a micro electron diffraction method (NBED: Nano Beam Electron Diffraction).
  • the diffraction pattern of the CAAC-IGZO film is shown in FIG. 14C.
  • FIG. 14C is a diffraction pattern observed by the NBED in which the electron beam is incident parallel to the substrate.
  • electron diffraction is performed with the probe diameter set to 1 nm.
  • oxide semiconductors When focusing on the crystal structure, oxide semiconductors may be classified differently from FIG. 14A.
  • oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors.
  • the non-single crystal oxide semiconductor include CAAC-OS (C Axis Aligned Crystal Semiconductor) and nc-OS (nanocrystalline Oxide Semiconductor).
  • the non-single crystal oxide semiconductor includes a polycrystalline oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.
  • CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the plurality of crystal regions are oriented in a specific direction on the c-axis.
  • the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface to be formed of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film.
  • the crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region in which the lattice arrangement is aligned. Further, the CAAC-OS has a region in which a plurality of crystal regions are connected in the ab plane direction, and the region may have distortion.
  • the strain refers to a region in which a plurality of crystal regions are connected in which the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another grid arrangement is aligned. That is, CAAC-OS is an oxide semiconductor that is c-axis oriented and not clearly oriented in the ab plane direction.
  • Each of the plurality of crystal regions is composed of one or a plurality of minute crystals (crystals having a maximum diameter of less than 10 nm).
  • the maximum diameter of the crystal region is less than 10 nm.
  • the size of the crystal region may be about several tens of nm.
  • CAAC-OS contains a layer having indium (In) and oxygen (hereinafter, In layer) and a layer having elements M, zinc (Zn), and oxygen (hereinafter referred to as "In layer”). It tends to have a layered crystal structure (also referred to as a layered structure) in which (M, Zn) layers) are laminated. Indium and element M can be replaced with each other. Therefore, the (M, Zn) layer may contain indium. In addition, the In layer may contain the element M. The In layer may contain Zn.
  • the layered structure is observed as a lattice image in, for example, a high-resolution TEM image.
  • the position of the peak indicating the c-axis orientation may vary depending on the type and composition of the metal elements constituting CAAC-OS.
  • a plurality of bright spots are observed in the electron diffraction pattern of the CAAC-OS film.
  • a certain spot and another spot are observed at point-symmetrical positions with the spot of the incident electron beam passing through the sample (also referred to as a direct spot) as the center of symmetry.
  • the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit lattice is not limited to a regular hexagon and may be a non-regular hexagon. Further, in the above strain, it may have a lattice arrangement such as a pentagon or a heptagon.
  • a clear grain boundary cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion because the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to the replacement of metal atoms. It is thought that this is the reason.
  • CAAC-OS for which no clear crystal grain boundary is confirmed, is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of the transistor.
  • a configuration having Zn is preferable.
  • In-Zn oxide and In-Ga-Zn oxide are more suitable than In oxide because they can suppress the generation of grain boundaries.
  • CAAC-OS is an oxide semiconductor having high crystallinity and no clear grain boundary is confirmed. Therefore, it can be said that CAAC-OS is unlikely to cause a decrease in electron mobility due to grain boundaries. Further, since the crystallinity of the oxide semiconductor may be lowered due to the mixing of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor having few impurities and defects (oxygen deficiency, etc.). Therefore, the oxide semiconductor having CAAC-OS has stable physical properties. Therefore, the oxide semiconductor having CAAC-OS is resistant to heat and has high reliability. CAAC-OS is also stable against high temperatures (so-called thermal budgets) in the manufacturing process. Therefore, when CAAC-OS is used for the OS transistor, the degree of freedom in the manufacturing process can be expanded.
  • nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less).
  • nc-OS has tiny crystals. Since the size of the minute crystal is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystal is also referred to as a nanocrystal.
  • nc-OS does not show regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film.
  • the nc-OS may be indistinguishable from the a-like OS and the amorphous oxide semiconductor depending on the analysis method. For example, when a structural analysis is performed on an nc-OS film using an XRD apparatus, a peak indicating crystallinity is not detected in the Out-of-plane XRD measurement using a ⁇ / 2 ⁇ scan. Further, when electron beam diffraction (also referred to as selected area electron diffraction) using an electron beam having a probe diameter larger than that of nanocrystals (for example, 50 nm or more) is performed on the nc-OS film, a diffraction pattern such as a halo pattern is performed. Is observed.
  • electron beam diffraction also referred to as selected area electron diffraction
  • nanocrystals for example, 50 nm or more
  • electron diffraction also referred to as nanobeam electron diffraction
  • an electron beam having a probe diameter for example, 1 nm or more and 30 nm or less
  • An electron diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be acquired.
  • the a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor.
  • the a-like OS has a void or low density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS. In addition, a-like OS has a higher hydrogen concentration in the membrane than nc-OS and CAAC-OS.
  • CAC-OS relates to the material composition.
  • CAC-OS is, for example, a composition of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size close thereto.
  • the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size close thereto.
  • the mixed state is also called a mosaic shape or a patch shape.
  • CAC-OS has a structure in which the material is separated into a first region and a second region to form a mosaic shape, and the first region is distributed in the membrane (hereinafter, also referred to as a cloud shape). It says.). That is, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.
  • the atomic number ratios of In, Ga, and Zn with respect to the metal elements constituting CAC-OS in the In-Ga-Zn oxide are expressed as [In], [Ga], and [Zn], respectively.
  • the first region is a region in which [In] is larger than [In] in the composition of the CAC-OS film.
  • the second region is a region in which [Ga] is larger than [Ga] in the composition of the CAC-OS film.
  • the first region is a region in which [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region.
  • the second region is a region in which [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.
  • the first region is a region in which indium oxide, indium zinc oxide, or the like is the main component.
  • the second region is a region in which gallium oxide, gallium zinc oxide, or the like is the main component. That is, the first region can be rephrased as a region containing In as a main component. Further, the second region can be rephrased as a region containing Ga as a main component.
  • a region containing In as a main component (No. 1) by EDX mapping acquired by using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy). It can be confirmed that the region (1 region) and the region containing Ga as a main component (second region) have a structure in which they are unevenly distributed and mixed.
  • EDX Energy Dispersive X-ray spectroscopy
  • CAC-OS When CAC-OS is used for a transistor, the conductivity caused by the first region and the insulating property caused by the second region act in a complementary manner to switch the switching function (On / Off function). Can be added to the CAC-OS. That is, the CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS as a transistor, high on-current ( Ion ), high field-effect mobility ( ⁇ ), and good switching operation can be realized.
  • Ion on-current
  • ⁇ high field-effect mobility
  • Oxide semiconductors have various structures, and each has different characteristics.
  • the oxide semiconductor of one aspect of the present invention has two or more of amorphous oxide semiconductor, polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS. You may.
  • the oxide semiconductor as a transistor, a transistor having high field effect mobility can be realized. Moreover, a highly reliable transistor can be realized.
  • the carrier concentration in the channel formation region of the oxide semiconductor is preferably 1 ⁇ 10 18 cm -3 or less, more preferably less than 1 ⁇ 10 17 cm -3 , and 1 ⁇ 10 16 cm -3. It is more preferably less than 1 ⁇ 10 13 cm -3 , even more preferably less than 1 ⁇ 10 12 cm -3.
  • the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density.
  • a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • An oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
  • high-purity intrinsic or substantially high-purity intrinsic may be referred to as i-type or substantially i-type.
  • the trap level density may also be low.
  • the charge captured at the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics.
  • Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.
  • the concentration of silicon and carbon in the channel formation region of the oxide semiconductor and the concentration of silicon and carbon near the interface with the channel formation region of the oxide semiconductor (secondary ion mass spectrometry (SIMS)). 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the oxide semiconductor contains an alkali metal or an alkaline earth metal
  • defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less. ..
  • the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 5 ⁇ 10 19 atoms / cm 3 , preferably 5 ⁇ 10 18 atoms / cm 3 or less, more preferably 1 ⁇ 10 18 atoms. / Cm 3 or less, more preferably 5 ⁇ 10 17 atoms / cm 3 or less.
  • hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency.
  • oxygen deficiency When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated.
  • a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have a normally-on characteristic. Therefore, it is preferable that hydrogen in the channel forming region of the oxide semiconductor is reduced as much as possible.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 5 ⁇ 10 19 atoms / cm 3 , more preferably 1 ⁇ 10. It should be less than 19 atoms / cm 3 , more preferably less than 5 ⁇ 10 18 atoms / cm 3 , and even more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • the semiconductor material that can be used for the semiconductor 114 and the semiconductor 117 is not limited to the oxide semiconductor described above.
  • a semiconductor material having a bandgap (a semiconductor material that is not a zero-gap semiconductor) may be used.
  • a semiconductor of a single element such as silicon, a compound semiconductor such as gallium arsenide, a layered substance (also referred to as an atomic layer substance, a two-dimensional material, or the like) that functions as a semiconductor may be used as the semiconductor material.
  • the layered substance is a general term for a group of materials having a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are laminated via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces.
  • the layered material has high electrical conductivity in the unit layer, that is, high two-dimensional electrical conductivity.
  • Layered materials include graphene, silicene, chalcogenides and the like.
  • Chalcogenides are compounds containing chalcogens.
  • chalcogen is a general term for elements belonging to Group 16, and includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium.
  • Examples of chalcogenides include transition metal chalcogenides and group 13 chalcogenides.
  • a transition metal chalcogenide that functions as a semiconductor may be used.
  • molybdenum sulfide typically MoS 2
  • molybdenum selenate typically MoSe 2
  • molybdenum tellurium typically MoTe 2
  • tungsten sulfide typically WS 2
  • Tungsten selenate typically WSe 2
  • tungsten tellurium typically WTe 2
  • hafnium sulfide typically HfS 2
  • hafnium selenate typically HfSe 2
  • zirconium sulfide representative
  • ZrS 2 zirconium selenium
  • ZrSe 2 zirconium selenium
  • the formation of conductors, insulators, and semiconductors is performed by a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or an atomic layer deposition (ALD) method. ) It can be done by using the method or the like.
  • the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, an optical CVD (Photo CVD) method using light, and the like. .. Further, it can be divided into a metal CVD (MCVD: Metal CVD) method and an organometallic CVD (MOCVD: Metal Organic CVD) method depending on the raw material gas used.
  • PECVD Plasma Enhanced CVD
  • TCVD Thermal CVD
  • Photo CVD Photo CVD
  • MCVD Metal CVD
  • MOCVD Metal Organic CVD
  • the plasma CVD method can obtain a high quality film at a relatively low temperature. Further, since the thermal CVD method does not use plasma, it is a film forming method capable of reducing plasma damage to the object to be processed. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) and the like included in a semiconductor device may be charged up by receiving electric charges from plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, elements, and the like included in the semiconductor device. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of the semiconductor device can be increased. Further, in the thermal CVD method, plasma damage during film formation does not occur, so that a film having few defects can be obtained.
  • the ALD method is also a film forming method capable of reducing plasma damage to the object to be processed. Further, the ALD method also does not cause plasma damage during film formation, so that a film having few defects can be obtained.
  • the CVD method and the ALD method are different from the film forming method in which particles emitted from a target or the like are deposited, and are film forming methods in which a film is formed by a reaction on the surface of an object to be treated. Therefore, it is a film forming method that is not easily affected by the shape of the object to be treated and has good step coverage.
  • the ALD method has excellent step covering property and excellent thickness uniformity, and is therefore suitable for covering the surface of an opening having a high aspect ratio.
  • the ALD method since the ALD method has a relatively slow film forming rate, it may be preferable to use it in combination with another film forming method such as a CVD method having a high film forming rate.
  • the composition of the obtained film can be controlled by the flow rate ratio of the raw material gas.
  • a film having an arbitrary composition can be formed depending on the flow rate ratio of the raw material gas.
  • a film having a continuously changed composition can be formed by changing the flow rate ratio of the raw material gas while forming the film.
  • the inside of the chamber may be under atmospheric pressure or reduced pressure
  • the raw material gas for the reaction is sequentially introduced into the chamber
  • the film formation may be performed by repeating the order of introducing the gas.
  • each switching valve also called a high-speed valve
  • the first raw material gas is not mixed at the same time or after that so that the multiple kinds of raw materials gas are not mixed.
  • An active gas argon, nitrogen, etc. or the like is introduced, and a second raw material gas is introduced.
  • the inert gas becomes a carrier gas, and the inert gas may be introduced at the same time when the second raw material gas is introduced.
  • the first raw material gas may be discharged by vacuum exhaust, and then the second raw material gas may be introduced.
  • the first raw material gas is adsorbed on the surface of the substrate to form a first thin layer, and reacts with the second raw material gas introduced later, so that the second thin layer is on the first thin layer.
  • a thin film is formed by being laminated on.
  • Thermal CVD methods such as the MOCVD method and the ALD method can form various films such as a metal film, a semiconductor film, and an inorganic insulating film.
  • a metal film such as a metal film, a semiconductor film, and an inorganic insulating film.
  • an In-Ga-Zn-O film trimethylindium (In (CH 3 ) 3 ), trimethylgallium (Ga (CH 3 ) 3 ), and dimethylzinc (Zn (CH 3 ) 2) ) May be used.
  • the combination is not limited to these, and triethylgallium (Ga (C 2 H 5 ) 3 ) can be used instead of trimethylgallium, and diethylzinc (Zn (C 2 H 5 ) 2 ) can be used instead of dimethylzinc.
  • diethylzinc Zn (C 2 H 5 ) 2
  • dimethylzinc can also be used.
  • hafnium oxide film is formed by a film forming apparatus using ALD, a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide or tetrakisdimethylamide hafnium (TDHA, Hf [N (CH 3 ) 2 ]]. 4) a raw material gas hafnium amide) was vaporized, such as, using the two kinds of gases ozone (O 3) as an oxidizing agent.
  • other materials include tetrakis (ethylmethylamide) hafnium and the like.
  • a raw material gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor compound (trimethylaluminum (TMA, Al (CH 3 ) 3), etc.).
  • TMA trimethylaluminum
  • Al Al (CH 3 ) 3
  • H 2 O gases
  • Other materials include tris (dimethylamide) aluminum, triisobutylaluminum, and aluminum tris (2,2,6,6-tetramethyl-3,5-heptane dinate).
  • a silicon oxide film using a deposition apparatus employing ALD is hexachlorodisilane adsorbed on the film-forming surface, and supplying radicals for oxidizing gas (O 2, dinitrogen monoxide) adsorption React with things.
  • oxidizing gas O 2, dinitrogen monoxide
  • tungsten film when a tungsten film is formed by a film forming apparatus using ALD, WF 6 gas and B 2 H 6 gas are sequentially and repeatedly introduced to form an initial tungsten film, and then WF 6 gas and H 2 are formed. The gas is sequentially and repeatedly introduced to form a tungsten film.
  • SiH 4 gas may be used instead of B 2 H 6 gas.
  • an oxide semiconductor film for example, an In-Ga-Zn-O film is formed by a film forming apparatus using ALD
  • In (CH 3 ) 3 gas and O 3 gas are sequentially and repeatedly introduced into In.
  • the ⁇ O layer is formed, and then Ga (CH 3 ) 3 gas and O 3 gas are sequentially and repeatedly introduced to form a GaO layer, and then Zn (CH 3 ) 2 gas and O 3 gas are sequentially and repeatedly introduced.
  • Zn (CH 3 ) 2 gas and O 3 gas are sequentially and repeatedly introduced.
  • ZnO layer ZnO layer.
  • these gases may be used to form a mixed oxide layer such as an In—Ga—O layer, an In—Zn—O layer, and a Ga—Zn—O layer.
  • O 3 may be used of H 2 O gas obtained by bubbling water with an inert gas such as Ar in place of the gas, but better to use an O 3 gas containing no H are preferred.
  • In (C 2 H 5 ) 3 gas may be used instead of In (CH 3 ) 3 gas.
  • Ga (C 2 H 5 ) 3 gas may be used instead of Ga (CH 3 ) 3 gas.
  • Zn (C 2 H 5 ) 2 gas may be used instead of Zn (CH 3 ) 2 gas.
  • the laminate 140 shown in FIG. 15A is produced.
  • the laminate 140 has an insulator 101, a conductor 102, and a conductor 103.
  • the insulator 101 [i] is placed above the substrate (not shown), the conductor 102 is placed on the insulator 101 [i], the insulator 101 [i + 1] is placed on the conductor 102, and the conductor is conductive.
  • the body 103 is arranged on the insulator 101 [i + 1], and the insulator 101 [i + 2] is arranged on the conductor 103.
  • the insulator 101 is preferably a material having a reduced concentration of impurities such as water and hydrogen.
  • the amount of desorption of hydrogen molecules of the insulator 101 per unit area is 2 ⁇ 10 15 in the range of 50 ° C. or higher and 500 ° C. or lower in the temperature desorption gas analysis method (TDS (Thermal Desorption Spectroscopy)).
  • TDS Temperatur Desorption Gas analysis method
  • the moles / cm 2 or less preferably 1 ⁇ 10 15 moles / cm 2 or less, more preferably 5 ⁇ 10 14 moles / cm 2 or less.
  • an insulator in which oxygen is released by heating may be used as the insulator 101.
  • the material applicable to the insulator 101 is not limited to the above description.
  • the insulator 101 may have a laminated structure of a plurality of insulators.
  • the insulator 101 may be a laminate of hafnium oxide and silicon oxide.
  • a resist mask is formed on the laminate 140, and a part of the insulator 101, the conductor 103, and the conductor 102 is removed by an etching process using the resist mask as a mask, and an opening 131 is opened in the laminate 140. (See FIG. 15B).
  • the resist mask can be formed by appropriately using, for example, a lithography method, a printing method, an inkjet method, or the like.
  • the etching process may be a dry etching method or a wet etching method, or both may be used. Processing by the dry etching method is suitable for microfabrication.
  • the resist mask In the formation of the resist mask by the lithography method, first, the resist is formed, and then the resist is exposed through the photomask. Next, the exposed region is removed or left with a developing solution to form a resist mask.
  • a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape.
  • a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like.
  • an immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure.
  • an electron beam or an ion beam may be used instead of the above-mentioned light. When an electron beam or an ion beam is used, a photomask is not required.
  • the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process.
  • a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process.
  • a hard mask made of an insulator or a conductor may be used instead of the resist mask.
  • a hard mask an insulating film or a conductive film to be a hard mask material is formed on the conductive film, a resist mask is formed on the insulating film or a conductive film, and the hard mask material is etched to form a hard mask having a desired shape. be able to.
  • a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching apparatus having a parallel plate type electrode can be used as a dry etching apparatus for performing the etching process by the dry etching method.
  • CCP Capacitively Coupled Plasma
  • the capacitance coupling type plasma etching apparatus having the parallel plate type electrode may be configured to apply a high frequency power source to one electrode of the parallel plate type electrode.
  • a plurality of different high-frequency power supplies may be applied to one of the parallel plate type electrodes.
  • a high frequency power supply having the same frequency may be applied to each of the parallel plate type electrodes.
  • a high frequency power supply having a different frequency may be applied to each of the parallel plate type electrodes.
  • a dry etching apparatus having a high-density plasma source can be used.
  • a dry etching apparatus having a high-density plasma source for example, an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching apparatus or the like can be used.
  • ICP Inductively Coupled Plasma
  • a part of the conductor 103 exposed on the side surface of the opening 131 is etched to retract the conductor 103 from the side surface of the opening 131 (see FIG. 16A).
  • the etching of the conductor 103 may be performed under conditions where a selection ratio with that of the insulator 101 and the conductor 102 can be obtained.
  • the insulator 111 is formed along the side surface of the opening 131 (see FIG. 16B).
  • the surfaces of the insulator 101, the conductor 103, and the conductor 102 exposed in the opening 131 are covered with the insulator 111.
  • silicon oxide is used as the insulator 111.
  • the insulator 111 may have a laminated structure of a plurality of insulators.
  • the functional body 112 is formed along the surface of the insulator 111 (see FIG. 17A).
  • silicon nitride is used as the insulator 111.
  • the functional body 112 may have a laminated structure of a plurality of insulators.
  • insulator 111 and the functional body 112 in the opening 131 is etched.
  • the insulator 111 and the functional body 112 are etched except for the portion overlapping with the insulator 101 when viewed from the Z direction (see FIG. 17B).
  • a part of the conductor 102 exposed on the side surface of the opening 131 is etched to retract the conductor 102 from the side surface of the opening 131 (see FIG. 18A).
  • the etching of the conductor 102 may be performed under conditions where a selection ratio with that of the insulator 101 and the conductor 103 can be obtained.
  • the insulator 113 is formed along the side surface of the opening 131 (see FIG. 18B).
  • the surfaces of the insulator 101, the insulator 111, the functional body 112, and the conductor 102 exposed in the opening 131 are covered with the insulator 113.
  • the semiconductor 114 When an oxide semiconductor is used for the semiconductor 114, for example, silicon oxide, silicon oxide nitride, or the like may be appropriately used as the insulator 113. By providing an insulator containing oxygen in contact with the semiconductor 114, oxygen deficiency in the semiconductor 114 can be reduced and the reliability of the transistor can be improved.
  • silicon oxide, silicon oxide nitride, or the like may be appropriately used as the insulator 113.
  • an oxide material in which a part of oxygen is desorbed by heating in other words, an insulator material having an excess oxygen region.
  • An oxide that desorbs oxygen by heating has an oxygen molecule desorption amount of 1.0 ⁇ 10 18 molecules / cm 3 or more, preferably 1.0 ⁇ 10 19 molecules / cm 3 or more, as determined by TDS analysis. More preferably, it is an oxide film having 2.0 ⁇ 10 19 molecules / cm 3 or more, or 3.0 ⁇ 10 20 molecules / cm 3 or more.
  • the surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 400 ° C. or lower.
  • the insulator 113 may have a laminated structure of a plurality of insulators.
  • an oxygenation treatment described later may be performed.
  • the semiconductor 114 and the conductor 115 are formed along the side surface of the opening 131 (see FIG. 18B).
  • the semiconductor 114 may have a laminated structure having a plurality of layers.
  • the heat treatment may be performed, for example, at 100 ° C. or higher and 600 ° C. or lower, more preferably 350 ° C. or higher and 550 ° C. or lower.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the heat treatment is preferably performed in an oxygen atmosphere.
  • oxygen can be supplied to the semiconductor 114 to reduce oxygen deficiency (VO ).
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas in order to supplement the desorbed oxygen after heat treatment in an atmosphere of nitrogen gas or an inert gas.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of the oxidizing gas, and then the heat treatment may be continuously performed in an atmosphere of nitrogen gas or an inert gas.
  • the processing for supplying oxygen to the semiconductor 114 (also referred to as "oxygen supplying treatment”.) By performing the oxygen deficiency in the semiconductor 114, is repaired by supplied oxygen, when other words “V O + O ⁇ The reaction "null" can be promoted. Further, since the oxygen supplied to the hydrogen remaining in the semiconductor 114 reacts to remove the hydrogen as H 2 O (to dehydration) can. This allows the hydrogen which has been remaining in the semiconductor 114 can be inhibited from recombining to V O H is formed by oxygen vacancies.
  • the oxygenation treatment can be performed by performing the microwave treatment in an atmosphere containing oxygen.
  • the semiconductor 114 is irradiated with microwaves, high frequencies such as RF, oxygen plasma, oxygen radicals, and the like.
  • microwave processing for example, it is preferable to use a microwave processing apparatus having a power source for generating high-density plasma using microwaves.
  • the microwave processing apparatus may have a power source for applying RF to the substrate side.
  • high-density plasma high-density oxygen radicals can be generated.
  • RF radio frequency
  • the microwave treatment is preferably performed under reduced pressure, and the pressure may be 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, and further preferably 400 Pa or more.
  • the oxygen flow rate ratio O 2 / (O 2 + Ar) is 50% or less, preferably 10% or more and 30% or less.
  • the treatment temperature may be 750 ° C. or lower, preferably 500 ° C. or lower, for example, about 400 ° C.
  • the heat treatment may be continuously performed without exposing to the outside air.
  • Plasma by the action such as a microwave, and divide the V O H included in the semiconductor 114, it is possible to remove hydrogen H from the semiconductor 114. That is, in the semiconductor 114, it is possible to reduce the "V O H ⁇ H + V O ) ", happening further reaction of "V O + O ⁇ null", the hydrogen concentration of the semiconductor 114. Therefore, the oxygen deficiency in the semiconductor 114, and to reduce the V O H, the carrier concentration can be decreased.
  • the conductor 115 is formed.
  • tungsten is formed as the conductor 115.
  • a part of the conductor 115 in the opening 131 is etched.
  • the conductor 115 is etched except for the portion that overlaps with the semiconductor 114 when viewed from the Z direction (see FIG. 19A).
  • the oxygenation treatment may be performed after the semiconductor 114 and the conductor 115 are exposed.
  • the insulator 116 is formed along the side surface of the opening 131 (see FIG. 19B).
  • the surfaces of the semiconductor 114 and the conductor 115 exposed in the opening 131 are covered with the insulator 116.
  • an oxide semiconductor for the semiconductor 114, for example, silicon oxide, silicon oxide nitride, or the like may be appropriately used as the insulator 116.
  • the insulator 116 the same material as the insulator 113 may be used.
  • the insulator 116 may have a laminated structure of a plurality of insulators.
  • the insulator 116 is preferably an insulator having a region containing oxygen desorbed by heating.
  • the insulator 116 may have a laminated structure of a plurality of insulators.
  • the insulator 116 may have a three-layer structure of silicon oxide or silicon oxide nitride, hafnium oxide or aluminum oxide, and silicon oxide or silicon oxide nitride. .. That is, a structure in which one layer of hafnium oxide or aluminum oxide is sandwiched between two layers of silicon oxide or silicon oxide may be used.
  • the insulator 116 may have a laminated structure of two layers, or may have a laminated structure of four or more layers.
  • An oxygenation treatment may be performed after the insulator 116 is formed (see FIG. 20A).
  • the semiconductor 117 is formed along the side surface of the opening 131 (see FIG. 20B).
  • the surface of the insulator 116 exposed in the opening 131 is covered with the semiconductor 117.
  • oxygenation treatment may be performed in the same manner as when the oxide semiconductor is used for the semiconductor 114.
  • the insulator 118 is formed along the side surface of the opening 131 (see FIG. 21A).
  • the surface of the semiconductor 117 exposed in the opening 131 is covered with the insulator 118.
  • an oxide semiconductor for the semiconductor 117
  • silicon oxide, silicon oxide or the like may be appropriately used as the insulator 118.
  • oxygen deficiency in the semiconductor 117 can be reduced and the reliability of the transistor can be improved.
  • the insulator 118 the same material as the insulator 113 or the insulator 116 may be used.
  • the insulator 118 may have a laminated structure of a plurality of insulators.
  • the insulator in contact with the semiconductor 117 may be an insulator having a region containing oxygen desorbed by heating. preferable. Further, it is preferable to use an insulator having a function of suppressing oxygen permeation as the insulator in contact with the conductor 119.
  • silicon oxide or silicon oxide nitride may be used as the insulator in contact with the semiconductor 117.
  • hafnium oxide or aluminum oxide may be used as the insulator in contact with the conductor 119.
  • the insulator 118 may be a laminate of silicon oxide or silicon nitride nitride, aluminum oxide, and silicon nitride.
  • silicon nitride it is preferable to use silicon nitride having a low hydrogen content.
  • the conductor 119 is formed after the insulator 118 is formed (see FIG. 21B).
  • tungsten is used as the conductor 119.
  • the conductor 119 may have a laminated structure of a plurality of conductors. Of the plurality of conductors constituting the conductor 119, it is preferable to use a conductive material that does not easily oxidize as the conductor in contact with the insulator 118.
  • a conductive material that does not easily oxidize as the conductor in contact with the insulator 118.
  • titanium nitride may be used as the conductor in contact with the insulator 118.
  • the conductor 119 may be a laminate of titanium nitride and tungsten.
  • the structure 130 is formed in the opening 131.
  • a part of the laminated body 140 is removed in a region that does not overlap with the structure 130 when viewed from the Z direction to form a region 132 (see FIG. 22A).
  • the region 132 can be formed in the same manner as the opening 131. In the region 132, the side surfaces of the insulator 101, the conductor 102, and the conductor 103 are exposed.
  • the exposed insulator 101, the conductor 102, and the insulator 121 covering the side surfaces of the conductor 103 are formed (see FIG. 22B).
  • the insulator 121 for example, it is preferable to use an insulating material having a function of suppressing permeation of impurities such as water and hydrogen.
  • an insulating material having a function of suppressing permeation of impurities such as water and hydrogen.
  • aluminum oxide or the like may be used as the insulator 121.
  • the insulator 121 may have a laminated structure of a plurality of insulators.
  • the insulator 121 may be a laminate of hafnium oxide and silicon oxide.
  • the memory cell 100 can be manufactured.
  • the circuit configuration of the semiconductor device 300 will be described with reference to FIG.
  • the semiconductor device 300 has m memory strings 200.
  • the first memory string 200 is referred to as a memory string 200 [1]
  • the mth memory string 200 is referred to as a memory string 200 [m] (m is an integer of 1 or more).
  • the j-th memory string 200 is indicated as a memory string 200 [j] (j is an integer of 1 or more and m or less).
  • the memory string 200 has n memory cells 100.
  • the memory cell 100 having the circuit configuration shown in FIG. 4A is shown as the memory cell 100, but even if the memory cell 100 has the circuit configuration shown in FIGS. 4B, 4C, 5A, and 5B. It doesn't matter.
  • the k-th memory cell 100 included in the j-th memory string 200 (k is an integer of 1 or more and n or less) is referred to as a memory cell 100 [k, j].
  • the semiconductor device 300 shown in FIG. 23 has n wirings WWL, n wirings RWL, m wirings WBL, m wirings RBL, and m wirings BGL.
  • the kth wiring WWL and wiring RWL are referred to as wiring WWL [k] and wiring RWL [k], respectively.
  • the jth wiring WBL, wiring RBL, and wiring BGL are referred to as wiring WBL [j], wiring RBL [j], and wiring BGL [j], respectively.
  • the wiring WWL [1] is electrically connected to the gate (conductor 103) of the transistor WTr included in each of the memory cells 100 [1,1] to the memory cells 100 [1, m].
  • the wiring WWL [k] is electrically connected to the gate (conductor 103) of the transistor WTr included in each of the memory cells 100 [k, 1] to the memory cells 100 [k, m].
  • the wiring WWL [n] is electrically connected to the gate (conductor 103) of the transistor WTr included in each of the memory cells 100 [n, 1] to the memory cells 100 [n, m].
  • the wiring RWL [1] is electrically connected to the capacitive elements Cs included in each of the memory cells 100 [1,1] to the memory cells 100 [1, m].
  • the wiring RWL [k] is electrically connected to the capacitance elements Cs included in each of the memory cells 100 [k, 1] to the memory cells 100 [k, m].
  • the wiring RWL [n] is electrically connected to the capacitance elements Cs included in each of the memory cells 100 [n, 1] to the memory cells 100 [n, m].
  • the wiring RWL is electrically connected to the gate (conductor 115) of the transistor RTr via the capacitive element Cs.
  • the wiring WBL [1] is electrically connected to one of the source and drain of the transistor WTr included in the memory cell 100 [n, 1] (semiconductor 114).
  • the wiring WBL [j] is electrically connected to one of the source and drain of the transistor WTr included in the memory cell 100 [n, j] (semiconductor 114).
  • the wiring WBL [m] is electrically connected to one of the source and drain (semiconductor 114) of the transistor WTr included in the memory cell 100 [n, m].
  • the wiring RBL [1] is electrically connected to one of the source and drain of the transistor RTr included in the memory cell 100 [1,1] (semiconductor 117).
  • the wiring RBL [j] is electrically connected to one of the source and drain of the transistor RTr included in the memory cell 100 [1, j] (semiconductor 117).
  • the wiring RBL [m] is electrically connected to one of the source and drain (semiconductor 117) of the transistor RTr included in the memory cell 100 [1, m].
  • the wiring BGL [1] is electrically connected to the back gate (conductor 119) of the transistor RTr included in each of the memory cells 100 [1,1] to the memory cells 100 [n, 1].
  • the wiring BGL [j] is electrically connected to the back gate (conductor 119) of the transistor RTr included in each of the memory cells 100 [1, j] to the memory cells 100 [n, j].
  • the wiring BGL [m] is electrically connected to the back gate (conductor 119) of the transistor RTr included in each of the memory cells 100 [1, m] to the memory cells 100 [n, m].
  • the wiring WWL functions as a write word line
  • the wiring RWL functions as a read word line
  • the wiring WBL functions as a write bit line
  • the wiring RBL functions as a read bit line.
  • the area electrically connected to the other of the source or drain of the transistor RTr included in the memory cell 100 [1,1] is referred to as a node N1 [1], and the memory cell is shown.
  • the region electrically connected to one of the source and drain of the transistor RTr included in 100 [n, 1] is referred to as node N2 [1].
  • node N1 and node N2 of the memory string 200 [j] are referred to as node N1 [j] and node N2 [j], respectively.
  • the node N1 and the node N2 of the memory string 200 [m] are referred to as a node N1 [m] and a node N2 [m], respectively.
  • the low level potential (Low) and high level potential (High) used in the following description do not mean a specific potential, and the specific potential may differ depending on the wiring.
  • the low-level potential and the high-level potential applied to the wiring WWL may be different from the low-level potential and the high-level potential applied to the wiring RWL, respectively.
  • FIG. 25A is a timing chart for explaining an operation example of writing data to the memory string 200 [1]
  • FIG. 25B is a timing chart for explaining an operation example of reading data from the memory string 200 [1].
  • the timing chart shown in FIG. 25 shows wiring WWL [1], wiring WWL [2], wiring WWL [n-1], wiring WWL [n], wiring RWL [1], wiring RWL [2], and wiring RWL [n]. -1], wiring RWL [n], node N1 [1], and node N2 [1] show changes in the magnitude of the potential. Further, the wiring WBL [1] indicates the data supplied to the wiring WBL [1].
  • FIG. 25A shows an example in which each of the data D [1] to the data D [n] is written to the memory cells 100 [1,1] to the memory cells 100 [n, 1].
  • the data D [1] to the data D [n] can be binary or multi-valued. Then, it is assumed that the data D [1] to the data D [n] are supplied from the wiring WBL [1].
  • Data is written to the memory string 200 [1] sequentially from the memory cell 100 [n, 1] to the memory cell 100 [1, 1].
  • the data held in the memory cell 100 [1,1] becomes the memory cell. It is lost at the stage of writing data to 100 [2,1]. Therefore, it is necessary to once read the data written in the memory cell 100 [1,1] and save it in another location.
  • the wiring RBL [1] can be controlled independently, so that it is not necessary to set a specific potential.
  • the potential of the wiring RBL [1] may be set to a low level potential.
  • the potentials of the nodes N1 [1] and the nodes N2 [1] may be low level potentials.
  • ⁇ Charge injection operation An example of charge injection operation will be described with reference to the timing chart of FIG. 24. First, an operation example in which an electric charge is injected into the functional body 112 to increase the threshold voltage of the transistor WTr will be described. In the present embodiment, the operation of injecting an electric charge into the functional body 112 of the transistor WTr included in the memory cell 100 [k, j] will be described.
  • the program potential (Prog) is supplied to the wiring WBL [j].
  • the program potential is higher than the high level potential.
  • the program potential is supplied to the wiring WWL other than the wiring WWL [k]. Further, a low level potential is supplied to the wiring WWL [k]. Then, an electric charge is injected into the functional body 112 from the wiring WWL [k] via the insulator 111.
  • a low level potential is supplied to the wiring WWL and the wiring WBL.
  • the wiring RWL [1] to the wiring RWL [n] may have any potential during the charge injection operation, but in the present embodiment, a low level potential is supplied.
  • the charge injection operation may be performed at the initial startup of the semiconductor device 300.
  • the charge injection operation may be performed every time the semiconductor device 300 is started up, or may be performed at regular time intervals.
  • the transistor WTr can be made into a normally-off type transistor. For example, by changing the transistor RTr to a normally-on type transistor, a normally-off type transistor and a normally-on type transistor can be made separately in the memory cell 100.
  • a high level potential is supplied to the wiring WWL [1] to the wiring WWL [n].
  • the transistors WTr of each of the memory cells 100 [1,1] to the memory cells 100 [n, 1] are sufficiently turned on.
  • the data D [n] is supplied to the wiring WBL [1]. Since the transistors WTr included in each of the memory cells 100 [1,1] to the memory cells 100 [n, 1] are in a sufficiently on state, the data D [n] is the memory cell 100 [n, 1]. Supplied to the storage node.
  • the wiring WWL [n] is supplied with a low level potential, and the wiring WWL [n-1] to the wiring WWL [1] are subsequently supplied with a high level potential.
  • the transistor WTr of the memory cell 100 [n, 1] is turned off, and the transistor WTr of each of the memory cells 100 [n-1,1] to the memory cell 100 [1,1] is kept on. Will be done.
  • the data D [n-1] is supplied to the wiring WBL [1]. Since the transistors WTr of each of the memory cells 100 [n-1,1] to the memory cells 100 [1,1] are in a sufficiently on state, the data D [n-1] can be stored in the memory cells 100 [n-1]. It is supplied to the storage node of -1,1]. Further, since the transistor WTr of the memory cell 100 [n, 1] is in the off state, the data D [n] written in the memory cell 100 [n, 1] during the period T11 is retained.
  • the transistor WTr of the memory cells 100 [n, 1] to the memory cells 100 [k + 1,1] to which the data has already been written is turned off, and the memory cells 100 [k, 1] to which the data has not been written are turned off.
  • the data D [k] is supplied from the wiring WBL, and the data D [k] is written to the storage node of the memory cell 100 [k, 1].
  • the transistor WTr of the memory cell 100 [k, 1] is turned off.
  • the data D [k-1] is supplied from the wiring WBL [1], and the operation of writing to the storage node of the memory cell 100 [k-1,1] is performed.
  • the writing operation when k is 1 will be described in the period T14.
  • the wiring WWL [n] to the wiring WWL [2] are supplied with a low level potential, and the wiring WWL [1] is subsequently supplied with a high level potential.
  • the transistor WTr of the memory cells 100 [n, 1] to the memory cell 100 [2, 1] is turned off, and the transistor WTr of the memory cell 100 [1, 1] remains on.
  • the data D [1] is supplied to the wiring WBL [1]. Since the transistor WTr included in the memory cell 100 [1,1] is sufficiently turned on, the data D [1] reaches the storage node of the memory cell 100 [1,1] and is written.
  • each of the memory cells 100 [n, 1] to the memory cells 100 [2, 1] is turned off.
  • the data D [n] to the data D [2] held in the data D [2] are held in.
  • the writing operation has been described by focusing on the memory string 200 [1], but in the circuit configuration of the semiconductor device 300, when a high level potential is supplied to the wiring WWL [k], the wiring WWL All the transistors WTr that are electrically connected to [k] are turned on. Therefore, data is written not only to the memory string 200 [1] but also to the memory string 200 [2] to the memory string 200 [m] at the same time.
  • the memory cell 100 shown in this embodiment is an OS memory. Therefore, the semiconductor device 300 including the memory cell 100 does not need to perform an erasing operation before rewriting the data, and can realize a high-speed writing operation.
  • the time required for writing (rewriting) the data can be shortened. That is, the data writing (rewriting) speed can be increased.
  • the OS NAND type (including 3D OS NAND type) storage device can be operated like a RAM.
  • FIG. 25B shows an example in which each of the data D [1] to the data D [n] is read from the memory cells 100 [1,1] to the memory cells 100 [n, 1].
  • the transistor WTr is required to be in the off state. Therefore, the potential of the wiring WWL [1] to the wiring WWL [n] is set to a low level potential during the operation of reading data from the memory cells 100 [1,1] to the memory cells 100 [n, 1].
  • the transistor RTr of the other memory cell 100 when reading the data of the specific memory cell 100, the transistor RTr of the other memory cell 100 is sufficiently turned on, and then the memory cell 100 to be read has.
  • the transistor RTr is operated as a saturation region. That is, the magnitude of the current flowing between the source and drain of the transistor RTr of the memory cell 100 to be read is determined according to the voltage between the source and drain and the data held in the memory cell 100 to be read. Will be done.
  • the wiring RWL [ A high level potential is supplied to the wiring RWL [1] to the wiring RWL [n] excluding [k].
  • the transistor RTr included in the memory cell 100 [k, 1] switches between an on state and an off state according to the data held in the memory cell 100 [k, 1], so that the potential of the wiring RWL [k] is high.
  • the potential of the wiring RWL [k] during the writing operation and the reading operation is considered as a low level potential.
  • a potential of + 3V is applied to the node N1 [1] and a potential of 0V is applied to the node N2 [1]. Then, the node N2 [1] is placed in a floating state, and the potential of the subsequent node N2 [1] is measured.
  • the potential of the wiring RWL [1] to the wiring RWL [n] excluding the wiring RWL [k] is set to a high level potential
  • the memory cells 100 [1,1] to the memory excluding the memory cell 100 [k, 1] The transistors RTr of each of the cells 100 [n, 1] are sufficiently turned on.
  • the voltage between the source and drain of the transistor RTr of the memory cell 100 [k, 1] is determined by the potential of the gate of the transistor RTr and the potential of the node N1 [1], and therefore the potential of the node N2 [1]. Is determined according to the data held in the storage node of the memory cell 100 [k, 1].
  • the potentials of the wiring WWL [1] to the wiring WWL [n], the wiring RWL [1] to the wiring RWL [n], the wiring WBL, the node N1 [1], and the node N2 [1] are low. It is a level potential. In particular, node N2 [1] is in a floating state. Then, it is assumed that the storage nodes of the memory cells 100 [1,1] to the memory cells 100 [n, 1] hold the data D [1] to the data D [n], respectively.
  • the wiring RWL [1] is supplied with a low level potential, and the wiring RWL [2] to the wiring RWL [n] is supplied with a high level potential.
  • the transistors RTrs of the memory cells 100 [2, 1] to the memory cells 100 [n, 1] are sufficiently turned on.
  • the transistor RTr of the memory cell 100 [1,1] is determined to be on or off according to the data D [1] held in the storage node of the memory cell 100 [1,1].
  • the potential VR is supplied to the wiring RBL [1].
  • the potential of the node N1 [1] becomes VR
  • the potential of the node N2 [1] becomes the potential VR of the node N1 [1] and the data held in the storage node of the memory cell 100 [1,1]. It depends on.
  • the potential of the node N2 [1] is VD [1]. Then, by measuring the potential VD [1] of the node N2 [1], the data D [1] held in the storage node of the memory cell 100 [1,1] can be read out.
  • a low level potential is supplied to the wiring RWL [1] to the wiring RWL [n]. Further, a low level potential is supplied to the node N2 [1], and then the node N2 [1] is in a floating state. That is, in the period T22, the potentials of the wiring RWL [1] to the wiring RWL [n] and the node N2 [1] are the same as those in the period T20.
  • the potential VR may be continuously supplied to the wiring RBL [1], or a low level potential may be supplied. In this operation example, it is assumed that the potential VR is continuously supplied to the wiring RBL [1] after the period T21. Therefore, it is assumed that the potential VR is continuously supplied to the node N1 [1].
  • the wiring RWL [2] is supplied with a low level potential, and the wiring RWL [1] and the wiring RWL [3] to the wiring RWL [n] are supplied with a high level potential.
  • the transistors RTrs of the memory cells 100 [1,1] the memory cells 100 [3,1] to the memory cells 100 [n, 1] are sufficiently turned on.
  • the transistor RTr of the memory cell 100 [2,1] is determined to be on or off according to the data D [2] held in the storage node of the memory cell 100 [2,1]. Further, the potential VR is supplied to the wiring RBL [1].
  • the potential of the node N2 [1] is determined according to the potential VR of the node N1 [1] and the data held in the storage node of the memory cell 100 [2,1].
  • the potential of the node N2 [1] is VD [2]. Then, by measuring the potential VD [2] of the node N2 [1], the data D [2] held in the storage node of the memory cell 100 [2,1] can be read out.
  • the data D [3] to the data D [n ⁇ ] are sequentially started from the memory cells 100 [3,1] to the memory cells 100 [n-1,1], respectively. 1] is read out.
  • wiring is performed after the potential of node N2 [1] is set to a low level potential and node N2 [1] is placed in a floating state.
  • a high level potential is supplied to the wiring RWL [1] to the wiring RWL [n] excluding the RWL [k], and the memory cells 100 [1,1] to the memory cells 100 excluding the memory cells 100 [k, 1] are supplied.
  • the transistor RTr possessed by [n, 1] is sufficiently turned on, and the transistor RTr possessed by the memory cell 100 [k, 1] is turned on according to the data D [k].
  • the potential of the node N2 [1] becomes a potential corresponding to the data D [k], and by measuring this potential, the data D [k] Can be read.
  • a low level potential is applied to the wiring RWL [1] to the wiring RWL [n] in preparation for the next reading operation. Is supplied to supply a low level potential to the node N2 [1], and then the node N2 [1] is brought into a floating state.
  • a low level potential is supplied to the wiring RWL [1] to the wiring RWL [n]. Further, a low level potential is supplied to the node N2 [1], and then the node N2 [1] is brought into a floating state. That is, in the period T25, the potentials of the wiring RWL [1] to the wiring RWL [n] and the node N2 [1] are the same as those in the period T20.
  • the wiring RWL [n] is supplied with a low level potential, and the wiring RWL [1] to the wiring RWL [n-1] is supplied with a high level potential.
  • the transistors RTr of each of the memory cells 100 [1,1] to the memory cells 100 [n-1,1] are sufficiently turned on.
  • the transistor RTr of the memory cell 100 [n, 1] is turned on according to the data D [n] held in the storage node of the memory cell 100 [n, 1]. Further, the potential VR is continuously supplied to the wiring RBL [1].
  • the potential of the node N2 [1] is determined according to the potential VR of the node N1 [1] and the data held in the storage node of the memory cell 100 [n, 1].
  • the potential of the node N2 [1] is VD [n]. Then, by measuring the potential VD [n] of the node N2 [1], the data D [n] held in the storage node of the memory cell 100 [n, 1] can be read out.
  • the read operation has been described by focusing on the memory string 200 [1], but in the circuit configuration of the semiconductor device 300, not only the memory string 200 [1] but also the memory strings 200 [2] to Data reading of the memory string 200 [m] can also be performed at the same time. Further, by turning off the transistor WTr, the data held in the storage node is not damaged even during the data read operation. Therefore, only the data contained in the arbitrary memory string 200 can be read.
  • FIG. 26A to 26C are examples of schematic views showing a part of the semiconductor device 300.
  • FIG. 26A shows a perspective view of a part of the semiconductor device
  • FIG. 26B shows a top view of a part of the semiconductor device.
  • FIG. 26C shows a cross-sectional view corresponding to the alternate long and short dash line Z1-Z2 of FIG. 26B.
  • the semiconductor device has a structure in which a wiring WL (wiring WWL or wiring RWL) and an insulator (regions not hatched in FIGS. 26A to 26C) are laminated.
  • a wiring WL wiring WWL or wiring RWL
  • an insulator regions not hatched in FIGS. 26A to 26C
  • An opening is formed in the structure so as to penetrate the insulator and the wiring WL at once. Then, in order to provide the memory cell 100 in the region AR through which the wiring WL is penetrated, the structure 130 is formed in the opening.
  • region SA The region where the structure 130 is formed. Since the memory string 200 is formed along the structure 130, the memory string 200 is formed in the region SA.
  • the region TM where the wiring WL is exposed functions as a connection terminal for giving a potential to the wiring WL. That is, by electrically connecting the wiring WL and the wiring in the region TM, a potential can be applied to the gate of the transistor included in the memory cell 100.
  • the wiring WL corresponds to the conductor 103 or the conductor 102.
  • the shape of the region TM is not limited to the configuration examples shown in FIGS. 26A to 26C.
  • an insulator is formed on the region TM, an opening is provided in the insulator, and the opening is formed.
  • the conductor PG may be formed so as to fill it.
  • FIG. 27A shows a perspective view of a part of the semiconductor device
  • FIG. 27B shows a top view of a part of the semiconductor device
  • FIG. 27C shows a cross-sectional view corresponding to the alternate long and short dash line Z1-Z2 of FIG. 27B.
  • a wiring ER is formed on the conductor PG, whereby the wiring ER and the wiring WL are electrically connected.
  • the conductor PG provided inside the structure is shown by a broken line.
  • the semiconductor device 300 may form peripheral circuits of a memory cell array such as a read circuit and a precharge circuit in the lower layer thereof.
  • a Si transistor may be formed on a silicon substrate or the like to form the peripheral circuit, and then the semiconductor device 300 according to one aspect of the present invention may be formed on the peripheral circuit.
  • FIG. 28A is a cross-sectional view in which the peripheral circuit is composed of a planar type Si transistor, and the semiconductor device 300 according to one aspect of the present invention is formed on the upper layer thereof.
  • FIG. 29A is a cross-sectional view in which the peripheral circuit is composed of a FIN type Si transistor and the semiconductor device 300 according to one aspect of the present invention is formed on the upper layer thereof.
  • the Si transistors constituting the peripheral circuits are formed on the substrate 1700.
  • the element separation layer 1701 is formed between a plurality of Si transistors.
  • a conductor 1712 is formed as a source and a drain of the Si transistor.
  • the conductor 1730 is formed so as to extend in the channel width direction, and is connected to another Si transistor or the conductor 1712 (not shown).
  • the substrate shown in the above embodiment can be used.
  • a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, an SOI substrate, or the like can be used.
  • the substrate 1700 for example, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a flexible substrate, a laminated film, paper containing a fibrous material, a base film, or the like may be used. Further, a semiconductor element may be formed using a certain substrate, and then the semiconductor element may be transposed to another substrate.
  • FIGS. 28A and 29A as an example, an example in which a single crystal silicon wafer is used for the substrate 1700 is shown.
  • the conductor 1221, the conductor 1222, the conductor 1223, and the insulator 1202 provided on the memory string 200 are shown in the region SA.
  • the conductor 1221 is electrically connected to the source or drain of the transistor RTr located at the end of the memory string 200.
  • the insulator 1202 is provided so as to cover the conductor 1221.
  • the conductor 1222 is provided so as to be embedded in the insulator 1202 in a region overlapping the conductor 119.
  • the conductor 1223 is provided above the insulator 1202 and is electrically connected to the conductor 119 via the conductor 1222.
  • the insulator 1203 is formed so as to cover the conductor 1223, the insulator 1202, the memory string 200, and the like.
  • the insulator 1203 it is preferable to use an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen.
  • impurities from the outside world for example, water molecule, hydrogen atom, hydrogen molecule, oxygen atom, oxygen molecule, nitrogen atom, molecular nitrogen, nitrogen oxide molecules (N 2 O, NO, NO 2, etc.) of) the diffusion of the memory string 200 can be suppressed.
  • the planar type Si transistor shown in FIG. 28A shows a cross-sectional view in the channel length direction
  • the planar type Si transistor shown in FIG. 28B shows a cross-sectional view in the channel width direction.
  • the Si transistor is provided in contact with a channel forming region 1793 provided in the well 1792, a low concentration impurity region 1794, a high concentration impurity region 1795 (collectively referred to as an impurity region), and the impurity region.
  • a metal silicide or the like may be used for the conductive region 1796.
  • the FIN-type Si transistor shown in FIG. 29A shows a cross-sectional view in the channel length direction
  • the FIN-type Si transistor shown in FIG. 29B shows a cross-sectional view in the channel width direction.
  • the channel forming region 1793 has a convex shape
  • a gate insulating film 1797 and a gate electrode 1790 are provided along the side surfaces and the upper surface thereof.
  • the SOI substrate may be processed to form a semiconductor layer having a convex shape.
  • the reference numerals shown in FIGS. 29A and 29B are the same as those shown in FIGS. 28A and 28B.
  • FIG. 30 shows a block diagram showing a configuration example of the semiconductor device 400.
  • the semiconductor device 400 shown in FIG. 30 includes a drive circuit 410 and a memory array 420.
  • the memory array 420 has one or more memory strings 200.
  • FIG. 30 shows an example in which the memory array 420 has a plurality of memory strings 200 arranged in a matrix.
  • the drive circuit 410 includes a PSW241 (power switch), a PSW242, and a peripheral circuit 415.
  • the peripheral circuit 415 includes a peripheral circuit 411 (Low Decoder), a control circuit 412 (Control Circuit), and a voltage generation circuit 428.
  • each circuit, each signal, and each voltage can be appropriately discarded as needed. Alternatively, other circuits or other signals may be added.
  • the signal BW, signal CE, signal GW, signal CLK, signal WAKE, signal ADDR, signal WDA, signal PON1, and signal PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • the signal CLK is a clock signal.
  • the signals BW, CE, and signal GW are control signals.
  • the signal CE is a chip enable signal
  • the signal GW is a global write enable signal
  • the signal BW is a byte write enable signal.
  • the signal ADDR is an address signal.
  • the signal WDA is write data and the signal RDA is read data.
  • the signal PON1 and the signal PON2 are power gating control signals.
  • the signal PON1 and the signal PON2 may be generated by the control circuit 412.
  • the control circuit 412 is a logic circuit having a function of controlling the overall operation of the semiconductor device 400. For example, the control circuit logically performs a signal CE, a signal GW, and a signal BW to determine an operation mode (for example, a write operation and a read operation) of the semiconductor device 400. Alternatively, the control circuit 412 generates a control signal of the peripheral circuit 411 so that this operation mode is executed.
  • the voltage generation circuit 428 has a function of generating a negative voltage.
  • the signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 428. For example, when an H level signal is given as the signal WAKE, the signal CLK is input to the voltage generation circuit 428, and the voltage generation circuit 428 generates a negative voltage.
  • the peripheral circuit 411 is a circuit for writing and reading data to the memory string 200.
  • the peripheral circuit 411 includes a row decoder 441, a column decoder 442 (Column Decoder), a row driver 423 (Low Driver), a column driver 424 (Column Driver), an input circuit 425 (Input Cir.), And an output circuit 426 (Output Cir.).
  • Has a sense amplifier 427 Sense Amplifier).
  • the row decoder 441 and the column decoder 442 have a function of decoding the signal ADDR.
  • the row decoder 441 is a circuit for designating the row to be accessed
  • the column decoder 442 is a circuit for designating the column to be accessed.
  • the row driver 423 has a function of selecting the wiring WL specified by the row decoder 441.
  • the column driver 424 has a function of writing data to the memory string 200, a function of reading data from the memory string 200, a function of holding the read data, and the like.
  • the input circuit 425 has a function of holding the signal WDA.
  • the data held by the input circuit 425 is output to the column driver 424.
  • the output data of the input circuit 425 is the data (Din) to be written to the memory string 200.
  • the data (Dout) read from the memory string 200 by the column driver 424 is output to the output circuit 426.
  • the output circuit 426 has a function of holding the Dout. Further, the output circuit 426 has a function of outputting the Dout to the outside of the semiconductor device 400.
  • the data output from the output circuit 426 is the signal RDA.
  • the PSW241 has a function of controlling the supply of VDD to the peripheral circuit 415.
  • the PSW242 has a function of controlling the supply of VHM to the row driver 423.
  • the high power supply voltage of the semiconductor device 400 is VDD
  • the low power supply voltage is GND (ground potential).
  • VHM is a high power supply voltage used to raise the word line to a high level, which is higher than VDD.
  • the signal PON1 controls the on / off of the PSW241, and the signal PON2 controls the on / off of the PSW242.
  • the number of power supply domains to which VDD is supplied in the peripheral circuit 415 is set to 1, but it can be set to a plurality. In this case, a power switch may be provided for each power supply domain.
  • the drive circuit 410 and the memory array 420 included in the semiconductor device 400 may be provided on the same plane. Further, as shown in FIG. 31, the drive circuit 410 and the memory array 420 may be provided in an overlapping manner. By providing the drive circuit 410 and the memory array 420 in an overlapping manner, the signal propagation distance can be shortened. Further, in FIG. 31, an enlarged perspective view of a part of the semiconductor device 400 is added.
  • the semiconductor device 400 may use an arithmetic processing unit such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit) for the control circuit 412 included in the drive circuit 410.
  • an arithmetic processing unit such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit) for the control circuit 412 included in the drive circuit 410.
  • a CPU and / or GPU a semiconductor device 400 having an arithmetic processing function can be realized.
  • the memory string 200 can function as RAM. Therefore, a part of the memory array 420 can function as a main memory or a cache memory. Further, as described above, the memory string 200 can function as a flash memory. Therefore, a part of the memory array 420 can function as a flash memory.
  • the semiconductor device 400 according to one aspect of the present invention can function as a universal memory.
  • functions as a CPU, a NAND flash memory, and a cache memory can be produced on the same chip.
  • the semiconductor device 400 shown in FIG. 31 includes a drive circuit 410 including a CPU, and a memory array 420 having a 3D OS NAND type storage device according to an aspect of the present invention.
  • the 3D OS NAND type storage device according to one aspect of the present invention has a function as a cache memory and a function as a flash memory.
  • FIG. 32 shows how the host 450 manages a plurality of semiconductor devices 400.
  • Each semiconductor device 400 has an arithmetic processing function, and can perform parallel writing and reading to a flash memory and a cache memory.
  • the host 450 manages a plurality of semiconductor devices 400, it is possible to construct an information processing system that realizes non-Von Neumann computing.
  • FIG. 33 shows a block diagram of the central processing unit 1100.
  • FIG. 33 shows a CPU configuration example as a configuration example that can be used in the central processing unit 1100.
  • the central processing unit 1100 shown in FIG. 33 has an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, and a register controller 1197 on a substrate 1190. , Bus interface 1198), cache 1199, and cache interface 1189.
  • ALU Arithmetic logic unit, arithmetic circuit
  • ALU controller 1192 Arithmetic logic unit, arithmetic circuit
  • the cache 1199 is connected to the main memory provided on another chip via the cache interface 1189.
  • the cache interface 1189 has a function of supplying a part of the data held in the main memory to the cache 1199.
  • the cache 1199 has a function of holding the data.
  • the central processing unit 1100 shown in FIG. 33 is only an example in which its configuration is simplified, and the actual central processing unit 1100 has a wide variety of configurations depending on its use.
  • the configuration including the central processing unit 1100 or the arithmetic circuit shown in FIG. 33 may be one core, and a plurality of the cores may be included and each core may operate in parallel, that is, a configuration such as a GPU. ..
  • the number of bits that the central processing unit 1100 can handle in the internal arithmetic circuit or the data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, or the like.
  • the instructions input to the central processing unit 1100 via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.
  • the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. Further, the interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from its priority or mask state during program execution of the central processing unit 1100. The register controller 1197 generates the address of the register 1196, and reads or writes the register 1196 according to the state of the central processing unit 1100.
  • the timing controller 1195 generates a signal for controlling the operation timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197.
  • the timing controller 1195 includes an internal clock generator that generates an internal clock signal based on the reference clock signal, and supplies the internal clock signal to the above-mentioned various circuits.
  • a storage device is provided in the register 1196 and the cache 1199.
  • the storage device for example, the storage device shown in the previous embodiment can be used.
  • the register controller 1197 selects the holding operation in the register 1196 according to the instruction from the ALU 1191. That is, in the memory cell of the register 1196, it is selected whether to hold the data by the flip-flop or the data by the capacitive element. When the holding of data by the flip-flop is selected, the power supply voltage is supplied to the memory cell in the register 1196. When the retention of data in the capacitive element is selected, the data is rewritten to the capacitive element, and the supply of the power supply voltage to the memory cell in the register 1196 can be stopped.
  • the semiconductor device 400 and the central processing unit 1100 shown in the above embodiment can be provided in an overlapping manner.
  • a perspective view of the semiconductor device 1150A is shown in FIGS. 34A and 34B.
  • the semiconductor device 1150A has a semiconductor device 400 that functions as a storage device on the central processing unit 1100.
  • the central processing unit 1100 and the semiconductor device 400 have regions that overlap each other.
  • the central processing unit 1100 and the semiconductor device 400 are shown separately in FIG. 34B.
  • connection distance between the two can be shortened. Therefore, the communication speed between the two can be increased. Moreover, since the connection distance is short, power consumption can be reduced.
  • the semiconductor device 400 by using the OS NAND type storage device for the semiconductor device 400, a part or all of the memory strings 200 among the plurality of memory strings 200 included in the semiconductor device 400 can function as RAM. Can be made to. Therefore, the semiconductor device 400 can function as a main memory.
  • the semiconductor device 400 that functions as the main memory is connected to the cache 1199 via the cache interface 1189.
  • the control circuit 412 can make a part or all of the plurality of memory strings 200 included in the semiconductor device 400 function as RAM based on the signal supplied from the central processing unit 1100.
  • the semiconductor device 400 can make some memory strings 200 function as RAM and other memory strings 200 function as storage among the plurality of memory strings 200.
  • an OS NAND type storage device for the semiconductor device 400, it is possible to have both a function as a cache, a function as a main memory, and a function as a storage.
  • the semiconductor device 400 according to one aspect of the present invention can function as, for example, a universal memory.
  • the semiconductor device 400 When the semiconductor device 400 is used as the main memory, its storage capacity can be increased or decreased as needed. When the semiconductor device 400 is used as a cache, its storage capacity can be increased or decreased as needed.
  • control circuit 412 shown in FIG. 30 has a function of detecting and correcting an error when moving or duplicating data between an area functioning as a storage and an area functioning as a main memory of the semiconductor device 400 (ECC: It may have (also referred to as Error Check and Select). Further, the control circuit 412 may have a function of performing ECC when moving or duplicating data between the area functioning as the main memory of the semiconductor device 400 and the cache 1199.
  • ECC Error Check and Select
  • a plurality of semiconductor devices 400 may be provided so as to overlap with the central processing unit 1100.
  • 35A and 35B are perspective views of the semiconductor device 1150B.
  • the semiconductor device 1150B has a semiconductor device 400a and a semiconductor device 400b on the central processing unit 1100.
  • the central processing unit 1100, the semiconductor device 400a, and the semiconductor device 400b have regions that overlap each other.
  • the central processing unit 1100, the semiconductor device 400a, and the semiconductor device 400b are shown separately in FIG. 35B.
  • the semiconductor device 400a and the semiconductor device 400b function as a storage device.
  • a NOR type storage device may be used as the semiconductor device 400a.
  • a NAND type storage device may be used as the semiconductor device 400b.
  • Both the semiconductor device 400a and the semiconductor device 400b may be NAND type storage devices. Since the NOR type storage device can operate at a higher speed than the NAND type storage device, for example, a part of the semiconductor device 400a can be used as the main memory and / or the cache 1199.
  • the stacking order of the semiconductor device 400a and the semiconductor device 400b may be reversed.
  • FIG. 36A and 36B are perspective views of the semiconductor device 1150C.
  • the semiconductor device 1150C has a configuration in which the central processing unit 1100 is sandwiched between the semiconductor device 400a and the semiconductor device 400b. Therefore, the central processing unit 1100, the semiconductor device 400a, and the semiconductor device 400b have regions that overlap each other.
  • FIG. 36B shows the central processing unit 1100, the semiconductor device 400a, and the semiconductor device 400b separately.
  • both the communication speed between the semiconductor device 400a and the central processing unit 1100 and the communication speed between the semiconductor device 400b and the central processing unit 1100 can be increased.
  • the power consumption can be reduced as compared with the semiconductor device 1150B.
  • the semiconductor wafer 4800 shown in FIG. 37A has a wafer 4801 and a plurality of circuit units 4802 provided on the upper surface of the wafer 4801.
  • the portion without the circuit portion 4802 is the spacing 4803, which is a dicing region.
  • the semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 by a previous step. Further, after that, the surface on the opposite side on which the plurality of circuit portions 4802 of the wafer 4801 are formed may be ground to reduce the thickness of the wafer 4801. By this step, the warp of the wafer 4801 can be reduced and the size of the wafer can be reduced.
  • a dicing step is performed. Dicing is performed along the scribing line SCL1 and the scribing line SCL2 (sometimes referred to as a dicing line or a cutting line) indicated by an alternate long and short dash line.
  • the spacing 4803 is provided so that a plurality of scribe lines SCL1 are parallel to each other and a plurality of scribe lines SCL2 are parallel to each other so that the dicing process can be easily performed. It is preferable to provide it so that it is vertical.
  • the chip 4800a as shown in FIG. 37B can be cut out from the semiconductor wafer 4800.
  • the chip 4800a has a wafer 4801a, a circuit unit 4802, and a spacing 4803a.
  • the spacing 4803a is preferably made as small as possible. In this case, the width of the spacing 4803 between the adjacent circuit units 4802 may be substantially the same as the cutting margin of the scribe line SCL1 or the cutting margin of the scribe line SCL2.
  • the shape of the element substrate of one aspect of the present invention is not limited to the shape of the semiconductor wafer 4800 shown in FIG. 37A.
  • the shape of the element substrate can be appropriately changed depending on the process of manufacturing the device and the device for manufacturing the device.
  • FIG. 37C shows a perspective view of a substrate (mounting substrate 4704) on which the electronic component 4700 and the electronic component 4700 are mounted.
  • the electronic component 4700 shown in FIG. 37C has a chip 4800a in the mold 4711.
  • As the chip 4800a a storage device or the like according to one aspect of the present invention can be used.
  • the electronic component 4700 has a land 4712 on the outside of the mold 4711.
  • the land 4712 is electrically connected to the electrode pad 4713, and the electrode pad 4713 is electrically connected to the chip 4800a by a wire 4714.
  • the electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined and electrically connected to each other on the printed circuit board 4702 to complete the mounting board 4704.
  • FIG. 37D shows a perspective view of the electronic component 4730.
  • the electronic component 4730 is an example of SiP (System in package) or MCM (Multi Chip Module).
  • an interposer 4731 is provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and a plurality of semiconductor devices 4710 are provided on the interposer 4731.
  • Examples of the semiconductor device 4710 include a chip 4800a, the semiconductor device described in the above embodiment, and a wideband memory (HBM: High Bandwidth Memory). Further, as the semiconductor device 4735, an integrated circuit (semiconductor device) such as a CPU, GPU, FPGA, or storage device can be used.
  • a semiconductor device such as a CPU, GPU, FPGA, or storage device.
  • the package substrate 4732 a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used.
  • the interposer 4731 a silicon interposer, a resin interposer, or the like can be used.
  • the interposer 4731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches.
  • the plurality of wirings are provided in a single layer or multiple layers.
  • the interposer 4731 has a function of electrically connecting the integrated circuit provided on the interposer 4731 to the electrode provided on the package substrate 4732.
  • the interposer may be referred to as a "rewiring board” or an "intermediate board”.
  • a through electrode may be provided on the interposer 4731, and the integrated circuit and the package substrate 4732 may be electrically connected using the through electrode.
  • a TSV Through Silicon Via
  • interposer 4731 It is preferable to use a silicon interposer as the interposer 4731. Since it is not necessary to provide an active element in the silicon interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult with a resin interposer.
  • the interposer on which the HBM is mounted is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer as the interposer on which the HBM is mounted.
  • the reliability is unlikely to be lowered due to the difference in the expansion coefficient between the integrated circuit and the interposer. Further, since the surface of the silicon interposer is high, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is unlikely to occur. In particular, in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on an interposer, it is preferable to use a silicon interposer.
  • a heat sink may be provided so as to be overlapped with the electronic component 4730.
  • the heat sink it is preferable that the heights of the integrated circuits provided on the interposer 4731 are the same.
  • the heights of the semiconductor device 4710 and the semiconductor device 4735 are the same.
  • an electrode 4733 may be provided on the bottom of the package substrate 4732.
  • FIG. 37D shows an example in which the electrode 4733 is formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 4732, BGA (Ball Grid Array) mounting can be realized. Further, the electrode 4733 may be formed of a conductive pin. By providing conductive pins in a matrix on the bottom of the package substrate 4732, PGA (Pin Grid Array) mounting can be realized.
  • the electronic component 4730 can be mounted on another substrate by using various mounting methods, not limited to BGA and PGA.
  • BGA Band-GPU
  • PGA Stimble Pin Grid Array
  • LGA Land Grid Array
  • QFP Quad Flat Package
  • QFJ Quad Flat J-leaded package
  • QFN QuadFNeged
  • FIG. 38A shows various storage devices used in semiconductor devices for each layer.
  • a storage device located in the upper layer is required to have a faster operating speed, and a storage device located in the lower layer is required to have a large storage capacity and a high recording density.
  • FIG. 38A shows, in order from the top layer, a memory, a SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), and a 3D NAND memory, which are mixedly mounted as registers in an arithmetic processing unit such as a CPU.
  • SRAM Static Random Access Memory
  • DRAM Dynamic Random Access Memory
  • 3D NAND memory which are mixedly mounted as registers in an arithmetic processing unit such as a CPU.
  • a memory that is mixedly loaded as a register in an arithmetic processing unit such as a CPU is used for temporary storage of arithmetic results, and therefore is frequently accessed from the arithmetic processing unit. Therefore, an operation speed faster than the storage capacity is required.
  • the register also has a function of holding setting information of the arithmetic processing unit.
  • SRAM is used, for example, as a cache.
  • the cache has a function of duplicating and holding a part of the data held in the main memory (main memory). By duplicating frequently used data and keeping it in the cache, the access speed to the data can be increased.
  • the storage capacity required for the cache is smaller than that of the main memory, but the operating speed is required to be faster than that of the main memory.
  • the data rewritten in the cache is duplicated and supplied to the main memory.
  • DRAM is used, for example, in main memory.
  • the main memory has a function of holding programs and data read from the storage.
  • the recording density of the DRAM is approximately 0.1 Gbit / mm 2 to 0.3 Gbit / mm 2 .
  • 3D NAND memory is used, for example, for storage.
  • the storage has a function of holding data that needs to be stored for a long period of time and various programs used in the arithmetic processing unit. Therefore, the storage is required to have a storage capacity larger than the operating speed and a high recording density.
  • the recording density of the storage device used for storage is approximately 0.6 Gbit / mm 2 to 6.0 Gbit / mm 2 .
  • the storage device has a high operating speed and can retain data for a long period of time.
  • the storage device can be suitably used as a storage device located in the boundary area 901 including both the layer in which the cache is located and the layer in which the main memory is located.
  • the storage device can be suitably used as a storage device located in the boundary area 902 including both the layer in which the main memory is located and the layer in which the storage is located.
  • the storage device according to one aspect of the present invention can be suitably used for both the layer in which the main memory is located and the layer in which the storage is located. Further, the storage device according to one aspect of the present invention can be suitably used in the hierarchy in which the cache is located.
  • FIG. 38B shows a hierarchy of various storage devices different from those in FIG. 38A.
  • FIG. 38B shows, in order from the top layer, a memory that is mixedly loaded as a register in an arithmetic processing unit such as a CPU, an SRAM that is used as a cache, and a 3D OS NAND memory.
  • a storage device can be used for the cache, the main memory, and the storage.
  • the cache is mixedly mounted on an arithmetic processing unit such as a CPU.
  • the storage device is, for example, the storage of various electronic devices (for example, information terminals, computers, smartphones, electronic book terminals, digital still cameras, video cameras, recording / playback devices, navigation systems, game machines, etc.). Applicable to devices. It can also be used for image sensors, IoT (Internet of Things), health care, and the like.
  • the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
  • 39A to 39J and 40A to 40E show how each electronic device includes an electronic component 4700 or an electronic component 4730 having the storage device.
  • the information terminal 5500 shown in FIG. 39A is a mobile phone (smartphone) which is a kind of information terminal.
  • the information terminal 5500 has a housing 5510 and a display unit 5511, and as an input interface, a touch panel is provided in the display unit 5511 and buttons are provided in the housing 5510.
  • the information terminal 5500 can hold a temporary file (for example, a cache when using a web browser) generated when the application is executed.
  • a temporary file for example, a cache when using a web browser
  • FIG. 39B shows an information terminal 5900 which is an example of a wearable terminal.
  • the information terminal 5900 has a housing 5901, a display unit 5902, an operation switch 5903, an operation switch 5904, a band 5905, and the like.
  • the wearable terminal can hold a temporary file generated when the application is executed by applying the storage device according to one aspect of the present invention.
  • FIG. 39C shows a desktop information terminal 5300.
  • the desktop type information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.
  • the desktop information terminal 5300 can hold a temporary file generated when the application is executed by applying the storage device according to one aspect of the present invention.
  • smartphones, wearable terminals, and desktop information terminals are taken as examples of electronic devices and are shown in FIGS. 39A to 39C, respectively.
  • information terminals other than smartphones, wearable terminals, and desktop information terminals can be applied. It can.
  • Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook-type information terminals, and workstations.
  • FIG. 39D shows an electric freezer / refrigerator 5800 as an example of an electric appliance.
  • the electric freezer / refrigerator 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.
  • the electric freezer / refrigerator 5800 is an electric freezer / refrigerator compatible with IoT (Internet of Things).
  • the storage device can be applied to the electric refrigerator-freezer 5800.
  • the electric refrigerator-freezer 5800 can send and receive information such as foodstuffs stored in the electric refrigerator-freezer 5800 and the expiration date of the foodstuffs to an information terminal or the like via the Internet or the like.
  • the electric refrigerator-freezer 5800 can hold a temporary file generated when transmitting the information in the storage device.
  • an electric refrigerator / freezer has been described as an electric appliance, but other electric appliances include, for example, a vacuum cleaner, a microwave oven, an electric oven, a rice cooker, a water heater, an IH cooker, a water server, and an air conditioner. Equipment, washing machines, dryers, audiovisual equipment, etc. can be mentioned.
  • FIG. 39E shows a portable game machine 5200, which is an example of a game machine.
  • the portable game machine 5200 has a housing 5201, a display unit 5202, a button 5203, and the like.
  • FIG. 39F shows a stationary game machine 7500, which is an example of a game machine.
  • the stationary game machine 7500 has a main body 7520 and a controller 7522.
  • the controller 7522 can be connected to the main body 7520 wirelessly or by wire.
  • the controller 7522 can be provided with a display unit for displaying a game image, a touch panel or stick as an input interface other than buttons, a rotary knob, a slide knob, and the like.
  • the controller 7522 is not limited to the shape shown in FIG. 39F, and the shape of the controller 7522 may be variously changed according to the genre of the game.
  • a controller shaped like a gun can be used by using a trigger as a button.
  • a controller having a shape imitating a musical instrument, a music device, or the like can be used.
  • the stationary game machine may be in a form in which a controller is not used and instead a camera, a depth sensor, a microphone and the like are provided and operated by the gesture of the game player and / or the voice.
  • the video of the game machine described above can be output by a display device such as a television device, a personal computer display, a game display, or a head-mounted display.
  • a display device such as a television device, a personal computer display, a game display, or a head-mounted display.
  • the low power consumption portable game machine 5200 or the low power consumption stationary game machine 7500 can be realized. .. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • FIG. 39E shows a portable game machine.
  • FIG. 39F shows a stationary game machine for home use.
  • the electronic device of one aspect of the present invention is not limited to this. Examples of the electronic device of one aspect of the present invention include an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), a pitching machine for batting practice installed in a sports facility, and the like.
  • the storage device described in the above embodiment can be applied to an automobile which is a moving body and around the driver's seat of the automobile.
  • FIG. 39G shows an automobile 5700 which is an example of a moving body.
  • an instrument panel that provides various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear status, an air conditioner setting, and the like is provided. Further, a display device for displaying such information may be provided around the driver's seat.
  • the storage device described in the above embodiment can temporarily hold information, it is necessary for, for example, in an automatic driving system of an automobile 5700, a road guidance, a system for predicting danger, and the like. It can be used to temporarily retain information.
  • the display device may be configured to display temporary information such as road guidance and danger prediction. Further, the image of the driving recorder installed in the automobile 5700 may be held.
  • moving objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), and the like.
  • FIG. 39H shows a digital camera 6240, which is an example of an imaging device.
  • the digital camera 6240 has a housing 6241, a display unit 6242, an operation switch 6243, a shutter button 6244, and the like, and a removable lens 6246 is attached to the digital camera 6240.
  • the digital camera 6240 has a configuration in which the lens 6246 can be removed from the housing 6241 and replaced here, the lens 6246 and the housing 6241 may be integrated. Further, the digital camera 6240 may be configured so that a strobe device, a viewfinder, or the like can be separately attached.
  • the digital camera 6240 with low power consumption can be realized. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • Video camera The storage device described in the above embodiment can be applied to a video camera.
  • FIG. 39I shows a video camera 6300, which is an example of an imaging device.
  • the video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like.
  • the operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302.
  • the first housing 6301 and the second housing 6302 are connected by a connecting portion 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connecting portion 6306. is there.
  • the image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 on the connecting unit 6306.
  • the video camera 6300 When recording the video captured by the video camera 6300, it is necessary to encode the data according to the recording format. By utilizing the storage device described above, the video camera 6300 can hold a temporary file generated during encoding.
  • ICD implantable cardioverter defibrillator
  • FIG. 39J is a schematic cross-sectional view showing an example of ICD.
  • the ICD body 5400 has at least a battery 5401, an electronic component 4700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.
  • the ICD body 5400 is surgically placed in the body, and two wires are passed through the subclavian vein 5405 and the superior vena cava 5406 of the human body, and one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium. To be done.
  • the ICD main body 5400 has a function as a pacemaker and performs pacing to the heart when the heart rate deviates from a specified range. Also, if pacing does not improve heart rate (such as fast ventricular tachycardia or ventricular fibrillation), electric shock treatment is given.
  • the ICD body 5400 needs to constantly monitor the heart rate in order to properly perform pacing and electric shock. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. Further, the ICD main body 5400 can store the heart rate data acquired by the sensor or the like, the number of times of treatment by pacing, the time, etc. in the electronic component 4700.
  • the ICD main body 5400 has a plurality of batteries, so that the safety can be enhanced. Specifically, even if a part of the battery of the ICD main body 5400 becomes unusable, the remaining battery can function, so that it also functions as an auxiliary power source.
  • the antenna 5404 that can receive power it may have an antenna that can transmit physiological signals.
  • physiological signals such as pulse, respiratory rate, heart rate, and body temperature can be confirmed by an external monitoring device.
  • a system for monitoring various cardiac activities may be configured.
  • the storage device described in the above embodiment can be applied to a computer such as a PC (Personal Computer) and an expansion device for an information terminal.
  • a computer such as a PC (Personal Computer) and an expansion device for an information terminal.
  • FIG. 40A shows, as an example of the expansion device, an expansion device 6100 externally attached to a PC, which is equipped with a portable chip capable of storing information.
  • the expansion device 6100 can store information by the chip by connecting to a PC by, for example, USB (Universal Serial Bus) or the like.
  • USB Universal Serial Bus
  • FIG. 40A illustrates a portable expansion device 6100, but the expansion device according to one aspect of the present invention is not limited to this, and is relatively equipped with, for example, a cooling fan. It may be a large form of expansion device.
  • the expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a substrate 6104.
  • the substrate 6104 is housed in the housing 6101.
  • the substrate 6104 is provided with a circuit for driving the storage device and the like described in the above embodiment.
  • an electronic component 4700 and a controller chip 6106 are attached to the substrate 6104.
  • the USB connector 6103 functions as an interface for connecting to an external device.
  • SD card The storage device described in the above embodiment can be applied to an SD card that can be attached to an electronic device such as an information terminal or a digital camera.
  • FIG. 40B is a schematic view of the appearance of the SD card
  • FIG. 40C is a schematic view of the internal structure of the SD card.
  • the SD card 5110 has a housing 5111, a connector 5112, and a substrate 5113.
  • the connector 5112 functions as an interface for connecting to an external device.
  • the substrate 5113 is housed in the housing 5111.
  • the substrate 5113 is provided with a storage device and a circuit for driving the storage device.
  • an electronic component 4700 and a controller chip 5115 are attached to the substrate 5113.
  • the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to the above description, and the circuit configurations may be appropriately changed depending on the situation.
  • the writing circuit, the low driver, the reading circuit, and the like provided in the electronic component may be incorporated in the controller chip 5115 instead of the electronic component 4700.
  • the capacity of the SD card 5110 can be increased.
  • a wireless chip having a wireless communication function may be provided on the substrate 5113. As a result, wireless communication can be performed between the external device and the SD card 5110, and the data of the electronic component 4700 can be read and written.
  • SSD Solid State Drive
  • electronic device such as an information terminal.
  • FIG. 40D is a schematic view of the appearance of the SSD
  • FIG. 40E is a schematic view of the internal structure of the SSD.
  • the SSD 5150 has a housing 5151, a connector 5152, and a substrate 5153.
  • the connector 5152 functions as an interface for connecting to an external device.
  • the substrate 5153 is housed in the housing 5151.
  • the substrate 5153 is provided with a storage device and a circuit for driving the storage device.
  • an electronic component 4700, a memory chip 5155, and a controller chip 5156 are attached to the substrate 5153.
  • a work memory is incorporated in the memory chip 5155.
  • a DRAM chip may be used as the memory chip 5155.
  • a processor, an ECC circuit, and the like are incorporated in the controller chip 5156.
  • the circuit configurations of the electronic component 4700, the memory chip 5155, and the controller chip 5156 are not limited to the above description, and the circuit configurations may be appropriately changed depending on the situation.
  • the controller chip 5156 may also be provided with a memory that functions as a work memory.
  • the computer 5600 shown in FIG. 41A is an example of a large-scale computer.
  • a plurality of rack-mounted computers 5620 are stored in the rack 5610.
  • the computer 5620 may have, for example, the configuration of the perspective view shown in FIG. 41B.
  • the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals.
  • a PC card 5621 is inserted in slot 5631.
  • the PC card 5621 has a connection terminal 5623, a connection terminal 5624, and a connection terminal 5625, each of which is connected to the motherboard 5630.
  • the PC card 5621 shown in FIG. 41C is an example of a processing board including a CPU, GPU, storage device, and the like.
  • the PC card 5621 has a board 5622.
  • the board 5622 has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629.
  • FIG. 41C illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628. Regarding these semiconductor devices, the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5627 described below are shown. The description of the semiconductor device 5628 may be taken into consideration.
  • connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630.
  • Examples of the standard of the connection terminal 5629 include PCIe and the like.
  • connection terminal 5623, the connection terminal 5624, and the connection terminal 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, and the like. Further, for example, it can be an interface for outputting a signal calculated by the PC card 5621.
  • Examples of the standards of the connection terminal 5623, the connection terminal 5624, and the connection terminal 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface).
  • USB Universal Serial Bus
  • SATA Serial ATA
  • SCSI Serial Computer System Interface
  • HDMI registered trademark
  • HDMI registered trademark
  • the semiconductor device 5626 has a terminal (not shown) for inputting / outputting signals, and the semiconductor device 5626 and the board 5622 can be inserted by inserting the terminal into a socket (not shown) included in the board 5622. Can be electrically connected.
  • the semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 are electrically connected to the wiring provided by the board 5622 by, for example, reflow soldering. be able to.
  • Examples of the semiconductor device 5627 include FPGA (Field Programmable Gate Array), GPU, CPU, and the like.
  • an electronic component 4730 can be used as the semiconductor device 5627.
  • the semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 are electrically connected by, for example, reflow soldering to the wiring provided with the terminals 5622. be able to.
  • Examples of the semiconductor device 5628 include a storage device and the like.
  • an electronic component 4700 can be used as the semiconductor device 5628.
  • the computer 5600 can also function as a parallel computer.
  • the computer 5600 By using the computer 5600 as a parallel computer, for example, it is possible to perform large-scale calculations necessary for learning artificial intelligence and inference.
  • the semiconductor device of one aspect of the present invention for the above-mentioned various electronic devices, it is possible to reduce the size, speed, or power consumption of the electronic devices. Further, since the semiconductor device of one aspect of the present invention consumes less power, heat generation from the circuit can be reduced. Therefore, it is possible to reduce the adverse effect of the heat generation on the circuit itself, the peripheral circuits, and the module. Further, by using the semiconductor device of one aspect of the present invention, it is possible to realize an electronic device whose operation is stable even in a high temperature environment. Therefore, the reliability of the electronic device can be improved.
  • FIG. 42 is a diagram illustrating a configuration example of the computer system 700.
  • the computer system 700 includes software (Software) and hardware (Hardware).
  • the hardware included in the computer system may be referred to as an information processing device.
  • the software constituting the computer system 700 includes an operating system including a device driver, middleware, various development environments, an application program related to AI (AI Application), an application program unrelated to AI (Application), and the like.
  • Device drivers include auxiliary storage devices, display devices, and application programs for controlling externally connected devices such as printers.
  • the hardware constituting the computer system 700 includes a first arithmetic processing unit, a second arithmetic processing unit, a first storage device, and the like. Further, the second arithmetic processing unit has a second storage device.
  • a central arithmetic processing unit such as a Noff OS CPU may be used.
  • the Noff OS CPU has a storage means (for example, a non-volatile memory) using an OS transistor, and when operation is not required, the necessary information is held in the storage means and power is supplied to the central processing unit. Has a function to stop.
  • the second arithmetic processing unit for example, a GPU, an FPGA, or the like can be used. It is preferable to use AI OS Accelerator as the second arithmetic processing unit.
  • the AI OS Accelerator is configured by using an OS transistor and has a calculation means such as a product-sum calculation circuit. AI OS Accelerator consumes less power than general GPUs. By using the AI OS Accelerator as the second arithmetic processing unit, the power consumption of the computer system 700 can be reduced.
  • the storage device according to one aspect of the present invention is preferable to use as the first storage device and the second storage device.
  • a 3D OS NAND type storage device can function as a cache, main memory, and storage. Further, by using a 3D OS NAND type storage device, it becomes easy to realize a non-Von Neumann type computer system.
  • the 3D OS NAND type storage device consumes less power than the 3D NAND type storage device using a Si transistor.
  • the power consumption of the computer system 700 can be reduced.
  • the 3D OS NAND type storage device can function as a universal memory, the number of parts for forming the computer system 700 can be reduced.
  • the semiconductor device constituting the hardware By configuring the semiconductor device constituting the hardware with the semiconductor device including the OS transistor, it becomes easy to monolithize the hardware including the central processing unit, the arithmetic processing unit, and the storage device. By making the hardware monolithic, not only miniaturization, weight reduction, and thinning, but also further reduction of power consumption becomes easy.
  • a normally-off CPU (also referred to as "Noff-CPU") can be realized by using the OS memory shown in the present specification and the like.
  • the Nonf-CPU is an integrated circuit including a normally-off type transistor that is in a non-conducting state (also referred to as an off state) even when the gate voltage is 0V.
  • the Noff-CPU can stop the power supply to the unnecessary circuit in the Noff-CPU and put the circuit in the standby state. No power is consumed in the circuit where the power supply is stopped and the circuit is in the standby state. Therefore, the Nonf-CPU can minimize the amount of power used. Further, the Nonf-CPU can retain information necessary for operation such as setting conditions for a long period of time even if the power supply is stopped. To return from the standby state, it is only necessary to restart the power supply to the circuit, and it is not necessary to rewrite the setting conditions and the like. That is, high-speed recovery from the standby state is possible. In this way, the Nonf-CPU can reduce the power consumption without significantly reducing the operating speed.
  • the Noff-CPU can be suitably used for a small-scale system such as an IoT terminal device (also referred to as an "endpoint microcomputer") 803 in the field of IoT (Internet of Things).
  • IoT terminal device also referred to as an "endpoint microcomputer” 803 in the field of IoT (Internet of Things).
  • FIG. 43 shows the hierarchical structure of the IoT network and the tendency of the required specifications.
  • FIG. 43 shows power consumption 804 and processing performance 805 as required specifications.
  • the hierarchical structure of the IoT network is roughly divided into a cloud field 801 which is an upper layer and an embedded field 802 which is a lower layer.
  • the cloud field 801 includes, for example, a server.
  • the embedded field 802 includes, for example, machines, industrial robots, in-vehicle devices, home appliances, and the like.
  • the semiconductor device according to one aspect of the present invention can be suitably used for a communication device of an IoT terminal device that requires low power consumption.
  • the "endpoint” refers to the terminal region of the embedded field 802. Examples of devices used for endpoints include microcomputers used in factories, home appliances, infrastructure, agriculture, and the like.
  • FIG. 44 shows an image diagram of factory automation as an application example of an endpoint microcomputer.
  • the factory 884 is connected to the cloud (server) 883 via the Internet line (Internet).
  • the cloud 883 is also connected to the home 881 and the office 882 via an internet line.
  • the Internet line may be a wired communication system or a wireless communication system.
  • a semiconductor device according to one aspect of the present invention is used as a communication device in accordance with communication standards such as a 4th generation mobile communication system (4G) and a 5th generation mobile communication system (5G). All you have to do is perform wireless communication.
  • the factory 884 may be connected to the factory 885 and the factory 886 via an internet line.
  • the Factory 884 has a master device (control device) 831.
  • the master device 831 has a function of connecting to the cloud 883 and exchanging information. Further, the master device 831 is connected to a plurality of industrial robots 842 included in the IoT terminal device 841 via an M2M (Machine to Machine) interface 832.
  • M2M interface 832 for example, industrial Ethernet (“Ethernet” is a registered trademark) which is a kind of wired communication method, local 5G which is a kind of wireless communication method, or the like may be used.
  • the factory manager can connect to the factory 884 from the home 881 or the office 882 via the cloud 883 and know the operating status and the like. In addition, it is possible to check for incorrect or missing items, indicate the location, and measure the tact time.
  • the rewrite resistance of the NAND memory string using the OS memory according to one aspect of the present invention was evaluated using device simulation software. In this embodiment, the evaluation result will be described.
  • the rewrite resistance was evaluated using the device simulation software TCAD centaurus manufactured by Synopsys.
  • FIG. 45A shows a perspective conceptual diagram of a semiconductor device including a plurality of NAND type memory strings (also referred to as “3D OS NAND strings”) using an OS memory.
  • the semiconductor device shown in FIG. 45A is a 3D OS NAND type storage device described in the above embodiment.
  • FIG. 45A shows a NAND type memory string, a control gate CG (Control gates), a write gate WG (Writing gates), and the like.
  • FIG. 45B shows an equivalent circuit diagram of the memory cell.
  • the memory cell shown in FIG. 45B is a 2T-1C type memory cell having two transistors (transistor WTr and transistor RTr) and one capacitive element Cs. Note that FIG. 45B is equivalent to the circuit diagram shown in FIG. 5A described in the above embodiment.
  • the transistor WTr and the transistor RTr shown in FIG. 45B are OS transistors.
  • the transistor WTr is a transistor having a floating gate (FG).
  • FG floating gate
  • polycrystalline silicon containing boron was assumed as the FG.
  • the gate of the transistor WTr is electrically connected to the write gate WG, and one of the source and drain is electrically connected to the write bit line WBL.
  • the source or drain of the transistor WTr is electrically connected to one electrode of the capacitive element Cs and the gate of the transistor RTr.
  • a node electrically connected to the other of the source or drain of the transistor WTr, one electrode of the capacitive element Cs, and the gate of the transistor RTr functions as a holding node SN. Further, the holding node SN is electrically connected to the wiring BWBL.
  • the other electrode of the capacitive element Cs is electrically connected to the control gate CG.
  • One of the source and drain of the transistor RTr is electrically connected to the read bit line RBL and the back gate of the transistor WTr.
  • the back gate of the transistor RTr is electrically connected to the back gate line BG.
  • the other of the source or drain of the transistor RTr is electrically connected to the wiring BRBL.
  • FIG. 46 shows a timing chart of the writing and reading operations of the 3D OS NAND string.
  • FIG. 46 shows a case where four memory cells are connected as a 3D OS NAND string.
  • the potential of the read bit line RBL is written to all the cells located on the drain terminal (read bit line RBL) side of the memory cell to be written. Therefore, the writing operation needs to be performed in order from the cell farthest from the read bit line RBL.
  • the read operation can follow the read operation of the NAND flash memory.
  • Table 2 shows the setting parameters of the oxide semiconductor used in the simulation.
  • Table 3 shows the power supply voltages used in simulations such as writing / reading operations.
  • the charge is injected into the FG only once at 15V, but the power supply voltage used for other operations is 4V. That is, a high power supply voltage such as a NAND flash memory is not used during the writing operation.
  • FIG. 47A shows the Id-Vwg characteristics of the transistor WTr.
  • FIG. 47A shows the Id-Vwg characteristics for each voltage (Vpre: pre-charge voltage) when the electric charge is injected into the FG of the transistor WTr.
  • FIG. 47B is a diagram showing the relationship between the threshold voltage (Vth) of the transistor WTr and Vpre. It can be seen that as Vpre increases, Vth shifts to the plus side.
  • the holding characteristics of the 3D OS NAND type storage device are determined by the magnitude of the Vth of the transistor WTr and the current (off current) flowing between the source and drain when a voltage smaller than Vth is applied to the gate. Since the OS transistor has an extremely small off current, it is suitable for the transistor WTr.
  • FIG. 48 shows the holding characteristics of the 3D OS NAND memory string.
  • FIG. 48 shows the holding characteristics of six memory cells excluding the central two among the eight memory cells connected in series.
  • the data patterns to be written when evaluating the holding characteristics are a checker pattern (writes "1" to the odd-numbered memory cells and "0" to the even-numbered memory cells) and an inverted checker pattern (writes to the odd-numbered memory cells). Two types (“0” is written and “1” is written in the even-numbered memory cell) are used.
  • the horizontal axis represents the elapsed time (Time) and the vertical axis represents the voltage Vsn of the holding node SN.
  • the vertical axis represents the voltage Vsn of the holding node SN.
  • FIGS. 49A and 49B show simulation results of the retention characteristics of the memory cells when the checker pattern and the inversion checker pattern are alternately written in the memory string.
  • "writing the checker pattern and the inverted checker pattern alternately to the memory string” means that the operation of writing "0" to the same memory cell is repeated after a certain period of time has passed since "1" was written to one memory cell. Say that. At this time, different data is always written to the adjacent memory cells.
  • the worst case of the holding characteristic can be predicted by examining the holding characteristic of the memory cell close to the wiring BWBL.
  • FIGS. 49A and 49B the horizontal axis represents the elapsed time (Time) and the vertical axis represents the voltage Vsn of the holding node SN.
  • FIG. 49A shows the holding characteristics of the holding node SN (holding node SN [1]) of the memory cell closest to the wiring BWBL.
  • FIG. 49B shows the holding characteristics of the holding node SN (holding node SN [2]) of the memory cell second closest to the wiring BWBL.
  • the read current Irbl (the magnitude of the current flowing through the read bit line RBL during the read operation) when “0” is held in the holding node SN [1] to the holding node SN [8] and “ The simulation result of the read current Irbl when 1 ”is held is shown.
  • the holding node SN [8] is a holding node SN included in the memory cell closest to the write bit line WBL in this embodiment.
  • Table 4 shows a comparison table of general DRAM and NAND flash memory and 3D OS NAND type storage device.
  • the 3D OS NAND type storage device can be expected to reduce the power supply voltage while ensuring the characteristics of holding for 10 years. Further, since the 3D OS NAND type storage device holds data in the holding node via a transistor, the rewrite endurance is expected to be about the same as that of DRAM. As described above, the 3D OS NAND type storage device has both the advantages of the NAND flash memory and the advantages of the DRAM. Therefore, the 3D OS NAND type storage device can be used as a universal memory.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
  • Non-Volatile Memory (AREA)
PCT/IB2020/061059 2019-12-06 2020-11-24 半導体装置および電子機器 Ceased WO2021111243A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2021562199A JP7714471B2 (ja) 2019-12-06 2020-11-24 半導体装置および電子機器
KR1020227018560A KR20220110201A (ko) 2019-12-06 2020-11-24 반도체 장치 및 전자 기기
US17/776,342 US12207462B2 (en) 2019-12-06 2020-11-24 Semiconductor device and electronic device
CN202080084468.7A CN114787998A (zh) 2019-12-06 2020-11-24 半导体装置及电子设备
US19/004,719 US20260122891A1 (en) 2019-12-06 2024-12-30 Semiconductor device and electronic device
JP2025119962A JP2025157403A (ja) 2019-12-06 2025-07-16 半導体装置

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2019-220945 2019-12-06
JP2019220945 2019-12-06
JP2020-069023 2020-04-07
JP2020069023 2020-04-07

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US17/776,342 A-371-Of-International US12207462B2 (en) 2019-12-06 2020-11-24 Semiconductor device and electronic device
US19/004,719 Continuation US20260122891A1 (en) 2019-12-06 2024-12-30 Semiconductor device and electronic device

Publications (1)

Publication Number Publication Date
WO2021111243A1 true WO2021111243A1 (ja) 2021-06-10

Family

ID=76221085

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2020/061059 Ceased WO2021111243A1 (ja) 2019-12-06 2020-11-24 半導体装置および電子機器

Country Status (5)

Country Link
US (2) US12207462B2 (https=)
JP (2) JP7714471B2 (https=)
KR (1) KR20220110201A (https=)
CN (1) CN114787998A (https=)
WO (1) WO2021111243A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021144648A1 (ja) * 2020-01-16 2021-07-22 株式会社半導体エネルギー研究所 記憶装置およびその作製方法
KR20230074757A (ko) 2020-10-02 2023-05-31 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
KR102910882B1 (ko) * 2021-06-21 2026-01-14 삼성전자주식회사 반도체 장치 및 이를 포함하는 데이터 저장 시스템
US20230354578A1 (en) * 2022-04-28 2023-11-02 Yangtze Memory Technologies Co., Ltd. Dynamic flash memory (dfm) with channel first scheme

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018207039A (ja) * 2017-06-08 2018-12-27 株式会社半導体エネルギー研究所 半導体装置、記憶装置、及び電子機器
WO2019003060A1 (ja) * 2017-06-27 2019-01-03 株式会社半導体エネルギー研究所 半導体装置、半導体ウェハ、記憶装置、及び電子機器
JP2019024087A (ja) * 2017-07-21 2019-02-14 株式会社半導体エネルギー研究所 半導体装置、半導体ウェハ、記憶装置、及び電子機器

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6756631B2 (en) * 2002-11-14 2004-06-29 Intelligent Sources Development Corp. Stacked-gate cell structure and its NAND-type flash memory array
KR100880338B1 (ko) * 2006-12-04 2009-01-28 주식회사 하이닉스반도체 플래시 메모리 소자의 제조방법
US9076824B2 (en) * 2012-11-02 2015-07-07 Micron Technology, Inc. Memory arrays with a memory cell adjacent to a smaller size of a pillar having a greater channel length than a memory cell adjacent to a larger size of the pillar and methods
KR20160094186A (ko) * 2015-01-30 2016-08-09 에스케이하이닉스 주식회사 반도체 장치 및 이의 제조방법
JP2016225614A (ja) 2015-05-26 2016-12-28 株式会社半導体エネルギー研究所 半導体装置
JP6693907B2 (ja) 2017-06-08 2020-05-13 株式会社半導体エネルギー研究所 半導体装置、記憶装置、及び電子機器
JP7137913B2 (ja) * 2017-06-23 2022-09-15 株式会社半導体エネルギー研究所 半導体装置
JP7195068B2 (ja) 2017-06-26 2022-12-23 株式会社半導体エネルギー研究所 半導体装置、電子機器
TW202602212A (zh) * 2019-10-31 2026-01-01 日商半導體能源研究所股份有限公司 半導體裝置及電子裝置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018207039A (ja) * 2017-06-08 2018-12-27 株式会社半導体エネルギー研究所 半導体装置、記憶装置、及び電子機器
WO2019003060A1 (ja) * 2017-06-27 2019-01-03 株式会社半導体エネルギー研究所 半導体装置、半導体ウェハ、記憶装置、及び電子機器
JP2019024087A (ja) * 2017-07-21 2019-02-14 株式会社半導体エネルギー研究所 半導体装置、半導体ウェハ、記憶装置、及び電子機器

Also Published As

Publication number Publication date
US20220399355A1 (en) 2022-12-15
JP2025157403A (ja) 2025-10-15
US12207462B2 (en) 2025-01-21
JP7714471B2 (ja) 2025-07-29
JPWO2021111243A1 (https=) 2021-06-10
KR20220110201A (ko) 2022-08-05
US20260122891A1 (en) 2026-04-30
CN114787998A (zh) 2022-07-22

Similar Documents

Publication Publication Date Title
US12396215B2 (en) Semiconductor device and electronic device
JP7714471B2 (ja) 半導体装置および電子機器
JP7720256B2 (ja) 半導体装置及び電子機器
JP7769824B2 (ja) 演算処理装置の動作方法
JP2024058633A (ja) 半導体装置
JP2025094087A (ja) 記憶装置
JP2025185071A (ja) 半導体装置
JP7711280B2 (ja) 情報処理装置の動作方法
WO2021059074A1 (ja) 記憶装置
JP7653416B2 (ja) 半導体装置
WO2022064318A1 (ja) 半導体装置、半導体装置の駆動方法、および電子機器

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20895288

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2021562199

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20895288

Country of ref document: EP

Kind code of ref document: A1