JP7714471B2 - 半導体装置および電子機器 - Google Patents

半導体装置および電子機器

Info

Publication number
JP7714471B2
JP7714471B2 JP2021562199A JP2021562199A JP7714471B2 JP 7714471 B2 JP7714471 B2 JP 7714471B2 JP 2021562199 A JP2021562199 A JP 2021562199A JP 2021562199 A JP2021562199 A JP 2021562199A JP 7714471 B2 JP7714471 B2 JP 7714471B2
Authority
JP
Japan
Prior art keywords
semiconductor
insulator
transistor
memory
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2021562199A
Other languages
English (en)
Japanese (ja)
Other versions
JPWO2021111243A5 (https=
JPWO2021111243A1 (https=
Inventor
一樹 津田
宏充 郷戸
智 大下
寛司 國武
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Publication of JPWO2021111243A1 publication Critical patent/JPWO2021111243A1/ja
Publication of JPWO2021111243A5 publication Critical patent/JPWO2021111243A5/ja
Priority to JP2025119962A priority Critical patent/JP2025157403A/ja
Application granted granted Critical
Publication of JP7714471B2 publication Critical patent/JP7714471B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6757Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/68Floating-gate IGFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/69IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/011Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/69IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/693Vertical IGFETs having charge trapping gate insulators
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00Three-dimensional [3D] integrated devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
JP2021562199A 2019-12-06 2020-11-24 半導体装置および電子機器 Active JP7714471B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2025119962A JP2025157403A (ja) 2019-12-06 2025-07-16 半導体装置

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2019220945 2019-12-06
JP2019220945 2019-12-06
JP2020069023 2020-04-07
JP2020069023 2020-04-07
PCT/IB2020/061059 WO2021111243A1 (ja) 2019-12-06 2020-11-24 半導体装置および電子機器

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2025119962A Division JP2025157403A (ja) 2019-12-06 2025-07-16 半導体装置

Publications (3)

Publication Number Publication Date
JPWO2021111243A1 JPWO2021111243A1 (https=) 2021-06-10
JPWO2021111243A5 JPWO2021111243A5 (https=) 2023-11-27
JP7714471B2 true JP7714471B2 (ja) 2025-07-29

Family

ID=76221085

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2021562199A Active JP7714471B2 (ja) 2019-12-06 2020-11-24 半導体装置および電子機器
JP2025119962A Pending JP2025157403A (ja) 2019-12-06 2025-07-16 半導体装置

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2025119962A Pending JP2025157403A (ja) 2019-12-06 2025-07-16 半導体装置

Country Status (5)

Country Link
US (1) US12207462B2 (https=)
JP (2) JP7714471B2 (https=)
KR (1) KR20220110201A (https=)
CN (1) CN114787998A (https=)
WO (1) WO2021111243A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12444466B2 (en) * 2020-01-16 2025-10-14 Semiconductor Energy Laboratory Co., Ltd. Memory device and method for manufacturing the same
CN116368602A (zh) 2020-10-02 2023-06-30 株式会社半导体能源研究所 半导体装置
KR102910882B1 (ko) * 2021-06-21 2026-01-14 삼성전자주식회사 반도체 장치 및 이를 포함하는 데이터 저장 시스템
US20230354578A1 (en) * 2022-04-28 2023-11-02 Yangtze Memory Technologies Co., Ltd. Dynamic flash memory (dfm) with channel first scheme

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018207039A (ja) 2017-06-08 2018-12-27 株式会社半導体エネルギー研究所 半導体装置、記憶装置、及び電子機器
WO2019003060A1 (ja) 2017-06-27 2019-01-03 株式会社半導体エネルギー研究所 半導体装置、半導体ウェハ、記憶装置、及び電子機器
JP2019009259A (ja) 2017-06-23 2019-01-17 株式会社半導体エネルギー研究所 半導体装置
JP2019024087A (ja) 2017-07-21 2019-02-14 株式会社半導体エネルギー研究所 半導体装置、半導体ウェハ、記憶装置、及び電子機器

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6756631B2 (en) * 2002-11-14 2004-06-29 Intelligent Sources Development Corp. Stacked-gate cell structure and its NAND-type flash memory array
KR100880338B1 (ko) * 2006-12-04 2009-01-28 주식회사 하이닉스반도체 플래시 메모리 소자의 제조방법
US9076824B2 (en) * 2012-11-02 2015-07-07 Micron Technology, Inc. Memory arrays with a memory cell adjacent to a smaller size of a pillar having a greater channel length than a memory cell adjacent to a larger size of the pillar and methods
KR20160094186A (ko) * 2015-01-30 2016-08-09 에스케이하이닉스 주식회사 반도체 장치 및 이의 제조방법
JP2016225614A (ja) 2015-05-26 2016-12-28 株式会社半導体エネルギー研究所 半導体装置
JP6693907B2 (ja) 2017-06-08 2020-05-13 株式会社半導体エネルギー研究所 半導体装置、記憶装置、及び電子機器
JP7195068B2 (ja) 2017-06-26 2022-12-23 株式会社半導体エネルギー研究所 半導体装置、電子機器
TWI882001B (zh) * 2019-10-31 2025-05-01 日商半導體能源研究所股份有限公司 半導體裝置及電子裝置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018207039A (ja) 2017-06-08 2018-12-27 株式会社半導体エネルギー研究所 半導体装置、記憶装置、及び電子機器
JP2019009259A (ja) 2017-06-23 2019-01-17 株式会社半導体エネルギー研究所 半導体装置
WO2019003060A1 (ja) 2017-06-27 2019-01-03 株式会社半導体エネルギー研究所 半導体装置、半導体ウェハ、記憶装置、及び電子機器
JP2019024087A (ja) 2017-07-21 2019-02-14 株式会社半導体エネルギー研究所 半導体装置、半導体ウェハ、記憶装置、及び電子機器

Also Published As

Publication number Publication date
US12207462B2 (en) 2025-01-21
CN114787998A (zh) 2022-07-22
US20220399355A1 (en) 2022-12-15
WO2021111243A1 (ja) 2021-06-10
JP2025157403A (ja) 2025-10-15
KR20220110201A (ko) 2022-08-05
JPWO2021111243A1 (https=) 2021-06-10

Similar Documents

Publication Publication Date Title
US12396215B2 (en) Semiconductor device and electronic device
JP7714471B2 (ja) 半導体装置および電子機器
JP7720256B2 (ja) 半導体装置及び電子機器
US20250166713A1 (en) Memory Device, Operation Method of Memory Device, Data Processing Device, Data Processing System, and Electronic Device
JP7798778B2 (ja) 半導体装置
JP7769824B2 (ja) 演算処理装置の動作方法
JP2024058633A (ja) 半導体装置
JP2025185071A (ja) 半導体装置
JP7711280B2 (ja) 情報処理装置の動作方法
US20260122891A1 (en) Semiconductor device and electronic device
WO2022064318A1 (ja) 半導体装置、半導体装置の駆動方法、および電子機器

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20231116

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20231116

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20241105

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20241213

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20250325

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20250428

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20250708

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20250716

R150 Certificate of patent or registration of utility model

Ref document number: 7714471

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150