WO2021103097A1 - 一种半导体超结功率器件 - Google Patents

一种半导体超结功率器件 Download PDF

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Publication number
WO2021103097A1
WO2021103097A1 PCT/CN2019/123424 CN2019123424W WO2021103097A1 WO 2021103097 A1 WO2021103097 A1 WO 2021103097A1 CN 2019123424 W CN2019123424 W CN 2019123424W WO 2021103097 A1 WO2021103097 A1 WO 2021103097A1
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Prior art keywords
type
gate
super
floating gate
junction
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PCT/CN2019/123424
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English (en)
French (fr)
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龚轶
刘伟
刘磊
袁愿林
王睿
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苏州东微半导体有限公司
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Priority to JP2021551598A priority Critical patent/JP7173645B2/ja
Priority to DE112019006962.4T priority patent/DE112019006962T5/de
Priority to KR1020217042484A priority patent/KR102519235B1/ko
Priority to US17/439,689 priority patent/US12027519B2/en
Publication of WO2021103097A1 publication Critical patent/WO2021103097A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Definitions

  • This application belongs to the technical field of semiconductor super junction power devices, for example, relates to a semiconductor super junction power device with adjustable reverse recovery speed.
  • FIG. 1 A cross-sectional structure of a semiconductor super junction power device in the related art is shown in FIG. 1, and includes: an n-type drain region 50, which is connected to the drain through a drain contact metal layer 58; and is located between the n-type drain region 50
  • the upper n-type drift region 51, the p-type body region 52 on the top of the n-type drift region 51, the n-type source region 53 in the p-type body region 52, the n-type source region 53 and the p-type body region 52 pass through the source
  • the contact metal layer 57 is connected to the source;
  • the p-type columnar doped region 59 is located under the p-type body region; the current channel is located in the p-type body region 52 and between the n-type source region 53 and the n-type drift region 51 ,
  • the gate structure includes a gate dielectric layer 54 and a gate 55.
  • the reverse current will flow through the parasitic body diode in the semiconductor super junction power device.
  • the body diode current has the phenomenon of injecting minority carrier carriers, and these minority carrier carriers Reverse recovery is performed when the semiconductor super junction power device is turned on again, resulting in a larger reverse recovery current and a long reverse recovery time.
  • life control technologies such as electron irradiation, deep-level recombination centers, etc. are usually used to improve the reverse recovery speed of semiconductor super-junction power devices.
  • the disadvantages of this method are increased process difficulty, increased manufacturing costs, and inaccuracy. Control the reverse recovery speed of semiconductor super junction power devices.
  • the present application provides a semiconductor super junction power device with adjustable reverse recovery speed to solve the technical problem that the reverse recovery speed of the semiconductor super junction power device cannot be accurately controlled in the related art.
  • a p-type body region the p-type body region is located on top of the n-type drift region; a p-type columnar doped region located below the p-type body region; an n-type source region located in the p-type body region;
  • the gate is located on the side close to the n-type source region
  • the n-type floating gate is located on the side close to the n-type drift region
  • the gate acts on the side close to the n-type drift region through capacitive coupling.
  • the n-type floating gate of at least one super-junction MOSFET cell is isolated from the p-type body region by the gate dielectric layer, and there is at least one super-junction MOSFET
  • the n-type floating gate of the cell contacts the p-type body region through an opening in the gate dielectric layer under the n-type floating gate to form a pn junction diode.
  • the gate extends above the n-type floating gate.
  • the gate extends above the n-type floating gate and covers the sidewall of the n-type floating gate close to the n-type drift region.
  • the opening is located below the n-type floating gate and close to the n-type drift region.
  • At least one gate of the super-junction MOSFET unit is electrically connected to the n-type source region.
  • the reverse recovery speed of the semiconductor super junction power device can be conveniently and accurately controlled by controlling the number of super junction MOSFET cells formed with pn junction diodes, so that the semiconductor super junction Power devices have a wider range of applications.
  • the number of MOSFET cells formed with p-n junction diodes it is only necessary to modify a mask used to form the opening in the gate dielectric layer, which can effectively control the manufacturing cost of the semiconductor super junction power device.
  • FIG. 1 is a schematic diagram of a cross-sectional structure of a semiconductor super junction power device in the related art
  • FIG. 2 is a schematic cross-sectional structure diagram of a first embodiment of a semiconductor super junction power device provided by the present application
  • FIG. 3 is a schematic cross-sectional structure diagram of a second embodiment of a semiconductor super junction power device provided by the present application.
  • FIG. 2 is a schematic cross-sectional structure diagram of a first embodiment of a semiconductor super junction power device provided by the present application.
  • a semiconductor super junction power device provided by an embodiment of the present invention includes an n-type drain region 20 , The n-type drift region 21 located above the n-type drain region 20, and a super-junction MOSFET cell array composed of a plurality of super-junction MOSFET cells, FIG. 2 exemplarily shows two super-junction MOSFET cells (super-junction MOSFET cells).
  • the super-junction MOSFET cell of the embodiment of the present invention includes: a p-type body region 22, which is located on top of the n-type drift region 21; a p-type columnar doped region 29 located below the p-type body region 22, which is doped with p-type columnar A charge balance is formed between the impurity region 29 and the adjacent n-type drift region 21 to improve the withstand voltage of the semiconductor super power device; the n-type source region 23 is located in the p-type body region 22; and the n-type source region 23 is located in the p-type body region 22
  • the gate structure includes a gate dielectric layer 24, an n-type floating gate 25 and a gate 26.
  • the gate 26 and the n-type floating gate 25 are located on the gate dielectric layer 24, and in the lateral direction, the n-type The floating gate 25 is located on the side close to the n-type drift region 21, and the gate 26 is located on the side close to the n-type source region 23 and extends above the n-type floating gate 25.
  • the gate 26 and the n-type floating gate 25 are made of an insulating medium.
  • the layer 27 is isolated, and the gate 26 acts on the n-type floating gate 25 through capacitive coupling.
  • the insulating dielectric layer 27 is usually silicon dioxide.
  • the n-type floating gate 25 of at least one super-junction MOSFET cell is isolated from the p-type body region 22 by the gate dielectric layer 24 (the super-junction MOSFET cell 201 in FIG. 2), And the n-type floating gate 25 of at least one super-junction MOSFET unit contacts the p-type body region 22 through an opening 28 in the gate dielectric layer 24 under the n-type floating gate 25 to form a pn junction diode (as shown in FIG. 2 Super junction MOSFET cell 200).
  • the gate 26 in the lateral direction, is located on the side close to the n-type source region 23, and the n-type floating gate 25 is located on the side close to the n-type drift region 21, that is, in the lateral direction, the n-type floating gate 25 It is arranged close to the n-type drift region, and the gate 26 is arranged close to the n-type source region 23.
  • the gate 26 may all be located on the side close to the n-type source region 23, that is, the gate 26 may be located only on the side close to the n-type source region 23, or a part of the gate 26 may be located close to the n-type source region 23.
  • FIG. 3 is a schematic cross-sectional structure diagram of a second embodiment of a semiconductor super junction power device provided by the present application.
  • FIG. 3 only exemplarily shows the gate 26 of the super junction MOSFET unit 200 in FIG. A structure in which one side of the type drift region 21 extends above the n-type floating gate 25 and covers the sidewall of the n-type floating gate 25 close to the n-type drift region 21.
  • Extending the gate 26 to one side of the n-type drift region 21 can increase the area of the gate 26 covering the n-type floating gate 25, thereby increasing the capacitive coupling ratio of the gate 26 to the n-type floating gate 26.
  • a high voltage is applied to the n-type drain region 20, and the super-junction MOSFET unit 200 consists of an n-type floating gate 25 and a p-type body region 22
  • the formed pn junction diode is forward biased, and the n-type floating gate 25 in the super-junction MOSFET cell 200 is charged with a positive charge, which makes the threshold of the current channel below the n-type floating gate 25 in the super-junction MOSFET cell 200
  • the voltage Vht1 decreases.
  • the opening 28 in the gate dielectric layer 24 is located below the n-type floating gate 25 and close to the n-type drift region 21, that is, in the lateral direction, the opening 28 is located in the gate dielectric layer 24 closer to the n-type drift region. 21, which makes it easier for the n-type floating gate 25 in the MOSFET cell 200 to be charged with positive charges.
  • the drain-source voltage Vds is greater than 0V, and the threshold voltage Vht1 of the current channel under the n-type floating gate 25 in the super junction MOSFET unit 200
  • the impact on the threshold voltage Vth of the entire super-junction MOSFET cell 200 is very low, and the super-junction MOSFET cell 200 still has a high threshold voltage.
  • the semiconductor super-junction power device of the embodiment of the present invention When the semiconductor super-junction power device of the embodiment of the present invention is turned off, when the source-drain voltage Vsd is greater than 0V, the threshold voltage Vht1 of the current channel under the n-type floating gate 25 in the super-junction MOSFET unit 200 affects the entire super-junction MOSFET.
  • the threshold voltage Vth of the cell 200 has a great influence, so that the super-junction MOSFET cell 200 has a low threshold voltage Vth, so that the current channel of the super-junction MOSFET cell 200 is turned on at a low gate voltage (or 0V voltage), thereby enabling
  • the reverse current flowing through the super junction MOSFET unit 200 is increased, the current flowing through the parasitic body diode in the semiconductor super junction power device is reduced, and the reverse recovery speed of the semiconductor super junction power device is improved.
  • the super-junction MOSFET cell array of the semiconductor super-junction power device of the embodiment of the present invention by controlling the number of openings 28 in the gate dielectric layer 24, that is, by controlling the number of super-junction MOSFET cells formed with pn junction diodes, it is convenient and Accurately controlling the reverse recovery speed of semiconductor super junction power devices makes semiconductor super junction power devices more widely used.
  • the number of superjunction MOSFET cells formed with pn junction diodes it is only necessary to modify a mask used to form the opening 28 in the gate dielectric layer 24, which can greatly reduce the semiconductor superjunction. The manufacturing cost of power devices.
  • the gate 26 of at least one super-junction MOSFET cell can be electrically connected to the n-type source region 23, that is, the part of the gate 26 is connected to the source voltage , which can reduce the gate charge of semiconductor superjunction power devices.

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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

本发明实施例提供的一种半导体超结功率器件，包括由多个超结MOSFET单元组成的超结MOSFET单元阵列，超结MOSFET单元的栅极结构包括栅介质层、栅极和n型浮栅，栅极和n型浮栅位于栅介质层之上，且在横向上，栅极位于靠近n型源区的一侧，n型浮栅位于靠近n型漂移区的一侧，栅极通过电容耦合作用于n型浮栅；至少有一个超结MOSFET单元的n型浮栅通过栅介质层与p型体区隔离，且至少有一个超结MOSFET单元的n型浮栅通过一个位于该n型浮栅下方的栅介质层中的开口与p型体区接触形成p-n结二极管。本发明实施例可以方便的调节半导体超结功率器件的反向恢复速度。

Description

一种半导体超结功率器件
本公开要求在2019年11月29日提交中国专利局、申请号为201911202240.9的中国专利申请的优先权，以上申请的全部内容通过引用结合在本公开中。
技术领域
本申请属于半导体超结功率器件技术领域，例如涉及一种反向恢复速度可调的半导体超结功率器件。
背景技术
相关技术的一种半导体超结功率器件的剖面结构如图1所示，包括：n型漏区50，n型漏区50通过漏极接触金属层58接漏极；位于n型漏区50之上的n型漂移区51，位于n型漂移区51顶部的p型体区52，位于p型体区52内的n型源区53，n型源区53和p型体区52通过源极接触金属层57接源极；位于p型体区下方的p型柱状掺杂区59；位于p型体区52内且介于n型源区53和n型漂移区51之间的电流沟道，以及控制该电流沟道开启和关断的栅极结构，该栅极结构包括栅介质层54和栅极55。
相关技术的半导体超结功率器件在关断时，反向电流会流过半导体超结功率器件内寄生的体二极管，此时体二极管的电流存在注入少子载流子现象，而这些少子载流子在半导体超结功率器件再一次开启时进行反向恢复，导致较大的反向恢复电流，反向恢复时间长。相关技术中，通常采用寿命控制技术如：电子辐照、深能级复合中心等来提高半导体超结功率器件的反向恢复速度，该方法的缺点是工艺难度提高、制造成本上升，而且不能准确控制半导体超结功率器件的反向恢复速度。
发明内容
本申请提供一种反向恢复速度可调的半导体超结功率器件，以解决相关技术中的不能准确控制半导体超结功率器件的反向恢复速度的技术问题。
本发明实施例提供的一种半导体超结功率器件，包括：
n型漏区，位于所述n型漏区之上的n型漂移区，以及由多个超结MOSFET单元组成的超结MOSFET单元阵列，所述超结MOSFET单元包括：
p型体区，所述p型体区位于所述n型漂移区顶部；位于所述p型体区下方 的p型柱状掺杂区；位于所述p型体区内的n型源区；位于所述p型体区之上的栅极结构，所述栅极结构包括栅介质层、栅极和n型浮栅，所述栅极和所述n型浮栅位于所述栅介质层之上，且在横向上，所述栅极位于靠近所述n型源区的一侧，所述n型浮栅位于靠近所述n型漂移区的一侧，所述栅极通过电容耦合作用于所述n型浮栅；
在所述超结MOSFET单元阵列中，至少有一个所述超结MOSFET单元的所述n型浮栅通过所述栅介质层与所述p型体区隔离，且至少有一个所述超结MOSFET单元的所述n型浮栅通过一个位于该n型浮栅下方的所述栅介质层中的开口与所述p型体区接触形成p-n结二极管。
可选的，本申请的半导体超结功率器件，所述栅极延伸至所述n型浮栅之上。
可选的，本申请的半导体超结功率器件，所述栅极延伸至所述n型浮栅之上且覆盖所述n型浮栅靠近所述n型漂移区一侧的侧壁。
可选的，本申请的半导体超结功率器件，所述开口位于所述n型浮栅下方且靠近所述n型漂移区的一侧。
可选的，本申请的半导体超结功率器件，至少有一个所述超结MOSFET单元的栅极与所述n型源区电性连接。
本发明实施例提供的一种半导体超结功率器件，通过控制形成有p-n结二极管的超结MOSFET单元的数量，可以方便且准确的控制半导体超结功率器件的反向恢复速度，使得半导体超结功率器件具有更广泛的应用。同时，在调整形成有p-n结二极管的MOSFET单元的数量时，只需要通过修改用于形成栅介质层中的开口的一块掩膜版即可，这可以有效控制半导体超结功率器件的制造成本。
附图说明
下面对描述实施例中所需要用到的附图做一简单介绍。
图1是相关技术的一种半导体超结功率器件的剖面结构示意图；
图2是本申请提供的一种半导体超结功率器件的第一个实施例的剖面结构示意图；
图3是本申请提供的一种半导体超结功率器件的第二个实施例的剖面结构示意图。
具体实施方式
以下将结合本申请实施例中的附图，通过具体实施方式，完整地描述本申请的技术方案。同时，说明书附图中所列示意图，放大了本申请所述的层和区域的尺寸，且所列图形大小并不代表实际尺寸。说明书中所列实施例不应仅限于说明书附图中所示区域的特定形状，而是包括所得到的形状如制备引起的偏差等。
图2是本申请提供的一种半导体超结功率器件的第一个实施例的剖面结构示意图，如图2所示，本发明实施例提供的一种半导体超结功率器件包括n型漏区20，位于n型漏区20之上的n型漂移区21，以及由多个超结MOSFET单元组成的超结MOSFET单元阵列，图2中示例性的示出了两个超结MOSFET单元(超结MOSFET单元200和超结MOSFET单元201)。
本发明实施例的超结MOSFET单元包括：p型体区22，p型体区22位于n型漂移区21顶部；位于p型体区22下方的p型柱状掺杂区29，p型柱状掺杂区29与相邻的n型漂移区21之间形成电荷平衡，用以提高半导体超级功率器件的耐压；位于p型体区22内的n型源区23；位于p型体区22之上的栅极结构，该栅极结构包括栅介质层24、n型浮栅25和栅极26，栅极26和n型浮栅25位于栅介质层24之上，且在横向上，n型浮栅25位于靠近n型漂移区21的一侧，栅极26位于靠近n型源区23的一侧且延伸至n型浮栅25之上，栅极26和n型浮栅25由绝缘介质层27隔离，栅极26通过电容耦合作用于n型浮栅25。绝缘介质层27通常为二氧化硅。
本发明实施例的超结MOSFET单元阵列中，至少有一个超结MOSFET单元的n型浮栅25通过栅介质层24与p型体区22隔离(如图2中的超结MOSFET单元201)，且至少有一个超结MOSFET单元的n型浮栅25通过一个位于该n型浮栅25下方的栅介质层24中的开口28与p型体区22接触形成p-n结二极管(如图2中的超结MOSFET单元200)。
本发明实施例中，在横向上，栅极26位于靠近n型源区23的一侧，n型浮栅25位于靠近n型漂移区21的一侧，即在横向上，n型浮栅25靠近n型漂移区设置，栅极26靠近n型源区23设置。另外，栅极26可全部位于靠近n型源区23的一侧，即栅极26可以仅位于靠近n型源区23的一侧，也可以是栅极26一部分位于靠近n型源区23的一侧，另一部分延伸至n型浮栅25之上(如图2 所示)，或者是栅极26延伸至n型浮栅25之上且覆盖n型浮栅25靠近n型漂移区21一侧的侧壁(如图3所示)。图3是本申请提供的一种半导体超结功率器件的第二个实施例的剖面结构示意图，图3中仅示例性的示出了图2中的超结MOSFET单元200的栅极26向n型漂移区21的一侧延伸至n型浮栅25之上且覆盖n型浮栅25靠近n型漂移区21一侧的侧壁的结构。
栅极26向n型漂移区21的一侧延伸可以增大栅极26覆盖n型浮栅25的面积，进而能够增大栅极26对n型浮栅26的电容耦合率。
本发明实施例的一种半导体超结功率器件，在正向阻断状态时，n型漏区20被施加高电压，超结MOSFET单元200中的由n型浮栅25与p型体区22形成的p-n结二极管被正向偏置，超结MOSFET单元200中的n型浮栅25被充入正电荷，这使得超结MOSFET单元200中的n型浮栅25下面的电流沟道的阈值电压Vht1降低。可选的，位于栅介质层24中的开口28位于n型浮栅25下方且靠近n型漂移区21的一侧，即在横向上，开口28位于栅介质层24的更靠近n型漂移区21的区域，这可以使得MOSFET单元200中的n型浮栅25更容易的被充入正电荷。
本发明实施例的半导体超结功率器件在正向阻断状态和正向开启状态时，漏源电压Vds大于0V，超结MOSFET单元200中的n型浮栅25下面的电流沟道的阈值电压Vht1对整个超结MOSFET单元200的阈值电压Vth的影响很低，超结MOSFET单元200仍具有高阈值电压。本发明实施例的半导体超结功率器件在关断时，当源漏电压Vsd大于0V时，超结MOSFET单元200中的n型浮栅25下面的电流沟道的阈值电压Vht1对整个超结MOSFET单元200的阈值电压Vth的影响很大，使得超结MOSFET单元200具有低阈值电压Vth，从而使超结MOSFET单元200的电流沟道在低栅极电压(或0V电压)下导通，从而能够增加流过超结MOSFET单元200的反向电流，减少流过半导体超结功率器件中寄生的体二极管的电流，提高半导体超结功率器件的反向恢复速度。
本发明实施例的半导体超结功率器件的超结MOSFET单元阵列中，通过控制栅介质层24中的开口28的数量，即通过控制形成有p-n结二极管的超结MOSFET单元的数量，可以方便且准确的控制半导体超结功率器件的反向恢复速度，使得半导体超结功率器件具有更广泛的应用。同时，在调整形成有p-n结二极管的超结MOSFET单元的数量时，只需要通过修改用于形成栅介质层24中的开口28的一块掩膜版即可，这可以极大的降低半导体超结功率器件的制造 成本。
本发明实施例的半导体超结功率器件的超结MOSFET单元阵列中，可以使得至少一个超结MOSFET单元的栅极26与n型源区23电性连接，即该部分栅极26接源极电压，这可以降低半导体超结功率器件的栅电荷。

Claims (5)

  1. 一种半导体超结功率器件，包括：
    n型漏区，位于所述n型漏区之上的n型漂移区，以及由多个超结MOSFET单元组成的超结MOSFET单元阵列，所述超结MOSFET单元包括：
    p型体区，所述p型体区位于所述n型漂移区顶部；位于所述p型体区下方的p型柱状掺杂区；位于所述p型体区内的n型源区；位于所述p型体区之上的栅极结构，所述栅极结构包括栅介质层、栅极和n型浮栅，所述栅极和所述n型浮栅位于所述栅介质层之上，且在横向上，所述栅极位于靠近所述n型源区的一侧，所述n型浮栅位于靠近所述n型漂移区的一侧，所述栅极通过电容耦合作用于所述n型浮栅；
    在所述超结MOSFET单元阵列中，至少有一个所述超结MOSFET单元的所述n型浮栅通过所述栅介质层与所述p型体区隔离，且至少有一个所述超结MOSFET单元的所述n型浮栅通过一个位于该n型浮栅下方的所述栅介质层中的开口与所述p型体区接触形成p-n结二极管。
  2. 如权利要求1所述的半导体超结功率器件，其中，所述栅极延伸至所述n型浮栅之上。
  3. 如权利要求1所述的半导体超结功率器件，其中，所述栅极延伸至所述n型浮栅之上且覆盖所述n型浮栅靠近所述n型漂移区一侧的侧壁。
  4. 如权利要求1所述的半导体超结功率器件，其中，所述开口位于所述n型浮栅下方且靠近所述n型漂移区的一侧。
  5. 如权利要求1所述的半导体超结功率器件，其中，至少有一个所述超结MOSFET单元的栅极与所述n型源区电性连接。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011142339A (ja) * 2011-03-17 2011-07-21 Fuji Electric Co Ltd 半導体素子
US20130334565A1 (en) * 2012-06-14 2013-12-19 Infineon Technologies Austria Ag Method of Manufacturing a Semiconductor Device Using an Impurity Source Containing a Metallic Recombination Element and Semiconductor Device
CN106229343A (zh) * 2016-08-12 2016-12-14 上海鼎阳通半导体科技有限公司 超结器件
US20170213887A1 (en) * 2009-08-31 2017-07-27 Lingpeng Guan Integrated schottky diode in high voltage semiconductor device
CN107768371A (zh) * 2017-10-24 2018-03-06 贵州芯长征科技有限公司 集成肖特基结的超结mosfet结构及其制备方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62254468A (ja) * 1986-04-28 1987-11-06 Seiko Instr & Electronics Ltd 半導体不揮発性メモリ
JP3979258B2 (ja) * 2002-05-21 2007-09-19 富士電機デバイステクノロジー株式会社 Ｍｉｓ半導体装置およびその製造方法
US6882573B2 (en) * 2002-08-13 2005-04-19 General Semiconductor, Inc. DMOS device with a programmable threshold voltage
WO2004015745A2 (en) * 2002-08-13 2004-02-19 General Semiconductor, Inc. A dmos device with a programmable threshold voltage
US7986005B2 (en) * 2007-07-27 2011-07-26 Infineon Technologies Austria Ag Short circuit limiting in power semiconductor devices
US8304829B2 (en) * 2008-12-08 2012-11-06 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
KR20110058332A (ko) * 2009-11-26 2011-06-01 페어차일드코리아반도체 주식회사 플로팅 게이트 구조를 이용한 인핸스먼트 질화물계 반도체 소자
CN103839982A (zh) * 2012-11-23 2014-06-04 上海华虹宏力半导体制造有限公司 平面栅超级结产品栅极版图结构
CN104465381B (zh) * 2013-09-23 2017-12-01 苏州东微半导体有限公司 一种平面沟道的半浮栅器件的制造方法
CN104576646B (zh) * 2013-10-11 2017-09-05 苏州东微半导体有限公司 一种集成电路芯片及其制造方法
US9324856B2 (en) * 2014-05-30 2016-04-26 Texas Instruments Incorporated MOSFET having dual-gate cells with an integrated channel diode
JP6652802B2 (ja) 2015-09-15 2020-02-26 ローム株式会社 半導体装置、および当該半導体装置を備えるインバータ装置
CN109755241B (zh) * 2017-11-01 2021-03-02 苏州东微半导体股份有限公司 一种功率mosfet器件
WO2019085752A1 (zh) 2017-11-01 2019-05-09 苏州东微半导体有限公司 功率mosfet器件

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170213887A1 (en) * 2009-08-31 2017-07-27 Lingpeng Guan Integrated schottky diode in high voltage semiconductor device
JP2011142339A (ja) * 2011-03-17 2011-07-21 Fuji Electric Co Ltd 半導体素子
US20130334565A1 (en) * 2012-06-14 2013-12-19 Infineon Technologies Austria Ag Method of Manufacturing a Semiconductor Device Using an Impurity Source Containing a Metallic Recombination Element and Semiconductor Device
CN106229343A (zh) * 2016-08-12 2016-12-14 上海鼎阳通半导体科技有限公司 超结器件
CN107768371A (zh) * 2017-10-24 2018-03-06 贵州芯长征科技有限公司 集成肖特基结的超结mosfet结构及其制备方法

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