WO2021084902A1 - チップ付き基板の製造方法、及び基板処理装置 - Google Patents

チップ付き基板の製造方法、及び基板処理装置 Download PDF

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WO2021084902A1
WO2021084902A1 PCT/JP2020/033410 JP2020033410W WO2021084902A1 WO 2021084902 A1 WO2021084902 A1 WO 2021084902A1 JP 2020033410 W JP2020033410 W JP 2020033410W WO 2021084902 A1 WO2021084902 A1 WO 2021084902A1
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Prior art keywords
substrate
chips
bonded
layer
manufacturing
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Ceased
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PCT/JP2020/033410
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English (en)
French (fr)
Japanese (ja)
Inventor
隼斗 田之上
溝本　康隆
陽平 山下
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Priority to CN202511278398.XA priority Critical patent/CN121123034A/zh
Priority to JP2021554128A priority patent/JP7330284B2/ja
Priority to KR1020257025004A priority patent/KR20250121140A/ko
Priority to KR1020227017319A priority patent/KR102839966B1/ko
Priority to CN202080073979.9A priority patent/CN114586135B/zh
Priority to US17/772,166 priority patent/US20220406603A1/en
Publication of WO2021084902A1 publication Critical patent/WO2021084902A1/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67115—Apparatus for thermal treatment mainly by radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H01L21/67721—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations the substrates to be conveyed not being semiconductor wafers or large planar substrates, e.g. chips, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
    • H10P72/0428—
    • H10P72/74—
    • H10P90/1914—
    • H10P95/062—
    • H10W74/019—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H10P72/7408—
    • H10P72/7428—
    • H10P72/7434—
    • H10P72/744—

Definitions

  • This disclosure relates to a method for manufacturing a substrate with a chip and a substrate processing apparatus.
  • FIG. 20 of Patent Document 1 illustrates a chip-on-wafer manufacturing process.
  • the individualized first memory chips are bonded one by one to the base wafer on which the plurality of second memory chips are formed.
  • One aspect of the present disclosure provides a technique capable of suppressing poor bonding between a chip and a substrate.
  • the method for manufacturing a substrate with a chip is as follows. To prepare a laminated substrate including a plurality of the chips, a first substrate to which the plurality of chips are temporarily bonded, and a second substrate bonded to the first substrate via the plurality of chips. , To separate the first substrate and the plurality of chips bonded to the second substrate from the first substrate in order to bond them to one side including the device layer of the third substrate. Have.
  • FIG. 1 is a flowchart showing a method of manufacturing a substrate with a chip according to an embodiment.
  • FIG. 2 is a flowchart showing the details of S1 of FIG.
  • FIG. 3 is a flowchart showing the details of S6 of FIG.
  • FIG. 4A is a cross-sectional view showing a state in the middle of S1 of FIG.
  • FIG. 4B is a cross-sectional view showing a state at the time of completion of S1 of FIG.
  • FIG. 4C is a cross-sectional view showing a state at the time of completion of S2 of FIG.
  • FIG. 4D is a cross-sectional view showing a state at the time of completion of S3 of FIG.
  • FIG. 4E is a cross-sectional view showing a state in the middle of S4 of FIG.
  • FIG. 4F is a cross-sectional view showing a state at the time of completion of S4 of FIG.
  • FIG. 4G is a cross-sectional view showing a state at the time of completion of S5 of FIG.
  • FIG. 4H is a cross-sectional view showing a state at the time of completion of S61 of FIG. 3, which is included in S6 of FIG.
  • FIG. 4I is a cross-sectional view showing a state at the time of completion of S62 of FIG. 3, which is included in S6 of FIG.
  • FIG. 4J is a cross-sectional view showing a state at the time of completion of S63 of FIG. 3, which is included in S6 of FIG.
  • FIG. 4K is a cross-sectional view showing a state at the time of completion of S7 of FIG.
  • FIG. 5 is a plan view showing a substrate processing apparatus according to an embodiment.
  • the method for manufacturing a substrate with a chip includes, for example, S1 to S7 shown in FIG. S1 of FIG. 1 has, for example, S11 to S14 shown in FIG. Further, S6 shown in FIG. 1 has, for example, S61 to S63 shown in FIG.
  • the first substrate 1 has, for example, a silicon wafer 11, an absorption layer 12, and a bonding layer 13.
  • the absorption layer 12 may also serve as a bonding layer 13 as described later, and the first substrate 1 may have a silicon wafer 11 and an absorption layer 12.
  • the absorption layer 12 is arranged between the silicon wafer 11 and the chips 2A and 2B. Although details will be described later, the laser beam LB2 shown in FIG. 4H passes through the silicon wafer 11 and is absorbed by the absorption layer 12. Since the laser beam LB2 is absorbed by the absorption layer 12 and does not hit the chips 2A and 2B, damage to the chips 2A and 2B can be suppressed.
  • the absorption layer 12 is, for example, a silicon oxide layer, and is formed by a thermal oxidation method, a CVD (Chemical Vapor Deposition) method, or the like.
  • the absorption layer 12 may be a silicon nitride layer, a silicon carbonitrider layer, or the like, as long as it can absorb the laser beam LB2 to the extent that damage to the chips 2A and 2B can be suppressed.
  • the silicon nitride layer is formed by a thermal nitriding method, a CVD method, or the like.
  • the silicon carbonitriding layer is formed by a CVD method or the like.
  • the bonding layer 13 is arranged between the absorbing layer 12 and the chips 2A and 2B, and comes into contact with the chips 2A and 2B.
  • the bonding layer 13 is, for example, an insulating layer such as a silicon oxide layer.
  • the bonding layer 13 may be made of a material different from that of the absorbing layer 12, or may be made of the same material. In the latter case, the absorption layer 12 may also serve as the bonding layer 13.
  • the bonding layer 13 includes an alignment mark 15 on the bonding surface 14 with the chips 2A and 2B.
  • the alignment mark 15 is imaged by a camera or the like and is used for position control of the chips 2A and 2B.
  • the position of the alignment mark 15 is not limited to the bonding surface 14 of the bonding layer 13, and may be, for example, the absorbing layer 12, or between the absorbing layer 12 and the bonding layer 13.
  • the chip 2A has a silicon wafer 21A and a device layer 22A.
  • the device layer 22A is formed on the surface of the silicon wafer 21A.
  • the device layer 22A includes semiconductor elements, circuits, terminals, and the like. After the device layer 22A is formed, the silicon wafer 21A is fragmented into a plurality of chips 2A.
  • the chip 2B has a silicon wafer 21B and a device layer 22B, similarly to the chip 2A.
  • the device layer 22B has a function different from that of the device layer 22A, and the chip 2A and the chip 2B have different thicknesses. After the device layer 22B is formed, the silicon wafer 21B is fragmented into a plurality of chips 2B.
  • the joint surface 14 of the first substrate 1 is surface-modified with plasma or the like. Specifically, the bond of SiO 2 on the joint surface 14 is cut to form an unbonded hand of Si, which enables hydrophilicization of the joint surface 14.
  • oxygen gas which is a processing gas
  • oxygen gas is excited to be turned into plasma and ionized in a reduced pressure atmosphere.
  • Oxygen ions are applied to the joint surface 14, and the joint surface 14 is modified.
  • the processing gas is not limited to oxygen gas, and may be, for example, nitrogen gas.
  • the bonding surface 14 of the first substrate 1 may be surface-modified. At least one of the bonding surface 14 of the first substrate 1 and the bonding surfaces 24A and 24B of the chips 2A and 2B is surface-modified.
  • the joint surface 14 of the first substrate 1 is made hydrophilic.
  • the first substrate 1 is held by a spin chuck, and pure water such as DIW (deionized water) is supplied to the joint surface 14 of the first substrate 1 that rotates together with the spin chuck.
  • An OH group is attached to the unbonded hands of Si on the joint surface 14, and the joint surface 14 is made hydrophilic.
  • the bonding surface 14 of the first substrate 1 but also the bonding surfaces 24A and 24B of the chips 2A and 2B may be made hydrophilic. At least one of the bonding surface 14 of the first substrate 1 and the bonding surfaces 24A and 24B of the chips 2A and 2B is hydrophilized.
  • the chips 2A and 2B are temporarily joined to the joint surface 14 of the first substrate 1 one by one.
  • the chips 2A and 2B are joined to the first substrate 1 with the device layers 22A and 22B facing the first substrate 1.
  • Chips 2A and 2B and the first substrate 1 are bonded by van der Waals force (intermolecular force) and hydrogen bonds between OH groups. After that, heat treatment may be carried out in order to increase the bonding strength. The heat treatment causes a dehydration reaction. Since the solids are directly bonded to each other without using a liquid adhesive, it is possible to prevent misalignment due to deformation of the adhesive and inclination due to uneven thickness of the adhesive.
  • the chips 2A and 2B are permanently attached to the third substrate 6 described later without taking the step of temporarily joining the chips 2A and 2B to the first substrate 1. To join. Therefore, it is required at the same time to suppress the biting of air bubbles and foreign substances at the time of joining and to perform the position control with high accuracy.
  • the chips 2A and 2B When the chips 2A and 2B are joined to the third substrate 6 one by one as in Patent Document 1, the chips 2A and 2B may be deformed one by one in order to suppress the biting of air bubbles at the time of joining. ..
  • the bonding surfaces 24A and 24B of the chips 2A and 2B are deformed into a downwardly convex curved surface, gradually bonded to the third substrate 6 from the center toward the peripheral edge, and finally return to a flat surface.
  • Transforming the joint surfaces 24A and 24B of the chips 2A and 2B into a downwardly convex curved surface includes fixing the peripheral edges of the chips 2A and 2B and pushing down the centers of the chips 2A and 2B, respectively.
  • the distance between the fixed portion and the pressed portion is narrow. Therefore, it is difficult to deform the chips 2A and 2B one by one.
  • the chips 2A and 2B are temporarily bonded to the first substrate 1 and later separated from the first substrate 1. Therefore, it does not matter if air bubbles are caught when the chips 2A and 2B are joined to the first substrate 1. Therefore, in S14, the bonding surfaces 24A and 24B of the chips 2A and 2B can be bonded to the bonding surface 14 of the first substrate 1 while remaining flat surfaces. Since the chips 2A and 2B are not deformed, the accuracy of the position control of the chips 2A and 2B can be improved, and the chips 2A and 2B can be accurately placed at the target positions.
  • the chips 2A and 2B are temporarily bonded to the first substrate 1 and later separated from the first substrate 1. Therefore, it does not matter if particles are caught when the chips 2A and 2B are joined to the first substrate 1. Therefore, the bonding surface 14 of the first substrate 1 and the bonding surfaces 24A and 24B of the chips 2A and 2B may be dirty to the extent that they do not interfere with the bonding. The required cleanliness is low.
  • the plurality of chips 2A and 2B are thinned to make the thickness uniform.
  • the alternate long and short dash line shows the state immediately before S2, and the solid line shows the state at the completion of S2.
  • the silicon wafers 21A and 21B are thinned, and the device layers 22A and 22B are not thinned. Thinning includes grinding or laser machining.
  • the bonding layer 3 is formed on the surfaces of the chips 2A and 2B.
  • the bonding layer 3 is an insulating layer such as a silicon oxide layer, and is formed by a CVD method or the like. Since the chips 2A and 2B are arranged at intervals and the lower ground of the bonding layer 3 has irregularities, the surface of the bonding layer 3 also has irregularities.
  • the surface of the bonding layer 3 is flattened. Since the bonding layer 3 is a silicon oxide layer or the like and has high hardness, polishing such as CMP (Chemical Mechanical Polishing) requires time for flattening.
  • CMP Chemical Mechanical Polishing
  • the convex portion 31 of the bonding layer 3 is irradiated with the laser beam LB1.
  • the convex portion 31 absorbs the laser beam LB1 and changes its state from the solid phase to the gas phase and scatters, or scatters in the solid phase.
  • the laser beam LB1 may also irradiate the recess 32 of the bonding layer 3. If the irradiation intensity of the concave portion 32 is lower than the irradiation intensity of the convex portion 31, the surface of the bonding layer 3 can be flattened.
  • the irradiation point of the laser beam LB1 is moved by the galvano scanner or the XY ⁇ stage.
  • the galvano scanner moves the laser beam LB1.
  • the XY ⁇ stage moves the first substrate 1 in the horizontal direction (X-axis direction and Y-axis direction) and rotates it around the vertical axis.
  • the XYZ ⁇ stage may be used instead of the XY ⁇ stage.
  • the surface of the bonding layer 3 is further flattened by CMP or the like. Since the convex portion 31 has been selectively removed before the CMP, the waviness remaining on the surface of the bonding layer 3 after the CMP can be reduced.
  • the chips 2A and 2B are joined to the second substrate 5.
  • the second substrate 5 comes into contact with the flattened surface of the bonding layer 3 and is bonded to the chips 2A and 2B via the bonding layer 3.
  • the second substrate 5 has, for example, a silicon wafer 51 and a bonding layer 53.
  • the bonding layer 53 is an insulating layer such as a silicon oxide layer, like the bonding layer 13 of the first substrate 1, and is formed by a CVD method or the like.
  • At least one of the bonding surface 54 of the second substrate 5 and the bonding surface 34 of the bonding layer 3 may be surface-modified and hydrophilized before bonding.
  • the second substrate 5 and the bonding layer 3 are bonded by van der Waals force (intermolecular force), hydrogen bonds between OH groups, and the like. Since the solids are directly bonded to each other without using a liquid adhesive, it is possible to prevent misalignment due to deformation of the adhesive. In addition, it is possible to prevent the occurrence of inclination due to uneven thickness of the adhesive.
  • the second substrate 5 is joined to the first substrate 1 via the bonding layer 3 with its bonding surface 54 facing downward. That is, the substrates are bonded to each other. At that time, the joint surface 54 of the second substrate 5 is deformed into a downwardly convex curved surface in order to prevent air bubbles from being caught, and is gradually joined from the center to the peripheral edge, and finally returns to a flat surface.
  • the deformation of the second substrate 5 can be realized by fixing the peripheral edge of the second substrate 5 and pressing the center of the second substrate 5.
  • the distance between the fixed portion and the pressed portion is wider than when the chips 2A and 2B are deformed one by one, so that the deformation is easy. Deformation is easy because the substrates are bonded together.
  • the arrangement of the second substrate 5 and the first substrate 1 may be reversed, the second substrate 5 may be arranged below the first substrate 1, and the joint surface 54 of the second substrate 5 may be upward. Good.
  • the joint surface 54 of the second substrate 5 is deformed into an upwardly convex curved surface in order to prevent air bubbles from being caught, and is gradually joined from the center to the peripheral edge, and finally returns to a flat surface.
  • the second substrate 5 is first bent and deformed, but the first substrate 1 is first bent and deformed. May be good. In this case as well, the substrates are bonded to each other. However, it is preferable to hold the first substrate 1 flat and the chips 2A and 2B flat from the viewpoint of protecting the chips 2A and 2B.
  • the chips 2A and 2B are separated from the first substrate 1 as shown in FIGS. 4H, 4I and 4J.
  • S61 of FIG. 3 which is included in S6 of FIG. 1, a plurality of modified layers M are formed by the laser beam LB2 on the dividing surface D where the first substrate 1 is to be divided in the thickness direction, as shown in FIG. 4H. ..
  • the modified layer M is formed in a dot shape, and is formed above, for example, a condensing point or a condensing point.
  • the laser beam LB2 passes through the silicon wafer 11 of the first substrate 1 and forms the modified layer M on the absorption layer 12 of the first substrate 1.
  • the absorption layer 12 is arranged between the silicon wafer 11 and the chips 2A and 2B, and absorbs the laser beam LB2. Since the laser beam LB2 hardly hits the chips 2A and 2B, damage to the chips 2A and 2B can be suppressed.
  • the laser beam LB2 has a wavelength of, for example, 8.8 ⁇ m to 11 ⁇ m so as to pass through the silicon wafer 11 and be absorbed by the absorption layer 12.
  • the light source of the laser beam LB2 is, for example, a CO 2 laser.
  • the wavelength of the CO 2 laser is about 9.3 ⁇ m.
  • the laser beam LB2 is pulse-oscillated.
  • the formation position of the modified layer M is moved by the galvano scanner or the XY ⁇ stage.
  • the galvano scanner moves the laser beam LB2.
  • the XY ⁇ stage moves the first substrate 1 in the horizontal direction (X-axis direction and Y-axis direction) and rotates it around the vertical axis.
  • the XYZ ⁇ stage may be used instead of the XY ⁇ stage.
  • a plurality of modified layers M are formed at intervals in the circumferential direction and the radial direction of the first substrate 1.
  • a crack CR connecting the modified layers M is also formed.
  • the first substrate 1 is divided starting from the modified layer M as shown in FIG. 4I.
  • the upper chuck 131 holds the first substrate 1
  • the lower chuck 132 holds the second substrate 5.
  • the arrangement of the first substrate 1 and the second substrate 5 may be upside down, and the upper chuck 131 may hold the second substrate 5 and the lower chuck 132 may hold the first substrate 1.
  • the crack CR spreads in a plane shape starting from the modified layer M, and the first substrate 1 is divided by the dividing surface D.
  • the upper chuck 131 may be rotated around the vertical axis as the upper chuck 131 is raised.
  • the first substrate 1 can be threaded on the dividing surface D.
  • the lower chuck 132 may be lowered instead of the upper chuck 131 or in addition to the upper chuck 131 being raised. Further, the lower chuck 132 may be rotated about the vertical axis.
  • the chips 2A and 2B are bonded to the single side 64 including the device layer 62 of the third substrate 6 in a state of being bonded to the second substrate 5.
  • the third substrate 6 includes a silicon wafer 61 and a device layer 62.
  • the device layer 62 is formed on the surface of the silicon wafer 61.
  • the device layer 62 includes semiconductor elements, circuits, terminals, and the like, and is electrically connected to the device layers 22A and 22B of the chips 2A and 2B.
  • At least one of the bonding surface 64 of the third substrate 6 and the bonding surfaces 24A and 24B of the chips 2A and 2B may be surface-modified and hydrophilized before bonding.
  • the third substrate 6 and the chips 2A and 2B are joined by van der Waals force (intermolecular force) and hydrogen bonds between OH groups. Since the solids are directly bonded to each other without using a liquid adhesive, it is possible to prevent misalignment due to deformation of the adhesive. In addition, it is possible to prevent the occurrence of inclination due to uneven thickness of the adhesive.
  • the third substrate 6 is bonded to the second substrate 5 via the chips 2A and 2B with its bonding surface 64 facing downward. That is, the substrates are bonded to each other. At that time, the joint surface 64 of the third substrate 6 is deformed into a downwardly convex curved surface in order to prevent air bubbles from being caught, and is gradually joined from the center to the peripheral edge, and finally returns to a flat surface.
  • the deformation of the third substrate 6 can be realized by fixing the peripheral edge of the third substrate 6 and pressing the center of the third substrate 6.
  • the third substrate 6 is deformed, the distance between the fixed portion and the pressed portion is wider than when the chips 2A and 2B are deformed one by one, so that the deformation is easy. Deformation is easy because the substrates are bonded together.
  • the arrangement of the third substrate 6 and the second substrate 5 may be reversed, the third substrate 6 may be arranged below the second substrate 5, and the joint surface 64 of the third substrate 6 may be upward. Good.
  • the joint surface 64 of the third substrate 6 is deformed into an upwardly convex curved surface in order to prevent air bubbles from being caught, is gradually joined from the center to the peripheral edge, and finally returns to a flat surface.
  • the substrates are bonded to each other.
  • the third substrate 6 is first bent and deformed, but the second substrate 5 is first bent and deformed. May be good. In this case as well, the substrates are bonded to each other.
  • the substrate 7 with a chip can be obtained.
  • the chipped substrate 7 includes a third substrate 6 and a plurality of chips 2A and 2B.
  • the substrate 7 with a chip further includes a second substrate 5.
  • the second substrate 5 may be separated from the chips 2A and 2B, and the substrate with a chip 7 may include the third substrate 6 and the chips 2A and 2B.
  • the first substrate is used. Temporarily join to one side of 1. Since the biting of air bubbles at this stage does not matter, the bonding surfaces 24A and 24B of the chips 2A and 2B can be bonded to the bonding surface 14 of the first substrate 1 while remaining flat. Since it is not necessary to forcibly deform the chips 2A and 2B, the accuracy of the position control of the chips 2A and 2B can be improved, and the chips 2A and 2B can be accurately placed at the target positions.
  • the plurality of chips 2A and 2B bonded to the first substrate 1 are bonded to the facing surface of the second substrate 5 with the first substrate 1. Subsequently, the plurality of chips 2A and 2B bonded to the first substrate 1 and the second substrate 5 are separated from the first substrate 1. Next, the plurality of chips 2A and 2B separated from the first substrate 1 are bonded to the single side 64 including the device layer 62 of the third substrate 6 in a state of being bonded to the second substrate 5.
  • the joint surface 64 of the third substrate 6 is deformed into a downwardly convex curved surface in order to prevent air bubbles from being caught, gradually joined from the center to the peripheral edge, and finally returns to a flat surface.
  • Deforming the third substrate 6 is easier than deforming the chips 2A and 2B one by one. This is because the boards are bonded together. Therefore, as compared with the case where the chips 2A and 2B are permanently bonded to the third substrate 6 without taking the step of temporarily bonding the chips 2A and 2B to the first substrate 1 as in Patent Document 1.
  • a substrate 7 with a chip can be obtained, which has no air bubbles and has good position accuracy.
  • the substrate processing apparatus 100 that implements S61 and S62 of FIG. 3 will be described with reference to FIG. 5 and the like.
  • the X-axis direction, the Y-axis direction, and the Z-axis direction are perpendicular to each other
  • the X-axis direction and the Y-axis direction are the horizontal direction
  • the Z-axis direction is the vertical direction.
  • the substrate processing device 100 includes a loading / unloading section 101, a transport section 110, a laser machining section 120, a dividing section 130, and a control section 140.
  • the loading / unloading section 101 has a mounting section 102 on which the cassette C is mounted.
  • the cassette C accommodates a plurality of laminated substrates 8 shown in FIG. 4G and the like at intervals in the vertical direction.
  • the laminated substrate 8 includes a plurality of chips 2A and 2B, a first substrate 1, and a second substrate 5.
  • the laminated substrate 8 is divided into a first divided body 81 and a second divided body 82 on the dividing surface D. After that, the first divided body 81 and the second divided body 82 are separately housed in the cassette C.
  • the first divided body 81 includes the silicon wafer 11, and after being carried out to the outside of the substrate processing apparatus 100, can be reused as a new first substrate 1 again.
  • the second divided body 82 includes the chips 2A and 2B, is carried out to the outside of the substrate processing apparatus 100, and then is provided to S63 in FIG. 3 and S7 in FIG.
  • the number of mounting portions 102 and the number of cassettes C are not limited to those shown in FIG.
  • the transport unit 110 is arranged next to the carry-in / out unit 101, the laser processing unit 120, and the division unit 130, and conveys the laminated substrate 8 and the like to these.
  • the transport unit 110 has a holding mechanism for holding the laminated substrate 8 and the like.
  • the holding mechanism can move in the horizontal direction (both directions in the X-axis direction and the Y-axis direction) and in the vertical direction, and can rotate about the vertical axis.
  • the laser processing unit 120 forms a plurality of modified layers M with the laser beam LB2 on the dividing surface D where the first substrate 1 is to be divided in the thickness direction.
  • the modified layer M is formed in a dot shape, for example, a condensing point or a condensing point above the condensing point.
  • the laser processing unit 120 includes, for example, a stage 121 that holds the first substrate 1 and an optical system 122 that irradiates the first substrate 1 held by the stage 121 with the laser beam LB2.
  • the stage 121 is, for example, an XY ⁇ stage or an XYZ ⁇ stage.
  • the optical system 122 includes, for example, a condenser lens.
  • the condenser lens focuses the laser beam LB2 toward the first substrate 1.
  • the optical system 122 may further include a galvano scanner.
  • the dividing unit 130 divides the first substrate 1 starting from the modified layer M.
  • the dividing portion 130 includes, for example, an upper chuck 131 and a lower chuck 132.
  • the upper chuck 131 holds the first substrate 1, and the lower chuck 132 holds the second substrate 5.
  • the arrangement of the first substrate 1 and the second substrate 5 may be upside down.
  • the crack CR spreads in a plane shape starting from the modified layer M, and the first substrate 1 is divided by the dividing surface D.
  • the laminated substrate 8 is divided into a first divided body 81 and a second divided body 82 on the dividing surface D.
  • the upper chuck 131 may rotate around the vertical axis.
  • the first substrate 1 can be threaded on the dividing surface D.
  • the control unit 140 is, for example, a computer, and includes a CPU (Central Processing Unit) 141 and a storage medium 142 such as a memory, as shown in FIG.
  • the storage medium 142 stores programs that control various processes executed by the substrate processing apparatus 100.
  • the control unit 140 controls the operation of the substrate processing device 100 by causing the CPU 141 to execute the program stored in the storage medium 142.
  • the control unit 140 includes an input interface 143 and an output interface 144.
  • the control unit 140 receives a signal from the outside through the input interface 143 and transmits the signal to the outside through the output interface 144.
  • the above program is stored in, for example, a computer-readable storage medium, and is installed from the storage medium in the storage medium 142 of the control unit 140.
  • Examples of the storage medium that can be read by a computer include a hard disk (HD), a flexible disk (FD), a compact disk (CD), a magnet optical desk (MO), and a memory card.
  • the program may be downloaded from the server via the Internet and installed on the storage medium 142 of the control unit 140.

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  • Power Engineering (AREA)
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  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
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  • Die Bonding (AREA)
PCT/JP2020/033410 2019-10-29 2020-09-03 チップ付き基板の製造方法、及び基板処理装置 Ceased WO2021084902A1 (ja)

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CN202511278398.XA CN121123034A (zh) 2019-10-29 2020-09-03 带芯片基板的制造方法
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KR1020257025004A KR20250121140A (ko) 2019-10-29 2020-09-03 칩 부착 기판의 제조 방법
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CN202080073979.9A CN114586135B (zh) 2019-10-29 2020-09-03 带芯片基板的制造方法和基板处理装置
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TW202135276A (zh) 2021-09-16

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