CN114597138A - 半导体封装的制造方法 - Google Patents

半导体封装的制造方法 Download PDF

Info

Publication number
CN114597138A
CN114597138A CN202011395786.3A CN202011395786A CN114597138A CN 114597138 A CN114597138 A CN 114597138A CN 202011395786 A CN202011395786 A CN 202011395786A CN 114597138 A CN114597138 A CN 114597138A
Authority
CN
China
Prior art keywords
semiconductor
semiconductor elements
substrate
heating
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202011395786.3A
Other languages
English (en)
Inventor
王程麒
廖文祥
陈永一
周鸿昇
郑承恩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Innolux Corp
Original Assignee
Innolux Display Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Innolux Display Corp filed Critical Innolux Display Corp
Priority to CN202011395786.3A priority Critical patent/CN114597138A/zh
Priority to US17/520,599 priority patent/US11769685B2/en
Publication of CN114597138A publication Critical patent/CN114597138A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68354—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13157—Cobalt [Co] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/1317—Zirconium [Zr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13171—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13179—Niobium [Nb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/1318—Molybdenum [Mo] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301—Bonding head
    • H01L2224/75302—Shape
    • H01L2224/7531—Shape of other parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7598—Apparatus for connecting with bump connectors or layer connectors specially adapted for batch processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053—Bonding environment
    • H01L2224/81095—Temperature settings
    • H01L2224/81096—Transient conditions
    • H01L2224/81097—Heating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

本揭露一实施例提供一种半导体封装的制造方法，包括以下步骤。提供多个半导体元件，每一个半导体元件具有至少一个导电凸块。提供基板，基板具有多个导电接垫。提供转移装置。转移装置转移多个半导体元件至基板上。提供加热装置。以及，加热装置加热或加压至少二个半导体元件。于转移多个半导体元件至基板的步骤中，每一个半导体元件的至少一个导电凸块对接至对应的多个导电接垫。

Description

半导体封装的制造方法
技术领域
本揭露的实施例涉及一种封装的制造方法，尤其涉及一种半导体封装的制造方法。
背景技术
随着电子装置的应用持续的增广，显示技术的发展也日新月异。随着不同的制程条件，对于电子装置的封装结构与质量的要求越来越高,进而电子装置面临不同的问题。因此，电子装置的研发须持续更新与调整。
发明内容
本揭露是针对一种半导体封装的制造方法，其可简化制程、减少时间、改善导热性能或提升封装质量。
根据本揭露的实施例，半导体封装的制造方法包括以下步骤。提供多个半导体元件，每一个半导体元件具有至少一个导电凸块。提供基板，基板具有多个导电接垫。提供转移装置。转移装置转移多个半导体元件至基板上。提供加热装置。加热装置加热或加压至少二个半导体元件。于转移多个半导体元件至基板的步骤中，每一个半导体元件的至少一个导电凸块对接至对应的多个导电接垫。
综上所述，在本揭露一实施例的半导体封装的制造方法中，由于可将多个半导体元件转移至基板上，因此可达成在大尺寸的基板上进行巨量转移制程的技术。如此一来，半导体封装的制程可被简化或减少制程时间。此外，于制程中可通过加热装置对多个半导体元件进行加热的步骤或加压的步骤，可进一步简化制程或减少制程时间。另外，相对于在基板设置半导体元件侧的另一侧进行加热，本揭露实施例通过加热装置加热多个半导体元件，可使整体半导体封装的温度升温快或升温均匀度佳，因此可改善制程中的导热性能、减少基板翘曲的机率或提升封装的质量。此外，半导体封装的导电接垫与导电凸块可达成金属-金属对接的效果，以提升半导体封装的电性质量或可靠性。
附图说明
图1至图7为本揭露一实施例的半导体封装的制造流程的剖面示意图；
图8至图9为本揭露另一实施例的半导体封装的制造流程的剖面示意图；
图10为本揭露又一实施例的半导体封装的制造流程的剖面示意图。
具体实施方式
通过参考以下的详细描述并同时结合附图可以理解本揭露，须注意的是，为了使读者能容易了解及为了附图的简洁，本揭露中的多张附图只绘出电子装置的一部分，且附图中的特定元件并非依照实际比例绘图。此外，图中各元件的数量及尺寸仅作为示意，并非用来限制本揭露的范围。
揭露通篇说明书与后附的权利要求中会使用某些词汇来指称特定元件。本领域技术人员应理解，电子设备制造商可能会以不同的名称来指称相同的元件。本文并不意在区分那些功能相同但名称不同的元件。在下文说明书与权利要求中，“包括”、“含有”、“具有”等词为开放式词语，因此其应被解释为“含有但不限定为…”之意。因此，当本揭露的描述中使用术语“包括”、“含有”和/或“具有”时，其指定了相应的特征、区域、步骤、操作和/或构件的存在，但不排除一个或多个相应的特征、区域、步骤、操作和/或构件的存在。
本文中所提到的方向用语，例如：“上”、“下”、“前”、“后”、“左”、“右”等，仅是参考附图的方向。因此，使用的方向用语是用来说明，而并非用来限制本揭露。在附图中，各附图示出的是特定实施例中所使用的方法、结构和/或材料的通常性特征。然而，这些附图不应被解释为界定或限制由这些实施例所涵盖的范围或性质。举例来说，为了清楚起见，各膜层、区域和/或结构的相对尺寸、厚度及位置可能缩小或放大。
应当理解到，当组件或膜层被称为“连接至”另一个组件或膜层时，它可以直接连接到此另一组件或膜层，或者两者之间存在有插入的组件或膜层。当组件被称为“直接连接至”另一个组件或膜层时，两者之间不存在有插入的组件或膜层。另外，当构件被称为“耦接于另一个构件(或其变体)”时，它可以直接地连接到此另一构件，通过一或多个构件间接地连接(例如电性接)到此另一构件。
在本揭露中，长度与宽度的测量方式可以是采用光学显微镜测量而得，厚度则可以由电子显微镜中的剖面图像测量而得，但不以此为限。另外，任两个用来比较的数值或方向，可存在着一定的误差。
术语“大约”、“等于”、“相等”或“相同”、“实质上”或“大致上”一般解释为在所给定的值或范围的20％以内，或解释为在所给定的值或范围的10％、5％、3％、2％、1％或0.5％以内。
本揭露中所叙述之一结构(或层别、组件、基材)位于另一结构(或层别、元件、基材)之上，可以指二结构相邻且直接连接，或是可以指二结构相邻而非直接连接，非直接连接是指二结构之间具有至少一仲介结构(或仲介层别、仲介组件、仲介基材、仲介间隔)，一结构的下侧表面相邻或直接连接于仲介结构的上侧表面，另一结构的上侧表面相邻或直接连接于仲介结构的下侧表面，而仲介结构可以是单层或多层的实体结构或非实体结构所组成，并无限制。在本揭露中，当某结构配置在其它结构“上”时，有可能是指某结构“直接”在其它结构上，或指某结构“间接”在其它结构上，即某结构和其它结构间还夹设有至少一结构。
本揭露说明书内的“第一”、“第二”...等在本文中可以用于描述各种元件、部件、区域、层和/或部分，但是这些元件、部件、区域、和/或部分不应受这些术语的限制。这些术语仅用于将一个元件、部件、区域、层或部分与另一个元件、部件、区域、层或部分区分开。因此，下面讨论的“第一元件”、“部件”、“区域”、“层”、或“部分”是用于与“第二元件”、“部件”、“区域”、“层”、或“部分”区隔，而非用于限定顺序或特定元件、部件、区域、层和/或部分。
电子装置通过本揭露实施例的半导体封装可达到显示效果，其中电子装置可包括显示装置、天线装置、感测装置、拼接装置或透明显示装置，但不以此为限。电子装置可为可卷曲、可拉伸、可弯折或可挠式电子装置。电子装置可例如包括液晶(liquid crystal)、发光二极管(light emitting diode，LED)、量子点(quantum dot，QD)、萤光(fluorescence)、磷光(phosphor)或其他适合的材料且其材料可任意排列组合或其他适合的显示介质，或前述的组合；发光二极管可例如包括有机发光二极管(organic light emitting diode，OLED)、毫米/次毫米发光二极管(mini LED)、微发光二极管(micro LED)或量子点发光二极管(quantum dot，QD，可例如为QLED、QDLED)，但不以此为限。天线装置可例如是液晶天线，但不以此为限。拼接装置可例如是显示器拼接装置或天线拼接装置，但不以此为限。需注意的是，电子装置可为前述之任意排列组合，但不以此为限。此外，电子装置的外型可为矩形、圆形、多边形、具有弯曲边缘的形状或其他适合的形状。电子装置可以具有驱动系统、控制系统、光源系统、层架系统…等周边系统以支援显示装置、天线装置或拼接装置。下文将以半导体封装说明本揭露内容，但本揭露不以此为限。
在本揭露中，以下所述的各种实施例可在不背离本揭露的精神与范围内做混合搭配使用，例如一实施例的部分特征可与另一实施例的部分特征组合而成为另一实施例。
现将详细地参考本发明的示范性实施例，示范性实施例的实例说明于附图中。只要有可能，相同元件符号在附图和描述中用来表示相同或相似部分。
图1至图7为本揭露一实施例的半导体封装的制造流程的剖面示意图。为了附图清楚及方便说明，图1至图7省略示出了若干元件。请先参考图7，本揭露的半导体封装10包括基板200及多个半导体元件300。多个半导体元件300的导电凸块320对接于基板200上的多个导电接垫220。在一些实施例中，半导体封装10可以是晶片级封装(wafer-levelpackage，WLP)或扇出型面板级封装(fan-out panel-level package，FOPLP)，但不以此为限。在上述的设置下，本实施例的半导体封装10的制造方法可以达成在大尺寸面板上进行巨量转移(mass transfer)的制程。另外，在一些实施例中，半导体封装10的制造方法可以简化制程或减少制程时间。在另一些实施例中，半导体封装10的制造方法可以改善导热性能或提升封装的质量。以下将以一实施例对半导体封装10的制造方法简单地进行说明。
请参考图1，半导体封装10的制造方法包括先提供多个半导体元件300。在一些实施例中，多个半导体元件300可由晶片(wafer)单体化出来后，先设置在载板100上。多个半导体元件300可以在X轴方向上设置于载板100上。Z轴垂直于X轴，且可为载板100的法线方向。Y轴垂直于X轴或Z轴。载板100可以是玻璃基板，但不以此为限。在一些实施例中，载板100可以是切割胶带(dicing tape)或管芯黏结薄膜(die attach film，DAF)，但不以此为限。
半导体元件300例如是芯片(chip)。每一个半导体元件300包括主体310以及设置于主体310上的至少一个个导电凸块320。主体310具有主动面(active surface)311及相对于主动面311的被动面(passive surface)312。至少一个导电凸块320例如为多个。多个导电凸块320设置在主动面311上。导电凸块320例如是接垫(pad)、焊球(ball)或受控塌陷芯片连接(controlled collapse chip connection，C4)，但不以此为限。在一些实施例中，导电凸块320可以是单层金属或多层金属的叠层，但不以此为限。导电凸块320的材料可包括钼(molybdenum，Mo)、钽(tantalum，Ta)、铌(niobium，Nb)、铪(hafnium，Hf)、镍(nickel，Ni)、铬(chromium，Cr)、钴(cobalt，Co)、锆(zirconium，Zr)、钨(tungsten，W)、铝(aluminum，Al)、钛(titanium,Ti)、铜(copper，Cu)、其他合适的金属、或上述材料的合金或组合。在一些实施例中，导电凸块320例如是铜金属的凸块。
接着，提供基板200。举例来说，基板200可包括重布线层结构(redistributionlayer，RDL)，重布线层结构(redistribution layer，RDL)包括多层导电层与多层介电层(未示出)在Z轴方向(例如是基板200的法线方向)上交替堆叠。导电层例如为金属层，其材料包括钼、钽、铌、铪、镍、铬、钴、锆、钨、铝、钛、铜、其他合适的金属、或上述材料的合金或组合。导电层例如为单层金属层或为具有多个子金属层堆叠的叠层结构，但不以此为限。介电层的材料可包括感光性聚酰亚胺类材料(photosensitive polyimide)、有机高分子材料、光刻胶材料或其他合适的材料。在一些实施例中，介电层的材料可包括聚碳酸酯(polycarbonate，PC)、聚丙烯(polypropylene，PP)、聚对苯二甲酸乙二酯(polyethyleneterephthalate，PET)、氮化硅、氧化硅或氮氧化硅或其他合适的材料或前述材料的组合，但不以此为限。介电层例如为单层或多层堆叠的叠层结构，但不以此为限。
在一些实施例中，多层介电层可将对应的多层导电层隔离开。多个导电孔(conductive via)可贯穿多层介电层，以耦接对应的多层导电层。在上述的设置下，多层导电层可以彼此电性连接以提供重新分布电路的功能。
在一些实施例中，基板200例如是面板级(panel level)的尺寸。举例来说，基板200的尺寸可为620毫米(mm)x 750毫米(mm)，但不以此为限。也就是说，本揭露的实施例可视为是在大尺寸的基板上进行封装制程。
请再次参考图1，基板200具有多个导电接垫220(pad)。基板200的多个导电接垫220位于基板200的最上层表面，但不以此为限。在一些实施例中，导电接垫220电性连接至基板200的最上层的导电层。也就是说，导电接垫220例如为重布线层结构的最上层接垫，但不以此为限。
请参考图1、图2及图3。接着，提供转移装置400。然后以转移装置400转移多个半导体元件300至基板200上。在上述的转移步骤中，每一个被转移的半导体元件300的至少一个导电凸块320可对接至对应的导电接垫220。
详细来说，以转移装置400转移多个半导体元件300至基板200的步骤包括，以转移装置400接触多个半导体元件300。详细来说，转移装置400包括多个接触头420。接触头420例如为吸头。吸头可为以真空吸引的吸头或为以磁力吸引的吸头。在另一些实施例中，接触头420可为具有黏性的接触头或者是具有静电力的接触头，但不以此为限。在又一些实施例中，提供转移装置400的步骤还包括提供多个转移装置400，但不以此为限。
接着，将多个接触头420移动至多个半导体元件300上，使多个接触头420在Z轴上重叠多个半导体元件300。
然后，在Z轴上移动多个接触头420，使多个接触头420接触或实质接触多个半导体元件300的被动侧312。接着，以多个接触头420分别吸附多个半导体元件300。举例来说，接触头420可以真空吸引的方式吸附半导体元件300。在一些实施例中，接触头420吸附半导体元件300的方式还包括磁力吸引、黏着或静电吸引的方式，但不以此为限。
请参考图2。然后，在Z轴上移动转移装置400，使多个接触头420及其所吸附的多个半导体元件300远离载板100。藉此，可将多个半导体元件300自载板100上剥离。
接着，在X轴上(或垂直于Z轴的任意方向)沿着移动方向M移动转移装置400的多个接触头420，以将多个半导体元件300移动至基板200的上方。在一些实施例中，多个半导体元件300可在Z轴上对应重叠多个导电接垫220。在另一些实施例中，每一个半导体元件300的每一个导电凸块320可在Z轴上对应重叠每一个导电接垫220，但不以此为限。
请参考图3。然后，在Z轴上移动转移装置400，使多个接触头420及其所吸附的多个半导体元件300靠近基板200。多个接触头420将多个半导体元件300对应地接合至基板200上的导电接垫220。
接着，在多个半导体元件300接合至基板200上后，使多个接触头420停止吸附多个半导体元件300。然后，在Z轴上移动转移装置400，使多个接触头420远离基板200。举例来说，停止吸附多个半导体元件300的方法包括，使多个接触头420停止进行真空吸引。在一些实施例中，停止吸附多个半导体元件300的方法还包括：使多个接触头420停止进行磁力吸引或静电吸引，但不以此为限。如此一来，多个接触头420可以自多个半导体元件300上移除。
在另一些实施例中，可以通过基板200与半导体元件300之间的接合力大于接触头420与半导体元件300之间的黏着力，使接触头420往远离基板200的方向移动时，自半导体元件300上分离。
在上述的设置下，本揭露的实施例可达成在大尺寸的基板200上进行巨量转移制程的技术。
请参考图4。接着，使用加热装置500对多个半导体元件300进行加热或加压。在一些实施例中，加热装置500例如是一个或多个加热平板(heating plate)或一个或多加热块(heating block)。加热装置500包括最小加热单元，例如是一个加热平板具有面向基板200的平面501。加热装置500中的加热平板(即最小加热单元)通过平面501接触至少二个半导体元件300的被动面312，以同时对所述至少二个半导体元件300进行加热的步骤或加压的步骤。
在一些实施例中，加热装置500可以分区地进行加热的步骤或加压的步骤。举例来说，基板200可分为多个区域，例如区域21及区域22。区域21与区域22可为相邻的两个区域。多个半导体元件300可设置于区域21中或区域22中。举例来说，如图4所示，至少两个半导体元件300可设置于区域21中，且至少两个半导体元件300可设置于区域22中。在此须注意的是，图4所示的区域21或区域22中的半导体元件300中的数量不旨在限缩本揭露。在一些实施例中，区域21或区域22中的半导体元件300的数量可为三个、四个、五个、十个、数十个或更多个，但不以此为限。另外，区域的数量也不以图4所示的数量为限，在一些实施例中，基板200上所定义的区域可以为三个、四个、五个、十个、数十个或更多个，但不以此为限。
如图4所示，加热装置500可先移动至区域21中的多个半导体元件300的上方，使加热装置500在Z轴上重叠多个半导体元件300。接着，在Z轴上移动加热装置500，使加热装置500靠近基板200。加热装置500的平面501接触多个半导体元件300的被动面312。然后，加热装置500可以升温以对多个半导体元件300进行加热步骤。或者，加热装置500可以施力于多个半导体元件300以对多个半导体元件300进行加压步骤。藉此，半导体封装10的制造方法的制程可被简化或减少制程时间。另外，加热装置500的最小加热单元可同时对多个半导体元件300或至少两个半导体元件300进行加热或加压。相对于在基板200设置半导体元件300侧的另一侧进行加热，通过加热装置500加热多个半导体元件300，可使温度升温快或升温均匀度佳，因此可改善制程中的导热性能、减少基板200翘曲的机率或提升封装的质量。
在一些实施例中，在加热步骤中，多个半导体元件300可被加热装置500加热至25℃至350℃。在另一些实施例中，加热温度的范围可为350℃至550℃，但不以此为限。
在一些实施例中，在加压步骤中，多个半导体元件300可被加热装置500所施加的压力为0.5MPa至40MPa。在另一些实施例中，施加的压力的范围可为40MPa至100MPa，但不以此为限。
在上述的设置下，多个半导体元件300的导电凸块320与所对接的基板200的导电接垫220可以达成金属-金属对接的效果。如此一来，可以提升半导体封装10的电性质量或可靠性。
在一些实施例中，在将多个半导体元件300对应地接合至基板200上的步骤之前，可先选择性地在基板200的多个导电接垫220上设置导电材料(未示出)。导电材料例如为焊料(solder)。接着，进行将多个半导体元件300对应地接合至基板200上的步骤，以及加热的步骤或加压的步骤。由于导电接垫220与导电凸块320之间可设置有焊料，因此加热装置500的加热温度范围可进一步地降低，或加热的温度可实质相似于室温，但不以此为限。或者，加热装置500所施加的压力可进一步地降低。在上述的设置下，可减少半导体元件300受到伤害的机率，进一步提升加热装置500的制程良率或提升加热装置500的质量。
请参考图5及图6。接着，在Z轴上移动加热装置500，使加热装置500远离基板200。
然后，在X轴上移动加热装置500至区域22中的多个半导体元件300的上方，使加热装置500在Z轴上重叠多个半导体元件300。接着，在Z轴上移动加热装置500，使加热装置500靠近基板200。加热装置500的平面501接触多个半导体元件300。然后，加热装置500可以升温以对区域22中的多个半导体元件300进行加热步骤。或者，加热装置500可以施力于多个半导体元件300以对区域22中的多个半导体元件300进行加压步骤。本段所述的加热步骤或加压步骤与先前段落所述的加热步骤或加压步骤类似，故于此不再赘述。在经过加热步骤或加压步骤后，多个半导体元件300的导电凸块320与所对接的导电接垫220可以达成金属-金属对接的效果。如此一来，可以提升半导体封装10的电性质量或可靠性。
在一些实施例中，可接着使用加热装置500对其他区域中的多个半导体300进行加热的步骤或加压的步骤，但不以此为限。
在另一些实施例中，也可以同时提供多个加热装置500对不同区域中的多个半导体300进行加热的步骤或加压的步骤。在又一些实施例中，也可以不进行分区，而对多个加热装置500进行加热的步骤或加压的步骤，本揭露并不予以限制。
请参考图7。在完成加热步骤或加压步骤后，可在Z轴上移动加热装置500，以移除加热装置500。至此，完成半导体封装10的制造。
值得注意的是，本揭露一实施例所示的半导体封装10的制造方法，由于可在面板级的大尺寸的基板200上进行巨量转移制程，因此半导体封装10的制程可被简化或减少制程时间。接着，可通过加热装置500的最小加热单元对多个半导体元件300或至少两个半导体元件300进行加热的步骤或加压的步骤，可简化制程或减少制程时间。另外，相对于在基板200设置半导体元件300侧的另一侧进行加热，本揭露实施例通过加热装置500加热多个半导体元件300，可使整体半导体封装10的温度升温快或升温均匀度佳，因此可改善制程中的导热性能、减少基板200翘曲的机率或提升封装的质量。此外，半导体封装10的导电接垫220与导电凸块320可达成金属-金属对接的效果，以提升半导体封装10的电性质量或可靠性。
以下将列举其他实施例以作为制作方法的说明。在此必须说明的是，下述实施例沿用前述实施例的元件标号与部分内容，其中采用相同的标号来表示相同或近似的元件，并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例，下述实施例不再重复赘述。
图8至图9为本揭露另一实施例的半导体封装的制造流程的剖面示意图。为了附图清楚及方便说明，图8及图9省略示出了若干元件。本实施例所示的制造方法与图1的半导体封装10的制造方法的差异在于，半导体封装10A的制造方法所用的加热装置500A具有多个凹槽520A。举例来说，加热装置500A具有外侧壁510A、外侧壁550A及隔墙530A。外侧壁510A及外侧壁550A分别为加热装置500A的相对两个外缘。外侧壁510A及外侧壁550A之间设置有隔墙530A。外侧壁510A与隔墙530A之间可由加热装置500A位于底部的平面501A连接。外侧壁550A与隔墙530A之间可由加热装置500A位于底部的平面501A连接。在上述的设置下，外侧壁510A、隔墙530A及平面501A可围绕出凹槽520A。外侧壁550A、隔墙530A及平面501A可围绕出凹槽520A。
从另一角度来说，凹槽520A可视为加热装置500A上具有深度的容置空间。举例来说，外侧壁510A具有底面502A。于Z轴上，底面502A与平面501A分别位于不同水平高度上，因而具有高度差。也就是说，凹槽520A的深度可由平面501A与底面502A之间的高度差所定义。
在本实施例中，于Z轴上(例如是俯视方向)，每一个半导体元件300的外轮廓例如是矩形或其他合适的形状。矩形可包括正方形或长方形。也就是说，半导体元件300包括长与宽(图8所示的剖面图示出了半导体元件300的长)。举例来说，半导体元件300的长L1可定义为：在X轴上，主体310的相对两个侧壁303、303’之间的最短距离。类似于半导体元件300的长L1的定义，半导体元件300的宽(图未示)可定义为：在Y轴上，主体310的相对两个侧壁之间的最短距离。
于Z轴上(例如是俯视方向)，每一个凹槽520A的外轮廓例如是矩形或其他合适的形状。矩形可包括正方形或长方形。也就是说，凹槽520A包括长与宽(图8所示的剖面图示出了凹槽520A的长)。在一些实施例中，凹槽520A的外轮廓对应于半导体元件300的外轮廓，但不以此为限。举例来说，凹槽520A的长L2可定义为：在X轴上，外侧壁510A的内缘至侧墙530A靠近外侧壁510A的边之间的最短距离。从另一角度来说，凹槽520A的长L2可定义为：凹槽520A在X轴上延伸的最短距离。类似于凹槽520A的长L2的定义，凹槽520A的宽(图未示)可定义为：在Y轴上，外侧壁的内缘至侧墙靠近外侧壁的边之间的最短距离。或者是，凹槽520A在Y轴上延伸的最短距离。
在一些实施例中，凹槽520A的长L2为所对应的半导体元件300的长L1的105％至115％。也就是说。凹槽520A的长L2大于半导体元件300的长L1。在另一些实施例中，凹槽520A的宽为所对应的半导体元件300的宽的105％至115％。也就是说。凹槽520A的宽大于半导体元件300的宽。也就是说，凹槽520A的面积(例如：长x宽)会大于半导体元件300的面积。如此一来，当凹槽520A在Z轴上重叠半导体元件300时，半导体元件300的外轮廓会位于凹槽520A的外轮廓内。
在上述的设置下，加热装置500A可在区域21中，于Z轴上重叠多个半导体元件300。多个凹槽520A可分别对应重叠多个半导体元件300。
请参考图9。接着，在Z轴上移动加热装置500A，使加热装置500A靠近基板200。多个半导体元件300会分别对位于多个凹槽520A。当加热装置500A的平面501A接触多个半导体元件300的被动面312时，多个半导体元件300会分别对应地容置于多个凹槽520A中。然后，对多个半导体元件300进行加热的步骤或加压的步骤。
在一些实施例中，环绕凹槽520A的外侧壁510A或隔墙530A可以在Z轴上完全覆盖半导体元件300的侧边303。在另一些实施例中，外侧壁510A或隔墙530A可以在Z轴上部分覆盖半导体元件300的侧边303。举例来说，半导体元件300的厚度H1可以大于凹槽520A的深度H2。半导体元件300的厚度H1可定义为：在Z轴上，主体310的最短高度。或者是，在Z轴上，主动面311与被动面312之间的最短距离。凹槽520A的深度H2可定义为：在Z轴上，平面501A与底面502A之间的高度差。或者是，在Z轴上，平面501A与底面502A之间的最短距离。在一些实施例中，凹槽520A的深度H2为半导体元件300的厚度H1的80％至90％。
在其他实施例中，凹槽520A的深度H2也可以大于或等于半导体元件300的厚度H1。在上述的设置下，凹槽520A的深度H2比半导体元件300的厚度H1大，但不以此为限。
接着，在对多个半导体元件300进行加热的步骤中，凹槽520A对容置于凹槽520A中的半导体元件300的侧壁303进行加热。
值得注意的是，本揭露一实施例的半导体封装10A的制造方法，由于多个半导体元件300可在加热装置500A的多个凹槽520A中通过加热装置500A的最小加热单元进行加热，因此外侧壁510A、外侧壁550A或隔墙530A可对多个半导体元件300的侧壁303进行加热。如此一来，本揭露实施例的半导体封装10A的制造方法可以增加对半导体元件300的侧边303的加热效率，可使温度升温快或升温均匀度佳。另外，相对于在基板200设置半导体元件300侧的另一侧进行加热，本揭露实施例通过加热装置500A加热多个半导体元件300，可使整体半导体封装10A的温度升温快或升温均匀度佳。在上述的设置下，可改善半导体封装10A的制程中的导热性能、减少基板200翘曲的机率或提升封装的质量。此外，半导体封装10A的制程可被简化或减少制程时间。另外，半导体封装10A可获致上述的优良技术效果。
在一些实施例中，可接着将加热装置500A移动至区域22中，再使用加热装置500A对区域22中的多个半导体300进行加热的步骤或加压的步骤，但不以此为限。在另一些实施例中，还可接着使用加热装置500A对其他区域中的多个半导体300进行加热的步骤或加压的步骤，但不以此为限。
图10为本揭露又一实施例的半导体封装的制造流程的剖面示意图。为了附图清楚及方便说明，图10省略示出了若干元件。本实施例所示的制造方法与图8或图9的半导体封装10A的制造方法的差异在于，半导体封装10B的制造方法所用的加热装置500B可重叠多个区域。举例来说，加热装置500B可重叠区域21及区域22，且在Z轴上重叠区域21及区域22中的多个半导体元件300。在另一些实施例中，加热装置500B可重叠两个以上的区域。在又一些实施例中，加热装置500B可重叠基板200上的全部区域或整面地重叠基板200，但不以此为限。
如图10所示，加热装置500A具有外侧壁510B、外侧壁550B及多个隔墙530B。外侧壁510B位于重叠区域21的加热装置500A的部分。外侧壁550B位于重叠区域22的加热装置500A的部分。外侧壁510B及外侧壁550A分别为加热装置500B的相对两个外缘。外侧壁510B及外侧壁550B之间设置有多个隔墙530B。外侧壁510B与隔墙530B之间可由加热装置500B位于底部的平面501B连接。外侧壁550B与隔墙530B之间可由加热装置500B位于底部的平面501B连接。多个隔墙530B之间可由平面501B连接。在上述的设置下，外侧壁510B、隔墙530B及平面501B可围绕出凹槽520B。外侧壁550B、隔墙530B及平面501B可围绕出凹槽520B。相邻两个隔墙530B及连接相邻两个隔墙530B的平面501B可围绕出凹槽520B。也就是说，凹槽520B可视为加热装置500B上具有深度的容置空间。
在本实施例中，于Z轴上(例如是俯视方向)，每一个半导体元件300的外轮廓例如是矩形或其他合适的形状。矩形可包括正方形或长方形。每一个凹槽520B的外轮廓例如是矩形或其他合适的形状。矩形可包括正方形或长方形。也就是说，凹槽520B的外轮廓对应于半导体元件300的外轮廓，但不以此为限。在上述的设置下，加热装置500B的多个凹槽520B可在区域21及区域22中，于Z轴上分别对应重叠多个半导体元件300。
如此一来，本揭露一实施例的半导体封装10B的制造方法，由于多个半导体元件300可在加热装置500B的多个凹槽520B中通过加热装置500B的最小加热单元进行加热，因此外侧壁510B、外侧壁550B或隔墙530B可对多个半导体元件300的侧壁进行加热。如此一来，本揭露实施例的半导体封装10B的制造方法可以增加对半导体元件300的侧边的加热效率，可使温度升温快或升温均匀度佳。另外，相对于在基板200设置半导体元件300侧的另一侧进行加热，本揭露实施例通过加热装置500B加热多个半导体元件300，可使整体半导体封装10B的温度升温快或升温均匀度佳。在上述的设置下，可改善半导体封装10B的制程中的导热性能、减少基板200翘曲的机率或提升封装的质量。此外，半导体封装10B的制程可被简化或减少制程时间。另外，半导体封装10A可获致上述的优良技术效果。
另外，加热装置500B可同时重叠多个区域(例如：区域21及区域22)。因此，加热装置500B可同时对多个区域中的多个半导体元件300进行加热的步骤或加压的步骤。在另一些实施例中，加热装置500B可对基板200上的实质全部半导体元件300进行加热的步骤或加压的步骤，但不以此为限。因此，半导体封装10B的制程可被简化或减少制程时间。
综上所述，在本揭露一实施例的半导体封装的制造方法中，由于可将多个半导体元件转移至基板上，因此可达成在大尺寸的基板上进行巨量转移制程的技术。如此一来，半导体封装的制程可被简化或减少制程时间。此外，于制程中可通过加热装置对多个半导体元件进行加热的步骤或加压的步骤，可进一步简化制程或减少制程时间。另外，相对于在基板设置半导体元件侧的另一侧进行加热，本揭露实施例通过加热装置加热多个半导体元件，可使整体半导体封装的温度升温快或升温均匀度佳，因此可改善制程中的导热性能、减少基板翘曲的机率或提升封装的质量。此外，半导体封装的导电接垫与导电凸块可达成金属-金属对接的效果，以提升半导体封装的电性质量或可靠性。
另外，多个半导体元件可在加热装置的多个凹槽中进行加热，因此可对多个半导体元件的侧壁进行加热。如此一来，半导体封装的制造方法可以增加对半导体元件的侧边的加热效率，可使半导体封装整体的温度升温快或升温均匀度佳。在上述的设置下，可改善半导体封装的制程中的导热性能、减少基板翘曲的机率或提升封装的质量。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (10)

1.一种半导体封装的制造方法，其特征在于，包括：
提供多个半导体元件，每一个所述多个半导体元件具有至少一个导电凸块；
提供基板，所述基板具有多个导电接垫；
提供转移装置；
所述转移装置转移所述多个半导体元件至所述基板上；
提供加热装置；以及
所述加热装置加热或加压至少二个所述多个半导体元件，
其中，于转移所述多个半导体元件至所述基板的步骤中，每一个所述多个半导体元件的所述至少一个导电凸块对接至对应的所述多个导电接垫。
2.根据权利要求1所述的半导体封装的制造方法，其特征在于，所述加热装置具有平面，所述加热装置通过所述平面接触所述多个半导体元件，以进行所述加热的步骤或所述加压的步骤。
3.根据权利要求1所述的半导体封装的制造方法，其特征在于，所述加热装置具有多个凹槽，当所述加热装置接触所述多个半导体元件时，所述多个半导体元件对应地容置于所述多个凹槽中，以进行所述加热的步骤或所述加压的步骤。
4.根据权利要求3所述的半导体封装的制造方法，其特征在于，在所述加热的步骤中，所述多个凹槽对容置于所述多个凹槽中的所述多个半导体元件的侧壁进行加热。
5.根据权利要求3所述的半导体封装的制造方法，其特征在于，每一个所述多个凹槽的长为每一个所述多个半导体元件的长的105％至115％，且每一个所述多个凹槽的宽为每一个所述多个半导体元件的宽的105％至115％。
6.根据权利要求3所述的半导体封装的制造方法，其特征在于，每一个所述多个凹槽的深度为每一个所述多个半导体元件的厚度的80％至90％。
7.根据权利要求1所述的半导体封装的制造方法，其特征在于，在所述加热步骤中，将所述多个半导体元件加热至25℃至350℃，或在所加压步骤中，对所述多个半导体元件施加的压力为0.5MPa至40MPa。
8.根据权利要求1所述的半导体封装的制造方法，其特征在于，所述转移装置转移的步骤包括:
所述转移装置包括多个接触头，以所述多个接触头吸附所述多个半导体元件；
移动所述多个接触头，以将所述多个半导体元件移动至所述基板上方；以及
以所述多个接触头将所述多个半导体元件接合至所述基板上的所述多个导电接垫。
9.根据权利要求8所述的半导体封装的制造方法，其特征在于，所述转移装置转移的步骤还包括，在所述多个半导体元件接合至所述基板上之后，将所述多个接触头自所述多个半导体元件上移除。
10.根据权利要求1所述的半导体封装的制造方法，其特征在于，所述加热装置包括最小加热单元，所述最小加热单元同时加热或加压至少二个所述半导体元件。
CN202011395786.3A 2020-12-03 2020-12-03 半导体封装的制造方法 Pending CN114597138A (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202011395786.3A CN114597138A (zh) 2020-12-03 2020-12-03 半导体封装的制造方法
US17/520,599 US11769685B2 (en) 2020-12-03 2021-11-05 Manufacturing method of semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011395786.3A CN114597138A (zh) 2020-12-03 2020-12-03 半导体封装的制造方法

Publications (1)

Publication Number Publication Date
CN114597138A true CN114597138A (zh) 2022-06-07

Family

ID=81812166

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011395786.3A Pending CN114597138A (zh) 2020-12-03 2020-12-03 半导体封装的制造方法

Country Status (2)

Country Link
US (1) US11769685B2 (zh)
CN (1) CN114597138A (zh)

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS532648Y2 (zh) 1973-07-02 1978-01-24
DE60001776T2 (de) * 1999-01-27 2004-02-05 Citizen Watch Co., Ltd. Einkapselungsverfahren einer halbleiteranordnung mit einem anisotropisch leitenden klebstoff
JP4166997B2 (ja) * 2002-03-29 2008-10-15 富士通メディアデバイス株式会社 弾性表面波素子の実装方法及び樹脂封止された弾性表面波素子を有する弾性表面波装置
JP5167779B2 (ja) * 2007-11-16 2013-03-21 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US7854365B2 (en) 2008-10-27 2010-12-21 Asm Assembly Automation Ltd Direct die attach utilizing heated bond head
KR101169001B1 (ko) * 2009-07-10 2012-07-26 주식회사 엔씰텍 증착장치의 증착용 기판, 상기 증착용 기판을 사용한 성막 방법 및 유기전계발광표시장치의 제조방법
US20130140592A1 (en) * 2011-12-01 2013-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Light emitting diode with improved light extraction efficiency and methods of manufacturing same
JP6806774B2 (ja) * 2015-12-07 2021-01-06 グロ アーベーＧｌｏ Ａｂ 基板間ｌｅｄ移送のための、孤立ｉｉｉ族窒化物光アイランド上のレーザリフトオフ
TWI692044B (zh) * 2017-05-29 2020-04-21 日商新川股份有限公司 封裝裝置以及半導體裝置的製造方法
KR102369934B1 (ko) * 2017-06-23 2022-03-03 삼성전자주식회사 칩 실장장치 및 이를 이용한 칩 실장방법
TWI653694B (zh) * 2017-09-13 2019-03-11 英屬開曼群島商錼創科技股份有限公司 微型發光元件陣列製造方法、轉移載板以及微型發光元件陣列
TWI648871B (zh) * 2017-09-22 2019-01-21 台灣愛司帝科技股份有限公司 發光模組的製作方法
KR20210004324A (ko) * 2019-07-04 2021-01-13 삼성전자주식회사 마이크로 led 디스플레이 모듈 및 이를 제조하는 방법
US10818643B1 (en) * 2019-09-23 2020-10-27 Facebook Technologies, Llc Rigid pickup head with conformable layer
TWI770612B (zh) * 2020-09-18 2022-07-11 歆熾電氣技術股份有限公司 晶片移轉系統與晶片移轉方法

Also Published As

Publication number Publication date
US20220181189A1 (en) 2022-06-09
US11769685B2 (en) 2023-09-26

Similar Documents

Publication Publication Date Title
US7285864B2 (en) Stack MCP
US11289633B2 (en) LED array package and manufacturing method thereof
JP2006270046A (ja) 発光ダイオードパッケージ及びその製造方法
US8811031B2 (en) Multichip module and method for manufacturing the same
KR102101760B1 (ko) 반도체 제조 장치, 반도체 장치의 제조 방법 및 콜릿
US10411062B2 (en) Substrate bonding apparatus having adsorption sectors with different vacuum pressures and method of manufacturing semiconductor device using the same
US20190103532A1 (en) Laminating structure of electronic device using transferring element, transferring apparatus for fabricating the electronic device and method for fabricating the electronic device
CN112703596A (zh) 显示器制造中的发光结构对准保持
WO2022114172A1 (ja) Ｌｓｉ素子の熱伝構造及びその熱伝構造を備えるｌｓｉ素子の製造方法
CN114597138A (zh) 半导体封装的制造方法
KR100536823B1 (ko) 열전도성 에폭시 예비성형체를 갖는 실리콘 세그먼트용 수직 상호접속 프로세스
KR20220048018A (ko) 접합 장치, 접합 시스템 및 접합 방법
US20070045864A1 (en) Semiconductor device including a plurality of semiconductor chips stacked three-dimensionally, and method of manufacturing the same
US20160111317A1 (en) Semiconductor manufacturing apparatus
TW201347140A (zh) 多晶片覆晶封裝模組及相關的製造方法
US20230069670A1 (en) Display substrate, tiled display panel and display device
CN114334784A (zh) 显示面板的制备方法、显示面板及显示装置
CN111383953B (zh) 用于制造半导体装置的方法和系统
KR20220112651A (ko) 반도체 디바이스 및 제조 방법
JP2005209829A (ja) 半導体ウェハ固定方法及び装置、並びに半導体ウェハが固定された構造体
US11764077B2 (en) Composite layer circuit element and manufacturing method thereof
US20220216084A1 (en) Method for transferring electronic component
TWI819692B (zh) 電子裝置
CN111952195B (zh) 一种液态微流道互联接口及其焊接工艺
US20220319870A1 (en) Packaging structure radiating electromagnetic waves in horizontal direction and method making the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination