JP7330284B2 - チップ付き基板の製造方法、及び基板処理装置 - Google Patents

チップ付き基板の製造方法、及び基板処理装置 Download PDF

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JP7330284B2
JP7330284B2 JP2021554128A JP2021554128A JP7330284B2 JP 7330284 B2 JP7330284 B2 JP 7330284B2 JP 2021554128 A JP2021554128 A JP 2021554128A JP 2021554128 A JP2021554128 A JP 2021554128A JP 7330284 B2 JP7330284 B2 JP 7330284B2
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substrate
chips
bonding
bonded
chip
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JPWO2021084902A5 (enExample
JPWO2021084902A1 (enExample
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隼斗 田之上
康隆 溝本
陽平 山下
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Tokyo Electron Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67115—Apparatus for thermal treatment mainly by radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H01L21/67721—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations the substrates to be conveyed not being semiconductor wafers or large planar substrates, e.g. chips, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
    • H10P72/0428—
    • H10P72/74—
    • H10P90/1914—
    • H10P95/062—
    • H10W74/019—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H10P72/7408—
    • H10P72/7428—
    • H10P72/7434—
    • H10P72/744—

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Dicing (AREA)
  • Laser Beam Processing (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Die Bonding (AREA)
JP2021554128A 2019-10-29 2020-09-03 チップ付き基板の製造方法、及び基板処理装置 Active JP7330284B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2019196386 2019-10-29
JP2019196386 2019-10-29
PCT/JP2020/033410 WO2021084902A1 (ja) 2019-10-29 2020-09-03 チップ付き基板の製造方法、及び基板処理装置

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JPWO2021084902A1 JPWO2021084902A1 (enExample) 2021-05-06
JPWO2021084902A5 JPWO2021084902A5 (enExample) 2022-06-27
JP7330284B2 true JP7330284B2 (ja) 2023-08-21

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US (1) US20220406603A1 (enExample)
JP (1) JP7330284B2 (enExample)
KR (2) KR20250121140A (enExample)
CN (2) CN114586135B (enExample)
TW (2) TWI874441B (enExample)
WO (1) WO2021084902A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20240016994A (ko) * 2021-06-03 2024-02-06 도쿄엘렉트론가부시키가이샤 기판 처리 방법
WO2023032833A1 (ja) * 2021-09-06 2023-03-09 東京エレクトロン株式会社 基板処理方法及び基板処理装置
US20230343606A1 (en) * 2022-04-22 2023-10-26 Tokyo Electron Limited Method for forming semiconductor packages using dielectric alignment marks and laser liftoff process
US20240178180A1 (en) * 2022-11-30 2024-05-30 Tokyo Electron Limited Systems and methods for bonding semiconductor devices
KR102853614B1 (ko) * 2024-08-07 2025-09-04 (주)에이치아이티에스 칩 본딩 방법

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004288689A (ja) 2003-03-19 2004-10-14 Matsushita Electric Ind Co Ltd 電子部品製造方法および電子部品の集合体の製造方法
JP2015046569A (ja) 2013-07-31 2015-03-12 マイクロン テクノロジー， インク． 半導体装置の製造方法
WO2018003602A1 (ja) 2016-06-28 2018-01-04 リンテック株式会社 整列治具、整列方法及び転着方法
WO2018157937A1 (de) 2017-03-02 2018-09-07 Ev Group E. Thallner Gmbh Verfahren und vorrichtung zum bonden von chips
US20190035688A1 (en) 2017-07-26 2019-01-31 Ultra Display Technology Corp. Method of batch transferring micro semiconductor structures
US20190081200A1 (en) 2017-09-13 2019-03-14 PlayNitride Inc. Method of manufacturing micro light-emitting element array, transfer carrier, and micro light-emitting element array
WO2019098102A1 (ja) 2017-11-16 2019-05-23 リンテック株式会社 半導体装置の製造方法
US20190276308A1 (en) 2016-12-12 2019-09-12 Xiamen San'an Optoelectronics Co., Ltd. Transfer system and transfer method for microelements, manufacturing method for microelement device and microelement device made therefrom, and electronic apparatus including the microelement device

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04340251A (ja) * 1991-02-07 1992-11-26 Fujitsu Ltd 半導体装置の製造方法
JP4389447B2 (ja) * 2003-01-28 2009-12-24 セイコーエプソン株式会社 電気光学装置の製造方法
KR20070018713A (ko) * 2005-08-10 2007-02-14 가부시끼가이샤 르네사스 테크놀로지 반도체 장치의 제조 방법 및 반도체 장치
JP5389490B2 (ja) * 2009-03-23 2014-01-15 東京エレクトロン株式会社 三次元集積回路の製造方法及び装置
JP2011049210A (ja) * 2009-08-25 2011-03-10 Seiko Epson Corp 薄膜素子群の転写方法
WO2012133760A1 (ja) * 2011-03-30 2012-10-04 ボンドテック株式会社 電子部品実装方法、電子部品実装システムおよび基板
JP6008940B2 (ja) * 2012-03-13 2016-10-19 シチズンホールディングス株式会社 半導体発光装置及びその製造方法
JP6145061B2 (ja) * 2014-03-04 2017-06-07 東京エレクトロン株式会社 接合システムおよび接合方法
US10446531B2 (en) * 2014-09-26 2019-10-15 Renesas Electronics Corporation Electronic device and semiconductor device
US10403537B2 (en) * 2017-03-10 2019-09-03 Facebook Technologies, Llc Inorganic light emitting diode (ILED) assembly via direct bonding
JP6973927B2 (ja) * 2017-10-24 2021-12-01 株式会社ディスコ チップの製造方法
US10325791B1 (en) * 2017-12-13 2019-06-18 Facebook Technologies, Llc Formation of elastomeric layer on selective regions of light emitting device
US11227812B2 (en) * 2019-08-28 2022-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package and manufacturing method thereof
US11264343B2 (en) * 2019-08-30 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad structure for semiconductor device and method of forming same
US11557581B2 (en) * 2019-09-23 2023-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same
US12080672B2 (en) * 2019-09-26 2024-09-03 Adeia Semiconductor Bonding Technologies Inc. Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive
US11094672B2 (en) * 2019-09-27 2021-08-17 Intel Corporation Composite IC chips including a chiplet embedded within metallization layers of a host IC chip
US11804469B2 (en) * 2020-05-07 2023-10-31 Invensas Llc Active bridging apparatus
US11631647B2 (en) * 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
CN114597138A (zh) * 2020-12-03 2022-06-07 群创光电股份有限公司 半导体封装的制造方法
US12125820B2 (en) * 2021-02-12 2024-10-22 Taiwan Semiconductor Manufacturing Co., Ltd. Through-dielectric vias for direct connection and method forming same
US11664315B2 (en) * 2021-03-11 2023-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Structure with interconnection die and method of making same
JP2022170858A (ja) * 2021-04-30 2022-11-11 シャープ株式会社 マイクロｌｅｄ実装基板、マイクロｌｅｄディスプレイ及びマイクロｌｅｄ実装基板の製造方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004288689A (ja) 2003-03-19 2004-10-14 Matsushita Electric Ind Co Ltd 電子部品製造方法および電子部品の集合体の製造方法
JP2015046569A (ja) 2013-07-31 2015-03-12 マイクロン テクノロジー， インク． 半導体装置の製造方法
WO2018003602A1 (ja) 2016-06-28 2018-01-04 リンテック株式会社 整列治具、整列方法及び転着方法
US20190276308A1 (en) 2016-12-12 2019-09-12 Xiamen San'an Optoelectronics Co., Ltd. Transfer system and transfer method for microelements, manufacturing method for microelement device and microelement device made therefrom, and electronic apparatus including the microelement device
WO2018157937A1 (de) 2017-03-02 2018-09-07 Ev Group E. Thallner Gmbh Verfahren und vorrichtung zum bonden von chips
US20190035688A1 (en) 2017-07-26 2019-01-31 Ultra Display Technology Corp. Method of batch transferring micro semiconductor structures
US20190081200A1 (en) 2017-09-13 2019-03-14 PlayNitride Inc. Method of manufacturing micro light-emitting element array, transfer carrier, and micro light-emitting element array
WO2019098102A1 (ja) 2017-11-16 2019-05-23 リンテック株式会社 半導体装置の製造方法

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Publication number Publication date
TW202522760A (zh) 2025-06-01
WO2021084902A1 (ja) 2021-05-06
KR20250121140A (ko) 2025-08-11
CN114586135A (zh) 2022-06-03
CN121123034A (zh) 2025-12-12
US20220406603A1 (en) 2022-12-22
KR102839966B1 (ko) 2025-07-29
KR20220091511A (ko) 2022-06-30
JPWO2021084902A1 (enExample) 2021-05-06
CN114586135B (zh) 2025-09-30
TWI874441B (zh) 2025-03-01
TW202135276A (zh) 2021-09-16

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