WO2021083268A1 - 采样时钟相位失配误差估计方法、装置及存储介质 - Google Patents

采样时钟相位失配误差估计方法、装置及存储介质 Download PDF

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WO2021083268A1
WO2021083268A1 PCT/CN2020/124788 CN2020124788W WO2021083268A1 WO 2021083268 A1 WO2021083268 A1 WO 2021083268A1 CN 2020124788 W CN2020124788 W CN 2020124788W WO 2021083268 A1 WO2021083268 A1 WO 2021083268A1
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sampling clock
phase mismatch
clock phase
frequency
mismatch error
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PCT/CN2020/124788
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English (en)
French (fr)
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邬钢
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深圳市中兴微电子技术有限公司
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Priority to US17/772,970 priority Critical patent/US20240162911A1/en
Priority to EP20883198.2A priority patent/EP4068632A4/en
Publication of WO2021083268A1 publication Critical patent/WO2021083268A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
    • H03M1/0604—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H03M1/0607—Offset or drift compensation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0624—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1028—Calibration at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1033—Calibration over the full range of the converter, e.g. for correcting differential non-linearity
    • H03M1/1038—Calibration over the full range of the converter, e.g. for correcting differential non-linearity by storing corrected or correction values in one or more digital look-up tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
    • H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods

Definitions

  • the present disclosure relates to the field of communications, for example, to a method, device and storage medium for estimating phase mismatch error of a sampling clock.
  • Time-interleaved ADC Time-interleaved ADC
  • TIADC Time-interleaved ADC
  • TIADC is composed of multiple sub-ADCs with the same resolution.
  • the multiple sub-ADCs alternately sample and convert the input signal, and finally use a multiplexer (MUX) to alternately output their respective outputs to double the ground Increase the sampling rate.
  • MUX multiplexer
  • M-channel TIADC composed of M parallel sub-ADCs, each sub-ADC has a sampling rate of f S /M, and each sub-ADC passes through its own sample/hold (S/H) circuit in turn
  • S/H sample/hold
  • sampling clock phase mismatch error of multiple channels is fixed. As the frequency of the input signal increases, the final sampling clock phase mismatch error has an increasing impact on the ADC performance, and this change varies with the frequency of the input signal. The characteristic of the change cannot be directly identified from the output result, making its impact on the system performance far greater than the offset error and gain error.
  • the present disclosure provides a sampling clock phase mismatch error estimation method, device, and storage medium to at least solve the problem of the modular subtraction method of sampling clock phase mismatch error estimation. As the number of sub-ADCs increases, the estimation error also increases. The problem becomes bigger.
  • a method for estimating the phase mismatch error of a sampling clock which includes:
  • the slope of the proportional line segment corresponding to the real-time estimated frequency is converted according to the estimated value of the phase mismatch error of the sampling clock obtained by the estimation operator of the modular subtraction method.
  • the offset value corresponding to the real-time estimated frequency is estimated through interpolation, and the actual error value of the phase mismatch of the sampling clock is estimated according to the converted slope and the offset value estimated through the interpolation.
  • a sampling clock phase mismatch error estimation device which includes:
  • the partition module is set to obtain the proportional relationship between the estimation operator of the modulo square subtraction method corresponding to each frequency interval in multiple frequency intervals and the phase mismatch error of the TIADC sampling clock, where the proportional relationship corresponding to each frequency interval is approximately Linear
  • the statistical module is set to count the slope and offset value of the fitting proportional line segment between the actual value of the sampling clock phase mismatch error and the estimated value of the sampling clock phase mismatch error corresponding to the frequency demarcation point of each frequency interval, and Store the slope and offset value of offline statistics, wherein the estimated value of the sampling clock phase mismatch error is determined according to the proportional relationship corresponding to the frequency interval;
  • the estimation module is set to convert the slope of the proportional line segment corresponding to the real-time estimated frequency according to the estimated value of the sampling clock phase mismatch error obtained by the estimation operator of the modular subtraction method in the real-time estimation of the TIADC sampling clock phase mismatch error. Find the slope range corresponding to the slope of the proportional line segment corresponding to the real-time estimated frequency from the slope of the offline statistics, and obtain the offset value of the boundary point of the slope range, and estimate the offset of the real-time estimated frequency through interpolation The actual error value of the phase mismatch of the sampling clock is estimated through the converted slope and the offset value estimated through interpolation.
  • a storage medium is also provided, and a computer program is stored in the storage medium, wherein the computer program is configured to execute the above sampling clock phase mismatch error estimation method during operation.
  • An electronic device including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the above sampling clock phase mismatch error estimation method.
  • Figure 1 is a schematic diagram of a TIADC architecture
  • FIG. 2 is a flowchart of a method for estimating phase mismatch error of a sampling clock according to an embodiment of the present invention
  • Figure 3 is a flow chart of blind adaptive processing provided by an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of the position of a two-channel TIADC clock sampling point provided by an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a sampling clock phase mismatch error estimation device provided by an embodiment of the present invention.
  • FIG. 2 is a flowchart of a sampling clock phase mismatch error estimation method provided by an embodiment of the present invention. As shown in FIG. 2, the process includes the following step:
  • step S202 the proportional relationship between the estimation operator of the modular subtraction method and the phase mismatch error of the TIADC sampling clock is divided into multiple intervals according to frequency, wherein the corresponding proportional relationship in each interval is approximately linear.
  • step S204 the slope and offset value of the corresponding proportional line segment of the actual sampling clock phase mismatch error and the estimated value at the frequency dividing point of each interval are counted offline, and the slope and offset value of the offline statistics are stored.
  • Step S206 In the real-time estimation of the phase mismatch error of the TIADC sampling clock, the slope of the corresponding proportional line segment at the real-time estimated frequency is converted according to the error estimation value obtained by the estimation operator of the modular subtraction method, and the slope of the statistics under the line Find the corresponding slope range in the, and get the offset value of the boundary point of the range, estimate the offset value of the real-time estimated frequency through interpolation, and estimate the sampling clock phase offset through the converted slope and the offset value estimated by the interpolation.
  • the actual error value of the configuration is the slope of the corresponding proportional line segment at the real-time estimated frequency is converted according to the error estimation value obtained by the estimation operator of the modular subtraction method, and the slope of the statistics under the line Find the corresponding slope range in the, and get the offset value of the boundary point of the range, estimate the offset value of the real-time estimated frequency through interpolation, and estimate the sampling clock phase offset through the converted slope and the offset value estimated by the interpolation.
  • step S202 of this embodiment it is assumed that the frequencies corresponding to the multiple dividing points of the (M+1) intervals are: f 0 , f 1 ,..., f i , f i+1 ,..., f M-1 , for the frequency point f i , divide the actual sampling clock phase mismatch error range into 2N equal intervals, and the multiple actual sampling clock phase mismatch error points are: aT s , where T s is the system sampling period, and a is a constant.
  • the estimating operator of modulo subtraction is After statistics, the estimated value of each sampling clock phase mismatch error point is s -N ,s -(N-1) ,...,s -1 ,0,s 1 ,...,s (N-1 ) , s N ; multiple actual sampling clock phase mismatch error points And the corresponding estimated values s -N ,s -(N-1) ,...,s -1 ,0,s 1 ,...,s (N-1) ,s N to do a linear fit to get the frequency the slope at point f i sampling clock phase mismatch error segment k i and the sampling clock phase offset value is a mismatch error when 0 b i; sampling clock phase do the same procedure for the other frequencies, to obtain different frequency loss
  • the slope of the error line segment and the offset value when the sampling clock phase mismatch error is 0; multiple frequency points f 0 , f 1 ,...,f i ,f i+1 ,...,f M-
  • step S206 of this embodiment the slope k of the corresponding proportional line segment at the real-time estimated frequency is converted according to the estimated value obtained by the estimation operator of the modular subtraction method; the obtained slope k is at k 0 , k 1 ,... .,k i ,k i+1 ,...,k M-1 Query to find the corresponding slope range between k i and k i+1 ; the offset value b of the real-time estimated frequency is estimated by the following interpolation :
  • the method may further include: the TIADC sampling the input signal, and calculating the error estimation value by using a modular subtraction method.
  • the method may further include: outputting the estimated actual error value of the phase mismatch of the sampling clock to the compensator for error compensation.
  • the above-mentioned steps solve the problem that in the modular subtraction method of sampling clock phase mismatch error estimation, the estimation error increases as the number of sub-ADCs increases, and the estimation accuracy is improved to improve the estimation accuracy. Satisfy the system's demand for high-speed and high-performance ADC without excessively increasing processing complexity.
  • a new sampling clock phase mismatch error estimation method is provided. As shown in FIG. 3, the method in this embodiment mainly includes the following steps:
  • step S301 the input signal is sampled, and the sampling points are x 1 , x 2 and x 3 , and the first error estimation value is calculated by the modular subtraction method
  • Step S303 output to the compensator for the first error compensation.
  • Step S304 For the compensated sampled signal, the second time error estimation value is calculated by the modular subtraction method
  • Step S308 output to the compensator for the second error compensation.
  • the initial slope and offset of the proportional line segment corresponding to the calculated error value and the actual error value are obtained from offline statistics. As shown in Figure 4, it is necessary to calculate the slope and offset value of each frequency point for a long period of time. Including the following steps:
  • Step S401 Select M frequency points that need to be counted. Assume that the corresponding frequencies of multiple dividing points in (M+1) intervals are: f 0 , f 1 ,..., f i , f i+1 ,... ,f M-1 , the sampling clock phase mismatch error range required by the system [-aT s , aT s ], where T s is the system sampling period, and a is a constant. For each frequency point, the offset values of multiple sampling clock phase mismatch error points are scanned at equal intervals within the sampling clock phase mismatch error range required by the system.
  • step S402 for example, for f i , the actual sampling clock phase mismatch error range is divided into 2N equal intervals, and the multiple actual sampling clock phase mismatch error points are respectively:
  • Step S403 the estimation operator of the subtraction method by modulo square
  • the estimated value of each sampling clock phase mismatch error point is s -N ,s -(N-1) ,...,s -1 ,0,s 1 ,...,s (N- 1) ,s N.
  • Step 404 the multiple actual sampling clock phase mismatch error points And the corresponding estimated value s -N ,s -(N-1) ,...,s -1 ,0,s 1 ,...,s (N-1) ,s N to do linear fitting, you can Obtain the slope k i of the phase mismatch error line segment of the f i down sampling clock and the offset value b i when the phase mismatch error of the sampling clock is 0.
  • step S405 similar operations are performed on other frequency points to obtain the slope of the phase mismatch error line segment of the sampling clock at different frequency points and the offset value when the phase mismatch error of the sampling clock is zero.
  • Step S406 Finally, the slopes k 0 , k 1 ,..., k i corresponding to the multiple frequency points f 0 , f 1 ,...,f i ,f i+1 ,...,f M-1 ,k i+1 ,...,k M-1 and offset values b 0 ,b 1 ,...,b i ,b i+1 ,...,b M-1 are stored.
  • the proportional relationship between the estimation operator of the modular subtraction method and the phase mismatch error of the sampling clock is divided into multiple intervals according to frequency, and the corresponding ratio of each interval is approximately linear.
  • Offline long-term statistics of the actual sampling clock phase mismatch error and the slope and offset value of the estimated value corresponding to the proportional line segment at the frequency demarcation point of each interval and store it for subsequent real-time estimation.
  • real-time estimation In real-time estimation, first convert the slope of the corresponding proportional line segment at the real-time estimation frequency according to the estimated value obtained by the estimation operator of the modular subtraction method, and then find the corresponding slope range from the previously stored slopes, and then obtain the range boundary
  • the offset value of the point is estimated by interpolation to estimate the offset value of the real-time estimated frequency, and finally the actual error value of the phase mismatch of the sampling clock is estimated through the slope and the offset value.
  • the above-mentioned technical solution provided in this embodiment is applicable to scenarios with a large number of sub-ADC channels, and the actual estimated frequency is not limited to a single audio point, but is also applicable to a comprehensive frequency scenario under multiple audio points.
  • ⁇ 2 represents the average power of each sampling point. Assuming that the average power of the sampling point x 1 of channel 1 is the same as the average power of the sampling point x 2 of channel 2, x(t 1 ) represents the sampling at time t 1, T s represents the sampling period. E[x(t 1 +T s + ⁇ )x(t 1 )] is the expectation of the cross-correlation function of adjacent sampling points, denoted as R(T s + ⁇ ),
  • R'(T S + ⁇ ) is the first derivative of R(T s + ⁇ ). From a statistical point of view, when the sample size is large enough, an input frequency R'(T S + ⁇ ) for a TIADC system can be regarded as a certain value. In this way, the metric on the left side of the equation has a fixed proportional relationship with ⁇ , which is the basic estimation operator of the modular subtraction method.
  • the above-mentioned 2-channel TIADC is extended to 8-channel TIADC, with the 0th channel as a reference, the error of the 4th channel is estimated first, and after calibration, Estimate the errors of the 2nd and 6th channels, and finally estimate the errors of the 1st, 3rd, 5th and 7th channels, then the estimation operator of the modular subtraction method can be written as:
  • the input signal frequency cannot be known, and blind adaptive estimation is required. Because of the modular subtraction method of formula (4), although the input signal frequency and the mean value of the error estimate are linearly proportional, the error value cannot be directly obtained. Because the slope of the proportional line segment increases as the frequency increases, and the value of the line segment at different frequencies will be different when there is no error, blind adaptive estimation is required.
  • actual sampling is e.
  • the formula (4) is a linear ratio
  • the estimated value and error value are respectively used as the ordinate and abscissa of the proportional relationship line segment, and the slope of the proportional line segment is set to k and the offset is b.
  • the slope initial value k 0 and the bias initial value b 0 in the first estimation are both statistically and set offline, then the first estimation output actual sampling clock phase mismatch error value is:
  • the slope of the proportional line segment can be obtained through (6) and (7):
  • the actual sampling clock phase mismatch error value in the second error estimation is:
  • the ratio of the estimated operator of the modular subtraction method to the phase mismatch error of the sampling clock is divided into multiple intervals by frequency under the line, and the corresponding ratio of each interval is approximately linear. relationship.
  • the corresponding frequencies of multiple dividing points in (M+1) intervals are: f 0 , f 1 ,...,f i ,f i+1 ,...,f M-1 , the sampling clock required by the system
  • the offset value of each sampling clock phase mismatch error point is scanned at equal intervals within the sampling clock phase mismatch error range required by the system.
  • the actual sampling clock phase mismatch error range is divided into 2N equal intervals, and the multiple actual sampling clock phase mismatch error points are: Estimation operator of subtraction method by modulo square After long-term statistics, the estimated value of each sampling clock phase mismatch error point is s -N ,s -(N-1) ,...,s -1 ,0,s 1 ,...,s (N- 1) ,s N.
  • an 8-way TIADC is taken as an example to evaluate the performance of the method.
  • AWGN Additive White Gaussian Noise
  • the statistical data length is estimated to be 65536*256 sampling points each time, and the running error is estimated to be 8000 times.
  • the bandwidth is scanned from 1MHz to 200MH for the effective number of bits (ENOB) of TIADC. After compensation, many frequency points of the ENOB of the conventional averaging method cannot reach 12 bits, while the ENOB of the segment interpolation method provided by the embodiment of the present invention can be greater than 12 bits, which meets the sampling requirements of the 5G system.
  • the slope and offset of the proportional line segment of the partial frequency points are counted and stored offline.
  • only linear interpolation is used to obtain the real-time slope and offset value. Therefore, the processing is simple and does not cause excessive complexity. increase.
  • the method of the above embodiment can be implemented by software plus a necessary general hardware platform, or by hardware.
  • the technical solution of the present disclosure can be embodied in the form of a software product.
  • the computer software product is stored in a storage medium (such as Read-Only Memory (ROM)/Random Access Memory (RAM)), magnetic Disk, optical disk) includes multiple instructions to enable a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to execute the method described in the embodiment of the present invention.
  • ROM Read-Only Memory
  • RAM Random Access Memory
  • optical disk includes multiple instructions to enable a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to execute the method described in the embodiment of the present invention.
  • a sampling clock phase mismatch error estimation device is also provided.
  • the device is configured to implement the above-mentioned embodiments and implementation modes, and what has been described will not be repeated.
  • the term “module” or “unit” may be a combination of software and/or hardware that implements a predetermined function.
  • FIG. 6 is a structural block diagram of a sampling clock phase mismatch error estimation device provided by an embodiment of the present invention. As shown in FIG. 6, the device includes a partition module 10, a statistics module 20, and an estimation module 30.
  • the partition module 10 is configured to divide the proportional relationship between the estimation operator of the modular subtraction method and the phase mismatch error of the TIADC sampling clock into multiple intervals according to frequency, wherein the corresponding ratio of each interval is approximately linear.
  • the statistics module 20 is configured to count the actual sampling clock phase mismatch error and the slope and offset value of the estimated value corresponding to the proportional line segment under the frequency dividing point of each interval offline, and store the slope and offset value of the offline statistics.
  • the estimation module 30 is configured to calculate the slope of the corresponding proportional line segment at the real-time estimated frequency according to the error estimation value obtained by the estimation operator of the modular subtraction method in the real-time estimation of the TIADC sampling clock phase mismatch error, and perform statistics under the line Find the corresponding slope range from the slope of, and get the offset value of the boundary point of the range, estimate the offset value of the real-time estimated frequency through interpolation, estimate the sampling clock through the converted slope and the offset value estimated by the interpolation The actual error value of the phase mismatch.
  • the partition module 10 further includes: a dividing unit 11, which is set to correspond to frequencies of multiple dividing points in (M+1) intervals: f 0 , f 1 ,..., f i , f i+1 ,...,f M-1 , for the frequency point f i , divide the actual sampling clock phase mismatch error range into 2N equal intervals, and the multiple actual sampling clock phase mismatch error points are: Among them, T s is the system sampling period, and a is a constant.
  • the statistics module 20 includes a statistics unit 21, a fitting unit 22, an acquisition unit 23, and a storage unit 24.
  • the statistical unit 21 is set as an estimation operator based on the modular subtraction method After statistics, the estimated value of each sampling clock phase mismatch error point is s -N ,s -(N-1) ,...,s -1 ,0,s 1 ,...,s (N-1 ) ,s N.
  • the fitting unit 22 is configured to set multiple actual sampling clock phase mismatch error points And the corresponding estimated values s -N ,s -(N-1) ,...,s -1 ,0,s 1 ,...,s (N-1) ,s N to do a linear fit to get the frequency the slope at point f i sampling clock phase mismatch error segment k i and the sampling clock phase mismatch error offset value b i is zero.
  • the acquiring unit 23 is configured to perform the same operation on other frequency points to obtain the slope of the sampling clock phase mismatch error line segment of different frequency points and the offset value when the sampling clock phase mismatch error is zero.
  • the storage unit 24 is set to set the slopes k 0 , k 1 ,..., k corresponding to multiple frequency points f 0 , f 1 ,..., f i , f i+1 ,..., f M-1 i ,k i+1 ,...,k M-1 and offset values b 0 ,b 1 ,...,b i ,b i+1 ,...,b M-1 are stored.
  • the estimation module 30 includes a conversion module 31, a query module 32 and an interpolation module 33.
  • the conversion module 31 is configured to convert the slope k of the corresponding proportional line segment at the real-time estimated frequency according to the estimated value obtained by the estimation operator of the modular subtraction method.
  • the query module 32 is set to query the obtained slope k in k 0 , k 1 ,..., k i , k i+1 ,..., k M-1 to find the corresponding slope range in k i , k between i+1.
  • the interpolation module 33 is configured to estimate the offset value b of the real-time estimated frequency through the following interpolation:
  • the device further includes a sampling module 40 and an output module 50.
  • the sampling module 40 is configured to sample the input signal before converting the slope of the corresponding proportional line segment at the frequency according to the estimated error value, and calculate the estimated error value by using a modular subtraction method.
  • the output module 50 is configured to output the estimated actual error value of the phase mismatch of the sampling clock to the compensator for error compensation.
  • the above-mentioned multiple modules can be implemented by software or hardware. For the latter, it can be implemented in the following manner, but not limited to this: the above-mentioned modules are all located in the same processor; or, the above-mentioned multiple modules are respectively in the form of any combination Located in different processors.
  • the embodiment of the present invention also provides a storage medium in which a computer program is stored, wherein the computer program is configured to execute the steps in any one of the foregoing method embodiments when running.
  • the foregoing storage medium may include, but is not limited to: U disk, ROM, RAM, mobile hard disk, magnetic disk, or optical disk, and other media that can store computer programs.
  • An embodiment of the present invention also provides an electronic device, including a memory and a processor, the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the foregoing method embodiments.
  • the aforementioned electronic device may further include a transmission device and an input-output device, wherein the transmission device is connected to the aforementioned processor, and the input-output device is connected to the aforementioned processor.
  • the above-mentioned multiple modules or multiple steps of the present disclosure can be implemented by a general computing device. They can be concentrated on a single computing device or distributed on a network composed of multiple computing devices. Optionally, they can be It is implemented by the program code executable by the computing device, so that they can be stored in the storage device to be executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than here, Or they can be made into multiple integrated circuit modules respectively, or multiple modules or steps of them can be made into a single integrated circuit module to achieve. In this way, the present disclosure is not limited to any specific combination of hardware and software.

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Abstract

一种采样时钟相位失配误差估计方法、装置及存储介质。该采样时钟相位失配误差估计方法包括：获取多个频率区间中每个频率区间对应的模方相减法的估计算子与TIADC采样时钟相位失配误差之间的比例关系；统计每个频率区间的频率分界点对应的采样时钟相位失配误差实际值和采样时钟相位失配误差估计值之间的拟合比例线段的斜率和偏置值；在TIADC采样时钟相位失配误差实时估计中，根据由模方相减法的估计算子得到的采样时钟相位失配误差估计值折算出实时估计频率对应的比例线段的斜率，根据统计出的斜率和偏置值，通过插值估计出所述实时估计频率对应的偏置值，通过折算出的斜率和通过插值估计出的偏置值估计采样时钟相位失配的实际误差值。

Description

采样时钟相位失配误差估计方法、装置及存储介质
本申请要求在2019年10月31日提交中国专利局、申请号为201911056409.4的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本公开涉及通信领域，例如涉及一种采样时钟相位失配误差估计方法、装置及存储介质。
背景技术
在第五代(5th-Generation，5G)移动通信系统中，系统速率相对4G已经有了极大的提升，相应的基站和终端对于模数转换器(Analog to Digital Converter，ADC)均有更高的性能需求。时间交织ADC(Time-interleaved ADC，TIADC)是高速高性能ADC的主流技术，TIADC通常作为5G系统中ADC的首选。
TIADC由多路具有相同分辨率的子ADC构成，多路子ADC进行交替采样并转换输入信号，最后再用多路选择器(Multiplexer，MUX)将它们各自的输出交替输出，以此来成倍地提高采样率。如图1所示，M个并行子ADC组成的M通道TIADC，每个子ADC的采样率为f S/M，每一个子ADC都通过自己的采保(Sample/Hold，S/H)电路依次对模拟输入信号进行周期性采样，第m个子通道的采样时刻为t m＝nMT s+mT s，其中n＝0,1,2,...，m＝0,1,2,...,M-1，T s为采样周期，然后子ADC的输出结果被MUX进行数据重构，就获得M倍于子ADC采样频率的整体采样频率f s。
由于多通道在版图设计时很难做到完全对称和匹配，在芯片制造过程中由于温度、电压等环境条件的变化，也会造成TIADC的多个子通道之间存在的失配现象。为了实现高速高性能的TIADC，满足5G移动通信系统的ADC需求，必须对这些失配分别进行误差估计和误差补偿，否则会严重影响整体系统的性能。TIADC系统中失配通常包含三种：偏置失配、增益失配、采样时钟相位失配。在三种失配误差中，偏置和增益误差的引入会带来输出信号的规律性变化，而采样时钟相位失配误差主要是由孔径抖动和多个子通道之间的时延不一致造成，即使多个通道的采样时钟相位失配误差都是固定的，随着输入信号频率的增加，最终的采样时钟相位失配误差对ADC性能的影响也在增加，并且这种随着输入信号频率变化而变化的特性无法从输出结果中直接辨认，使得它对系统性能的影响远大于偏置误差和增益误差。
对于采样时钟相位失配误差估计，通常比较实用的是全数字盲自适应的估 计，其中，模方相减法是全数字盲自适应的估计的常用方法，该方法是认为模方相减的估计算子与采样时钟相位失配误差的估计呈现一定的线性比例关系，从中估计出误差值。但是随着子ADC数目增大，这种线性比例就不是非常严格了，估计误差也随之变大。
发明内容
本公开提供了一种采样时钟相位失配误差估计方法、装置及存储介质，以至少解决在采样时钟相位失配误差估计的模方相减法中，随着子ADC数目增大而估计误差也随之变大的问题。
提供了一种采样时钟相位失配误差估计方法，包括：
获取多个频率区间中每个频率区间对应的模方相减法的估计算子与TIADC采样时钟相位失配误差之间的比例关系；
统计每个频率区间的频率分界点对应的采样时钟相位失配误差实际值和采样时钟相位失配误差估计值之间的拟合比例线段的斜率和偏置值，其中，所述采样时钟相位失配误差估计值根据所述频率区间对应的比例关系确定；
在TIADC采样时钟相位失配误差实时估计中，根据由模方相减法的估计算子得到的采样时钟相位失配误差估计值折算出实时估计频率对应的比例线段的斜率，根据统计出的斜率和偏置值，通过插值估计出所述实时估计频率对应的偏置值，并根据折算出的斜率和通过插值估计出的偏置值估计采样时钟相位失配的实际误差值。
还提供了一种采样时钟相位失配误差估计装置，包括：
分区模块，设置为获取多个频率区间中每个频率区间对应的模方相减法的估计算子与TIADC采样时钟相位失配误差之间的比例关系，其中，每个频率区间对应的比例关系近似线性；
统计模块，设置为线下统计每个频率区间的频率分界点对应的采样时钟相位失配误差实际值和采样时钟相位失配误差估计值之间的拟合比例线段的斜率和偏置值，并存储线下统计的斜率和偏置值，其中，所述采样时钟相位失配误差估计值根据所述频率区间对应的比例关系确定；
估计模块，设置为在TIADC采样时钟相位失配误差实时估计中，根据由模方相减法的估计算子得到的采样时钟相位失配误差估计值折算出实时估计频率对应的比例线段的斜率，在所述线下统计的斜率中找到所述实时估计频率对应的比例线段的斜率对应的斜率范围，并得到所述斜率范围分界点的偏置值，通过插值估计出所述实时估计频率的偏置值，通过折算出的斜率和通过插值估计 出的偏置值估计出采样时钟相位失配的实际误差值。
还提供了一种存储介质，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行上述采样时钟相位失配误差估计方法。
还提供了一种电子装置，包括存储器和处理器，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行上述采样时钟相位失配误差估计方法。
附图说明
图1是一种TIADC架构示意图；
图2是本发明实施例提供的一种采样时钟相位失配误差估计方法流程图；
图3是本发明实施例提供的一种盲自适应处理流程图；
图4是本发明实施例提供的一种线下统计斜率和偏置的流程图；
图5是本发明实施例提供的一种两通道TIADC时钟采样点位置示意图；
图6是本发明实施例提供的一种采样时钟相位失配误差估计装置结构示意图。
具体实施方式
下文中将参考附图并结合实施例来说明本公开。
本文中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
在本实施例中提供了一种采样时钟相位失配误差估计方法，图2是本发明实施例提供的一种采样时钟相位失配误差估计方法流程图，如图2所示，该流程包括如下步骤：
步骤S202，将模方相减法的估计算子与TIADC采样时钟相位失配误差对应的比例关系按频率分成多个区间，其中，每个区间的对应比例关系近似线性。
步骤S204，线下统计每个区间的频率分界点下实际采样时钟相位失配误差和估计值的对应比例线段的斜率和偏置值，并存储所述线下统计的斜率和偏置值。
步骤S206，在TIADC采样时钟相位失配误差实时估计中，根据由模方相减法的估计算子得到的误差估计值折算出实时估计频率下对应比例线段的斜率，在所述线下统计的斜率中找到对应的斜率范围，并得到该范围分界点的偏置值，通过插值估计出该实时估计频率的偏置值，通过折算出的斜率和插值估计出的 偏置值估计出采样时钟相位失配的实际误差值。
在本实施例的步骤S202中，假设(M+1)个区间的多个分界点对应的频率为：f 0,f 1,...,f i,f i+1,...,f M-1，对于频点f i，将实际采样时钟相位失配误差范围做2N等间隔划分，多个实际采样时钟相位失配误差点分别为：
Figure PCTCN2020124788-appb-000001
aT s，其中，T s为系统采样周期，a为常数。
在本实施例的步骤S204中，按模方相减法的估计算子
Figure PCTCN2020124788-appb-000002
经过统计得到每个采样时钟相位失配误差点的估计值为s -N,s -(N-1),...,s -1,0,s 1,...,s (N-1),s N；将多个实际采样时钟相位失配误差点
Figure PCTCN2020124788-appb-000003
和对应的估计值s -N,s -(N-1),...,s -1,0,s 1,...,s (N-1),s N做线性拟合，得到频点f i下采样时钟相位失配误差线段的斜率k i以及采样时钟相位失配误差为0时的偏置值b i；对其他频点做同样的操作，得到不同频点的采样时钟相位失配误差线段的斜率以及采样时钟相位失配误差为0时的偏置值；将多个频点f 0,f 1,...,f i,f i+1,...,f M-1对应的斜率k 0,k 1,...,k i,k i+1,...,k M-1和偏置值b 0,b 1,...,b i,b i+1,...,b M-1进行存储。
在本实施例的步骤S206中，根据由模方相减法的估计算子得到的估计值折算出实时估计频率下对应比例线段的斜率k；将得到的斜率k在k 0,k 1,...,k i,k i+1,...,k M-1中查询找到对应的斜率范围位于k i,k i+1之间；通过如下插值估计出该实时估计频率的偏置值b：
Figure PCTCN2020124788-appb-000004
在本实施例的步骤S206之前，还可以包括：所述TIADC对输入信号进行采样，并采用模方相减法计算所述误差估计值。
在本实施例的步骤S206之后，还可以包括：将估计出的采样时钟相位失配的所述实际误差值输出给补偿器进行误差补偿。
在本发明实施例中，通过上述步骤解决了在采样时钟相位失配误差估计的模方相减法中，在随着子ADC数目增大而估计误差也随之变大的问题，提高估计精度以满足系统对ADC的高速高性能的需求，同时不会过大增加处理复杂度。
为了便于对本发明实施例的理解，下面将结合具体应用实施例进行相应的描述。
在本实施例中提供了一种新的采样时钟相位失配误差估计方法，如图3所示，本实施例的方法主要包括如下步骤：
步骤S301，对输入信号进行采样，采样点为x 1、x 2和x 3，采用模方相减法 计算第一次误差估计值
Figure PCTCN2020124788-appb-000005
步骤S302，基于计算误差值和实际误差值对应比例线段的初始斜率k 0和偏置b 0，折算出第一次实际的误差估计值e＝(c 1-b 0)/k 0。
步骤S303，再输出给补偿器进行第一次误差补偿。
步骤S304，对于补偿后的采样信号，采用模方相减法计算第二次误差估计值
Figure PCTCN2020124788-appb-000006
步骤S305，基于估计值计算第二次估计的斜率k＝1-(c 2-b 0)/(c 1-b 0)。
步骤S306，插值计算第二次估计的偏置b＝(b i+1+Ab i)/(1+A)。
步骤S307，折算出第二次实际的误差估计值e＝(c 2-b)/k。
步骤S308，再输出给补偿器进行第二次误差补偿。
计算误差值和实际误差值对应比例线段的初始斜率和偏置由线下统计得到，参见图4所示，需要分段长时间统计每个频点的斜率和偏置值。包括如下步骤：
步骤S401，选择M个需要统计的频点，假设(M+1)个区间的多个分界点对应频率为：f 0,f 1,...,f i,f i+1,...,f M-1，系统所要求的采样时钟相位失配误差范围[-aT s,aT s]，其中，T s为系统采样周期，a为常数。对于每个频点在系统所要求的采样时钟相位失配误差范围内等间隔地扫描统计多个采样时钟相位失配误差点的偏置值。
步骤S402，比如对于f i，将实际采样时钟相位失配误差范围做2N等间隔划分，多个实际采样时钟相位失配误差点分别为：
Figure PCTCN2020124788-appb-000007
步骤S403，按模方相减法的估计算子
Figure PCTCN2020124788-appb-000008
经过长期统计得到每个采样时钟相位失配误差点的估计值为s -N,s -(N-1),...,s -1,0,s 1,...,s (N-1),s N。
步骤404，将多个实际采样时钟相位失配误差点
Figure PCTCN2020124788-appb-000009
和对应的估计值s -N,s -(N-1),...,s -1,0,s 1,...,s (N-1),s N做线性拟合，就可得到f i下采样时钟相位失配误差线段的斜率k i以及采样时钟相位失配误差为0时的偏置值b i。
步骤S405，对其他频点做类似的操作，得到不同频点的采样时钟相位失配误差线段的斜率以及采样时钟相位失配误差为0时的偏置值。
步骤S406，最后将多个频点f 0,f 1,...,f i,f i+1,...,f M-1对应的斜率k 0,k 1,...,k i,k i+1,...,k M-1和偏置值b 0,b 1,...,b i,b i+1,...,b M-1进行存储。
在本实施例中，将模方相减法的估计算子与采样时钟相位失配误差对应的 比例关系按频率分成多个区间，每个区间的对应比例近似线性。线下长时间统计每个区间频率分界点下实际采样时钟相位失配误差和估计值对应比例线段的斜率和偏置值，并进行存储用作后续的实时估计。在实时估计中，先根据由模方相减法的估计算子得到的估计值折算出实时估计频率下对应比例线段的斜率，然后在之前存储的斜率中找到对应的斜率范围，进而得到该范围分界点的偏置值，再通过插值估计出该实时估计频率的偏置值，最后通过斜率和偏置值估计出采样时钟相位失配的实际误差值。
本实施例所提供上述技术方案适用于子ADC通道数目较多的场景，实际估计的频率不限于单音频点，同样适用于多音频点下的综合频率场景。
下面将结合模方相减法及其盲自适应处理，对本实施的具体实施过程进行描述。
一、模方相减法
下面以两通道TIADC为例对模方相减法进行说明，如图5所示，假设系统的偏置失配和增益失配都已校正好，当两个通道之间不存在采样时间相位失配时，通道1和通道2对输入的信号的采样点分别为x 1和x' 2。当系统存在采样时钟相位失配误差Δτ(远小于采样时钟周期T s)时，通道1和通道2的实际采样点是x 1和x 2，图中x 3为通道1下一个周期的采样点。如果以通道1为参考通道，通道2实际的采样时间点x 2偏离了理想采样时间点x' 2大小为Δτ的时间。对于一个幅值随时间变化的输入信号来说，Δτ的存在及大小使得通道2的采样点的值发生了变化。
为了找出Δτ与采样点x 1和x 2的关系，对通道1和通道2的输出分别作差(x 2-x 1)和(x 3-x 2)，对这两项的平方取数学期望，即公式(1)：
Figure PCTCN2020124788-appb-000010
其中，σ 2表示每个采样点的平均功率，假设通道1的采样点x 1的平均功率和通道2的采样点x 2的平均功率相同，x(t 1)表示在t 1时刻的采样，T s表示采样周期。E[x(t 1+T s+Δτ)x(t 1)]是相邻采样点的互相关函数的期望记为R(T s+Δτ)，
则公式(1)可写为：
Figure PCTCN2020124788-appb-000011
同理，
Figure PCTCN2020124788-appb-000012
将公式(2)与(3)相减，当Δτ很小时可将互相关函数用泰勒级数展开， 仅保留一阶求导项，可得到
Figure PCTCN2020124788-appb-000013
其中，R'(T S+Δτ)是R(T s+Δτ)的一阶导数。从统计角度来说，当样本量足够大时，对于一个TIADC系统的一个输入频率R'(T S+Δτ)可看做一个确定值。这样等式左边的度量与Δτ存在固定的比例关系，就是模方相减法的基本估计算子。
在本发明实施例中，以ADC数目较多的多通道场景为例，将上述2通道TIADC扩展到8通道TIADC，以第0路为基准，先估计第4路的误差，进行校准后，再估计第2和第6路的误差，最后估计第1、第3、第5和第7路的误差，那么模方相减法的估计算子可写为：
Figure PCTCN2020124788-appb-000014
二、盲自适应处理
实际的系统中不能知道输入信号频率，需要进行盲自适应估计。因为对公式(4)的模方相减法，虽然输入信号频率和误差估计均值呈线性比例，但是并不能直接得到误差值。因为该比例线段的斜率是随着频率升高而增大的，而且无误差时不同频率下线段的取值也会不同，所以要进行盲自适应估计。
基于模方相减法，假设公式(4)左边经过多次平均后的第1次估计值为c 1＝E[(x 2-x 1) 2]-E[(x 3-x 2) 2]，然后进行第1次补偿，再经过多次平均后的第2次估计值为c 2＝E[(x 2-x 1) 2]-E[(x 3-x 2) 2]，实际采样时钟相位失配误差值为e。如果公式(4)为线性比例，将估计值和误差值分别作为比例关系线段的纵坐标和横坐标，设比例线段斜率为k，偏置为b。对于盲处理，第1次估计中斜率初值k 0和偏置初值b 0都是分别经过线下统计并设置好的，那么第1次估计输出实际采样时钟相位失配误差值为：
e＝(c 1-b 0)/k 0     (6)
将e送入误差估计之后的误差补偿器后进行第1次补偿，因为是流水处理，第1次补偿后接着进行第2次估计输出实际采样时钟相位失配误差值为：
e-c 1＝(c 2-b 0)/k 0     (7)
通过(6)和(7)可以得到比例线段斜率：
k＝1-(c 2-b 0)/(c 1-b 0)      (8)
得到斜率k后，再根据上述步骤S306中的方法得到偏置b，则在第二次的误差估计中实际采样时钟相位失配误差值为：
e＝(c 2-b)/k      (9)
这样就实现了盲自适应估计，输入信号频率未知时也可进行误差估计。之后再进行第二次补偿。然后是通过公式(6)的第三次估计及补偿，和公式(9)的第四次估计和补偿，连续几次操作后误差即可收敛。如果是8路TIADC，将第4路的估计收敛，再进行第2路和第6路的误差估计和补偿，最后进行第1、第3、第5和第7路的误差估计和补偿。
三、斜率和偏置对应关系的统计和设定
如在本实施例的图4中所描述的，线下将模方相减法的估计算子与采样时钟相位失配误差对应的比例按频率分成多个区间，每个区间的对应比例近似为线性关系。假设(M+1)个区间的多个分界点对应频率为：f 0,f 1,...,f i,f i+1,...,f M-1，系统所要求的采样时钟相位失配误差范围[-aT s,aT s]，其中，T s为系统采样周期，a为常数。对于每个频点在系统所要求的采样时钟相位失配误差范围内等间隔地扫描统计每个采样时钟相位失配误差点的偏置值。
比如对于f i，将实际采样时钟相位失配误差范围做2N等间隔划分，多个实际采样时钟相位失配误差点分别为：
Figure PCTCN2020124788-appb-000015
按模方相减法的估计算子
Figure PCTCN2020124788-appb-000016
经过长期统计得到每个采样时钟相位失配误差点的估计值为s -N,s -(N-1),...,s -1,0,s 1,...,s (N-1),s N。将多个实际采样时钟相位失配误差点
Figure PCTCN2020124788-appb-000017
和对应的估计值s -N,s -(N-1),...,s -1,0,s 1,...,s (N-1),s N做线性拟合，就可得到f i下采样时钟相位失配误差线段的斜率k i以及采样时钟相位失配误差为0时的偏置值b i。对其他频点做类似的操作，得到不同频点的采样时钟相位失配误差线段的斜率以及采样时钟相位失配误差为0时的偏置值。最后将多个频点f 0,f 1,...,f i,f i+1,...,f M-1对应的斜率k 0,k 1,...,k i,k i+1,...,k M-1和偏置值b 0,b 1,...,b i,b i+1,...,b M-1进行存储。以上就是线下统计过程。
在实时估计中，由公式(8)得到的k在k 0,k 1,...,k i,k i+1,...,k M-1中查询，假设位于k i,k i+1之间，那么可认为公式(9)所用的偏置b由如下的对应关系：
Figure PCTCN2020124788-appb-000018
上式左边的值为已知，记为A，那么通过公式(10)可以得到偏置b的值为：
b＝(b i+1+Ab i)/(1+A)      (11)
这就是偏置值的插值估计过程。将b代入公式(9)就可得到实际的采样时钟相位失配误差值。
在本实施例中，引入了分段和插值的技术手段，而常规的处理方法是不进行分段的，且对两个端点对应的偏置进行平均作为计算中所要用的偏置值，显然没有本实施例的估计精度高。
在本公开的另一实际应用实施例中，以8路TIADC为例评估该方法的性能。参数设置为：采样速率2GHz、通道数M＝8，偏置失配误差[0 0 0 0 0 0 0 0]，增益失配误差[1 1 1 1 1 1 1 1]，采样时钟相位失配误差[0 0.03 -0.03 0.03 0.03 -0.03 0.03 -0.03]Ts，加性高斯白噪声(Additive White Gaussian Noise，AWGN)信道，信噪比100dB，采用模方相减法来估计采样时钟相位失配误差，每次估计统计数据长度65536*256个采样点，共运行误差估计8000次，带宽从1MHz～200MH之间扫描TIADC的有效位数(Effective Number of Bits，ENOB)。经过补偿，常规平均法的ENOB的很多频点都不能达到12比特(bit)，而本发明实施例提供的分段插值方法的ENOB可做到大于12bit，满足5G系统的采样要求。
本发明实施例是线下统计存储部分频点的比例线段的斜率和偏置，实际估计中只要通过线性插值来得到实时的斜率和偏置值，因此处理简单，不会造成复杂度的过大增加。
通过以上的实施方式的描述，上述实施例的方法可借助软件加必需的通用硬件平台的方式来实现，也可以通过硬件。本公开的技术方案可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如只读存储器(Read-Only Memory，ROM)/随机存取存储器(Random Access Memory，RAM)、磁碟、光盘)中，包括多个指令用以使得一台终端设备(可以是手机，计算机，服务器，或者网络设备等)执行本发明实施例所述的方法。
在本实施例中还提供了一种采样时钟相位失配误差估计装置，该装置设置为实现上述实施例及实施方式，已经进行过说明的不再赘述。如以下所使用的，术语“模块”或“单元”可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的装置以软件来实现，但是硬件，或者软件和硬件的组合的实现也是可能并被构想的。
图6是本发明实施例提供的一种采样时钟相位失配误差估计装置的结构框图，如图6所示，该装置包括分区模块10、统计模块20和估计模块30。
分区模块10设置为将模方相减法的估计算子与TIADC采样时钟相位失配误差对应的比例关系按频率分成多个区间，其中，每个区间的对应比例近似线性。
统计模块20设置为线下统计每个区间频率分界点下实际采样时钟相位失配误差和估计值对应比例线段的斜率和偏置值，并存储所述线下统计的斜率和偏置值。
估计模块30设置为在TIADC采样时钟相位失配误差实时估计中，根据由模方相减法的估计算子得到的误差估计值折算出实时估计频率下对应比例线段的斜率，在所述线下统计的斜率中找到对应的斜率范围，并得到该范围分界点的偏置值，通过插值估计出该实时估计频率的偏置值，通过折算出的斜率和插值估计出的偏置值估计出采样时钟相位失配的实际误差值。
在一实施例中，所述分区模块10还包括：划分单元11，设置为在(M+1)个区间的多个分界点对应频率为：f 0,f 1,...,f i,f i+1,...,f M-1，对于频点f i，将实际采样时钟相位失配误差范围做2N等间隔划分，多个实际采样时钟相位失配误差点分别为：
Figure PCTCN2020124788-appb-000019
其中，T s为系统采样周期，a为常数。
在一实施例中，所述统计模块20包括统计单元21、拟合单元22、获取单元23和存储单元24。
统计单元21设置为于按模方相减法的估计算子
Figure PCTCN2020124788-appb-000020
经过统计得到每个采样时钟相位失配误差点的估计值为s -N,s -(N-1),...,s -1,0,s 1,...,s (N-1),s N。
拟合单元22设置为将多个实际采样时钟相位失配误差点
Figure PCTCN2020124788-appb-000021
和对应的估计值s -N,s -(N-1),...,s -1,0,s 1,...,s (N-1),s N做线性拟合，得到频点f i下采样时钟相位失配误差线段的斜率k i以及采样时钟相位失配误差为0时的偏置值b i。
获取单元23设置为对其他频点做同样的操作，得到不同频点的采样时钟相位失配误差线段的斜率以及采样时钟相位失配误差为0时的偏置值。
存储单元24设置为将多个频点f 0,f 1,...,f i,f i+1,...,f M-1对应的斜率k 0,k 1,...,k i,k i+1,...,k M-1和偏置值b 0,b 1,...,b i,b i+1,...,b M-1进行存储。
在一实施例中，所述估计模块30包括折算模块31、查询模块32和插值模块33。
折算模块31，设置为根据由模方相减法的估计算子得到的估计值折算出实时估计频率下对应比例线段的斜率k。
查询模块32，设置为将得到的斜率k在k 0,k 1,...,k i,k i+1,...,k M-1中查询找到对应的斜率范围位于k i,k i+1之间。
插值模块33，设置为通过如下插值估计出该实时估计频率的偏置值b：
Figure PCTCN2020124788-appb-000022
在一实施例中，该装置还包括采样模块40和输出模块50。
采样模块40，设置为在根据误差估计值折算出该频率下对应比例线段的斜率之前，对输入信号进行采样，并采用模方相减法计算所述误差估计值。
输出模块50，设置为将估计出的采样时钟相位失配的所述实际误差值输出给补偿器进行误差补偿。
上述多个模块是可以通过软件或硬件来实现的，对于后者，可以通过以下方式实现，但不限于此：上述模块均位于同一处理器中；或者，上述多个模块以任意组合的形式分别位于不同的处理器中。
本发明的实施例还提供了一种存储介质，该存储介质中存储有计算机程序，其中，该计算机程序被设置为运行时执行上述任一项方法实施例中的步骤。
可选地，在本实施例中，上述存储介质可以包括但不限于：U盘、ROM、RAM、移动硬盘、磁碟或者光盘等多种可以存储计算机程序的介质。
本发明的实施例还提供了一种电子装置，包括存储器和处理器，该存储器中存储有计算机程序，该处理器被设置为运行计算机程序以执行上述任一项方法实施例中的步骤。
可选地，上述电子装置还可以包括传输设备以及输入输出设备，其中，该传输设备和上述处理器连接，该输入输出设备和上述处理器连接。
上述的本公开的多个模块或多个步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在一些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成多个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本公开不限制于任何特定的硬件和软件结合。

Claims (12)

  1. 一种采样时钟相位失配误差估计方法，包括：
    获取多个频率区间中每个频率区间对应的模方相减法的估计算子与时间交织模数转换器TIADC采样时钟相位失配误差之间的比例关系；
    统计每个频率区间的频率分界点对应的采样时钟相位失配误差实际值和采样时钟相位失配误差估计值之间的拟合比例线段的斜率和偏置值，其中，所述采样时钟相位失配误差估计值根据所述频率区间对应的比例关系确定；
    在TIADC采样时钟相位失配误差实时估计中，根据由模方相减法的估计算子得到的采样时钟相位失配误差估计值折算出实时估计频率对应的比例线段的斜率，根据统计出的斜率和偏置值，通过插值估计出所述实时估计频率对应的偏置值，并根据折算出的斜率和通过插值估计出的偏置值估计采样时钟相位失配的实际误差值。
  2. 根据权利要求1所述的方法，其中，在所述统计每个频率区间的频率分界点对应的采样时钟相位失配误差实际值和采样时钟相位失配误差估计值之间的拟合比例线段的斜率和偏置值之前，还包括：
    针对所述频率分界点，将TIADC实际采样时钟相位失配误差范围按等间隔划分，得到多个采样时钟相位失配误差点对应的实际值。
  3. 根据权利要求2所述的方法，其中，所述统计每个频率区间的频率分界点对应的采样时钟相位失配误差实际值和采样时钟相位失配误差估计值之间的拟合比例线段的斜率和偏置值，包括：
    按模方相减法的估计算子线下统计得到每个采样时钟相位失配误差点对应的估计值；
    将所述多个采样时钟相位失配误差点对应的实际值和估计值做线性拟合，得到所述频率分界点对应的采样时钟相位失配误差线段的斜率和偏置值；
    将所述频率分界点对应的斜率和偏置值进行存储。
  4. 根据权利要求1所述的方法，其中，所述根据统计出的斜率和偏置值，通过插值估计出所述实时估计频率对应的偏置值，包括：
    在所述统计出的斜率中查询所述实时估计频率对应的斜率范围，并根据所述统计出的偏置值得到所述斜率范围分界点的偏置值；
    根据斜率与偏置值之间的线性关系插值估计出所述实时估计频率的偏置值。
  5. 根据权利要求2所述的方法，其中，所述针对所述频率分界点，将TIADC实际采样时钟相位失配误差范围按等间隔划分，，得到多个采样时钟相位失配误差点对应的实际值，包括：
    对于频率分界点f i，将所述TIADC实际采样时钟相位失配误差范围做2N等间隔划分，得到的所述多个采样时钟相位失配误差点对应的实际值分别为：
    Figure PCTCN2020124788-appb-100001
    其中，(M+1)个频率区间的多个频率分界点对应的频率分别为：f 0,f 1,...,f i,f i+1,...,f M-1，T s为系统采样周期，a为常数，M和N均为大于或等于1的正整数，0≤i≤M-1。
  6. 根据权利要求5所述的方法，其中，所述统计每个频率区间的频率分界点对应的采样时钟相位失配误差实际值和采样时钟相位失配误差估计值之间的拟合比例线段的斜率和偏置值，包括：
    按模方相减法的估计算子
    Figure PCTCN2020124788-appb-100002
    经过统计得到每个采样时钟相位失配误差点对应的估计值为s -N,s -(N-1),...,s -1,0,s 1,...,s (N-1),s N；
    将所述多个采样时钟相位失配误差点对应的实际值
    Figure PCTCN2020124788-appb-100003
    和估计值s -N,s -(N-1),...,s -1,0,s 1,...,s (N-1),s N做线性拟合，得到所述频率分界点f i对应的采样时钟相位失配误差线段的斜率k i以及采样时钟相位失配误差为0的情况下的偏置值b i；
    针对其他频率分界点执行与所述频率分界点f i同样的操作，得到不同频率分界点对应的采样时钟相位失配误差线段的斜率以及采样时钟相位失配误差为0的情况下的偏置值；
    对所述多个频率分界点f 0,f 1,...,f i,f i+1,...,f M-1对应的斜率k 0,k 1,...,k i,k i+1,...,k M-1和偏置值b 0,b 1,...,b i,b i+1,...,b M-1进行存储。
  7. 根据权利要求6所述的方法，其中，所述根据由模方相减法的估计算子得到的采样时钟相位失配误差估计值折算出实时估计频率对应的比例线段的斜率，根据统计出的斜率和偏置值，通过插值估计出所述实时估计频率对应的偏置值，包括：
    根据由模方相减法的估计算子得到的采样时钟相位失配误差估计值折算出所述实时估计频率对应的比例线段的斜率k；
    将得到的k在k 0,k 1,...,k i,k i+1,...,k M-1中查询找到k对应的斜率范围位于k i和k i+1之间；
    通过如下插值估计出所述实时估计频率对应的偏置值b：
    Figure PCTCN2020124788-appb-100004
    b＝(b i+1+Ab i)/(1+A)。
  8. 根据权利要求1至7任一项所述的方法，在所述根据折算出的斜率和通 过插值估计出的偏置值估计采样时钟相位失配的实际误差值之后，还包括：
    将估计出的采样时钟相位失配的实际误差值输出给补偿器进行误差补偿。
  9. 根据权利要求1所述的方法，其中，每个频率区间对应的比例关系近似线性。
  10. 一种采样时钟相位失配误差估计装置，包括：
    分区模块，设置为获取多个频率区间中每个频率区间对应的模方相减法的估计算子与时间交织模数转换器TIADC采样时钟相位失配误差之间的比例关系，其中，每个频率区间对应的比例关系近似线性；
    统计模块，设置为线下统计每个频率区间的频率分界点对应的采样时钟相位失配误差实际值和采样时钟相位失配误差估计值之间的拟合比例线段的斜率和偏置值，并存储线下统计的斜率和偏置值，其中，所述采样时钟相位失配误差估计值根据所述频率区间对应的比例关系确定；
    估计模块，设置为在TIADC采样时钟相位失配误差实时估计中，根据由模方相减法的估计算子得到的采样时钟相位失配误差估计值折算出实时估计频率对应的比例线段的斜率，在所述线下统计的斜率中找到所述实时估计频率对应的比例线段的斜率对应的斜率范围，并得到所述斜率范围分界点的偏置值，通过插值估计出所述实时估计频率的偏置值，通过折算出的斜率和通过插值估计出的偏置值估计出采样时钟相位失配的实际误差值。
  11. 一种计算机可读存储介质，存储有计算机程序，其中，所述计算机程序被设置为运行时执行所述权利要求1至9中任一项所述的采样时钟相位失配误差估计方法。
  12. 一种电子装置，包括存储器和处理器，其中，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行所述权利要求1至9中任一项所述的采样时钟相位失配误差估计方法。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113517890A (zh) * 2021-07-21 2021-10-19 电子科技大学 一种用于时间交织adc采样时间失配的提取方法
CN114665876A (zh) * 2022-03-15 2022-06-24 深圳大学 基于数据驱动的多倍集采样时钟失配自适应校准方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113346901B (zh) * 2021-05-28 2024-03-29 中国科学技术大学 一种交替并行采样系统变温条件下修正系数自动适配方法
CN113258930B (zh) * 2021-06-02 2021-09-28 深圳市鼎阳科技股份有限公司 一种数字示波器及时间交织模数转换器的校正方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120326902A1 (en) * 2009-06-26 2012-12-27 Anthony Michael P Background calibration of offsets in interleaved analog to digital converters
CN108809306A (zh) * 2018-06-08 2018-11-13 中国电子科技集团公司第五十八研究所 一种具有失配误差自校准功能的多通道高精度adc电路
CN110113049A (zh) * 2019-04-12 2019-08-09 中国人民解放军国防科技大学 一种双通道tiadc非线性失配自适应估计方法
CN110266311A (zh) * 2019-05-29 2019-09-20 中国科学技术大学 一种tiadc系统失配误差校准方法、装置、设备及介质

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103312329B (zh) * 2013-05-23 2016-08-10 电子科技大学 用于时间交织adc采样时间失配的校正方法及校正器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120326902A1 (en) * 2009-06-26 2012-12-27 Anthony Michael P Background calibration of offsets in interleaved analog to digital converters
CN108809306A (zh) * 2018-06-08 2018-11-13 中国电子科技集团公司第五十八研究所 一种具有失配误差自校准功能的多通道高精度adc电路
CN110113049A (zh) * 2019-04-12 2019-08-09 中国人民解放军国防科技大学 一种双通道tiadc非线性失配自适应估计方法
CN110266311A (zh) * 2019-05-29 2019-09-20 中国科学技术大学 一种tiadc系统失配误差校准方法、装置、设备及介质

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4068632A4

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113517890A (zh) * 2021-07-21 2021-10-19 电子科技大学 一种用于时间交织adc采样时间失配的提取方法
CN114665876A (zh) * 2022-03-15 2022-06-24 深圳大学 基于数据驱动的多倍集采样时钟失配自适应校准方法
CN114665876B (zh) * 2022-03-15 2022-12-27 深圳大学 基于数据驱动的多倍集采样时钟失配自适应校准方法

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