GB2543786A

GB2543786A - Analog assisted multichannel digital post-correction for time-interleaved analog-to-digital converters

Info

Publication number: GB2543786A
Application number: GB1518997.0A
Authority: GB
Inventors: Zhu Anding; Huang Guanzhong
Original assignee: University College Dublin
Current assignee: University College Dublin
Priority date: 2015-10-27
Filing date: 2015-10-27
Publication date: 2017-05-03
Also published as: GB201518997D0

Abstract

A time-interleaved analogue-to-digital converter comprises a set of time-interleaved ADC channels and an additional ADC channel 130 which is clocked at the same rate as the ADC channels but has a sampling instant offset from the sampling instants for those channels. The interleaved and additional channels each comprise a polynomial correction element 120, and the interleaved channels each comprise an FIR filter 125 having inputs from the interleaved channels and the additional channel. The coefficients of the correction elements 120 and the FIR filters 125 may be determined during calibration to reduce the effect of timing skews and mismatches in offset, gain and bandwidth between channels. The additional ADC channel allows the use of shorter FIR filters and enables effective calibration up to the Nyquist frequency. The polynomial correction elements 120 and the FIR filters 125 may comprise a single time-shared element 120 and filter 125.

Description

Title

Analog Assisted Multichannel Digital Post-Correction for Time-Interleaved

Analog-to-Digital converters

Field of the Invention

The present teaching relates analog assisted multichannel digital post correction for time-interleaved analog to digital converters. In particular, the present teaching relates to a time-interleaved ADC and a method calibrating thereof.

Background

The development of advanced digital communication systems continuously drive the demand for high sampling rate of analog-to-digital converters (ADCs). It becomes more and more difficult to achieve satisfying power efficiency of single channel ADC even though technology scaling improves the speed of transistors considerably. Time-interleaved structure uses parallel low sampling rate sub-ADCs to achieve high speed analog-to-digital conversion by multiplexing. At the same time, time-interleaved ADC maintains the high power efficiency of low sampling rate sub-ADC. However, the channel mismatches, including time skew, gain, offset, and sampling bandwidth, could cause severe performance degradation. Therefore, they need to be calibrated. Among them, gain and offset mismatches can be corrected by averaging while time skew and bandwidth mismatches are more challenging to calibrate.

Channel mismatches can be detected and calibrated in analog domain or digital domain. Advanced fabrication technology makes digital processing more preferable than its analog counterpart. Time skew and sampling bandwidth mismatches are easier to process in frequency domain, but it will consumes a lot of power for so large amount of data from parallel ADCs. It is more efficient to do it in time domain.

Time skew mismatch may be detected in digital domain and corrected in analog domain. One way is to compare the relative sampling interval between (current channel - previous channel) and (current channel - next channel). Then adjust the sampling clock delay cell for current channel in the analog domain accordingly until the difference is close to zero. Every channel repeats this process one after another except the first one. An alternative way is to compare the interval of every channel with one additional-sample channel. The time skew can also be corrected by programmable sampling clock delay cell. Both ways need extra circuits and certain digital control logic. It can be a burden when the number of channels is large.

Multichannel digital post correction detects and calibrates the mismatches in digital domain. It collects the digital output of sub-ADCs and feeds to corresponding Finite Impulse Response (FIR) filter. The coefficients of the filters can be extracted by Least Mean Square or Least Square method. However, the performance drops significantly when the analog input frequency approaches Nyquist Rate. This is because M-channel ADC digital output with total data rate at fs can only reconstruct signal lower than the Nyquist Rate. Now that the length of filter is limited, the performance loss near Nyquist Rate is inevitable no matter what model or extraction algorithm is applied.

Figure 1A illustrates a typical parallel structure of time-interleaved ADC 10, where various types of mismatches such as time skew, gain, offset, sampling bandwidth are introduced which degrade the overall linearity. The ADC 10 comprises a plurality of parallel channels ADCo, ADCi ... ADCm-l . The rising edge of sampling clocks, CKo, CKi ... CKM-i, as illustrated in Figure 2 distribute one clock cycle (Ts) in even and control the front end sampling switches. As a result of routing and device mismatch, time skew mismatch is introduced in the format of sampling error, το, τι ... tm-i Conventional multichannel filters approach, shown in Figure IB, combines the samples coming from the M-channel and function as fractional delay filters. This approach suffers from two drawbacks. Firstly, filter length needs to be large enough to achieve satisfying performance, which will become a major issue if the number of channels is large. Secondly, finite filter length inevitably degrades the performance when the input frequency is close to the Nyquist Rate.

There is therefore a need to provide a time-interleaved analog-to-digital converter which addresses at least some of the drawbacks of the prior art.

Summary A digital post-correction circuit for time interleaved ADCs is provided. It is capable of calibrating time skew, gain, offset, and sampling bandwidth mismatches as well as the single channel nonlinearity without any knowledge of the ADC structure. By inserting one additional digital sample, captured by using an additional-sample channel, in the digital calibration mode, this method can effectively correct the mismatches within the whole first Nyquist Zone or the second Nyquist Zone.

In one aspect an analog-to-digital converter (ADC) is provided which comprises; a plurality of time-interleaved ADC channels each including a primary ADC element; at least one correction component in communication with the time-interleaved ADC channels; at least one finite impulse response (FIR) filter in communication with the at least one correction component; and an additional-sample channel having a secondary ADC element; wherein the additional-sample channel outputs an additional sample signal to the at least one FIR filter which is a digital sample of an analog input signal being input to the time-interleaved ADC channels.

In another aspect, a plurality of correction components are provided.

In one aspect, each time-interleaved channel has an associated correction component.

In a further aspect, the additional-sample channel has an associated correction element.

In one aspect a plurality of FIR filters are provided.

In another aspect each time-interleaved channel has an associated FIR filter.

In one exemplary aspect, the additional-sample channel has an associated FIR filter.

In another aspect, a single correction component is provided which is shared by the plurality of the time interleaved ADC channels.

In a further aspect, a single FIR filter is provided.

In one aspect, a first buffer is operably coupled between the single correction component and the single FIR filter.

In another aspect, a second buffer is associated with the additional-sample channel. Advantageously, the second buffer is operably coupled between the second ADC element and the single FIR filter.

In one aspect, the primary ADC element and the secondary ADC element are substantially identical.

In another aspect, each FIR filter includes a plurality of discrete taps for receiving the outputs from the respective time-interleaved ADC channels.

In one aspect, each FIR filter includes an additional-sample tap for receiving the additional-sample signal from the additional-sample channel.

In a further aspect, the primary ADC elements and the secondary ADC element are operated at the same sampling frequency.

In one aspect, each time-interleaved ADC channels has an associated sampling clock signal. Advantageously, the additional-sample channel uses the sampling clock signal of one of the time-interleaved ADC channels with a delay.

In one aspect, the FIR filters are configured to use Voltera series to model channel mismatches.

In another aspect, a series of sine waves spread over the first Nyquist Zone or the seond Nyquist Zone are used to extract the coefficients of the at least one FIR filters.

In a further aspect, the coefficients of the at least one FIR filter are calculated by the Least Square method.

The present disclosure is directed to a method of calibrating a time-interleaved analog-to-digital converter (ADC); the method comprises providing a plurality of time-interleaved ADC channels each including a primary ADC element; providing at least one correction component in communication with the time-interleaved ADC channels; providing at least one finite impulse response (FIR) filter in communication with the at least one correction component; and providing an additional-sample channel having a secondary ADC element; wherein the additional-sample channel outputs an additional sample signal to the at least one FIR filter which is a digital sample of an analog input signal being input to the time-interleaved ADC channels.

Furthermore, the present teaching is directed to a communication system comprising; a plurality of time-interleaved ADC channels each including a primary ADC element; at least one correction component in communication with the time-interleaved ADC channels; at least one finite impulse response (FIR) filter in communication with the at least one correction component; and

an additional-sample channel having a secondary ADC element; wherein the additional-sample channel outputs an additional sample signal to the at least one FIR filter which is a digital sample of an analog input signal being input to the time-interleaved ADC channels.

These and other features will be better understood with reference to the followings Figures which are provided to assist in an understanding of the present teaching.

Brief Description Of The Drawings

The present teaching will now be described with reference to the accompanying drawings in which:

Fig. 1A is a circuit diagram of a time-interleaved ADC.

Fig. IB is a time interleaved ADC wih a prior art multichannel calibration.

Fig. 2 is an illustration of clock signals associated with a time interleaved ADC. Fig. 3 is a time interleaved ADC in accordance with the present teaching.

Fig. 4 illustrates a sampled data pattern from the time interleaved ADC of figure 3.

Fig. 5 illustrates a low cost implementation of the proposed approach with hardware reuse.

Fig. 6A illustrates a simulated plot of SFDR before and after post-correction using the conventional approach.

Fig. 6B illustrates a simulated plot of SNDR before and after post-correction using the conventional approach.

Fig. 7 A illustrates a simulated plot of SFDR before and after post correction using the proposed approach.

Fig. 7B illustrates a simulated plot of SNDR before and after post correction using the proposed approach.

Fig. 8 A illustrates a spectrun plot of the single-tone test without calibration.

Fig. 8B illustrates a spectrun plot of the single-tone test with calibration of the proposed method.

Fig. 9A illustrates a spectrum plot of the two-tone test without calibration.

Fig. 9B illustrates a spectrum plot of the two-tone test with calibration of the proposed method.

Fig. 10 illustrates a simulated plot of SFDR/SNDR versus the sampling interval between the additional-sample channel and the normal channel before and after post correction using the proposed approach.

Fig. 11A illustrates a simulated plot of SFDR before and after post correction using the proposed approach with a double number of interleaved channels in Figs. 6A/6B.

Fig. 1 IB illustrates a simulated plot of SNDR before and after post correction using the proposed approach with a double number of interleaved channels in Figs. 6A/6B.

Detailed Description of the Drawings

The present teaching will now be described with reference to some exemplary time-interleaved ADCs. It will be understood that the exemplary ADCs are provided to assist in an understanding of the present teaching and are not to be construed as limiting in any fashion. Furthermore, circuit elements or components that are described with reference to any one Figure may be interchanged with those of other Figures or other equivalent circuit elements without departing from the spirit of the present teaching.

Referring now to Figure 3 there is provided a time-interleaved ADC 100 in accordance with the present teaching. In the exemplary arrangement the ADC 100 comprises four parallel time interleaved ADC channels. Each channel includes an ADC 110, a correction element 120, and a filter 125. A data sampled pattern from the 4-channel time-interleaved ADC 100 using the digital post-correction method of the present teaching is illustrated in Figure 4. While the ADC 100 includes four channels, it is not intended to limit the present teaching to four channels, as any desired number of channels may be provided as will be appreciated by those skilled in the art. The digital raw output of each channel is processed by a polynomial correction element 120 labelled PLY The polynomial correction element 120 is configured to correct the gain, offset mismatch and single channel nonlinearity with the equation expressed as:

Equation III where S, and d,(n) are the offset and the raw digital output of i-th channel respectively while x,(n) is the output of PLYi. Different from the conventional multichannel filters approach, in the present architecture, an additional-sample channel 130 is provided which captures a single digital sample which is used to calculate the output of filters 125 with the eqution expressed as:

Equation 12)

where xa(n) is the output of the additional-sample channel and Wi(L+1) is its coefficient while Xj(n)=x(i+M n), where M is the interleaving factor. For instance, in Fig. 3, ADCo is collecting sampled data from parallel outputs, i.e., yc)(n-\)=wn(7)xa(n-1 )+vt’o(6)x2(«)+n’()(5)xi(//)+vt’o(4)xo(»)+M’o(3 )X3 («-1 )+ηό(2)χ2(//- 1 )+H’0(l)xi(//-1 )+h’o(0)xo(a?- 1 )+w0(-1 )x3(«-2)+wo(-2)x2(«-2)+wo(-3)xi(«-2)+Wo(-4)xo(«-2)+wo(-5)x3(«-3)+w,,(-6)x2(;/-3). The next channel ADCi collects the same source of parallel data with one cycle delay while the additional channel sample stays the same, i.e., y\(n-1 )=w \(l)xa(n-1 )+w i (6 )x3(//)+w i(5 )x2(//)+H’i(4)Xi(»)+vr ι(3)χ0(//)+ηί(2)χ3(«- 1 )+w ,(l)x2(//-1 )+wi(0)xi(«-1 )+wi(-1 )xo(«-1 )+h’i(-2)X3(;/-2)+h’i(-3)x2(/j-2) l w i(-4)xi(«-2)+wi(-5)x0(/i-2)+wi(-6)x3(«-3). It continues until the next cycle of ADCo, yo(n), that xa(«-l) is shifted to xa(n). In this way, the multichannel part, Wj(j)x(n-j), is updated in fs, and the additional analog-assisted part, w,(Z+l)xa(«), is updated in fs/M. The additional-sample channel 130 comprises a secondary ADC element 126 and is configured to output an additional sample signal to the FIR filters 125 which is a digital sample of an analog input signal being input to the time-interleaved ADC channels.

The extra sample equivalently increases the input data rate of parallel filters from fs to slight oversampling, which makes reconstruction within the Nyquist Rate possible. The sampling rate of the additional-sample channel 130 is the same as that of the time interleaved channels, i.e., fs/M. The delay between the time interleaved channels may be chosen arbitrarily as long as it does not exactly overlap with any one of the other channels. In the exemplary arrangement, the additional-sample channel 130 uses the sampling clock of ADC2 with a delay of Δτ. The length of the digital filters 125 are much shorter than compared to that in the conventional model.

By cascading the polynomial functions (PLY) and the multichannel FIR filters, the digital post-correction method of the present teaching can calibrate all types of mismatches including nonlinearities in each channel. One group of coefficients is extracted in the foreground and may be applied to unknown input signals in normal operation. Reusable digital circuits further improve the power efficiency.

Sine waves of different frequencies are used as input signals for coefficients extraction. With the time-interleaved conversion, the estimated ideal output is calculated as:

Equation f3I where

Equation (4)

And com is the sine wave input frequency. Least Square (LS) is applied to estimate the coefficients as:

Equation (5) where

Equation 16)

The estimated ideal output, LvwxiO^n), is then de-multiplexed to every sub-ADC, as To,A' i(o)m), ..., Lw-i,vxi(<A„)· One set of PLY and FIR coefficients of each channel applies for the first Nyquist Zone. The output of PLYi is calculated as:

Equation (7) where

Equation (81 A series of sine waves with different frequencies, ω\, co2, ..., coK, spread over the first Nyquist Zone serve as the input signal for calibration. If the ADC works in second

Nyquist Zone, the training frequency range should be changed accordingly. Therefore, the estimated coefficients of PLYi can be expressed as:

Equation (9) where

Equation (101

The output of FIRi is:

Equation tilt where

Equation (ID

With the PLY array outputs, the estimated coefficients of FIRi can be written as:

Equation (13) where

Equation (14)

After acquiring cpi and cfi for each channel, the time-interleaved ADC 100 is able to achieve good linearity after the post correction with equation 7 and equation 11 in

cascade for any input within the Nyquist Rate. Previous foreground calibration cannot compensate the frequency dependent mismatches with one set of coefficients as the present method does.

The PLY functions and FIR filters at different channels use the same structure and they are not necessarily operated at the same time. It makes digital hardware reusable, as illustrated in the time-interleaved ADC 200 of Figure 5. One set of PLY and FIR running in fs is enough for four channels with four different sets of coefficients switched in time-interleaved manner. Two First-In-First-Outs (FIFOs) 210, operate as buffers between PLY and FIR array. With the switches set to the state as illustrated in Figure 5, FIR filter generates the corrected output of ADCo, yo(n-1). In the next clock cycle, the data in FIFOl shift to {x3(«), x2(n), ΧιΟή, ΧοΟή, x3(/?-l), x2(n-1), Xi(n-l), x0(n-1), x3(i/-2), x2(n-2), x\(n-2), x0(n-2), x3(«-3)} while FIF02 stays the same. It corresponds to the corrected output of ADCi, y\(n-\). After another three cycles, the data in FIF02 will shift to {xa{n-1)}. As a result, FIFOl runs at fs and FIF02 at fs/4. The number of multipliers is reduced to 1/4.

The simulations described below are built up with four kinds of mismatches and nonlinearities in single channels. The first order RC network is used to model the sampling bandwidth mismatch of each channel. The frequency response can be expressed as:

Equation 1151 where Ri and Q is the on-resistance and sampling capacitance of the i-th channel. As a result, the equivalent time skew and gain mismatches introduced by bandwidth mismatch are both input frequency dependent. The mismatch and nonlinearity parameters of a 12-bit, 4-channel, lGS/s time interleaved ADC are given in TABLE I.

TABLE I

MISMATCH AND NONLINEARITY PARAMETERS

The sampling capacitance of each channel is set to be a constant since the mismatch of on-resistance dominates their product. For comparison, conventional multichannel filters are employed to calibrate the distortion first. The performance of spurious free dynamic range (SFDR) and signal to noise and distortion ratio (SNDR) between before and after post-correction is shown in Figures 6A and 6B. The “training” points, depicted as circles, representing the frequency points that are used for coefficients extraction; the “test” points, depicted as triangles, are the arbitrary input frequencies. The performance degrades when fin approaches the Nyquist Rate. If the training frequencies range from 0 to 0.9*fnyquiSt, as shown in Figure 6, the calibrated performance is good within this region but drops dramatically when fin is over 0.9*fnyquiSt. On the other hand, if the training frequencies cover the first Nyquist Zone, it will smooth the degradation around iJ2, but the overall performance is compromised by around 5dB when fin<fs/4 and more than lOdB when £„>£/4. After the additional-sample channel 130 is used, the performance can be significantly improved, as shown in Figures 7A and 7B. Spectrum plots of the single-tone and two-tone tests are given in Figures 8A-8B and Figure 9A-9B, respectively.

There is no particular requirement for the additional-sample channel 130 on the delay, e g., Δτ, Fig. 4, as long as it does not overlap with the other channels. This can be seen from the results shown in Figure 10. The proposed calibration method also works for larger number of interleaving. An 8-channel ADC with the same sub-channel speed and mismatch level is corrected to good performance as shown in Figures 11A and 1 IB. In this case, the overhead of extra channel becomes smaller.

For system complexity of the digital part, the number of coefficients is smaller because the filter length is shorter compared to that in the conventional approach. For example, in this test, to achieve the same performance, 45 coefficients are required in the conventional model while only 22 coefficients for the proposed model, as given in TABLE II.

TABLE H

NUMBER OF COEFFICIENTS COMPARISON

The advantages of the present teaching are many. In particular, by adding the additional-sample channel 130, the proposed multichannel post-correction can maintain the calibration performance in the full Nyquist Rate. It also consumes less resource in digital domain when achieving the same performance, compared to the conventional multichannel filters approach. Reusing digital hardware can further save resources. Simulation results demonstrated that excellent calibration performance can be achieved by employing the proposed approach.

While the present teaching has been described with reference to exemplary arrangements and circuits it will be understood that it is not intended to limit the teaching of the present teaching to such arrangements as modifications can be made without departing from the spirit and scope of the present invention. It will be appreicated by those skilled in the art that the simulated plots of Figures 6-11 are provided by way of example only and it is not intended to limit the present teaching to the specific illustrated results. In the exemplary arrangement, the FIR filters are configured to use Voltera series to model channel mismatches. A series of sine waves spread over the first Nyquist Zone or the seond Nyquist Zone are used to extract the coefficients of the at least one FIR filters. The coefficients of the at least one FIR filter are calculated by the Least Square method. In this way it will be understood that the present teaching is to be limited only insofar as is deemed necessary in the light of the appended claims.

Similarly the words comprises/comprising when used in the specification are used to specify the presence of stated features, integers, steps or components but do not preclude the presence or addition of one or more additional features, integers, steps, components or groups thereof.

Claims

1. An analog-to-digital converter (ADC) comprising; a plurality of time-interleaved ADC channels each including a primary ADC element; at least one correction component in communication with the time-interleaved ADC channels; at least one finite impulse response (FIR) filter in communication with the at least one correction component; and an additional-sample channel having a secondary ADC element; wherein the additional-sample channel outputs an additional sample signal to the at least one FIR filter which is a digital sample of an analog input signal being input to the time-interleaved ADC channels.

2. An ADC as claimed in claim 1, further comprising a plurality of correction components.

3. An ADC as claimed in claim 2, wherein each time-interleaved channel has an associated correction component.

4. An ADC as claimed in claim 2, wherein the additional-sample channel has an associated correction element.

5. An ADC as claimed in any preceding claim, further comprising a plurality of FIR filters.

6. An ADC as claimed in claim 5, wherein each time-interleaved channel has an associated FIR filter.

7. An ADC as claimed in claim 5, wherein the additional-sample channel has an associated FIR filter.

8. An ADC as claimed in claim 1, wherein a single correction component is provided which is shared by the plurality of the time interleaved ADC channels.

9. An ADC as claimed in claim 8, wherein a single FIR filter is provided.

10. An ADC as claimed in claim 9, wherein a first buffer is operably coupled between the single correction component and the single FIR filter.

11. An ADC as claimed in claim 8, wherein a second buffer is associated with the additional-sample channel.

12. An ADC as claimed in claim 11, where the second buffer is operably coupled between the second ADC element and the single FIR filter.

13. An ADC as claimed in any preceding claim wherein the primary ADC element and the secondary ADC element are substantially identical.

14. An ADC as claimed in claim 5, wherein each FIR filter includes a plurality of discrete taps for receiving the outputs from the respective time-interleaved ADC channels.

15. An ADC as claimed in claim 14, wherein each FIR filter includes an additional-sample tap for receiving the additional sample signal from the additional-sample channel.

16. An ADC as claimed in any preceding claim, wherein the primary ADC elements and the secondary ADC element are operated at the same sampling frequency.

17. An ADC as claimed in claim 16, wherein the additional sample signal leads to equivalently increase in the sampling rate of the respective filters to be above the sampling frequency of the primary ADC elements and the secondary ADC element.

18. An ADC as claimed in any preceding claim, wherein each time-interleaved ADC channels has an associated sampling clock signal.

19. An ADC as claimed in claim 18, wherein the additional-sample channel uses the sampling clock signal of one of the time-interleaved ADC channels with a delay.

20. An ADC as claimed in any preceding claim, wherein the FIR filters are configured to use Voltera series to model channel mismatches.

21. An ADC as claimed in claim 20, wherein a series of sine waves spread over in the first Nyquist Zone or the second Nyquist Zone are used to extract the coefficients of the at least one FIR filters.

22. An ADC as claimed in any preceding claim, wherein the coefficients of the at least one FIR filter are calculated by the Least Square method.

23. A method of calibrating a time-interleaved analog-to-digital converter (ADC), the method comprises providing a plurality of time-interleaved ADC channels each including a primary ADC element; providing at least one correction component in communication with the time-interleaved ADC channels; providing at least one finite impulse response (FIR) filter in communication with the at least one correction component; and providing an additional-sample channel having a secondary ADC element; wherein the additional-sample channel outputs an additional-sample signal to the at least one FIR filter which is a digital sample of an analog input signal being input to the time-interleaved ADC channels.

24. A communication system comprising; a plurality of time-interleaved ADC channels each including a primary ADC element; at least one correction component in communication with the time-interleaved ADC channels; at least one finite impulse response (FIR) filter in communication with the at least one correction component; and an additional-sample channel having a secondary ADC element; wherein the additional-sample channel outputs an additional sample signal to the at least one FIR filter which is a digital sample of an analog input signal being input to the time-interleaved ADC channels.