WO2020205325A1

WO2020205325A1 - Calibrating a time-interleaved analog-to-digital converter

Info

Publication number: WO2020205325A1
Application number: PCT/US2020/024381
Authority: WO
Inventors: Eshel Gordon; Ofir Degani; Elan BANIN; Sarit Zur; Eran Ben AMI
Original assignee: Apple Inc.
Priority date: 2019-03-29
Filing date: 2020-03-24
Publication date: 2020-10-08
Also published as: CN113574803A; CN113574803B

Abstract

Examples relate to an apparatus, a device, a method and a computer program for calibrating a time-interleaved analog-to-digital converter. The apparatus for calibrating a time-inter- leaved analog-to-digital converter comprising a plurality of time-interleaved analog-to-digital converter circuits comprises signal generation circuitry configured to generate a periodic calibration signal for the plurality of time-interleaved analog-to-digital converter circuits, a period of the periodic calibration signal being a multiple of a clock cycle of a clock signal of the analog-to-digital converter. The apparatus comprises processing circuitry configured to ob- tain an output signal of the analog-to-digital converter, the output signal being based on a time-interleaved sampling of the periodic calibration signal by the plurality of time-inter- leaved analog-to-digital converter circuits, the processing circuitry is configured to compare sampling values of one or more pre-defmed portions of the periodic calibration signal originating from different analog-to-digital converter circuits of the plurality of time-interleaved analog-to-digital converter circuits. The processing circuitry is configured to determine a skew of the plurality of time-interleaved analog-to-digital converter circuits based on the comparison of the sampling values.

Description

Calibrating a Time-Interleaved Analog-to-Digital Converter

Field

Examples relate to an apparatus, a device, a method and a computer program for calibrating a time-interleaved analog-to-digital converter.

Background

A TI-ADC (Time-Interleaved Analog-to-Digital Converter) employs several lower speed sub- ADCs operating in parallel in order to achieve a desired aggregate sampling rate. Thus, each sub-ADC may operate at a lower speed compared to when a single ADC is used. TI-ADCs may suffer from timing skew (also known as timing mismatch), e.g., random delays in the clock phases of the individual sub-ADCs. This may cause severe performance degradation.

Description of the Figures

Some examples of apparatuses and/or methods will be described in the following by way of example only, and with reference to the accompanying figures, in which

Fig. 1 shows an example test signal generated for a 4-slice (4x) TI-ADC according to various aspects of the disclosure;

Fig. 2 shows a measurement of 4x-TI ADC before and after time skew calibration according to various aspects of the disclosure;

Fig. 3 shows two exemplary implementations of signal generation circuitry for generating a test signal according to various aspects of the disclosure;

Fig. 4 shows an example of 20 samples arranged in a matrix according to various aspects of the disclosure; Fig. 5 shows an example of an estimation of a test signal value in which averaging is per formed over columns of a matrix;

Fig. 6 shows an example of an error matrix calculation according to various aspects of the disclosure; and

Fig. 7 shows an example of a slope calculation according to various aspects of the disclosure.

Detailed Description

Various examples will now be described more fully with reference to the accompanying draw ings in which some examples are illustrated. In the figures, the thicknesses of lines, layers and/or regions may be exaggerated for clarity.

Accordingly, while further examples are capable of various modifications and alternative forms, some particular examples thereof are shown in the figures and will subsequently be described in detail. However, this detailed description does not limit further examples to the particular forms described. Further examples may cover all modifications, equivalents, and alternatives falling within the scope of the disclosure. Same or like numbers refer to like or similar elements throughout the description of the figures, which may be implemented iden tically or in modified form when compared to one another while providing for the same or a similar functionality.

It will be understood that when an element is referred to as being“connected” or“coupled” to another element, the elements may be directly connected or coupled or via one or more intervening elements. If two elements A and B are combined using an“or”, this is to be un derstood to disclose all possible combinations, i.e. only A, only B as well as A and B, if not explicitly or implicitly defined otherwise. An alternative wording for the same combinations is“at least one of A and B” or“A and/or B”. The same applies, mutatis mutandis, for combi nations of more than two Elements.

The terminology used herein for the purpose of describing particular examples is not intended to be limiting for further examples. Whenever a singular form such as“a,”“an” and“the” is used and using only a single element is neither explicitly or implicitly defined as being man datory, further examples may also use plural elements to implement the same functionality. Likewise, when a functionality is subsequently described as being implemented using multi ple elements, further examples may implement the same functionality using a single element or processing entity. It will be further understood that the terms“comprises,”“comprising,” “includes” and/or“including,” when used, specify the presence of the stated features, integers, steps, operations, processes, acts, elements and/or components, but do not preclude the pres ence or addition of one or more other features, integers, steps, operations, processes, acts, elements, components and/or any group thereof.

Unless otherwise defined, all terms (including technical and scientific terms) are used herein in their ordinary meaning of the art to which the examples belong.

Examples provide an apparatus for calibrating a time-interleaved analog-to-digital converter comprising a plurality of time-interleaved analog-to-digital converter circuits. The apparatus comprises signal generation circuitry configured to generate a periodic calibration signal for the plurality of time-interleaved analog-to-digital converter circuits. A period of the periodic calibration signal is a multiple of a clock cycle of the clock signal of the analog-to-digital converter. The apparatus comprises processing circuitry configured to obtain an output signal of the analog-to-digital converter, the output signal being based on a time-interleaved sam pling of the periodic calibration signal by the plurality of time-interleaved analog-to-digital converter circuits. The processing circuitry is configured to compare sampling values of one or more pre-defmed portions (e.g. of a plurality of pre-defmed portions) of the periodic cali bration signal originating from different analog-to-digital converter circuits of the plurality of time-interleaved analog-to-digital converter circuits. The processing circuitry is configured to determine a skew of the plurality of time-interleaved analog-to-digital converter circuits based on the comparison of the sampling values.

In at least some examples, the multiple is unequal to a number of time-interleaved analog-to- digital converter circuits of the plurality of time-interleaved analog-to-digital converter cir cuits. For example, the periodic calibration signal may have a period equal to R clock cycles, wherein the plurality of time-interleaved analog-to-digital converter circuits comprise Ns time-interleaved analog-to-digital converter circuits. R and Ns may be co-prime numbers. This may enable each time-interleaved analog-to-digital converter circuit to sample each pre defined portion of the periodic calibration signal.

In at least some examples, the processing circuitry is configured to determine an average sampling value for each of the one or more pre-defmed portions of the periodic calibration signal. The skew of the plurality of time-interleaved analog-to-digital converter circuits may be based on a deviation of the sampling values of the one or more pre-defmed portions of the periodic calibration signal from the average sampling value of each of the one or more pre- defmed portions of the periodic calibration signal. This may determine an average version of the periodic calibration signal. Thus, the processing circuitry may function even without knowing the exact shape of the periodic calibration signal.

In various examples, the output signal comprises a plurality of segments. The plurality of segments may each comprise a sampling value that is based on a combination of a pre-defmed portion of the one or more pre-defmed portions and an analog-to-digital converter circuit of the plurality of time-interleaved analog-to-digital converter circuits. For example, the plural ity of segments may comprise sampling values for all of the combinations of the one or more pre-defmed portions and the plurality of time-interleaved analog-to-digital converter circuits. This may ensure that every ADC converter circuity has sampled each pre-defmed portion, enabling the calculation of the average signal.

Each segment may have a length of one clock cycle of the clock signal of the analog-to-digital converter. This may facilitate a processing of the sampled periodic calibration signal.

In some examples, the signal generation circuitry is configured to add white noise to the pe riodic calibration signal. The plurality of segments may comprise multiple sampling values for all of the combinations of the one or more pre-defmed portions and the plurality of time- interleaved analog-to-digital converter circuits. The A2D quantization may limit the ability to distinguish between similar amplitudes, therefore, it may limit the resolution of the skew- estimation. This may be overcome by adding thermal-white-noise to the signal and averaging multiple occurrences of each sample. In various examples, the signal generation circuitry comprises low pass filter circuitry con figured to low-pass filter the periodic calibration signal. At least some examples show an improved performance with a periodic calibration signal that lacks fast amplitude changes.

For example, the signal generation circuitry may comprise clock divider circuitry. The peri odic calibration signal may be based on an integer-divided version of the clock signal of the analog-to-digital converter. A clock divider is an implementation of the signal generation cir cuitry that requires only few hardware modifications. Alternatively, the signal generation cir cuitry might comprises digital-to-analog conversion circuitry configured to generate the peri odic calibration signal based on the clock signal of the analog-to-digital converter or based on a further clock signal the clock signal of the analog-to-digital converter is based on.

In at last some examples, the processing circuitry is configured to estimate a slope of the periodic calibration signal. The processing circuitry may be configured to determine the skew of the plurality of time-interleaved analog-to-digital converter circuits based on the estimated slope of the periodic calibration signal. Based on the slope, the skew may be calculated, as shown in Figs. 7a to 7c.

In embodiments the processing circuitry may be implemented using one or more processing units, one or more processing devices, any means for processing, such as a processor, a com puter or a programmable hardware component being operable with accordingly adapted soft ware. In other words, the described function of the processing circuitry may as well be imple mented in software, which is then executed on one or more programmable hardware compo nents. Such hardware components may comprise a general purpose processor, a Digital Signal Processor (DSP), a micro-controller, etc.

Examples further provide a time-interleaved analog-to-digital converter comprising a plural ity of time-interleaved analog-to-digital converter circuits and an apparatus for calibrating the time-interleaved analog-to-digital converter according to one of the previous claims. The time-interleaved analog to digital converter may further comprise switching circuitry for switching between an input signal and the periodic calibration signal. The switching circuitry might provide either the input signal or the periodic calibration signal to the plurality of time- interleaved analog-to-digital converter circuits. Examples further provides a device for calibrating a time-interleaved analog-to-digital con verter comprising a plurality of time-interleaved analog-to-digital conversion means. The components of the device are defined as component means, which correspond to the respec tive structural components of the above-specified apparatus. The device comprises means for generating the periodic calibration signal for the plurality of time-interleaved analog-to-digi- tal converter circuits. The period of the periodic calibration signal is a multiple of the clock cycle of the clock signal of the analog-to-digital converter. The device comprises means for processing configured for obtaining the output signal of the analog-to-digital converter. The output signal is based on the time-interleaved sampling of the periodic calibration signal by the plurality of time-interleaved analog-to-digital converter circuits. The means for processing is configured for comparing the sampling values of the one or more pre-defmed portions of the periodic calibration signal originating from different analog-to-digital conversion means of the plurality of time-interleaved analog-to-digital conversion means. The means for pro cessing is configured to determine the skew of the plurality of time-interleaved analog-to- digital conversion means based on the comparison of the sampling values.

Examples further provide a time-interleaved analog-to-digital converter comprising a plural ity of time-interleaved analog-to-digital converter circuits and a device for calibrating the time-interleaved analog-to-digital converter according to one of the previous claims. The time-interleaved analog-to-digital converter may further comprise means for switching be tween an input signal and the periodic calibration signal, the means for switching providing either the input signal or the periodic calibration signal to the plurality of time-interleaved analog-to-digital converter circuits.

Examples further provide a corresponding method for calibrating a time-interleaved analog- to-digital converter comprising a plurality of time-interleaved analog-to-digital converter cir cuits. The method comprises generating a periodic calibration signal for the plurality of time- interleaved analog-to-digital converter circuits a period of the periodic calibration signal be ing a multiple of a clock cycle of the clock signal of the analog-to-digital converter. The method comprises obtaining an output signal of the analog-to-digital converter. The output signal is based on a time-interleaved sampling of the periodic calibration signal by the plural ity of time-interleaved analog-to-digital converter circuits. The method comprises comparing sampling values of one or more pre-defmed portions of the periodic calibration signal origi nating from different analog-to-digital converter circuits of the plurality of time-interleaved analog-to-digital converter circuits. The method comprises determining a skew of the plural ity of time-interleaved analog-to-digital converter circuits based on the comparison of the sampling values.

Examples further provide a machine-readable storage medium including program code, when executed, to cause a machine to perform the method. Examples further provide a computer program having a program code for performing the method, when the computer program is executed on a computer, a processor, or a programmable hardware component. Examples further provide a machine-readable storage including machine readable instructions, when executed, to implement a method or realize an apparatus in introduced in the context of this application.

Examples of the present disclosure provide a simple time-skew calibration for an interleaved A2D (Analog-to-Digital-Converter).

Many applications today require high speed high bandwidth accurate analog to digital con verters (A2D). A common way to implement such converter is to time interleave a number of lower speed converters (TI-ADC, Time-Interleaved Analog-to-Digital Converter). This may provide improvements in regards power per specific ADC dynamic range, however mis matches between the different converters may degrade TI-ADC performance, hence calibra tions may be used for mid to high resolution ADC, or for high sampling rate ADCs.

The dominant mismatches which cause errors in the conversion may be DC (Direct Current) offset, gain and timing skew. The DC offset and gain may be easy to overcome by simple and straightforward calibrations. Timing skew error may require more attention. Timing skews between slices may limit ADC performance as input BW (Bandwidth) increases. Time-skew mismatch between different slices, which is an inherent impairment, may be fixed as they limit ADC performance as input BW increases and are harder to calibrate.

Uncalibrated, it may reach up to +/- 3 Ops between slices, which may degrade ADC perfor mance significantly. Examples provide a (simple) digital low power, low area, and easy to implement approach for time interleaving calibration. Skews may be measured and calibrated by autonomous logic that might not require generation of an accurate signal like a sine wave, or even knowing the signal that is used for calibration. In some systems, such calibration may be provided by online calibrations based on very large statistics and correlations, additional A2D (in a different sampling rate) for comparison, or by eliminating time skew errors by implementing a single track-and-hold (T/H) / Implementing a single sample-and-hold (S/H).

Such approaches may requires at least one of the following:

Online calibration - Complex (calibration) algorithm with heavy digital implementation, long convergence time and extra power consumption

Additional A2D - Additional hardware on the analog side (e.g. additional converter for calibration), more load on the high frequency clock, load on signal driver

Common T/H - Sampling high BW signals at high frequency with a single track and hold consumes high power and in many cases it is not an efficient, or even feasible solution. Long convergence time for online algorithms and extra power consumption

Analog design challenges (e.g. common S/H, T/H)

Examples provide an offline algorithm to calibrate the skew mismatch between the slices. In order to avoid the need of knowing the exact test-signal, a periodic signal may be used (e.g. the periodic calibration signal) and the values between the slices may be compared, without characterizing the calibration signal. In other words, examples provide an autonomous offline algorithm that calibrates skew mismatch between different ADC slices. In order to avoid the need of generating or knowing the exact test-signal, a periodic signal generated from the sam pling clock (e.g. the signal generation circuitry) may be used and the sampled values of all the slices may be compared (e.g. using the processing circuitry). Examples might not require characterizing the calibration signal, or generating it in an accurate way.

The diagram of Fig. 1 illustrates 4 slices (1, 2, 3 and 4) sampling a periodic signal generated out of the sampling clock (the sampled signal is the input clock divided by 5). Fig. 1 shows an example of test signal generated for a 4 slices ADC (input clock divided by R=5). Fig. 1 reference sign 110 shows the length of the period of the sampled signal (e.g. the periodic calibration signal), which in this case is 5 clock cycles of the clock signal of the ADC long, as it is based on the input clock divided by 5. Reference sign 120 shows the length of a period sampled by the four slices, which is different from the period 110 of the sampled signal. Ref erence sign 130 shows the sampled signal, and reference sign 140 shows the clock signal of the ADC. In this example, there are five different input signal values (circle, trapezoid, pen tagon, square and star), sampled by each slice. By sampling the same occurrences of the test signal (e.g. the one or more pre-defmed portions of the periodic calibration signal) with each slice, we are able to calculate the systematic time error between the different slices.

The algorithm was implemented and measured in 8b 4x-TI ADC with sampling rate of 2.5GSPS (Giga Samples per Second). ADC signal to time skew spurs before and after cali bration are demonstrated in Fig. 2. Fig. Fig. 2 shows a measurement of 4x-TI ADC before and after Time skew calibration. The x-axis of the diagram of Fig. 2 shows the input signal frequency in MHz, the y-axis shows the signal to TI-spurs in dB. Reference sign 210 shows the graph of the silicon measurement after calibration (post-calibration), while reference sign 220 shows the graph of the silicon measurement before calibration (pre-calibration.

Examples may enable high-rate high-performance interleaved-A2D to be used on large BW signals (5G, WiGig) without running long or complex calibrations. Examples may enable time skew calculation without the need of additional hardware to generate an accurate test signal. Time skew error calculation may be simple, quick and might not require a high amount of logic. Calibration accuracy might not be limited and may be improved by increasing the number of samples. In any case, the number of cycles required to obtain high accuracy may be low compared to other approaches.

In ADCs that include time interleaved ADC, an integer clock divider or a DAC and a simple LPF filter (Low-Pass Filter) may be used. The clock divider or DAC may be fed by the sam pling clock, hence they can be easily distinguished among other blocks.

Furthermore, if a supply voltage or current of the ADC is monitored, frequency elements that are co-prime divisions of the sampling clock may be identified. The time skew calibration may be autonomic and offline, without a need for specific hardware.

In at least some examples, the algorithm may be broken down into three operations:

1. Generating a test signal (e.g. the periodic calibration signal) 2. Sampling and averaging multiple periods (e.g. my obtaining and comparing sampling values of one or more pre-defmed portions of the periodic calibration signal originat ing from different analog-to-digital converter circuits of the plurality of time-inter leaved analog-to-digital converter circuits)

3. Calculating skew estimation (e.g. by determining the skew of the plurality of time- interleaved analog-to-digital converter circuits based on the comparison of the sam pling values)

Generating an exact analog-test-signal is a difficult task. At least some examples may use an unknown test signal, which may facilitate the generation of the test signal. In some examples, there might be (only) two requirements from this signal: it should be a smooth and periodic signal, both of which may be easy to implement in HW. For example, the signal may be generated (e.g. by the signal generation circuitry) by one of the two following operations:

1. Divide the sampling clock by an integer divider and filter it by a simple R-C filter

2. Generate a wave with a DAC using the same sampling clock and pass it through RC filter

Other operations might also be used.

Fig. 3 shows two exemplary implementations 330 and 360 of signal generation circuitry for generating a test signal. Fig. 3 330 shows option 1, in which an integer clock divider 332 of signal generation circuitry 330 is used, in conjunction with a R-C-LPF 334, to generate the test signal based on a clock signal 320. During calibration, the test signal may be provided via logical or hardware switching circuitry 350 to the TI-A2D 340 (which is based on the same clock signal 310). When no calibration is performed, the input data 310 may be provided to the TI-A2D 340 (via the logical or hardware switching circuitry 350). Alternatively, the signal generation circuitry 360 of option 2 of Fig. 3 may be used. Fig. 3 360 shows option 2, in which a wave generation DAC (Digital -to- Analog converter) 362 of signal generation cir cuitry 360 is used, in conjunction with a R-C-LPF 336, to generate the test signal based on the clock signal 320. The other components of option 2 may be implemented similar to option 1. If option 1 is used, no additional hardware might be required except for a simple integer divider and R-C.

For example, for a given number of slices Ns (e.g. 8), the test signal may be periodic with period R coprime to Ns (e.g. 7, 5, 11). The signal might not be constant, because its slope is the link between amplitude and time-skew (if only the amplitude can be observed). One option is to generate a signal with a large STD (which is not saturated). One of the actions performed in the skew- calculation may involve estimating the slope from the samples, for this action, it might be best not to have very large/fast changes in the signal. In other words, the test-signal may be low-passed. Few easy ways to generate such a periodic signal may be to divide the sampling clock by R and pass it though a LPF, or to use a small DAC with a periodic code ramp (using same clock as the ADC), and to pass it through a LPF.

At least some examples may comprise sampling and averaging (e.g. obtaining and sampling the output signal, and comparing sampling values of one or more pre-defmed portions of the periodic calibration signal originating from different analog-to-digital converter circuits of the plurality of time-interleaved analog-to-digital converter circuits). Because Ns and R are coprime, the sampled signal may be periodic with period Ns R. The signal may be sampled at R different points, each of them may be sampled by all Ns slices. The exact sampling time depends on the time-skew of each sampling slice. Fig. 1 illustrates test signal for 4x time interleaved ADC (Ns=4), where R=5 (that is, input sampling clock was divided by 5).

The A2D quantization may limit the ability to distinguish between similar amplitudes, there fore, it may limit the resolution of the skew-estimation. This may be overcome by adding thermal-white-noise to the signal and averaging multiple occurrences of each Ns R sample.

At least some examples may comprise Skew estimation (e.g. the determining of the skew). Once the Ns R averaged-samples have been obtained, it may be easier to reshape them into a matrix ( M_NsxR ) for math-representation. Where each row represent a slice, and each column - a point in the test-signal. Fig. 4 shows an example of 20 samples (R x Ns = 5 x 4) arranged in a matrix. Reference signs 410 to 440 denote the samples sampled by slices 1, 2, 3, and 4 (Ns), respectively, while reference signs 450 to 490 denote the points 1 to 5 (R) sampled by the slices.

First, an estimation to the original signal ( v[r ]) may be calculated by averaging each of its R- points from all the N_s- slices:

In Figs. 5 and 6, and in Fig. 7 matrix 700, the estimated values are denoted with an apostrophe. In Figs. 5 and 6, the estimated values are denoted by reference signs 515, 516, 517, 518, and 519 (of the estimated values 510). Fig. 1 shows an example of a test signal for which the value is estimated by performing averaging over columns of a matrix.

Secondly, an amplitude-error ( E[n , r]) of each point in the matrix may be calculated, by sub tracting the estimated-original -test-signal:

E [ n , r\ = M [ n , r]— v [r]

Fig. 6 shows an example of a an error matrix calculation E[n,r] Reference signs 610 to 640 denote the respective error values for slices 1 to 4.

The time-skew error may be proportional to the amplitude-error. The ratio between them may be the slope of the signal (the derivative). A simple derivative estimation is:

Y[n + 1] - Y[n - 1]

Y' \n]

2

Fig. 7 shows an example of a slope calculation, Y’[n] Fig. 7 shows the calculation matrix 700, the slope 702, and a diagram 704 illustrating the ratio between voltage error 720 (the amplitude) and the time skew 710.

In the terms used before, it may be:

Note that a modulate operation may be used on the index due to the signal periodicity.

Now to the estimation. In some examples, the model is:

E [n, r] = d [r] Q [n] + e [n, r]

E n] = d - q\h] + e[h]

The least-square (LS) solution to this is:

Such calculations may be simple to implement in hardware, except for the division part, which may introduce complexities. As the denominator is not a function of [n], any error in the calculation of it (or in the division) may cause a common gain-error in all of the skew-esti mations. Such an error might not be a problem when using iterative-estimation-and-correction (because the error is proportional to the residual skew). An iterative approach may already be required when using analog corrections (because it eliminates the need to calibrate the correction-DAC).

Example 1 relates to an apparatus for calibrating a time-interleaved analog-to-digital con verter comprising a plurality of time-interleaved analog-to-digital converter circuit. The ap paratus comprises signal generation circuitry configured to generate a periodic calibration signal for the plurality of time-interleaved analog-to-digital converter circuits, a period of the periodic calibration signal being a multiple of a clock cycle of a clock signal of the analog- to-digital converter. The apparatus comprises processing circuitry configured to obtain an output signal of the analog-to-digital converter, the output signal being based on a time-inter leaved sampling of the periodic calibration signal by the plurality of time-interleaved analog- to-digital converter circuits, to compare sampling values of one or more pre-defmed portions of the periodic calibration signal originating from different analog-to-digital converter circuits of the plurality of time-interleaved analog-to-digital converter circuits, and to determine a skew of the plurality of time-interleaved analog-to-digital converter circuits based on the com parison of the sampling values.

In Example 2, the subject matter of example 1 or any of the Examples described herein may further include, that the multiple is unequal to a number of time-interleaved analog-to-digital converter circuits of the plurality of time-interleaved analog-to-digital converter circuits.

In Example 3, the subject matter of one of the examples 1 to 2 or any of the Examples de scribed herein may further include, that the periodic calibration signal has a period equal to R clock cycles, wherein the plurality of time-interleaved analog-to-digital converter circuits comprise Ns time-interleaved analog-to-digital converter circuits, wherein R and Ns are co prime numbers.

In Example 4, the subject matter of one of the examples 1 to 3 or any of the Examples de scribed herein may further include, that the processing circuitry is configured to determine an average sampling value for each of the one or more pre-defmed portions of the periodic cali bration signal, the skew of the plurality of time-interleaved analog-to-digital converter circuits being based on a deviation of the sampling values of the one or more pre-defmed portions of the periodic calibration signal from the average sampling value of each of the one or more pre-defmed portions of the periodic calibration signal.

In Example 5, the subject matter of one of the examples 1 to 4 or any of the Examples de scribed herein may further include, that the output signal comprises a plurality of segments, the plurality of segments each comprising a sampling value that is based on a combination of a pre-defmed portion of the one or more pre-defmed portions and an analog-to-digital con verter circuit of the plurality of time-interleaved analog-to-digital converter circuits.

In Example 6, the subject matter of example 5 or any of the Examples described herein may further include, that each segment has a length of one clock cycle of the clock signal of the analog-to-digital converter.

In Example 7, the subject matter of one of the examples 5 to 6 or any of the Examples de scribed herein may further include, that the plurality of segments comprises sampling values for all of the combinations of the one or more pre-defmed portions and the plurality of time- interleaved analog-to-digital converter circuits.

In Example 8, the subject matter of example 7 or any of the Examples described herein may further include, that the signal generation circuitry is configured to add white noise to the periodic calibration signal, wherein the plurality of segments comprises multiple sampling values for all of the combinations of the one or more pre-defmed portions and the plurality of time-interleaved analog-to-digital converter circuits.

In Example 9, the subject matter of one of the examples 1 to 8 or any of the Examples de scribed herein may further include, that the signal generation circuitry comprises low pass filter circuitry configured to low-pass filter the periodic calibration signal.

In Example 10, the subject matter of one of the examples 1 to 9 or any of the Examples described herein may further include, that the signal generation circuitry comprises clock di vider circuitry, wherein the periodic calibration signal is based on an integer-divided version of the clock signal of the analog-to-digital converter. In Example 11, the subject matter of one of the examples 1 to 9 or any of the Examples described herein may further include, that the signal generation circuitry comprises digital- to-analog conversion circuitry configured to generate the periodic calibration signal based on the clock signal of the analog-to-digital converter or based on a further clock signal the clock signal of the analog-to-digital converter is based on.

In Example 12, the subject matter of one of the examples 1 to 11 or any of the Examples described herein may further include, that the processing circuitry is configured to estimate a slope of the periodic calibration signal, wherein the processing circuitry is configured to de termine the skew of the plurality of time-interleaved analog-to-digital converter circuits based on the estimated slope of the periodic calibration signal.

Example 13 relates to a time-interleaved analog-to-digital converter comprising a plurality of time-interleaved analog-to-digital converter circuits and an apparatus for calibrating the time- interleaved analog-to-digital converter according to one of the previous examples.

In Example 14, the subject matter of example 13 or any of the Examples described herein may further include, that the time-interleaved analog-to-digital converter comprises switching circuitry for switching between an input signal and the periodic calibration signal, the switch ing circuitry providing either the input signal or the periodic calibration signal to the plurality of time-interleaved analog-to-digital converter circuits.

Examples 15 relates to a device for calibrating a time-interleaved analog-to-digital converter comprising a plurality of time-interleaved analog-to-digital conversion means. The device comprises means for generating a periodic calibration signal for the plurality of time-inter leaved analog-to-digital converter circuits, a period of the periodic calibration signal being a multiple of a clock cycle of a clock signal of the analog-to-digital converter. The device com prises means for processing configured for obtaining an output signal of the analog-to-digital converter, the output signal being based on a time-interleaved sampling of the periodic cali bration signal by the plurality of time-interleaved analog-to-digital converter circuits, com paring sampling values of one or more pre-defmed portions of the periodic calibration signal originating from different analog-to-digital conversion means of the plurality of time-inter leaved analog-to-digital conversion means, and determining a skew of the plurality of time- interleaved analog-to-digital conversion means based on the comparison of the sampling val ues.

Example 16 relates to time-interleaved analog-to-digital converter comprising a plurality of time-interleaved analog-to-digital converter circuits and a device for calibrating the time-in terleaved analog-to-digital converter according to example 15.

Example 17 relates to a method for calibrating a time-interleaved analog-to-digital converter comprising a plurality of time-interleaved analog-to-digital converter circuits. The method comprises generating a periodic calibration signal for the plurality of time-interleaved analog- to-digital converter circuits, a period of the periodic calibration signal being a multiple of a clock cycle of a clock signal of the analog-to-digital converter. The method comprises obtain ing an output signal of the analog-to-digital converter, the output signal being based on a time- interleaved sampling of the periodic calibration signal by the plurality of time-interleaved analog-to-digital converter circuits. The method comprises comparing sampling values of one or more pre-defmed portions of the periodic calibration signal originating from different an alog-to-digital converter circuits of the plurality of time-interleaved analog-to-digital con verter circuits. The method comprises Determining a skew of the plurality of time-interleaved analog-to-digital converter circuits based on the comparison of the sampling values.

Examples 19 relates to a machine readable storage medium including program code, when executed, to cause a machine to perform the method of example 17.

Example 19 relates to a computer program having a program code for performing the method of example 17, when the computer program is executed on a computer, a processor, or a programmable hardware component.

Example 20 relates to a machine readable storage including machine readable instructions, when executed, to implement a method or realize an apparatus as claimed in any pending claim or example. The aspects and features mentioned and described together with one or more of the previously detailed examples and figures, may as well be combined with one or more of the other exam ples in order to replace a like feature of the other example or in order to additionally introduce the feature to the other example.

Examples may further be or relate to a computer program having a program code for perform ing one or more of the above methods, when the computer program is executed on a computer or processor. Steps, operations or processes of various above-described methods may be per formed by programmed computers or processors. Examples may also cover program storage devices such as digital data storage media, which are machine, processor or computer readable and encode machine-executable, processor-executable or computer-executable programs of instructions. The instructions perform or cause performing some or all of the acts of the above- described methods. The program storage devices may comprise or be, for instance, digital memories, magnetic storage media such as magnetic disks and magnetic tapes, hard drives, or optically readable digital data storage media. Further examples may also cover computers, processors or control units programmed to perform the acts of the above-described methods or (field) programmable logic arrays ((F)PLAs) or (field) programmable gate arrays ((F)PGAs), programmed to perform the acts of the above-described methods.

The description and drawings merely illustrate the principles of the disclosure. Furthermore, all examples recited herein are principally intended expressly to be only for illustrative pur poses to aid the reader in understanding the principles of the disclosure and the concepts con tributed by the inventor(s) to furthering the art. All statements herein reciting principles, as pects, and examples of the disclosure, as well as specific examples thereof, are intended to encompass equivalents thereof.

A functional block denoted as“means for ...” performing a certain function may refer to a circuit that is configured to perform a certain function. Hence, a“means for s.th.” may be implemented as a“means configured to or suited for s.th.”, such as a device or a circuit con figured to or suited for the respective task.

Functions of various elements shown in the figures, including any functional blocks labeled as“means”,“means for providing a signal”,“means for generating a signal.”, etc., may be implemented in the form of dedicated hardware, such as“a signal provider”,“a signal pro cessing unit”,“a processor”,“a controller”, etc. as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the func tions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which or all of which may be shared. However, the term“processor” or“controller” is by far not limited to hardware exclusively capable of executing software, but may include digital signal processor (DSP) hardware, network pro cessor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read only memory (ROM) for storing software, random access memory (RAM), and non volatile storage. Other hardware, conventional and/or custom, may also be included.

A block diagram may, for instance, illustrate a high-level circuit diagram implementing the principles of the disclosure. Similarly, a flow chart, a flow diagram, a state transition diagram, a pseudo code, and the like may represent various processes, operations or steps, which may, for instance, be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown. Meth ods disclosed in the specification or in the claims may be implemented by a device having means for performing each of the respective acts of these methods.

It is to be understood that the disclosure of multiple acts, processes, operations, steps or func tions disclosed in the specification or claims may not be construed as to be within the specific order, unless explicitly or implicitly stated otherwise, for instance for technical reasons. Therefore, the disclosure of multiple acts or functions will not limit these to a particular order unless such acts or functions are not interchangeable for technical reasons. Furthermore, in some examples a single act, function, process, operation or step may include or may be broken into multiple sub-acts, -functions, -processes, -operations or -steps, respectively. Such sub acts may be included and part of the disclosure of this single act unless explicitly excluded.

Furthermore, the following claims are hereby incorporated into the detailed description, where each claim may stand on its own as a separate example. While each claim may stand on its own as a separate example, it is to be noted that - although a dependent claim may refer in the claims to a specific combination with one or more other claims - other examples may also include a combination of the dependent claim with the subject matter of each other de pendent or independent claim. Such combinations are explicitly proposed herein unless it is stated that a specific combination is not intended. Furthermore, it is intended to include also features of a claim to any other independent claim even if this claim is not directly made dependent to the independent claim.

Claims

Claims What is claimed is:

1. An apparatus for calibrating a time-interleaved analog-to-digital converter comprising a plurality of time-interleaved analog-to-digital converter circuits, the apparatus com prising: signal generation circuitry configured to generate a periodic calibration signal for the plurality of time-interleaved analog-to-digital converter circuits, wherein a pe riod of the periodic calibration signal is a multiple of a clock cycle of a clock signal of the analog-to-digital converter; and processing circuitry configured to:

obtain an output signal of the analog-to-digital converter, the output signal being based at least on a time-interleaved sampling of the periodic calibration signal by the plurality of time-interleaved analog-to-digital converter circuits,

compare sampling values of one or more pre-defmed portions of the periodic calibration signal originating from different analog-to-digital converter cir cuits of the plurality of time-interleaved analog-to-digital converter circuits, and determine a skew of the plurality of time-interleaved analog-to-digital converter circuits based on the comparison of the sampling values.

2. The apparatus according to claim 1, wherein the multiple is unequal to a number of time-interleaved analog-to-digital converter circuits of the plurality of time-inter leaved analog-to-digital converter circuits.

3. The apparatus according to claim 1, wherein the periodic calibration signal has a pe riod equal to R clock cycles, wherein the plurality of time-interleaved analog-to-digi- tal converter circuits comprise Ns time-interleaved analog-to-digital converter cir cuits, wherein R and Ns are co-prime numbers.

4. The apparatus according to claim 1, wherein the processing circuitry is configured to determine an average sampling value for each of the one or more pre-defmed portions of the periodic calibration signal, the skew of the plurality of time-interleaved analog- to-digital converter circuits being based on a deviation of the sampling values of the one or more pre-defmed portions of the periodic calibration signal from the average sampling value of each of the one or more pre-defmed portions of the periodic cali bration signal.

5. The apparatus according to claim 1, wherein the output signal comprises a plurality of segments, the plurality of segments each comprising a sampling value that is based on a combination of a pre-defmed portion of the one or more pre-defmed portions and an analog-to-digital converter circuit of the plurality of time-interleaved analog-to-digital converter circuits.

6. The apparatus according to claim 5, wherein each segment has a length of one clock cycle of the clock signal of the analog-to-digital converter.

7. The apparatus according to claim 5, wherein the plurality of segments comprises sam pling values for all of the combinations of the one or more pre-defmed portions and the plurality of time-interleaved analog-to-digital converter circuits.

8. The apparatus according to claim 7, wherein the signal generation circuitry is config ured to add white noise to the periodic calibration signal, wherein the plurality of seg ments comprises multiple sampling values for all of the combinations of the one or more pre-defmed portions and the plurality of time-interleaved analog-to-digital con verter circuits.

9. The apparatus according to claim 1, wherein the signal generation circuitry comprises low pass filter circuitry configured to low-pass filter the periodic calibration signal.

10. The apparatus according to claim 1, wherein the signal generation circuitry comprises clock divider circuitry, wherein the periodic calibration signal is based on an integer- divided version of the clock signal of the analog-to-digital converter.

11. The apparatus according to claim 1, wherein the signal generation circuitry comprises digital-to-analog conversion circuitry configured to generate the periodic calibration signal based on the clock signal of the analog-to-digital converter or based on a further clock signal the clock signal of the analog-to-digital converter is based on.

12. The apparatus according to claim 1, wherein the processing circuitry is configured to estimate a slope of the periodic calibration signal, wherein the processing circuitry is configured to determine the skew of the plurality of time-interleaved analog-to-digital converter circuits based on the estimated slope of the periodic calibration signal.

13. A time-interleaved analog-to-digital converter comprising a plurality of time-inter leaved analog-to-digital converter circuits and an apparatus for calibrating the time- interleaved analog-to-digital converter according to claim 1.

14. The time-interleaved analog-to-digital converter according to claim 13, further com prising switching circuitry for switching between an input signal and the periodic cal ibration signal, the switching circuitry providing either the input signal or the periodic calibration signal to the plurality of time-interleaved analog-to-digital converter cir cuits.

15. A device for calibrating a time-interleaved analog-to-digital converter comprising a plurality of time-interleaved analog-to-digital conversion means, the device compris ing: means for generating a periodic calibration signal for the plurality of time-in terleaved analog-to-digital converter circuits,

a period of the periodic calibration signal being a multiple of a clock cycle of a clock signal of the analog-to-digital converter; and means for processing configured for:

obtaining an output signal of the analog-to-digital converter, the output signal being based on a time-interleaved sampling of the periodic calibration signal by the plurality of time-interleaved analog-to-digital converter circuits, comparing sampling values of one or more pre-defmed portions of the periodic calibration signal originating from different analog-to-digital conversion means of the plurality of time-interleaved analog-to-digital conversion means, and determining a skew of the plurality of time-interleaved analog-to-digi- tal conversion means based on the comparison of the sampling values.

16. A time-interleaved analog-to-digital converter comprising a plurality of time-inter leaved analog-to-digital converter circuits and a device for calibrating the time-inter leaved analog-to-digital converter according to claim 15.

17. A method for calibrating a time-interleaved analog-to-digital converter comprising a plurality of time-interleaved analog-to-digital converter circuits, the method compris ing: generating a periodic calibration signal for the plurality of time-interleaved an- alog-to-digital converter circuits, a period of the periodic calibration signal being a multiple of a clock cycle of a clock signal of the analog-to-digital converter; obtaining an output signal of the analog-to-digital converter, the output signal being based on a time-interleaved sampling of the periodic calibration signal by the plurality of time-interleaved analog-to-digital converter circuits; comparing sampling values of one or more pre-defmed portions of the periodic calibration signal originating from different analog-to-digital converter circuits of the plurality of time-interleaved analog-to-digital converter circuits; and determining a skew of the plurality of time-interleaved analog-to-digital con verter circuits based on the comparison of the sampling values.

18. A machine readable storage medium including program code, when executed, to cause a machine to perform the method of claim 17.

19. A computer program having a program code for performing the method of claim 17, when the computer program is executed on a computer, a processor, or a programma ble hardware component.