WO2009098641A1

WO2009098641A1 - Signal converter

Info

Publication number: WO2009098641A1
Application number: PCT/IB2009/050439
Authority: WO
Inventors: Peter C. S. Scholtens; Konstantinos Doris; Erwin Janssen
Original assignee: Nxp B.V.
Priority date: 2008-02-06
Filing date: 2009-02-03
Publication date: 2009-08-13

Abstract

A time-interleaved signal converter (800) comprising a plurality of analogue-to- digital converters (ADCO-3), hereinafter termed ADCs, the ADCs being configured to sample an input signal at a common sampling rate and at differing phases to produce a corresponding plurality of digital signal outputs, the signal converter (800) being configured to produce a combined digital signal output from a combination of the plurality of digital signal outputs, wherein the signal converter (800) is configured to determine a sampling timing error (ΔT) between a pair of the ADCs by comparing an autocorrelation (710) of the combined digital signal output with a cross-correlation (720) of a respective pair of the plurality of digital signal outputs.

Description

DESCRIPTION

SIGNAL CONVERTER

The invention relates to time-interleaved analogue-to-digital signal converters, and in particular to adjustment of timing errors when taking samples at different phases in such signal converters.

To implement an analogue-to-digital converter (ADC) with a very high sampling rate, a timing-interleaved topology can be used. An exemplary topology of such a signal converter 100 is shown in figure 1. Multiple ADCs ADCO, ADC1 , ADC2, ADC3 with a common sample rate F_s are connected to the same input signal x(t). Multiple clock signals 110 are connected to these ADCs. By shifting the individual clock phases φo, φi, φ2, φ3 by 27τ/n, where n represents the number of parallel ADCs (in this case 4), all ADCs together will capture the input signal x(t) with the higher sampling rate n • F_: and together resemble a single ADC running at this higher sampling rate. This architecture enables acquisition of a wider bandwidth input spectrum of up to n • F_s/2, instead of up to F_s/2 for each of the individual ADCs. This arrangement can, for example, allow digital sampling of an entire bandwidth of interest, such as a complete cable television or satellite bandwidth. Selection of an individual channel of interest can then be carried out in the digital domain rather than through filtering in the analogue domain.

This topology, shown in the signal converter 100 illustrated in figure 1 with a plurality of ADCs arranged in parallel and each ADC running at a lower sampling speed, reduces the required power consumption of each ADC compared with a single ADC running at a sampling rate of n • F₅. This is because the increase in power consumption tends to rise more than linearly with an increasing sampling rate, resulting in a single ADC running at a sampling rate of n • F_s consuming more than n times the power of n ADCs running at a sampling rate of F₅. Multiple solutions to implement the ADC function will also become feasible. The sampling moment of the data signal however, requires accurate timing, for example through synchronising of the input switches 120, the switch function being implemented by the individual clock phases φ₀,

In the case of four time-interleaved ADCs as shown, of which only one ADC contains a phase error, the resulting behaviour is plotted in figures 2a and 2b. Data samples d₀, d₄, d₈ are the output values of ADCO, while the adjacent samples di, d₅, originate from ADC1 , U₂, d₆ from ADC2, and d₃, d₇ from ADC3. A sinewave signal 200, shown in figure 2a, having a frequency F|_N is applied at the input. After a sampling operation is performed, without showing any rounding effects due to quantization, a distorted signal 205 results from errors in timing between adjacent data samples. If F|_N < F_s/4, the timing error ΔT 230 corresponding to the phase error results in spurious tones 240 at F_s/4-F_ιn, F_s/4+F_ιn and F_s/2-F_ιn, as shown in a frequency domain plot of the distorted signal 205 in figure 2b. If F|_N > F_s/4, the signals will instead fold back in the frequency domain. This has no influence on the further derivation of a cross- correlation, only causing the positions of the phase error tones 240 to change. The amplitude of the spurious tones 240 shown in figure 2b is a measure of the magnitude of the timing error 230. The timing error present can therefore be detected when examining the output data stream when a known input signal is applied to the input 140 of the signal converter 100.

In practice, generating an accurate set of clock phases is difficult to realise with conventional circuit techniques. Device mismatch, different layout geometries, power supply variations and other effects can contribute to constant, but also varying, timing offsets of the clock phases.

Timing calibration schemes have been proposed to remove timing errors in the system, for example by Poulton et al in "A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 μm CMOS", Agilent Labs., Palo Alto, CA, USA; Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International, 9-13 Feb. 2003, pp. 318- 496, vol.1. A known signal is applied, and all the distortion measured in the digital domain is attributed to the timing error of the various ADCs. The measured timing error can be used to control a programmable delay Δτ in the clock tree to nullify the timing error. Such an arrangement is shown in figure 3. This programmable delay Δτ, made to counteract the timing error ΔT described above, corresponds to a change in the relevant clock phase, i.e. a shift of Δτ will cause a clock phase shift Δφ of 2πΔτF_s, where F_s is the sampling rate.

The time interleaving method in general allows the implementation of a low power ADC with a very wide band input spectrum. Including a programmable delay enables proper adjustment of the clock phases. Some implementations may use a calibration cycle using a known signal, before using the system, to measure the timing errors. This has some disadvantages, including the following: i) An accurate signal source inside the system is required to measure the timing error(s) and to control the programmable delay(s) on a regular basis (to suppress aging effects); ii) Some time is spent during start-up of the ADC for calibration; and iii) As the calibration is often an only one-time effort during start-up, temperature or voltage dependent timing errors will not necessarily be suppressed.

It is an object of the invention to address one or more of the above mentioned problems.

According to a first aspect, the invention provides a time-interleaved signal converter comprising a plurality of analogue-to-digital converters, hereinafter termed ADCs, the ADCs being configured to sample an input signal at a common sampling rate and at differing clock phases to produce a corresponding plurality of digital signal outputs, the signal converter being configured to produce a combined digital signal output from a combination of the plurality of digital signal outputs, wherein the signal converter is configured to determine a sampling timing error between a pair of the ADCs by comparing an autocorrelation of the combined digital signal output with a cross-correlation of a respective pair of the plurality of digital signal outputs. According to a second aspect, the invention provides a method of adjusting sampling timing errors in a time-interleaved signal converter, the method comprising: receiving a plurality of output sampled signals from a plurality of ADCs sampling an input signal at a common rate and at differing phases; performing an autocorrelation of a digital output signal combined from the plurality of output sampled signals; performing a cross-correlation of a pair of output sampled signals from a corresponding pair of the plurality of ADCs; and determining a timing error from a comparison of the autocorrelation with the cross-correlation. The invention does not require an accurate reference signal or calibration time.

Systems according to the invention can therefore be used immediately without the need for pre-calibration, and can be calibrated while being used. While the performance at start-up may be limited to best-effort circuit techniques, this will tend to increase over time using many calibration cycles.

The invention will now be described by way of non-limiting example embodiments and with reference to the appended drawings in which: figure 1 illustrates an exemplary time-interleaved ADC topology; figures 2a and 2b illustrate the influence of timing error on a captured signal; figure 3 illustrates a time-interleaved ADC topology with programmable delay cells; figure 4a illustrates the captured output spectrum of an time equidistant interleaved ADC resembling a monolithic or ideal ADC; figure 4b illustrates the captured output spectrum of a time interleaved ADC with a timing error; figure 5 illustrates a wide band data stream of a complete time interleaved system; figure 6 illustrates construction of an autocorrelation function from individual correlations between parallel ADCs; figure 7 illustrates autocorrelation values for complete and partial autocorrelation functions; figure 8 illustrates a 4-times interleaved ADC topology; and figure 9 illustrates an adjustable filter and a 4-times interleaved ADC controlled by correlation extraction and digital signal processing.

Throughout the description the following definitions and declarations will be used:

i) Variable n represents the interleaving ratio of the systems. A n-times interleaved system therefore contains n parallel ADCs, each with their own data stream _yι(k), y₂(k),... y_n(k).

ii) Index/? e [0, 1, 2, ..., n - 1] points to one of the ADCs present in the system.

iii) The output signal y(l) of the complete time interleaved system is the combination of the data streams

... y_n(k) of all the individual ADCs together, such that y_p(k) = y{n ^■ k + p).

iv) Variable m represents the number of data samples of one ADC in a time frame m — . F. v) Logically in total there are n ^■ m data samples available in the time frame of interest.

vi) Index k e [0, 1, 2, ..., m - 1] points to one data sample of a single ADC stream.

vii) Index / e [0, 1, 2, ..., n ^■ m - 1] points to one sample of the complete data stream.

It is interesting to study the properties of the input signals of the individual ADCs on one hand and the properties of the combined input signal of the complete time- interleaved system on the other hand. From this we will extract something of the errors inside the time interleaved ADC system. The average value μ_B of the datastream from ADC number n is given by the following:

1 mm--ϊϊ μ_« = — ∑y_n(k) (equation 1 ) m _k=0

Over a very long time period, with effectively an infinite amount of data, i.e. as m tends towards infinity, the average values of all datastreams y_n will end up being equal if the average μ_* of the input equals zero. The applied input signal should ideally contain no components at exact multiples of FJn, as they will be viewed as an offset inside the ADC. This means that the average value of one complete datastream is equal to the average value of one datastream and also the average value of the input signal, i.e.:

(equation 2)

If there is an offset present in one (or more) of the connected ADCs, the average value of its output stream will never converge to the average value of the sampled input. Therefore, this can be expressed as a difference between both average values, i.e.: 1 m— 1 i n—\ m—\ i n— 1 offset_{ΛDC( )} = \im —Y y (i) V V j (i) = μ — V μ (equation 3)

In this way the offset of each individual ADC can be estimated and corrected, either in the analog or digital domain. The average value of each data stream is consequently equal to the offset of the accompanying ADC, when looking at large number of data samples, for almost any type of input signal. Only the sum of all data samples, and the number of data samples m, therefore need to be stored. No storage of the signal is required.

In a similar way to that given above, the amplitude of the data captured for each

ADC can be estimated. In general the root mean square (RMS) value σ^ of any signal y_p(k) is given by the following:

I J m-l

°p ⁼ _Λ l—∑yfa) (equation 4)

For zero offsets between ADCs, or when the offsets are corrected, looking over very long time frames, i.e. where m → ∞ , the RMS value of all data streams will approach a limit value and end up being equal, thus:

σ₀ = σ, = = σ_ = EEjJ(O (equation 5)

If the input range of the ADCs is different this will not be the case. The difference in scale conversion from analog to digital is viewed as a gain error, which can be extracted as follows:

m-l

(n - l)∑y_p ²(i) gain _ error _ΛDC(p) = lim _n__χ ^₁ (equation 6)

^" j= Σ0,j≠p Σ ι=O-";«-> In conclusion, the gain error of an ADC can be estimated by dividing the RMS value of the signal from the ADC by the RMS value of the complete datastream. This can be done after the offsets are removed, either by analog or digital means. The accuracy of this gain error increases with the number of data samples taken into account. Only the sum of the squares of all data samples is required to be stored, together with the number of data samples m. No storage of the signal itself is required.

If the input signal is frequency band limited, for example as shown in figure 2a, the data sample d^ , taken by ADC3, which is shown as being captured late by a delay of ΔT, will correlate much more with the next sample d₄, which is captured a shorter time after, compared with the previous sample d-₂. This property can be used to calibrate the ADC while the system is in use. During normal operation a variety of signals is applied, often with multiple modulation schemes. In general, however, two effects typically occur:

i) The available spectrum of the ADC, from 0 to FsIl, is not completely filled, because the channel spacing allows a reasonable amount of unused bandwidth. Also the steepness of the anti-aliasing filter preceding the ADC is not infinite and thus the last part close to FsIl will be attenuated or even suppressed.

ii) Power losses due to connections can weaken the higher frequencies significantly. Even if the amount of attenuation is small (6-12dB), the slope of the applied input signal will be weakened, and its predictability increases.

An example of a wide band signal input spectrum illustrating both of the above effects is shown in figure 4a. The example signal shown has a bandwidth of around

1700MHz. This bandwidth is less than F_s/2, which in this case equals 2000 MHz, but is instead close to the full Nyquist condition at 0.4 F_s. Higher frequencies are shown to be more attenuated due to cable losses.

If a timing error is introduced in one or more of the ADCs, for example in the form presented in figure 2, noise will be generated covering the complete spectrum. The resulting sampled data will be polluted with noise both inside and outside the band of interest. This is illustrated in the plot shown in figure 4b.

A part of the signal represented by figure 4b is shown in the time domain in figure 5. Using different markers (+, o, x and D) to represent different ADC outputs, the signal in figure 5 shows that each time-interleaved ADC captures data at different points in time and at regular relative distances. Examining the individual data streams represented by the different markers, the correlation seems to be zero, as the signals are wide band. The correlation between the data samples of the complete system however, taking all data points together, is significant because the steps between two adjacent data samples is smaller than the variance of the signal itself.

Although the input signal could be considered as a sum of random phase sine waves, some correlation between data samples exists due to the empty frequency band(s) and effects such as cable-dependent spectral shaping (shown in figure 4a) or different power densities per channel. For continuous time signals the autocorrelation function is given by the following relationship:

R_{x x}(t,τ) = \ x(t)x(t -τ)dt (equation 7)

By definition, the value of the normalized autocorrelation function P_x,_x(0) equals unity. For the first ADC, the output being in the form of a discrete time series, the autocorrelation function is defined as follows: y (j) . yAj -k) (equation 8)

Similarly, for the next ADC (and likewise for the other ADCs):

1 m—\ py2y2(k) = - ∑y₂U) ^• y₂U - k) (equation 9)

For the total sampled signal, in the form of a n-times interleaved ADC output, the normalized autocorrelation function is given by the following:

1 n m—\ 1 m— 1 n— 1 py y(^l) = ₂ ∑ yϋ> yU - 0 = i∑∑y(n - i+ j) - y(n - i+ j -i) mnσ_y % mnσ_y ^p_o

(equation 10) If we calculate the autocorrelation of the system S_XιX, looking only at the special case where I = k ^■ n, then equation 10 becomes:

1 n—\ m— 1 1 n—\

^PyΛ^k- ⁿ) = τY∑An ' i + j) ' y(n ' {i -k) + j) =-∑P_{y ty} (equation 11 )

In fact only data samples of the same ADC are multiplied and summed. Thus, the autocorrelation function of the complete system at distance k ^■ n is equal to the sum of the individual autocorrelation functions at distance k, divided by the number n of parallel ADCs.

For the cross correlation functions between two adjacent ADCs, e.g. P_xi,_X2 , the following is assumed:

(equation 12)

For the special case where / = k ^■ n + 1 , this function can be reduced to:

1 n—V m—V 1 n—V

P_v (k-n + l) = Y Y y(n-i + j)-y(n-(i-k) + j-ϊ) = -TP_{v v}

(equation 13)

Equations 11 and 13 above can now be used to construct the autocorrelation function for every value of /. The resulting calculation method is visualized in figure 6, which shows the autocorrelation functions for P_yy{-\) to P_y,y(4). For an input signal as described above in relation to figure 4a, the signal having a partly filled band and some cable-dependent spectral shaping, the autocorrelation function 710 of the signal is plotted in figure 7, with the function for each sample being represented by 'Δ' markers. Sample 2001 represents the autocorrelation function P_y,_y(0), which is of course unity. Adjacent samples 2000 and 2002 represent the autocorrelation P_y,_y(-l) and P_y,_y(l) of the signal respectively, assuming no timing errors are present. Including timing errors, the cross-correlations 720 between adjacent pairs of

ADCs are also plotted in figure 7 for all four combinations of P_yi,_y2, P_y2y3, P_y3,y4 and

Py₄,_yi (using the markers +, o, x and D respectively). The value of P_yj,y_j+i(0) ideally approaches the value of P_y__y{-\), and all cross-correlation terms are aligned using this resemblance.

The autocorrelation of the signal captured by the whole system is compared with the cross-correlations of pairs of adjacent ADCs. A difference between these two values indicates a timing error. The difference can therefore be used to compensate for, and reduce, timing errors for pairs of adjacent time-interleaved ADCs. An exemplary embodiment of a complete system 800 is depicted in figure 8, the system 800 comprising several timing interleaved ADCs (ADCO, ADC1 , ADC2, ADC3), an optional filter 810, control logic 820 and programmable time delay cells or elements 830a-d. The system 800, using the control logic 820, is configured to compare P_y,_y(l) with P_yi,y₂(0) and adjust the timing of ADC2 compared with ADC1 accordingly, using the programmable delay cells 830a, 830b. Other pairs of ADCs are adjusted accordingly. In a general aspect therefore, each time delay element 830a-d is connected to a clock input 840a-d of a respective ADC ADCO-3, and is configured to adjust the respective ADC to alter the clock phase at which the ADC samples the input signal. Adjustment of the time delay elements 830a-d is made by means of the control logic 820.

Certain embodiments may include timing error detection alone, with no correction being performed by the system itself. Instead, post-processing of captured digital data may, for example, be implemented to eliminate the timing errors determined by the system. Such post-processing can therefore be advantageously carried out in the digital domain rather than through analog adjustments to the clock phases.

Because P_y,_y{V) is the average of all separate cross-correlations, given by Py_j,y_j+ι(0) (see equation 13), some iteration during calibration may be required, for example by carrying out cross-correlation comparisons and timing adjustments for each pair of ADCs in the system at least once to achieve optimum calibration. In figure 7 the validity of this approach can be demonstrated when examining the curves 720 of the correlation functions: the + marker at sample position 2000 is at a lower correlation value in comparison with the ideal autocorrelation function at the same sample position (indicated by the curve 710 and Δ markers). This means the time delay between the corresponding pair of adjacent ADCs is somewhat larger than ideal. On the other hand, the o markers show a higher correlation value at the same sample position, and therefore indicate a smaller time interval between corresponding pairs of ADCs. The other combinations, represented by the x and D markers, are closer to the ideal value of the autocorrelation function and therefore indicate a smaller timing error. In general therefore, a higher than ideal cross-correlation value indicates a shorter than ideal time interval between corresponding ADCs, whereas a lower than ideal cross-correlation value indicates a longer than ideal time interval between corresponding ADCs. If the cross-correlation value for a pair of ADCs is close to the ideal value from the autocorrelation value at the same sample position, the pair of ADCs are consequently sampling at close to the ideal required timing interval.

According to the above described embodiment, a difference between the autocorrelation of the combined output signal and a cross-correlation of a pair of output signals from a corresponding pair of ADCs is used to determine the timing error between the pair of ADCs. This timing error can then be reduced by applying a phase shift to the timing of one or both of the pair of ADCs. A reduction in timing error can then be indicated by repeating the comparison. In certain embodiments therefore, timing errors can be reduced through iteration of these processes, repeating the comparison and adjustment as often as necessary. Through such a process of continuous measurement and adjustment, timing errors can be kept to a minimum.

Any wide band input signal can be used to calibrate the timing error of the time interleaved ADC using the above described method and system, assuming a wide band stationary behaviour, i.e. where the statistical properties of the signal such as average value, RMS value and autocorrelation do not change rapidly over time. Because the error measurement can be operating continuously, slowly varying timing errors of the system, due for example to aging, temperature variations and other effects can be compensated for. Calculation of the autocorrelation function (either complete or partial) does not require a minimum or a fixed data rate. The timing error can instead be extracted from any collection of received sets of adjacent data samples regardless of the data rate or distance between samples, and regardless of whether the system is temporarily paused and then resumed. In the case where a pseudo-random distance is chosen instead of a regular distance, the above-described vulnerability to frequencies at multiples of F_s/n is removed.

The digital processing unit 820 can be implemented as dedicated hardware, or may be implemented in software, for example on a CPU present in, or connected to, the receiving system 800, The contribution to the total power consumption of the system through the use of the correlation methods described above can therefore be minimal. The (auto-)correlation function can be calculated by storing a sum of all cross- products y(k) • y(k + 1), for each pair of time interleaved ADCs. Thus, an n-times interleaved architecture will require n memory cells. Neither the separate signals y_p(k) nor the combined signal y(l) needs to be stored. The amount of hardware and memory required is consequently minimal.

The particular shape of the autocorrelation function is related to the cable- dependent spectral shaping (also known as cable tilt), and the presence of any empty bands within the Nyquist range of frequencies from 0 up to FsII- Only if all channels have exactly the same amplitude and the band is completely filled will the first next point of the autocorrelation function, P_yy{\) be equal to zero. In practice this is extremely unlikely to occur. The presence of some cable tilt or attenuation (e.g. -6dB either at the higher or lower frequencies) and the presence of some empty bands (as low as 20%) is generally required to use autocorrelation for calibrating the timing errors of the system. In practice this requirement will always be fulfilled. The control loop of the system can optionally comprise a digital filter 810 situated after the digitization process by the ADCs ADCO-3 (see figure 8). The digital filter 810 can be used to suppress the vulnerability of the system for frequencies at F_sln, for example by selectively filtering out, i.e. suppressing, certain frequencies from the outputs of the ADCs, such frequencies typically being integer fractions of the sampling frequency F_s. The filter 810 could also be configured to apply a low-pass and/or a high-pass filtering function. The filter 810 would preferably be implemented as shown in figure 8, but may alternatively be implemented by an analog circuit preceding the ADCs, for example in the form of an analog notch filter.

More sophisticated architectures may also be possible, for example as shown in figure 9. Before the ADC 920, an adaptable analog filter 910 can be introduced to increase or decrease the signal autocorrelation. Intervention on higher order parameters like power spectral density of certain frequency bands could be used to control or optimize the calibration loop or the reception of certain channels of interest. In certain embodiments, the analog filter 910 is programmable rather than being fixed. For example, the filter 910 can be programmed to be a low-pass filter during a calibration mode, and disabled during normal operation. Additionally, the attenuation or bandwidth of the low-pass filter could be adjusted to accommodate different input signals and to enable more accurate measurements to be performed.

In certain embodiments, the signal converter may comprise sampling circuits, such as sample-and-hold (S/H) or track-and-hold (T/H) circuits, separate from the ADCs, for example in arrangements where each sampling circuit is connected to more than one ADC. Each sampling circuit would be configured to provide sample values at specified time intervals to one or more of the ADCs from the input signal. Adjustment of timing errors may then be made between pairs of sampling circuits in addition, or alternatively to, adjustment between pairs of ADCs. In a particular example, two sampling circuits would each drive four ADCs, resulting in a total of 8 ADCs with 2 elements determining timing (assuming no timing error is present between each set of four ADCs). The detection and adjustment of timing error can then be carried out based on the timing of the sampling circuits, but still using the outputs from a pair of ADCs. The above-described system can be used in applications involving wide band or multi-channel systems. Typical applications may include television reception via cable, terrestrial or satellite, Ultra Wide Band (UWB) communications, mobile telephone base stations and others.

Other embodiments are also within the scope of the invention, which is to be defined by the appended claims.

Claims

1. A time-interleaved signal converter comprising a plurality of analogue-to-digital converters, hereinafter termed ADCs, the ADCs being configured to sample an input signal at a common sampling rate and at differing clock phases to produce a corresponding plurality of digital signal outputs, the signal converter being configured to produce a combined digital signal output from a combination of the plurality of digital signal outputs, wherein the signal converter is configured to determine a sampling timing error between a pair of the ADCs by comparing an autocorrelation of the combined digital signal output with a cross-correlation of a respective pair of the plurality of digital signal outputs.

2. The signal converter of claim 1 wherein the signal converter is configured to adjust the clock phase of one or both of the pair of ADCs to reduce the sampling timing error.

3. The signal converter of claim 1 or claim 2 comprising a pair of sampling circuits, each sampling circuit configured to provide sampled values to one or more of the plurality of ADCs, wherein the signal converter is configured to adjust the clock phase of one or both of the pair of sampling circuits to reduce the sampling timing error.

4. The signal converter of claim 2 comprising a corresponding plurality of adjustable time delay elements, each time delay element connected to a clock input of a respective ADC and configured to adjust the respective ADC to alter the clock phase at which the ADC samples the input signal.

5. The signal converter of claim 1 comprising a digital processing unit connected to an output from each of the plurality of ADCs, the digital processing unit being configured to produce the autocorrelation of the combined digital signal output and the cross-correlations of pairs of the plurality of digital signal outputs.

6. The signal converter of claim 5 comprising a digital filter situated between and connected to the plurality of ADCs and the digital processing unit, the digital filter configured to suppress frequency components at one or more integer fractions of the sampling rate.

7. The signal converter of claim 1 comprising a programmable filter connected to an input of the signal converter.

8. A method of adjusting sampling timing errors in a time-interleaved signal converter, the method comprising: receiving a plurality of output sampled signals from a plurality of ADCs sampling an input signal at a common rate and at differing phases; performing an autocorrelation of a digital output signal combined from the plurality of output sampled signals; performing a cross-correlation of a pair of output sampled signals from a corresponding pair of the plurality of ADCs; and determining a timing error from a comparison of the autocorrelation with the cross-correlation.

9. The method of claim 8 further comprising the step of adjusting a phase at which one of the pair of ADCs samples the input signal so as to reduce the timing error.

10. The method of claim 9 wherein the timing error is reduced by adjusting one or more adjustable time delay elements connected to a respective one of the plurality of ADCs.

1 1. The method of claim 8 wherein the autocorrelation and cross-correlation are performed and compared by a digital processing unit connected to an output from each of the plurality of ADCs.

12. The method of claim 11 wherein the output signals from each of the plurality of ADCs are filtered by a digital filter situated between and connected to the plurality of ADCs and the digital processing unit, the digital filter suppressing frequency components at one or more integer fractions of the sampling rate.

13. The method of claim 8 wherein the input signal is filtered by a programmable filter connected to an input of the signal converter.