CN103312329A - Correcting method and corrector used for sampling time mismatch of time-interweaving ADC (analog to digital converter) - Google Patents

Abstract

The present invention relates to microelectric techniques, particularly relate to a kind of time-interleaved analog-digital converter (ADC), more particularly to for time-interleaved ADC sampling time mismatch bearing calibration and corrector. Method of the present invention: mainly being made the difference by the numeral output to time-interleaved ADC adjacency channel, and residual quantity Ei [k] is acquired, and characterizes the actual samples time slot between adjacency channel with the mean value Ai after the summation of its absolute value, The standard sample time slot between adjacency channel is characterized, is passed through Each channel sample time mismatch amount is obtained, relative error Bi is filtered through AAR finally and eliminates statistical error, clock generating unit is fed back to after summation and adjusts channel sample clock, to realize the negative-feedback regu- lation of sampling time mismatch. Beneficial effects of the present invention are that can effectively improve and guarantee the performance of the time-interleaved analog-digital converter of multichannel, and have the advantages that complexity is low, hardware spending is small and is easily achieved. Present invention is particularly suitable for high-speed low-power-consumption analog-to-digital conversions.

Description

Bearing calibration and adjuster for time-interleaved ADC sampling time mismatch

Technical field

The present invention relates to microelectric technique, relate to specifically a kind of time-interleaved analog to digital converter (ADC), particularly relate to bearing calibration and adjuster for time-interleaved ADC sampling time mismatch.

Background technology

Along with the continuous progress of integrated circuit fabrication process, at a high speed, the digital circuit of high integration obtained the development of advancing by leaps and bounds, digital signal processing capability constantly strengthens.In order to meet the demand of high-speed digital circuit, the speed that how to improve analog to digital converter becomes the focus that integrated circuit (IC) design person pays close attention to.

A kind of a plurality of analog to digital converters are together in parallel, and the A/D conversion system that utilizes staggered clock that it is taken turns to operate is by extensive concern.Its feature is to be operated in lower frequency in the situation that maintain each sub-adc converter, makes whole speed get a promotion, and therefore is called as time-interleaved analog to digital converter (Time-interleaved ADC).

M channel time interweave analog to digital converter basic structure as shown in Figure 1, each passage comprises a sampling switch and a sub-ADC, operating frequency is f _s/ M, by staggered coming of the sampling time by each channel sample switch, make the operating frequency of whole system be increased to f _s(work period T _s=1/f _s), thereby improve the speed of time-interleaved analog to digital converter.

In theory, port number is more, and the operating rate of time-interleaved analog to digital converter is faster.But, in fact, there are the non-ideal factors such as sampling time mismatch (Timing mismatch), gain mismatch (Gain mismatch), imbalance mismatch (Offset mismatch) and bandwidth mismatch (Bandwidth mismatch) between each passage sub-adc converter, had a strong impact on the dynamic property of whole analog to digital converter.

Summary of the invention

Technical problem to be solved by this invention is to propose a kind of bearing calibration and adjuster for time-interleaved ADC sampling time mismatch.

The present invention solves the problems of the technologies described above adopted technical scheme: the bearing calibration for time-interleaved ADC sampling time mismatch, it is characterized in that, and comprise the following steps:

A. time-interleaved ADC is changed input signal;

B. obtain the sampling time gap between adjacency channel ADC according to the numeral output of time-interleaved each passage of ADC;

C. obtain the sampling time gap between all adjacency channel ADC, and obtain the standard sample time slot between adjacency channel ADC according to all sampling time gaps;

D. obtain the amount of mismatch of each channel sample time according to sampling time gap and the standard sample time slot of each passage;

E. amount of mismatch is fed back to clock generating unit, regulate the sampling clock of respective channel.

Concrete, step b also comprises:

B1. the adjacency channel ADC numeral output collected is asked to poor .

suppose to gather for incoming frequency be f _insinusoidal signal x (t), produce each passage numeral and be output as: Y=[y ₁[k], y ₂[k] ..., y _m[k]] (k=1,2 ..., P), the total number of channels that wherein M is time-interleaved ADC, P means the single channel sampling number, to adjacency channel ADC numeral, output asks difference to be: $\left\{\begin{array}{c}{E}_1\left[k\right]=y_2\left[k\right]-y_1\left[k\right]\\ E_2\left[k\right]=y_3\left[k\right]-y_2\left[k\right]\\ {\·\·\·\·\·\·}_{}\\ E_M\left[k\right]=y_1[k+1]-y_M\left[k\right],\end{array}\right.$ (k=1,2,…,P)；

B2. the difference E to obtaining _ithe absolute value summation of [k] is averaged and obtains A _i, A _ibe characterized by the sampling time gap between adjacency channel ADC, $A_i=\stackrel{\‾}{{|E}_i|}=\frac{1}{P}\underset{k=1}{\overset{N}{\mathrm{\Σ}}}\left|E_i\right[k\left]\right|$ (i=1,2,…,M)。

Concrete, step c also comprises: to all A _isummation is averaged and obtains

(i=1,2 ..., M), be characterized by the standard sample time slot between adjacency channel ADC.

Concrete, steps d also comprises: to all A _iwith

it is poor to do, and obtains:

$B_i=A_i-\stackrel{\‾}{A}$

$=\stackrel{\‾}{\left|E_i\right|}-\frac{1}{4}\underset{i=1}{\overset{4}{\mathrm{\Σ}}}\stackrel{\‾}{\left|E_i\right|}$

B _ifor the relative error of sampling time gap between adjacency channel ADC and standard sample time slot, i.e. each channel sample time mismatch amount.

Concrete, step e also comprises: by relative error B _ieliminate statistical error through cumulative sum replacement module filtered, feed back to vairable delay line after summation and regulate the channel sample clock, realize that the negative feedback of sampling time mismatch is regulated.

Be used for the adjuster of the bearing calibration of time-interleaved ADC sampling time mismatch, comprise time-interleaved ADC, data processing unit, feedback unit and clock unit, described data processing unit is connected with feedback unit with time-interleaved ADC respectively,

Described data processing unit is processed in real time to the output data of time-interleaved ADC, and the data after processing are outputed to feedback unit;

The data that described feedback unit transmits according to data processing unit, carry out feedback operation, and signal feedback is arrived to the clock unit.

Beneficial effect of the present invention is can effectively improve and guarantee the performance of the time-interleaved analog to digital converter of multichannel, and have advantages of that complexity is low, hardware spending is little and be easy to realize.

The accompanying drawing explanation

Fig. 1 is the interweave schematic diagram of analog to digital converter of traditional M channel time;

The schematic flow sheet that Fig. 2 is method of the present invention;

Fig. 3 is the M channel time ADC sample graph that interweaves;

The schematic diagram that Fig. 4 is the time-interleaved analog to digital converter of traditional four-way;

Fig. 5 is the time-interleaved ADC transformation curve of four-way;

Fig. 6 is not for existing the E of sampling time during mismatch _i(i=1,2,3,4) distribution map;

There is the E of sampling time during mismatch in Fig. 7 _i(i=1,2,3,4) distribution map;

Fig. 8 is A _i(i=1,2,3,4) and △ T/T _sfunctional relation;

The sampling time mismatch repair loop that Fig. 9 designs for the present invention;

Figure 10 is B _ithe analogous diagram restrained after overcorrect;

Figure 11 is the SNR figure before proofreading and correct;

Figure 12 is the SNR figure after proofreading and correct.

Embodiment

Below according to drawings and embodiments, the present invention is described in further detail:

It is poor that the present invention does by the output of the numeral to time-interleaved ADC adjacency channel, tries to achieve residual quantity E _i[k], with the average A after its absolute value summation _icharacterize the actual samples time slot between adjacency channel,

characterize the standard sample time slot between adjacency channel, therefore

obtain each channel sample time mismatch amount, finally by relative error B _ieliminate statistical error through AAR filtering, feed back to clock generating unit adjusting channel sample clock after summation, thereby realize the negative feedback adjusting of sampling time mismatch.

The key step of method of the present invention is as shown in Figure 2:

1, incoming frequency is f _insinusoidal signal x (t), time-interleaved ADC carries out normal conversion to x (t), produces each passage numeral output Y=[y ₁[k], y ₂[k] ..., y _m[k]] (k=1,2 ..., P) as shown in Figure 3.The total number of channels that wherein M is time-interleaved ADC, P means the single channel sampling number.

2, to adjacency channel ADC numeral output do poor, $\left\{\begin{array}{c}{E}_1\left[k\right]=y_2\left[k\right]-y_1\left[k\right]\\ E_2\left[k\right]=y_3\left[k\right]-y_2\left[k\right]\\ {\·\·\·\·\·\·}_{}\\ E_M\left[k\right]=y_1[k+1]-y_M\left[k\right]\end{array}\right.$ (k=1,2,…,P)；

3, to difference E _ithe absolute value summation of [k] is averaged and obtains A _i, in order to characterize the sampling time gap between adjacency channel ADC, $A_i=\stackrel{\‾}{\left|E_i\right|}=\frac{1}{P}\underset{k=1}{\overset{N}{\mathrm{\Σ}}}\left|E_i\right[k\left]\right|$ (i=1,2,…,M)；

4, to all A _isummation is averaged and obtains

(i=1,2 ..., M), in order to characterize standard sample time slot between adjacency channel ADC;

5, according to the above-mentioned A tried to achieve _iwith

by all A _iwith

it is poor to do,

$B_i=A_i-\stackrel{\‾}{A}$

$=\stackrel{\‾}{\left|E_i\right|}-\frac{1}{4}\underset{i=1}{\overset{4}{\mathrm{\Σ}}}\stackrel{\‾}{\left|E_i\right|}$

Obtain the relative error B of actual samples time slot and standard sample time slot between adjacency channel ADC _ithereby, symbolize each channel sample time mismatch amount.

6, by relative error B _ithrough the AAR(cumulative sum, reset) module filtered elimination statistical error, finally feed back to vairable delay line adjusting channel sample clock after summation, thereby realize the negative feedback adjusting of sampling time mismatch.

Embodiment:

The time-interleaved ADC of the four-way of take is example, and as shown in Figure 4, its operation principle is: the sampling that four clocks that produced by DLL are given respectively four passages keeps module, and makes staggered the coming of operating time of the sampling maintenance module of each passage.Passage ADC will sample, and to convert frequency to be f for the output that keeps module _s/ 8, the digital word of N position (wherein, f _ssample frequency for whole time-interleaved ADC).The output of passage ADC is delivered in multiplexer, and converting the output of each passage ADC to frequency by multiplexer is f _s/ 2 N bit digital output.

When interchannel does not exist the sampling time during mismatch, as shown in the solid line of vertical line in Fig. 5.Order:

$\left\{\begin{array}{c}{E}_1\left[k\right]=y_2\left[k\right]-y_1\left[k\right]\\ E_2\left[k\right]=y_3\left[k\right]-y_2\left[k\right]\\ E_3\left[k\right]=y_4\left[k\right]-y_3\left[k\right]\\ E_4\left[k\right]=y_1[k+1]-y_4\left[k\right]\end{array}\right.$

Due to life period mismatch not, E _ithe distribution of (i=1,2,3,4) should be as shown in Figure 6.According to Statistics, its mean value $A_i=\stackrel{\‾}{{|E}_i|}$ (i=1,2,3,4) should equate.

When life period mismatch △ T, situation shown in dotted lines in Figure 5 for example.The actual samples time of second channel, than ideal time advance, makes the one or two interchannel sampling interval T ₁reduce the sampling interval T between the second triple channel ₂increase, and its

He is constant the sampling interval of two adjacency channels.Due to T ₁reduce E ₁will reduce, and cause its mean value A ₁also reduce.In contrast, T ₂increase can make E ₂increase, and cause its mean value A ₂also increase.And E ₃, E ₄because of its sampling interval constant, its mean value A ₃, A ₄do not change yet.

Simulation result when there is sampling time mismatch △ T in second channel as shown in Figure 7.Comparison diagram 6 and Fig. 7 can find, due to life period mismatch △ T, E ₁and E ₂with respect to E ₃with E ₄skew has appearred.

Fig. 8 is by A _i(i=1,2,3,4) are depicted as △ T/T _sfunction, T wherein _sfor the sampling period of time-interleaved ADC.Due to the time mismatch of second channel to A ₃, A ₄not impact, A ₃, A ₄remain unchanged.And A ₁and A ₂respectively along with the variation of △ T, dull increase and reducing.Because $\stackrel{\&OverBar;}{A}=\frac{1}{4}\underset{i=1}{\overset{4}{\mathrm{\&Sigma;}}}{A}_i$ Remain unchanged, ${\mathrm{<figure-callout\; id="1"\; label="B"\; filenames="HDA00003236463600031.png,HDA00003236463600052.png"\; state="\{\{state\}\}">B</figure-callout>}}_1=A_1-\stackrel{\&OverBar;}{A}$ Be less than zero, ${\mathrm{<figure-callout\; id="2"\; label="B"\; filenames="HDA00003236463600011.png,HDA00003236463600032.png"\; state="\{\{state\}\}">B</figure-callout>}}_2=A_2-\stackrel{\&OverBar;}{A}$ Be greater than zero,

with all with

increase and increase.Visible, the sampling time mismatch can be passed through B _icharacterized and quantized.

According to above-mentioned principle, we have proposed a kind of digital Background calibration method of time-interleaved ADC sampling time mismatch.

As shown in Figure 9, by DLL, produce four phase clocks, deliver on each passage ADC via delay cell respectively.Passage ADC carries out sample conversion to simulation output and obtains numeral output y ₁[k] (i=1,2,3,4).To adjacency channel numeral output do poor:

$\left\{\begin{array}{c}{E}_1\left[k\right]=y_2\left[k\right]-y_1\left[k\right]\\ E_2\left[k\right]=y_3\left[k\right]-y_2\left[k\right]\\ E_3\left[k\right]=y_4\left[k\right]-y_3\left[k\right]\\ E_4\left[k\right]=y_1[k+1]-y_4\left[k\right]\end{array}\right.$

K is the sampling period.To E _ibe averaging and obtain

(i=1,2,3,4), in order to characterize interchannel actual samples time slot.Because

keep constant, so in order to characterize interchannel standard sample time slot.Therefore, relative error amount characterize and quantized interchannel relative sampling time mismatch.Utilize subsequently the AAR(cumulative sum to reset) module, the filtering statistical error is to B _iimpact.Again through the cumulative summation of ACC() module carries out the cumulative sum maintenance to error, output digital code C _i(i=1,2,3,4) carry out the time of delay of feedback regulation respective channel delay cell, thereby reduce the sampling time mismatch.

In order to verify this figure adjustment algorithm, utilize Matlab to build behavioral scaling model.Utilize Gaussian Profile (u=0, σ=0.01T _s), four-way sampling time mismatch is set and is followed successively by 9.6ps ,-8.2ps, 12.5ps and 5.5ps.

Figure 10 shows that the convergence process of each channel sample mismatch time.At initial time, each passage has maximum amount of mismatch, and along with the carrying out of proofreading and correct, mismatch reduces gradually, finally goes to zero.

Figure 11, Figure 12 are respectively the signal noise harmonic ratio (SNDR) of the time-interleaved ADC before and after proofreading and correct.As shown in figure 11, before correction,

with

the frequency place, because the sampling time mismatch causes high-octane harmonic wave, SNDR is only 59.7dB, number of significant digit (ENOB) is 9.62bits; As shown in figure 12, after proofreading and correct, above-mentioned harmonic wave is suppressed fully, and SNDR increases to 73.8dB, and ENOB is 11.96bits.

Claims (6)

1. for the bearing calibration of time-interleaved ADC sampling time mismatch, it is characterized in that, comprise the following steps:

A. time-interleaved ADC is changed input signal;

B. obtain the sampling time gap between adjacency channel ADC according to the numeral output of time-interleaved each passage of ADC;

C. obtain the sampling time gap between all adjacency channel ADC, and obtain the standard sample time slot between adjacency channel ADC according to all sampling time gaps;

D. obtain the amount of mismatch of each channel sample time according to sampling time gap and the standard sample time slot of each passage;

E. amount of mismatch is fed back to clock generating unit, regulate the sampling clock of respective channel.

2. the bearing calibration for time-interleaved ADC sampling time mismatch according to claim 1, is characterized in that, step b also comprises:

B1. to the adjacency channel ADC that collects numeral, output asks poor, suppose collection for incoming frequency be f _insinusoidal signal x (t), produce each passage numeral and be output as: Y=[y ₁[k], y ₂[k] ..., y _m[k]] (k=1,2 ..., P), the total number of channels that wherein M is time-interleaved ADC, P means the single channel sampling number, to adjacency channel ADC numeral, output asks difference to be:

$\left\{\begin{array}{c}{E}_1\left[k\right]=y_2\left[k\right]-y_1\left[k\right]\\ E_2\left[k\right]=y_3\left[k\right]-y_2\left[k\right]\\ {\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;}_{}\\ E_M\left[k\right]=y_1[k+1]-y_M\left[k\right],\end{array}\right.$ (k＝1，2，…，P）；

B2. the difference E to obtaining _ithe absolute value summation of [k] is averaged and obtains A _i, A _ibe characterized by the sampling time gap between adjacency channel ADC, $A_i=\stackrel{\&OverBar;}{\left|E_i\right|}=\frac{1}{P}\underset{k=1}{\overset{N}{\mathrm{\&Sigma;}}}\left|E_i\right[k\left]\right|$ (i＝1，2，…，M)。

3. the bearing calibration for time-interleaved ADC sampling time mismatch according to claim 2, is characterized in that, step c also comprises: to all A _isummation is averaged and obtains

(i=1,2 ..., M),

be characterized by the standard sample time slot between adjacency channel ADC.

4. the bearing calibration for time-interleaved ADC sampling time mismatch according to claim 3, is characterized in that, steps d also comprises: to all A _iwith

it is poor to do, and obtains:

$B_i=A_i-\stackrel{\&OverBar;}{A}$

$=\stackrel{\&OverBar;}{\left|E_i\right|}-\frac{1}{4}\underset{i=1}{\overset{4}{\mathrm{\&Sigma;}}}\stackrel{\&OverBar;}{\left|E_i\right|}$

B _ifor the relative error of sampling time gap between adjacency channel ADC and standard sample time slot, i.e. each channel sample time mismatch amount.

5. the bearing calibration for time-interleaved ADC sampling time mismatch according to claim 4, is characterized in that, step e also comprises: by relative error B _ieliminate statistical error through cumulative sum replacement module filtered, feed back to vairable delay line after summation and regulate the channel sample clock.

6. for the adjuster of the bearing calibration of time-interleaved ADC sampling time mismatch as claimed in claim 1, comprise time-interleaved ADC, data processing unit, feedback unit and clock unit, described data processing unit is connected with feedback unit with time-interleaved ADC respectively

Described data processing unit is processed in real time to the output data of time-interleaved ADC, and the data after processing are outputed to feedback unit;

The data that described feedback unit transmits according to data processing unit, carry out feedback operation, and signal feedback is arrived to the clock unit.

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