CN114244360A - Analog domain compensation circuit for time-interleaved ADC - Google Patents
Analog domain compensation circuit for time-interleaved ADC Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
- H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
- H03M1/1023—Offset correction
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
- H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing
Abstract
The invention belongs to the technical field of integrated circuits, and particularly relates to an analog domain compensation circuit for a time-interleaved ADC (analog to digital converter). According to the invention, the parallel MOS capacitor array is used as a variable capacitor to adjust the sampling time of each channel of the time-interleaved ADC, and the fifth MOS capacitor (M5) is introduced as a redundant bit when the MOS capacitor array is coded, so that the accurate compensation of the sampling time deviation of the time-interleaved ADC is effectively realized. The biggest innovation point of the structure is the addition of a fifth MOS capacitor (M5) of the redundant bit capacitor, the strict proportional relation needs to be met between the capacitor arrays of the traditional compensation circuit to ensure that the sampling time deviation after compensation can be accurately converged, however, in an actual chip, due to layout and process deviation, the multiple relation between the capacitor arrays is difficult to ensure, the redundant bit capacitor leaves margins for the problems, and the problem is effectively solved.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to an analog domain compensation circuit for a time-interleaved ADC (analog to digital converter).
Background
A method for compensating for the sampling time deviation of a time-interleaved ADC is shown in FIG. 1. A digital calibration module collects the output data of the time-interleaved ADC and uses the correlationThe algorithm calculates the direction of the sampling time deviation needing to be compensated, and then generates corresponding seventh to first digital control codes D7-D1 according to the sequence and feeds the codes back to an analog domain compensation circuit in the clock generation module to adjust the sampling time deviation, such as: the direction (positive or negative delay) of the sampling time needing to be adjusted when the digital module obtains the first round of compensation after the first round of calculation is fed back to the circuit through the seventh digital control code D7, and in this way, when the seventh to the first digital control codes D7-D1 are all adjusted, the multiphase sampling clock provided by the clock generation module to the ADC is corrected. Fig. 2 is a common analog domain compensation circuit, the size of adjacent MOS capacitors has a double relationship, and the offset value of the capacitor array satisfying this relationship can converge within the minimum step length of the MOS capacitor array at the sampling time after multiple rounds of compensation. The compensation method is a dichotomy searching value, the compensation size of the lowest position is t, and the step length from the lowest position to the highest position is t, 2t and 22t、23t、24t、25t、26t, each step can be adjusted in positive direction or negative direction, and the compensation range of the capacitor array is (-2)7t，27t) with a maximum range deviation of 27t is taken as an example, the feedback of the digital calibration module in the deviation for each round is delayed and compensated, and the deviation value after final compensation is 27t-26t-25t-24t-23t-22t-2t-t, converges to the minimum step size, and in fact for any deviation in the compensation range, the array can converge to the minimum step size.
However, the influence of mismatching of the MOS capacitor array is not considered in the conventional structure, in the actual chip design and manufacture, random mismatching of each MOS capacitor is generated so as to deviate from the original set value, the size of the adjacent MOS capacitor does not satisfy the strict two-fold relation any more, and thus Δ t is generated between the delay adjustment step length of each MOS capacitor and the original valuemisThe absolute value of the deviation has a certain proportional relation with the compensation of the corresponding MOS capacitor, and the larger the step length of the MOS capacitor is, the delta tmisThe larger the absolute value, but Δ tmisIs random (may be positive or negative), and takes into account this effect, from lowest to highestThe actual step size of the bit is t, 2t + delta tmis2、22t+Δtmis3、23t+Δtmis4、24t+Δtmis5、25t+Δtmis6、26t+Δtmis7. Maximum range deviation 2 if it is also maximum range deviation7t, the deviation value after convergence is finished is t + delta tmis7-Δtmis6-Δtmis5-Δtmis4-Δtmis3-Δtmis2Due to each Δ tmisIs not determined, and in an extreme case, the deviation of the sampling time after compensation is t + | Deltatmis7|+|Δtmis6|+|Δtmis5|+|Δtmis4|+|Δtmis3|+|Δtmis2Far from the target convergence value, greatly impairing the performance of the entire system.
Disclosure of Invention
Aiming at the problems, the invention provides a novel analog domain compensation circuit for calibrating the sampling time deviation of the time-interleaved ADC, a redundant bit MOS capacitor is introduced, when the MOS capacitor array generates mismatch, the larger the influence of the mismatch of the MOS capacitor on the overall convergence is, the influence of the subsequent MOS capacitor is eliminated through the redundant bit MOS capacitor, the mismatch part is compensated, and the accurate convergence of the sampling time deviation is finally realized.
The technical scheme of the invention is as follows:
an analog domain compensation circuit for a time-interleaved ADC is used for ADC sampling time deviation calibration, wherein ADC output data is input into a digital calibration module, a digital control code generated by the digital calibration module is fed back to a corresponding compensation bit of the analog domain compensation circuit in a clock generation module to adjust sampling time deviation, and the clock generation module is used for providing a clock signal for the ADC; the analog domain compensation circuit is characterized by comprising a first inverter inv1, a second inverter inv2, a first MOS capacitor M1, a second MOS capacitor M2, a third MOS capacitor M3, a fourth MOS capacitor M4, a fifth MOS capacitor M5, a sixth MOS capacitor M6, a seventh MOS capacitor M7 and an eighth MOS capacitor M8; wherein the gates of the first MOS capacitor M1, the second MOS capacitor M2, the third MOS capacitor M3, the fourth MOS capacitor M4, the fifth MOS capacitor M5, the sixth MOS capacitor M6, the seventh MOS capacitor M7, and the eighth MOS capacitor M8 are all connected to form a MOS capacitor array, the source-drain of each MOS capacitor is interconnected and then connected to the digital control code (D1-D8) generated by the digital calibration module, specifically, the source-drain of the first MOS capacitor M1 is connected to the first digital control code (D1), the source-drain of the second MOS capacitor M2 is connected to the second digital control code (D2), the source-drain of the third MOS capacitor M3 is connected to the third source-drain digital control code (D3), the source-drain of the fourth MOS capacitor M4 is connected to the fourth digital control code (D4), the source-drain of the fifth MOS capacitor M5 is connected to the fifth digital control code (D5), the source-drain of the sixth MOS capacitor M2 is connected to the sixth source-drain of the seventh MOS capacitor M8656 (D828653), the source drain electrode of the eighth MOS capacitor M8 is connected with the eighth digital control code word (D8);
the input end of the first inverter inv1 is connected with a preceding-stage clock signal, the output end of the first inverter inv1 is connected with the grid of the MOS capacitor array and the input end of the second inverter inv2, and the output end of the second inverter inv2 is connected with a following-stage clock path;
the fifth MOS capacitor M5 is a redundant bit capacitor, and is the same as the sixth MOS capacitor M6 in size.
The fifth MOS capacitor M5 is used as a redundant bit capacitor and is connected with the rest MOS capacitors in parallel, the grid electrode is connected with the output end of the first inverter inv1 and the input end of the second inverter inv1, the source electrode is in short circuit with the drain electrode, and then the fifth MOS capacitor M5 is connected with the digital control code word D5, and the size of the digital control code word is equal to that of the sixth MOS capacitor M6. When the MOS capacitor array generates mismatch, the larger MOS capacitor has larger influence on the overall convergence due to the mismatch, so the invention places the redundancy bit MOS capacitor at the fifth MOS capacitor M5 to eliminate the influence of the eighth, seventh and sixth MOS capacitors (M8, M7 and M6). If the eighth, seventh and sixth MOS capacitors (M8, M7 and M6) have large mismatch, the introduced redundancy bit fifth MOS capacitor M5 can compensate the mismatch, and finally, accurate convergence of the sampling time deviation is achieved. The actual step length of the structure from the lowest to the highest position is t, 2t + delta tmis2、22t+Δtmis3、23t+Δtmis4、24t+Δtmis5、24t+Δtmis6、25t+Δtmis7、26t+Δtmis8. The larger the known step sizeBit Δ t ofmisThe larger the bit, the smaller the step size is, relatively speaking, Δ tmisNeglect, to simplify the analysis, the three rounds of compensation, D8, D7, D6, were analyzed first. These three rounds of post-compensation Δ t regardless of any inputmisThe maximum influence is | Delta tmis8|+|Δtmis7|+|Δtmis6I, then the maximum sampling time error 2 is calculated for the previous three rounds of compensation7t, the residual error after the first three rounds of compensation is 24t+|Δtmis8|+|Δtmis7|+|Δtmis6If there are no redundant bits, the step length of the subsequent compensation rounds is 23t、22t, 2t, the compensation range is (-2)4t，24t) is insufficient to correct the remaining errors, and in the presence of redundant bits, the subsequent remaining compensation round steps are each 24t、23t、22t, 2t, the compensation range is (-2)5t，25t), completely covering the error range at this time, and realizing convergence. Therefore, the addition of the redundant bit ensures that the sampling time error can be accurately converged under the condition that the actual capacitor array has mismatch.
The invention has the beneficial effects that: the sampling time of each channel of the time-interleaved ADC is adjusted by adopting the MOS capacitor arrays connected in parallel as variable capacitors, and the accurate compensation of the sampling time deviation of the time-interleaved ADC is effectively realized by introducing a fifth MOS capacitor M5 as a redundant bit when the MOS capacitor arrays are coded; the biggest innovation point of the invention is the addition of a fifth MOS capacitor M5 of the redundant bit capacitor, and the traditional compensation circuit capacitor arrays need to meet strict proportional relation to ensure that the sampling time deviation after compensation can be accurately converged.
Drawings
FIG. 1 is a schematic diagram of a time-interleaved ADC sampling time offset compensation method;
FIG. 2 is a conventional analog domain compensation circuit;
fig. 3 is an analog domain compensation circuit according to the present invention.
Detailed Description
The technical scheme of the invention is described in detail in the following with the accompanying drawings:
the method for compensating the sampling time offset of the time-interleaved ADC is shown in fig. 1, in each round of calibration, the digital calibration module acquires output data of the time-interleaved ADC, processes the data by using a correlation algorithm to obtain a direction (forward or backward delay) to be compensated for the sampling time offset, then generates a corresponding digital control code, feeds the digital control code back to a corresponding compensation bit (as shown in fig. 2D7) of an analog domain compensation circuit in the clock generation module to adjust the sampling time offset, and at this time, completes one round of compensation. Fig. 2 is a conventional analog domain compensation circuit, which has twice the size of adjacent MOS capacitors, and the MOS capacitor array contains 7 bits in total, so when the circuit is used for compensation, a total of 7 rounds are required, the sequence is from D7 to D1, and after the D1 compensation is completed, the sampling time deviation will converge to the expected value. However, in practice, the capacitor arrays have mismatch and cannot satisfy a strict 2-fold relationship, and the conventional compensation circuit structure is difficult to converge to an expected value in consideration of the influence.
The invention provides an analog domain compensation circuit for calibrating sampling time deviation of a time-interleaved ADC (analog to digital converter). the analog domain compensation circuit comprises a first inverter inv1, a second inverter inv2, a first MOS capacitor M1, a second MOS capacitor M2, a third MOS capacitor M3, a fourth MOS capacitor M4, a fifth MOS capacitor M5, a sixth MOS capacitor M6, a seventh MOS capacitor M7 and an eighth MOS capacitor M8, and is characterized in that the fifth MOS capacitor M5 is used as a redundant bit capacitor and has the same size as the sixth MOS capacitor M6 and comprises 16 sub-unit MOS capacitors.
The input end of the first inverter inv1 is connected with a preceding stage output clock, and the output end of the first inverter inv1 is connected with the grid of the capacitor MOS capacitor array and the input end of the second inverter inv 1;
the input end of the second inverter inv2 is connected with the output end of the first inverter inv1 and the grid of the MOS capacitor array, and the output end of the second inverter inv2 is connected with the rear-stage clock path;
the grid of the first MOS capacitor M1 is connected with the output end of the first inverter inv1 and the input end of the second inverter inv1, the source electrode and the drain electrode are in short circuit, and then the first MOS capacitor M1 is connected with the first digital control code word D1;
the grid of the second MOS capacitor M2 is connected with the output end of the first inverter inv1 and the input end of the second inverter inv1, the source electrode is in short circuit with the drain electrode, and then the second MOS capacitor M2 is connected with the second digital control code word D2;
the grid electrode of the third MOS capacitor M3 is connected with the output end of the first inverter inv1 and the input end of the second inverter inv1, the source electrode and the drain electrode are in short circuit, and then the third MOS capacitor M3 is connected with the third digital control code word D3;
the grid electrode of the fourth MOS capacitor M4 is connected with the output end of the first inverter inv1 and the input end of the second inverter inv1, the source electrode is in short circuit with the drain electrode, and then the fourth MOS capacitor M4 is connected with the fourth digital control code word D4;
the grid electrode of the fifth MOS capacitor M5 is connected with the output end of the first inverter inv1 and the input end of the second inverter inv1, the source electrode is in short circuit with the drain electrode, and then the fifth MOS capacitor M5 is connected with the fifth digital control code word D5;
the gate of the sixth MOS capacitor M6 is connected to the output terminal of the first inverter inv1 and the input terminal of the second inverter inv1, the source is short-circuited with the drain, and then connected to the sixth digital control codeword D6;
the grid electrode of the seventh MOS capacitor M7 is connected with the output end of the first inverter inv1 and the input end of the second inverter inv1, the source electrode is in short circuit with the drain electrode, and then the seventh MOS capacitor M7 is connected with the seventh digital control code word D7;
the gate of the eighth MOS capacitor M8 is connected to the output terminal of the first inverter inv1 and the input terminal of the second inverter inv1, the source is short-circuited with the drain, and then connected to the eighth digital control codeword D8;
the method for compensating the sampling time offset of the time-interleaved ADC is shown in fig. 1, in each round of calibration, the digital calibration module acquires output data of the time-interleaved ADC, processes the data by using a correlation algorithm to obtain a direction (forward or backward delay) to be compensated for the sampling time offset, then generates a corresponding digital control code, feeds the digital control code back to a corresponding compensation bit (as shown in fig. 2D7) of an analog domain compensation circuit in the clock generation module to adjust the sampling time offset, and at this time, completes one round of compensation. Fig. 2 shows a conventional analog domain compensation circuit, in which the sizes of adjacent MOS capacitors are doubled, and the MOS capacitor array contains 7 bits in total, so when the circuit is used for compensation, a total of 7 rounds are required, the sequence is from the seventh MOS capacitor M7 controlled by the seventh digital control codeword D7 to the first MOS capacitor M1 controlled by the first digital control codeword D1, and after the compensation of the first MOS capacitor M1 is completed, the deviation of the sampling time will converge to the desired value. However, in practice, the capacitor arrays have mismatch and cannot satisfy a strict 2-fold relationship, and the conventional compensation circuit structure is difficult to converge to an expected value in consideration of the influence.
In order to avoid the problem that the traditional circuit structure can not be converged to an expected value, the invention adopts a novel analog domain compensation circuit for mismatch of sampling time of the time-interleaved ADC, a fifth MOS capacitor M5 is used as a redundant bit capacitor and is connected with the rest MOS capacitors in parallel, the grid is connected with the output end of a first inverter inv1 and the input end of a second inverter inv1, the source is in short circuit with the drain, and then is connected with a fifth digital control code word D5, so that the influence of mismatch of the eighth, seventh and sixth MOS capacitors (M8, M7 and M6) is solved, the precision of the compensation circuit is improved, and the accurate convergence of sampling time deviation is realized.
In summary, the invention provides a novel analog domain compensation circuit structure for eliminating the influence of capacitor array mismatch by using a redundant bit, and a fifth MOS capacitor M5 is used as a redundant bit capacitor and connected in parallel with the remaining MOS capacitors, so that the influence of capacitor array mismatch is effectively eliminated and the convergence accuracy of the analog domain compensation circuit is ensured, aiming at the problems that the final compensation accuracy is poor and the sampling time deviation cannot be accurately converged due to the fact that a time deviation analog domain compensation circuit adopted by a traditional time-interleaved ADC is mismatched.
Claims (1)
1. An analog domain compensation circuit for a time-interleaved ADC is used for ADC sampling time deviation calibration, wherein ADC output data is input into a digital calibration module, a digital control code generated by the digital calibration module is fed back to a corresponding compensation bit of the analog domain compensation circuit in a clock generation module to adjust sampling time deviation, and the clock generation module is used for providing a clock signal for the ADC; the analog domain compensation circuit is characterized by comprising a first inverter (inv1), a second inverter (inv2), a first MOS capacitor (M1), a second MOS capacitor (M2), a third MOS capacitor (M3), a fourth MOS capacitor (M4), a fifth MOS capacitor (M5), a sixth MOS capacitor (M6), a seventh MOS capacitor (M7) and an eighth MOS capacitor (M8); wherein the gates of the first MOS capacitor (M1), the second MOS capacitor (M2), the third MOS capacitor (M3), the fourth MOS capacitor (M4), the fifth MOS capacitor (M5), the sixth MOS capacitor (M6), the seventh MOS capacitor (M7) and the eighth MOS capacitor (M8) are all connected to form an MOS capacitor array, the source drain of each MOS capacitor is connected with a digital control code (D1-D8) generated by the digital calibration module, specifically, the source drain of the first MOS capacitor (M1) is connected with the first digital control codeword (D1), the source drain of the second MOS capacitor (M2) is connected with the second digital control codeword (D2), the source drain of the third MOS capacitor (M84) is connected with the third digital control codeword (D3), the source drain of the fourth MOS capacitor (M4) is connected with the fourth digital control codeword (D4), the source drain of the fifth MOS capacitor (M5) is connected with the fifth MOS capacitor (M375) and the sixth MOS capacitor (M5857323), the source drain electrode of the seventh MOS capacitor (M7) is connected with the seventh digital control code word (D7), and the source drain electrode of the eighth MOS capacitor (M8) is connected with the eighth digital control code word (D8);
the input end of the first inverter (inv1) is connected with a preceding-stage clock signal, the output end of the first inverter (inv1) is connected with the gate of the MOS capacitor array and the input end of the second inverter (inv2), and the output end of the second inverter (inv2) is connected with a following-stage clock path;
the fifth MOS capacitor (M5) is a redundant bit capacitor and has the same size as the sixth MOS capacitor (M6).
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