CN112152624A

CN112152624A - Compensation device and method, storage medium and electronic device

Info

Publication number: CN112152624A
Application number: CN201910580422.3A
Authority: CN
Inventors: 张骏凌; 邬钢
Original assignee: Sanechips Technology Co Ltd
Current assignee: Sanechips Technology Co Ltd
Priority date: 2019-06-28
Filing date: 2019-06-28
Publication date: 2020-12-29

Abstract

The invention provides a compensation device, a compensation method, a storage medium and an electronic device, wherein the compensation device comprises: a time-interleaved analog-to-digital converter (TIADC) configured to receive an input signal and output an output signal; the compensation module is configured to acquire first estimation information at a time n-a and second estimation information at a time n-b at the time n, and acquire third estimation information according to the first estimation information and the second estimation information, wherein the third estimation information is used for indicating the compensation module to compensate the output signal of the TIADC at a time n +1 according to the third estimation information; the invention solves the technical problem that the sampling clock mismatch estimator can not carry out effective error estimation and compensation according to the frequency change of the input signal of the TIADC when carrying out mismatch error estimation and compensation in the related technology, thereby achieving the effect that the sampling clock mismatch estimator can be self-adaptive to the frequency change of the input signal of the TIADC.

Description

Compensation device and method, storage medium and electronic device

Technical Field

The present invention relates to the field of electronics, and in particular, to a compensation apparatus and method, a storage medium, and an electronic apparatus.

Background

A Time-interleaved Analog-to-Digital Converter (TIADC) is composed of M parallel sub-ADCs, or subchannels; FIG. 1 is a schematic diagram of an M-channel TIADC in the related art, and as shown in FIG. 1, the M-channel TIADC includes M sub-ADCs, wherein each sub-AThe sampling rate of DC is f_S(ii) a/M; fig. 2 is an ideal sampling diagram of an M-channel TIADC in the related art, and as shown in fig. 2, a plurality of sub-ADCs in the TIADC are sampled in a time-alternating manner. Ideally, the M-channel TIADC described above enables the sampling rate of the system to be M times that of a single sub-ADC. However, due to the inherent disadvantages of the manufacturing process, the sub-ADCs cannot be completely identical, and thus mismatch errors exist between the sub-ADCs. The mismatch error of the TIADC mainly includes bias mismatch, gain mismatch, and sampling clock mismatch.

In order to avoid the above mismatch affecting the performance of the TIADC, an estimator is usually used in the related art to compensate for the error of the TIADC, for example, a sampling clock mismatch error estimator is used to compensate for the error of the sampling clock mismatch of the TIADC. However, the parameter value used by the sampling clock mismatch error estimator for estimation tends to be related to the frequency of the input signal of the TIADC when it is processing, i.e., the parameter fluctuates with changes in the frequency of the input signal of the TIADC.

Due to the characteristics of the sampling clock mismatch error estimator, the sampling clock mismatch error estimator cannot perform effective error compensation processing in an application scene that the frequency of an input signal is variable and unknown; for example, in a 4G or 5G communication system, for the TIADC, the base station or the terminal may not know the number of supported carriers and the activated frequency resource blocks in one carrier, for example, a fixed parameter is selected to estimate the mismatch error of the sampling clock, when the difference between the actual parameter of the estimator and the pre-selected fixed parameter is too large, the residual error and the convergence time of the estimator may be affected, and the mismatch error estimator of the sampling clock may not perform effective error estimation and compensation on the TIADC.

For the technical problem that in the related art, when a sampling clock mismatch estimator performs mismatch error estimation and compensation, effective error estimation and compensation cannot be performed according to the frequency change of an input signal of a TIADC, a solution is not proposed in the related art.

Disclosure of Invention

Embodiments of the present invention provide a compensation apparatus and method, a storage medium, and an electronic apparatus, so as to at least solve a technical problem that effective error estimation and compensation cannot be performed according to a frequency change of an input signal of a TIADC when a sampling clock mismatch estimator performs mismatch error estimation and compensation in a related art.

According to an embodiment of the present invention, there is provided a compensation apparatus including:

a time-interleaved analog-to-digital converter (TIADC) configured to receive an input signal and output an output signal;

a compensation module configured to obtain first estimation information at an nth time and second estimation information at an nth-a time, and obtain third estimation information according to the first estimation information and the second estimation information, where the third estimation information is used to instruct the compensation module to compensate the output signal of the TIADC according to the third estimation information at an n +1 time;

the nth-a time and the nth-b time are used for indicating a time before the nth time, and the (n +1) th time is used for indicating an adjacent time after the nth time.

There is also provided, in accordance with another embodiment of the present invention, a compensation method for use in a time-interleaved analog-to-digital converter, TIADC, configured to receive an input signal and output an output signal, the method including:

acquiring first estimation information at the nth moment and second estimation information at the nth-a moment; the nth-a time and the nth-b time are used for indicating the time before the nth time;

obtaining third estimation information according to the first estimation information and the second estimation information, wherein the third estimation information is used for indicating that the output signal of the TIADC is compensated according to the third estimation information at the n +1 th moment; the n +1 th time is used for indicating an adjacent time after the n-th time.

There is also provided, in accordance with another embodiment of the present invention, compensation apparatus for use in a time-interleaved analog-to-digital converter, TIADC, configured to receive an input signal and output an output signal; the device comprises:

the acquisition module is used for acquiring first estimation information at the nth moment and second estimation information at the nth-a moment; the nth-a time and the nth-b time are used for indicating the time before the nth time;

an estimating module, configured to obtain third estimation information according to the first estimation information and the second estimation information, where the third estimation information is used to indicate that the output signal of the TIADC is compensated according to the third estimation information at a time n + 1; the n +1 th time is used for indicating an adjacent time after the n-th time.

According to a further embodiment of the present invention, there is also provided a storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the above method embodiments when executed.

According to yet another embodiment of the present invention, there is also provided an electronic device, including a memory in which a computer program is stored and a processor configured to execute the computer program to perform the steps in any of the above method embodiments.

According to the invention, the compensation module obtains the third estimation information according to the first estimation information of the n-a before the nth time and the second estimation information of the n-b at the nth time so as to compensate the output signal of the TIADC according to the third estimation information at the next (n +1) th time; therefore, the invention can solve the technical problem that the sampling clock mismatch estimator can not carry out effective error estimation and compensation according to the frequency change of the input signal of the TIADC when carrying out mismatch error estimation and compensation in the related technology, thereby achieving the effect that the sampling clock mismatch estimator can self-adapt to the frequency change of the input signal of the TIADC, and achieving effective error estimation and compensation.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:

FIG. 1 is a schematic diagram of the architecture of a related art M-channel TIADC;

FIG. 2 is an idealized sampling schematic of a M-channel TIADC of the related art;

FIG. 3 is a schematic diagram of the mean change of the downsampled clock mismatch error estimator for input signals of different frequencies;

FIG. 4 is a schematic diagram of a bias distribution of a downsampled clock mismatch error estimator for input signals of different frequencies;

FIG. 5 is a schematic diagram of the variation of the offset of the downsampled clock mismatch error estimator for input signals of different frequencies;

FIG. 6 is a functional diagram of a compensation module according to an embodiment of the present invention;

FIG. 7 is a functional diagram of a compensation module according to an embodiment of the present invention (II);

FIG. 8 is a schematic diagram of a third estimated information estimation flow provided by an embodiment of the present invention;

FIG. 9 is a flow chart of a compensation method provided according to an embodiment of the invention;

fig. 10 is a block diagram of a compensation apparatus according to an embodiment of the present invention.

Detailed Description

The invention will be described in detail hereinafter with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

To further explain the error estimation process of the sampling clock mismatch error estimator of the present invention on the sampling clock mismatch and the influence of the frequency of the input signal in the TIADS in the related art on the sampling clock mismatch error estimator, the following describes in detail the estimation mode of the sampling clock mismatch error estimator for sampling clock mismatch error;

assuming that, in the mismatch of the TIADC, the offset mismatch and the gain mismatch are already ideally compensated, that is, the residual error after compensation for the offset mismatch and the gain mismatch does not affect the performance of the TIADC, such as Effective Number of Bits (ENOB) and Spurious Free Dynamic Range (SFDR), in the above case, the effect of the sampling clock mismatch of the TIADC on the TIADC in operation can be referred to the following formula:

y_k(n)＝x(Mn+k)＝A*sin[2πf_in((Mn+k)T_s+Δτ_k)+θ]k is 0,1, M-1 formula 1

Equation 1 above is used to express the relationship between the input signal and the output signal of the TIADC, where y_k(n) is used to represent the output of subchannel k in the TIADC at time n-nTs, f_s＝1/T_sFor representing the sampling frequency of the TIADC, corresponding to T_sIs the sampling period of the TIADC; m is used for representing the number of sub-channels in the TIADC; a is used to represent the gain of the subchannel; x (n) sin (2 pi f)_innT_s+ θ) is used to represent the sinusoidal signal of the TIADC input, where f_inFor indicating the frequency, Δ τ, of the input sinusoidal signal_k＝d_k*T_sFor representing sampling clock mismatch error on subchannel k, d_kIs to T_sAnd carrying out normalization processing to obtain a sampling clock mismatch error.

Based on this, the above equation 1 can be used to show that the sine signal input to the TIADC is x (n) -sin (2 pi f)_innT_s+ theta), obtaining y from the input signal and parameters such as the number of subchannels in the TIADC, gain, and mismatch error of sampling clock_k(n)。

Further, taking a TIADC with the number M of sub-channels being 2 as an example, the manner of obtaining the sampling clock mismatch in the above formula 1 is described. For the 2-channel TIADC, when there is no sampling clock mismatch between the two sub-channels, sub-channel 0 and sub-channel 1 for the input signal according to equation 1 aboveThe sampling points are respectively y₀(n) x (Mn) and y₁(n) ═ x (Mn + 1). On the basis, when the sampling clock mismatch error delta d in the TIADC is d₁-d₀＝Δτ₁-Δτ₀/T_s＝Δτ/T_sIn this case, the actual sampling points of the sub-channel 0 and the sub-channel 1 in the nth period may be expressed as y₀(n)＝x(Mn+d₀) And y₁(n)＝x(Mn+1+d₁)。

Further, in general, the absolute value of the mismatch error of the sampling clock in the above-mentioned TIADS is much smaller than 1, i.e., abs (Δ d) < 1. On this basis, with subchannel 0 as the reference channel, subchannel 1 is relative to the actual sampling time point y of subchannel 0₁(n)＝x(Mn+1+d₁) Deviating from the ideal sampling time point ad.

Δ d and the sampling points y of the sub-channel 0 and sub-channel 1₀And y₁See the following equation, equation 2:

in the above equation 2, σ²For representing the average power of each sample point, it can be assumed here that σ for sub-channel 0 and sub-channel 1 is approximated by the average power of two sample points²The same; the last term of equation 2 is used to represent the expectation of the cross-correlation function of adjacent sample points, which can be further expressed as R (1+ Δ d); based on this, the above formula 2 can be further expressed as:

E[(y₁(n)-y₀(n))²]＝2σ²-2R (1+ Δ d) equation 3

Similarly, in the n +1 th cycle, the above formula 2 can be further expressed as:

E[(y₀(n+1)-y₁(n))²]＝2σ²-2R (1- Δ d) equation 4

Performing subtraction processing on the above formula 3 and formula 4, wherein abs (Δ d) < 1, that is, the value of Δ d is small, so that taylor series expansion can be adopted for the cross-correlation function sampling, and only the first derivative term is retained, thereby obtaining the following formula:

e(n)＝E[(y₁(n)-y₀(n))²]-E[(y₀(n+1)-y₁(n))²]e≈ -4 Δ dR' (1) equation 1

In the above equation 5, R' (1) is the first derivative of R (1). Statistically, when the statistical sample comb is large enough, R' (1) at a certain input signal for a TIADC can be approximated to a certain value. Therefore, the above equation 5 can be understood that a fixed proportional relationship exists between e (n) and Δ d. It should be further noted that, in the above formula 5, e (n) is used to represent an observed value in the estimation process of the sampling clock mismatch.

From this, the estimated value of Δ d satisfies the following equation:

the estimation of the Δ d is performed by an estimator, such as a sampling clock mismatch error estimator, and the estimator samples part of the parameters in the process of obtaining the Δ d in an approximation manner, such as the sampling of the cross-correlation function by using a taylor series expansion to retain only a first derivative thereof, or approximating R' (1) to a determined value, so that the estimation result of the estimator is not the exact Δ d, but an estimation value of the Δ d, i.e. an estimation value of the Δ d

The

The error between Δ d and Δ d is within a controllable range, and therefore, can be controlled by

And performing compensation processing of sampling clock mismatch.

In the above formula 6, g is the gain of the estimator, and b is the deviation of the estimator; it should be further noted that, in the present solution, the sampling gain and the offset are used as parameters for estimating by the sampling clock mismatch error estimator, but are not limited thereto; the following description will be made with gain and offset as estimation parameters.

The above equation 6 performs error estimation on the basis of 2-channel TIADC, and this equation 6 may also be extended to any number M of TIADC systems, for example, when M is 4, the sampling clock mismatch error estimation of the sub-channel 2 may be estimated on the basis of the sub-channel 0, and after this is compensated, the sampling clock mismatch error estimation of the sub-channels 1 and 3 is performed; in the 4-channel TIADS with M being 4, the sampling clock mismatch error of the sub-channel 1, the sub-channel 2, and the sub-channel 3 can be estimated by using the following formula, that is, formula 7:

the above equations 6 and 7 constitute the estimation process of the TIADC sampling clock mismatch error when M is 2 and M is 4, respectively. However, as shown in equations 6 and 7, in estimating the sampling clock mismatch error, the estimated error is related to e (n), which is further related to the derivative of the cross-correlation function R '(1) as shown in equation 5, and R' (1) is related to R (1), which is further known from equation 2, where R (1) is related to the frequency of the input signal of the TIADC. Thus, in estimating the sampling clock mismatch error, the estimated error exhibits a correlation with the frequency of the input signal of the TIADC.

Meanwhile, as shown in equations 6 and 7, the parameter types of the sampling clock error estimator in the estimation process, such as the gain and the offset in equations 6 and 7, also have characteristics related to the frequency of the input signal. To further illustrate the relationship between the parameters such as gain and offset of the estimator and the frequency of the input signal of the TIADS, the relationship between the input signal and the related parameters at different frequencies is listed as follows:

FIG. 3 is a schematic diagram showing the mean value change of the downsampling clock mismatch error estimator for input signals of different frequencies, and FIG. 3 is a specific diagram for indicating that the input signals of different frequencies are input by TIADS with M4In the following, the mean value of the estimation of the mismatch error estimator of the sampling clock varies with the time error, wherein the sampling frequency f of the TIADS_sThe frequencies corresponding to the listed three input signals are 2 GHz: f. of_in1＝333MHz，f _in2＝239MHz，f_in3-166 MHz; and setting the time error within-0.03 Ts to 0.03Ts for the input signals corresponding to the three frequencies, and scanning at intervals of 0.01Ts, so that the estimated average value of the sampling clock mismatch error estimator corresponding to the time error can be obtained.

As shown in fig. 3, the slope of the mean variation line of the sampling clock mismatch error estimator for input signals with different frequencies is significantly different, and the slope represents the gain of the sampling clock mismatch error estimator, so that the gain of the sampling clock mismatch error estimator varies with the frequency of the input signal, and particularly increases with the frequency of the input signal.

Meanwhile, fig. 3 may further illustrate a variation trend of the deviation of the input signal downsampling clock mismatch error estimator with different frequencies, where when the time error is zero, that is, when the time error is zero, the mean value variation straight line of the sampling clock mismatch error estimator corresponding to the frequency of each input signal in fig. 3 is the mean value corresponding to the zero, that is, the deviation of the input signal downsampling clock mismatch error estimator with the frequency is indicated; fig. 4 is a schematic diagram of a distribution of deviations of the input signal downsampling clock mismatch error estimator with different frequencies, and as shown in fig. 4, after amplifying a zero position of a mean change straight line of the sampling clock mismatch error estimator corresponding to the frequency of each input signal in fig. 3, the distribution of the deviations of the sampling clock mismatch error estimator also changes significantly, specifically, the deviations of the sampling clock mismatch error estimator increase with the increase of the frequency of the input signal.

Fig. 5 is a schematic diagram of variation of a bias of a sampling clock mismatch error estimator under input signals of different frequencies, and fig. 5 is specifically used to indicate variation of variance of the sampling clock mismatch error estimator under different frequency input signals of TIADS where M is 4, where the sampling frequency f of TIADS is different_sThe frequencies corresponding to the listed three input signals are 2 GHz: f. of_in1＝333MHz，f _in2＝239MHz，f_in3-166 MHz; for the input signals corresponding to the three frequencies, setting the time error within-0.03 Ts to 0.03Ts, and scanning at intervals of 0.01Ts, namely obtaining the variance of a sampling clock mismatch error estimator corresponding to the time error.

As shown in fig. 5, the variance distribution of the sampling clock mismatch error estimator has a significant difference for input signals of different frequencies, and specifically, the variance of the sampling clock mismatch error estimator increases with the frequency of the input signal. Based on the above, it can be known that the gain, variance and deviation of the sampling clock mismatch error estimator form correlation with the frequency of the input signal of the TIADS. Therefore, the sampling clock mismatch error estimator is greatly affected by the frequency of the TIADS input signal when estimating the sampling clock mismatch error.

It should be further noted that, although the variation of the deviation of the sampling clock mismatch error estimator under the input signals with different frequencies is small, for the TIADC, especially for the TIADC with the number of sub-channels greater than 2, there is an estimation error propagation phenomenon when performing the estimation of the sampling clock mismatch error, for example, in the estimation and compensation process of the sampling time mismatch error between the sub-channels in the 4-channel TIADC shown in equation 7, the estimation of the sub-channel 1 and the estimation of the sub-channel 3 both need to use the error estimation of the sub-channel 2 and the result after the compensation to obtain, because of the characteristic influence of the sampling clock mismatch error estimator, the sub-channel 2 fails to form an effective estimation for the sampling clock mismatch error, so that a certain estimation-compensation residual error is formed in another sub-channel, thereby causing the propagation of the estimation-compensation residual error of the sub-channel 2, that is, the estimation-compensation residual error of subchannel 2 is added to the estimation process in subchannels 1 and 3, so that the estimation-compensation residual errors of the other subchannels 1 and 3 continue to expand. Thus, the above-described phenomenon of estimation error propagation causes the TIADS to have a higher requirement for estimation-compensation residual error per subchannel for the larger M.

Based on the above analysis, when the sampling clock mismatch error estimator performs error estimation, the adopted parameters, such as gain, deviation, variance, etc., are all related to the frequency of the input signal of the TIADC, and this characteristic may cause the sampling clock mismatch error estimator to generate a certain estimation-compensation residual error when performing error estimation on input signals of different frequencies, and this estimation-compensation residual error not only causes the corresponding sub-channel to be unable to perform effective error estimation and compensation, but also further causes the estimation-compensation residual error to propagate when referring to multiple sub-channels, so that the error is gradually enlarged. Therefore, the sampling clock mismatch error estimator cannot effectively estimate and compensate errors in the application scenarios such as 4G and 5G communication systems, in which the highest frequency of the input signal is variable and unknown.

For this reason, regarding the characteristics of the sampling clock mismatch error estimator in the related art, a smaller estimation gain is usually selected for estimation to ensure that the estimator can converge and the variance after convergence is smaller, and an average deviation is selected to ensure that the estimation-compensation residual error of the estimator is smaller; in this scenario, although the selection of the bias has a small effect on the estimator estimation-compensation residual error, for the estimated gain, when the actual gain of the estimator is higher than the selected fixed gain, the convergence of the estimator is too slow, and when the actual gain of the estimator is lower than the selected fixed gain, the variance of the estimator after convergence is large, which affects the performance of the ADC, even does not converge. The performance of the TIADC is reduced when the TIADC and the estimation compensation method of the error are used in a 4G or 5G communication system, for example, the sampling clock mismatch error estimation-compensation convergence time is too long, the output variance of the estimator is too large, or the ADC performance is reduced or even not converged due to the deviation.

Example 1

In this embodiment, a compensation apparatus is provided, and fig. 6 is a functional schematic diagram (one) of a compensation module according to an embodiment of the present invention, as shown in fig. 6, the compensation apparatus includes:

a time-interleaved analog-to-digital converter TIADC102 configured to receive an input signal and output an output signal;

the compensation module 104 is configured to obtain first estimation information at a time n-a and second estimation information at a time n-b at a time n, and obtain third estimation information according to the first estimation information and the second estimation information, where the third estimation information is used to instruct the compensation module to compensate the output signal of the TIADC101 according to the third estimation information at a time n + 1;

the nth-a time and the nth-b time are used for indicating the time before the nth time, and the (n +1) th time is used for indicating the adjacent time after the nth time.

With the compensation device in this embodiment, since the compensation module obtains the third estimation information at the nth time according to the first estimation information at the n-a and the second estimation information at the n-b before the nth time, the compensation module compensates the output signal of the TIADC at the next (n +1) th time according to the third estimation information; therefore, the compensation device in this embodiment can solve the technical problem that effective error estimation and compensation cannot be performed according to the frequency change of the input signal of the TIADC when the sampling clock mismatch estimator performs mismatch error estimation and compensation in the related art, so that the sampling clock mismatch estimator can adapt to the frequency change of the input signal of the TIADC, thereby achieving the effect of effective error estimation and compensation.

It should be further noted that the nth time is used to instruct the TIADC to perform any time during the normal operation, that is, on the premise that at least the nth-a time and the nth-b time are present before the nth time, the nth time may be any time. The nth-a time and the nth-b time are both used for indicating a time before the nth time, and the nth-a time and the nth-b time may be adjacent times, for example, the nth-1 time and the nth-2 time, or non-adjacent times, for example, the nth-1 time and the nth-3 time, correspondingly, in the process of selecting the time before the nth time, two adjacent times may be directly selected according to a preset requirement, or a set of multiple times may be selected, and two adjacent or non-adjacent times are selected again in the set, which is not limited in the present invention.

Accordingly, since the time n +1, i.e., the time next after the time n is indicated, the time TIADC at the time n has already completed estimation and compensation of the sampling clock mismatch error, the estimation and compensation of the sampling clock mismatch error can be performed only for the time TIADC at the time next with the third estimation information acquired.

In this embodiment, the nth time, the nth-a time, the nth-b time, and the nth +1 time are all used to indicate working processes of the compensation device at different times, and do not represent a specific time, and a cyclic operation of the compensation device in this embodiment can be realized by reassigning n, for example, the nth time is the 5 th time, the corresponding nth-a time is the 4 th time, the nth-b time is the 3 rd time, and the corresponding nth +1 time is the 6 th time, and the compensation device in this embodiment can obtain the third estimation information at the 5 th time according to the first estimation information at the 4 th time and the second estimation information at the 3 rd time, and compensate for a sampling clock mismatch error of an output signal of the TIADC at the 6 th time according to the third estimation information.

After the compensation is completed at the 6 th moment, the nth moment can be re-assigned as the 6 th moment, at this time, the (n +1) th moment is the 7 th moment, the corresponding nth-a and nth-b moments can be kept as the 4 th and 3 rd moments, and can also be re-assigned as the 5 th and 4 th moments, so that the third estimation information is obtained again according to the first estimation information and the second estimation information at the corresponding moments (if the re-assignment is performed on the nth-a moment and the nth-b moment, the first estimation information and the second estimation information need to be updated), and the sampling clock mismatch error of the output signal of the TIADC can be compensated at the 7 th moment; with this loop, the continuous third estimation information acquisition and the compensation for the TIADC can be realized during the operation of the TIADC.

When the compensation device in this embodiment performs sampling clock mismatch error compensation on the TIADC, for example, the third estimation information used is obtained based on the first estimation information and the second estimation information at previous time, and therefore, the third estimation information is not calculated based on the preset fixed parameter of the estimator, but instead, the estimation information corresponding to the input frequency at the current time obtained by considering the estimation information at different times is considered.

Specifically, for example, the frequency of the input signal at the 1 st time is 250MHz, and the frequency of the input signal at the 4 th time is changed to 350MHz, and in the related art, the arrangement of the estimation parameters is generally performed for the frequency of the input signal in the initial state, for example, the gain and the offset corresponding to the frequency of 250MHz at the 1 st time, and for the 4 th time and the subsequent times, the gain and the offset corresponding to the original frequency of 250MHz cannot be effectively estimated and compensated for the output of the TIADC at the present time due to the change in the frequency of the input signal. In this embodiment, the compensation device can form third estimation information and compensate for the 7 th time based on the estimation information of the 4 th time and the 5 th time, i.e. the first estimation information and the second estimation information in this embodiment, for example, at the 6 th time, and since the considered object of the third estimation information is the estimation information of the 4 th time and the 5 th time, the frequency of the considered input signal is the frequency after the change, therefore, the compensation device of this embodiment can adapt to the change of the input frequency, thereby achieving effective estimation and compensation of the output of the TIADC.

Based on the above analysis, in an application scenario where the highest frequency of the input signal is variable and unknown, such as a 4G communication system and a 5G communication system, when the frequency of the input signal of the TIADC changes at different times, the compensation module in this embodiment, that is, the third estimation information, adapts to the changed input frequency, so that the TIADC can obtain effective error compensation.

In an alternative embodiment, fig. 7 is a functional schematic diagram (ii) of a compensation module provided according to an embodiment of the present invention, and as shown in fig. 7, the compensation module 104 includes:

a compensation unit 1042 configured to compensate an output signal of the TIADC;

an estimating unit 1044 configured to provide the compensating unit with estimation information, wherein the estimation information is used for instructing the compensating unit to compensate the output signal of the TIADC;

an obtaining unit 1046 configured to obtain, at an nth time, first estimation information of the estimating unit at an nth-a time and second estimation information of the estimating unit at an nth-b time; acquiring an estimation parameter at the nth moment according to the first estimation information and the second estimation information, and sending the estimation parameter at the nth moment to an estimation unit;

the estimation unit 1044 is further configured to provide the third estimation information to the compensation unit according to the estimation parameter at the nth time; and the third estimation information is used for instructing the compensation unit to compensate the output signal of the TIADC according to the third estimation information at the (n +1) th moment.

It should be further noted that, in the compensation module, the compensation unit, the estimation unit, and the acquisition unit form a feedback type correction circuit, wherein the compensation unit is connected to the output of the TIADC for compensating the output of the TIADC, and the estimation unit is connected to the compensation unit on one hand for providing error estimation to the compensation unit and is connected to the acquisition unit on the other hand. The estimation unit may perform estimation processing of estimation information according to configured estimation parameters, such as gain, deviation, and the like; taking the nth time as an example, the obtaining unit obtains first estimation information provided by the estimating unit to the compensating unit at the nth-a time, and second estimation information provided by the estimating unit to the compensating unit at the nth-b time, where the obtaining of the first estimation information and the second estimation information may be performed by the estimating unit storing estimation information at different times in an internal or external storage medium, and the obtaining unit performs active query and obtaining, or may be performed by the estimating unit or the compensating unit actively issuing the first estimation information and the second estimation information to the obtaining unit when the obtaining unit operates, which is not limited in this disclosure.

After the obtaining unit obtains the first estimation information and the second estimation information, the estimation parameter at the nth time can be obtained, according to the above formula 6 and formula 7, the estimation parameter in the sampling clock mismatch error estimator is often related to the frequency of the output signal of the TIADC, so that the actual frequency of the input signal at the current time can be obtained according to the estimation parameter at the nth time, and the compensation is performed through the third estimation information at the next time, that is, the n +1 th time, so as to make the compensation of the TIADC conform to the current input frequency.

In an optional embodiment, the estimation unit 1044 is further configured to:

providing estimation information to the compensation unit according to the estimation parameters; wherein the estimation parameter is related to the frequency of the input signal to the TIADC.

It should be further noted that, when the estimated parameter of the sampling clock mismatch error estimator is related to the frequency of the input signal of the TIADC, that is, the estimated parameter changes with the change of the input signal of the TIADC, the compensation apparatus in this embodiment can be applied.

In an alternative embodiment, estimating the parameters includes: gain information, offset information.

In an alternative embodiment, the compensation module 1042 is further configured to:

when the TIADC is obtained to receive the input signals with different frequencies, the estimation unit establishes the corresponding relation between the frequency of the input signals and the simulation gain information and the corresponding relation between the frequency of the input signals and the simulation deviation information for the simulation gain information and the simulation deviation information under the input signals with different frequencies.

It should be further noted that, when the compensation unit obtains the input signals with different frequencies received by the TIADC, the estimation unit may perform off-line simulation processing on the frequencies of all possible input signals of the TIADC for the simulation gain information and the simulation deviation information under the input signals with different frequencies to obtain the simulation gain information and the simulation deviation information corresponding to the input signals with the frequencies, so as to establish the corresponding relationship between the frequencies of the input signals and the simulation gain information and the simulation deviation information; the corresponding relation can be stored in an internal or external storage medium of the compensation module for the estimation unit to query, and the storage mode is not limited by the invention.

In an optional embodiment, the obtaining unit 1046 is further configured to:

and acquiring the gain information of the nth time according to the first estimation information, the second estimation information, the gain information of the nth-a time and/or the gain information of the nth-b time.

Further, the following describes a manner of acquiring gain information at the nth time, taking a 2-channel TIADC as an example.

Let TIADC M be 2, the estimation unit may refer to the foregoing equation 6 for the sampling clock mismatch error estimation of the TIADC; setting the nth-a moment as the nth-1 moment and the nth-b moment as the nth-2 moment; and at the n-1 th time and the n-2 nd time, the estimation unit can record gain information and deviation information corresponding to the n-1 th time and the n-2 nd time when the estimation unit carries out sampling clock mismatch error estimation.

The gain information at the n-2 th moment is g (f, n-2), and the deviation information is b (f, n-2); the output of the sampling mismatch error estimation performed by the estimation unit at the n-2 th time, i.e. the second estimation information, can refer to the following equation:

based on the sampling mismatch error estimation performed at the n-2 th time in the above equation 8, the sampling mismatch error estimation may be provided to the compensation unit at the n-1 th time to compensate the output of the TIADC, and since the gains and deviations at the n-1 th time and the n-2 th time are set to be equal, the gain information and the deviation information at the n-1 th time satisfy g (f, n-1) ═ g (f, n-2) and b (f, n-1) ═ b (f, n-2), so as to perform the error estimation output, that is, the first estimation information may refer to the following equation:

taking g (f, n) and b (f, n) as actual gain information and actual bias information for representing the sampling mismatch error estimation corresponding to the frequency of the input signal of the TIADC at the nth time, and substituting the gain information and the bias information into the above formula 8, the actual sampling clock mismatch error at the nth-2 time can be expressed by using the following formula:

Δ d (n-2) ═ g (f, n) × (e (n-2) -b (f, n)) formula 10

By substituting the calculation method of e (n) in the above equation 5 into the above equation 10, the actual sampling clock mismatch error at the n-2 th time can be further expressed by the following equation 11:

similarly, for the n-1 th time, the actual sampling clock mismatch error at the n-1 th time can be expressed by the following equation 12:

further, substituting the above equation 11 into equation 12 can obtain:

the above equation 13 is used to represent the actual gain of the sampling clock mismatch error estimate under the current input signal, i.e. the sampling clock mismatch error estimate has a corresponding relationship between the gain at the nth time and the first estimation information at the n-1 th time and the second estimation information at the n-2 nd time. Therefore, when the acquiring unit acquires the first estimation information and the second estimation information, the actual gain at the nth time, that is, the gain information corresponding to the frequency of the input signal of the TIADC at the nth time can be obtained according to the above equation 13.

In an optional embodiment, the obtaining unit 1046 is further configured to:

determining the frequency of the input signal at the nth moment according to the gain information at the nth moment and the corresponding relation between the frequency of the input signal and the simulation gain information;

and determining the deviation information of the nth time according to the frequency of the input signal of the nth time and the corresponding relation between the frequency of the input signal and the simulation deviation information.

It should be further noted that, on the premise that the actual gain information g (f, n) of the estimator at the nth time is obtained according to the above formula 13, the corresponding relationship between the frequency of the input signal and the simulated gain information may be referred to by the g (f, n) to determine the frequency of the input signal at the nth time, and at the same time, the corresponding relationship between the frequency of the input signal and the simulated deviation information may be used to determine the actual deviation information b (f, n) at the nth time. Thus, the sampling clock mismatch error estimation information required at the n +1 th time, i.e. the third estimation information, can be obtained according to the foregoing formula 6 through g (f, n) and b (f, n). Fig. 8 is a schematic diagram of a third estimation information estimation process according to an embodiment of the present invention, and the third estimation information, that is, the acquisition process of the sampling clock mismatch error estimation information required at the n +1 th time is shown in fig. 8.

In an alternative embodiment, the gain information at time n-a and the gain information at time n-b are equal to each other; the deviation information at the n-a th time and the deviation information at the n-b th time are equal to each other.

It should be further noted that, on the premise that the above relationship is satisfied, the nth-a time and the nth-b time may be adjacent or not adjacent.

It should be further noted that, in the compensating apparatus in this embodiment, at the time when the TIADC starts to operate, for example, when n is 0 to 1, since two corresponding n-a-th and n-b-th times cannot be obtained before the nth time, when the compensating module estimates and compensates the sampling clock mismatch error output by the TIADC, the compensating module may directly sample the preset gain information and the offset information for estimation, and since the TIADC starts to operate in this state and there is no change in frequency, the error estimation and compensation can be effectively performed on the TIADC based on the initial gain information and the offset information.

Example 2

Also provided in this embodiment is a compensation method for use in a time-interleaved analog-to-digital converter, TIADC, configured to receive an input signal and output an output signal; fig. 9 is a flowchart of a compensation method according to an embodiment of the present invention, and as shown in fig. 9, the compensation method in the embodiment includes:

s202, acquiring first estimation information at the nth time and second estimation information at the nth-a time; the nth-a moment and the nth-b moment are used for indicating the moments before the nth moment;

s204, third estimation information is obtained according to the first estimation information and the second estimation information, wherein the third estimation information is used for indicating that the output signal of the TIADC is compensated according to the third estimation information at the n +1 th moment; the n +1 th time is used to indicate an adjacent time after the n-th time.

With the compensation method in this embodiment, since the third estimation information can be obtained at the nth time according to the first estimation information at the nth-a and the second estimation information at the nth-b before the nth time, the output signal of the TIADC can be compensated at the next nth +1 time according to the third estimation information; therefore, the compensation method in this embodiment can solve the technical problem that effective error estimation and compensation cannot be performed according to the frequency change of the input signal of the TIADC when the sampling clock mismatch estimator performs mismatch error estimation and compensation in the related art, so that the sampling clock mismatch estimator can adapt to the frequency change of the input signal of the TIADC, thereby achieving the effective error estimation and compensation effect.

In this embodiment, the nth time, the nth-a time, the nth-b time, and the nth +1 time are all used to indicate a working process of the compensation device at different times, and do not represent a specific time, and a round-robin north line of the compensation method in this embodiment can be implemented by reassigning n, for example, the nth time is the 5 th time, the corresponding nth-a time is the 4 th time, the nth-b time is the 3 rd time, and the corresponding nth +1 time is the 6 th time.

In the compensation method in this embodiment, when performing sampling clock mismatch error compensation on the TIADC, the third estimation information is obtained based on the first estimation information and the second estimation information at previous time, and therefore, the third estimation information is not calculated based on the preset fixed parameter of the estimator, but instead, estimation information corresponding to the input frequency at the current time is obtained by considering the estimation information at different times.

Based on the above analysis, in an application scenario where the highest frequency of the input signal is variable and unknown, such as a 4G communication system and a 5G communication system, when the frequency of the input signal of the TIADC changes at different times, the compensation method in this embodiment is to adapt to the changed input frequency by using the third estimation information, so that the TIADC can obtain effective error compensation.

In an optional embodiment, in the step S204, obtaining the third estimation information according to the first estimation information and the second estimation information includes:

acquiring first estimation information at the nth moment and second estimation information at the nth-a moment;

acquiring an estimation parameter at the nth moment according to the first estimation information and the second estimation information;

and acquiring third estimation information according to the estimation parameter at the nth moment.

In an alternative embodiment, the estimation parameter is related to the frequency of the input signal to the TIADC.

In an optional embodiment, the compensation method further comprises:

when the TIADC receives input signals with different frequencies, acquiring simulation gain information and simulation deviation information under the input signals with different frequencies to establish a corresponding relation between the frequency of the input signals and the simulation gain information and a corresponding relation between the frequency of the input signals and the simulation deviation information.

In an optional embodiment, the obtaining the estimation parameter at the nth time according to the first estimation information and the second estimation information includes:

In an optional embodiment, the obtaining the estimation parameter at the nth time according to the first estimation information and the second estimation information further includes:

The above-mentioned obtaining manner of the gain information and the deviation information at the nth time corresponds to the obtaining manner of the gain information and the deviation information at the nth time in the compensation apparatus in embodiment 1, and therefore, the details are not repeated in this embodiment.

To further illustrate the method for acquiring the third estimation information at the nth time in this embodiment, the following procedure is adopted for description:

s302, acquiring simulation gain information and simulation deviation information under input signals with different frequencies when the TIADC receives the input signals with different frequencies, so as to establish a corresponding relation between the frequency of the input signals and the simulation gain information and a corresponding relation between the frequency of the input signals and the simulation deviation information;

s304, configuring initial gain information and initial deviation information of a sampling clock mismatch error estimator at initial time of the TIADC, and performing error estimation of sampling clock mismatch at the initial time according to the initial gain information and the initial deviation information;

s306, acquiring first estimation information at the nth moment and second estimation information at the nth moment;

s308, acquiring gain information at the nth moment according to the first estimation information, the second estimation information, the gain information at the nth-a moment and/or the gain information at the nth-b moment;

s310, determining the frequency of the input signal at the nth moment according to the gain information at the nth moment and the corresponding relation between the frequency of the input signal and the simulation gain information;

s312, determining deviation information of the nth moment according to the frequency of the input signal of the nth moment and the corresponding relation between the frequency of the input signal and the simulation deviation information;

and S314, acquiring third estimation information according to the gain information and the deviation information at the nth moment, and providing compensation for the output signal of the TIADC according to the third estimation information.

It should be further noted that, in the step S304, since the time when the TIADC starts to operate, for example, when n is 0 to 1, two corresponding n-a-th and n-b-th times cannot be obtained before the nth time, when estimating and compensating the sampling clock mismatch error output by the TIADC, the preset gain information and the offset information can be directly sampled for estimation, and since the TIADC starts to operate in this state and there is no change in frequency, the error estimation and compensation can be effectively performed on the TIADC based on the initial gain information and the offset information.

Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.

Example 3

In this embodiment, a compensation device is further provided, and the compensation device is used to implement the above embodiments and preferred embodiments, which have already been described and will not be described again. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.

Fig. 10 is a block diagram of a compensating apparatus according to an embodiment of the present invention, as shown in fig. 10, the apparatus including:

an obtaining module 302, configured to obtain, at an nth time, first estimation information at an nth-a time and second estimation information at an nth-b time; the nth-a moment and the nth-b moment are used for indicating the moments before the nth moment;

an estimating module 304, configured to obtain third estimation information according to the first estimation information and the second estimation information, where the third estimation information is used to instruct to compensate the output signal of the TIADC at the n +1 th time according to the third estimation information; the n +1 th time is used to indicate an adjacent time after the n-th time.

With the compensation device in the embodiment, since the third estimation information can be obtained at the nth time according to the first estimation information at the nth-a and the second estimation information at the nth-b before the nth time, the output signal of the TIADC can be compensated at the next nth +1 time according to the third estimation information; therefore, the compensation device in this embodiment can solve the technical problem that effective error estimation and compensation cannot be performed according to the frequency change of the input signal of the TIADC when the sampling clock mismatch estimator performs mismatch error estimation and compensation in the related art, so that the sampling clock mismatch estimator can adapt to the frequency change of the input signal of the TIADC, thereby achieving the effect of effective error estimation and compensation.

The remaining technical effects, i.e., modes, of the present embodiment correspond to those of the compensation apparatus in embodiment 1, and therefore, are not described herein again.

In an optional embodiment, obtaining the third estimation information according to the first estimation information and the second estimation information includes:

In an optional embodiment, the obtaining unit is further configured to:

In an optional embodiment, obtaining the estimation parameter at the nth time according to the first estimation information and the second estimation information includes:

It should be noted that, the above modules may be implemented by software or hardware, and for the latter, the following may be implemented, but not limited to: the modules are all positioned in the same processor; alternatively, the modules are respectively located in different processors in any combination.

Example 4

Embodiments of the present invention also provide a storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the above method embodiments when executed.

Alternatively, in the present embodiment, the storage medium may be configured to store a computer program for executing the steps of:

s1, acquiring first estimation information at the nth time and second estimation information at the nth-a time; the nth-a moment and the nth-b moment are used for indicating the moments before the nth moment;

s2, obtaining third estimation information according to the first estimation information and the second estimation information, wherein the third estimation information is used for indicating that the output signal of the TIADC is compensated according to the third estimation information at the n +1 th moment; the n +1 th time is used to indicate an adjacent time after the n-th time.

Optionally, in this embodiment, the storage medium may include, but is not limited to: various media capable of storing computer programs, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.

Example 5

Embodiments of the present invention also provide an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the steps of any of the above method embodiments.

Optionally, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.

Optionally, in this embodiment, the processor may be configured to execute the following steps by a computer program:

Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments and optional implementation manners, and this embodiment is not described herein again.

It will be apparent to those skilled in the art that the modules or steps of the present invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A compensating apparatus, comprising:

2. The apparatus of claim 1, wherein the compensation module comprises:

a compensation unit configured to compensate the output signal of the TIADC;

an estimation unit configured to provide estimation information to the compensation unit, wherein the estimation information is used for instructing the compensation unit to compensate the output signal of the TIADC;

an acquisition unit configured to acquire the first estimation information of the estimation unit at the n-a time and the second estimation information of the estimation unit at the n-b time at an n-th time; acquiring the estimation parameter of the nth moment according to the first estimation information and the second estimation information, and sending the estimation parameter of the nth moment to the estimation unit;

the estimation unit is further configured to provide the third estimation information to the compensation unit according to the estimation parameter at the nth time; wherein the third estimation information is used to instruct the compensation unit to compensate the output signal of the TIADC according to the third estimation information at the n +1 th time.

3. The apparatus of claim 2, wherein the estimation unit is further configured to:

providing estimation information to the compensation unit according to the estimation parameters; wherein the estimated parameter is related to a frequency of an input signal of the TIADC.

4. The apparatus of claim 3, wherein the estimating the parameter comprises: gain information, offset information.

5. The apparatus of claim 4, wherein the compensation module is further configured to:

when the TIADC is acquired to receive the input signals with different frequencies, the estimation unit establishes the corresponding relation between the frequency of the input signals and the simulation gain information and the corresponding relation between the frequency of the input signals and the simulation deviation information for the simulation gain information and the simulation deviation information under the input signals with different frequencies.

6. The apparatus of claim 5, wherein the obtaining unit is further configured to:

and acquiring the gain information at the nth moment according to the first estimation information, the second estimation information, the gain information at the nth-a moment and/or the gain information at the nth-b moment.

7. The apparatus of claim 6, wherein the obtaining unit is further configured to:

and determining the deviation information at the nth moment according to the frequency of the input signal at the nth moment and the corresponding relation between the frequency of the input signal and the simulation deviation information.

8. The apparatus of any one of claims 1 to 7, wherein the gain information at the time n-a and the gain information at the time n-b are equal to each other; the deviation information at the n-a th time and the deviation information at the n-b th time are equal to each other.

9. A compensation method applied to a time-interleaved analog-to-digital converter, TIADC, configured to receive an input signal and output an output signal; the method comprises the following steps:

10. The method of claim 9, wherein the obtaining third estimation information from the first estimation information and the second estimation information comprises:

acquiring the first estimation information at the nth moment and the second estimation information at the nth-a moment;

acquiring an estimation parameter of the nth moment according to the first estimation information and the second estimation information;

and acquiring the third estimation information according to the estimation parameter at the nth moment.

11. The method of claim 10, wherein the estimated parameter is related to a frequency of an input signal to the TIADC.

12. The method of claim 11, wherein estimating the parameters comprises: gain information, offset information.

13. The method of claim 12, further comprising:

and acquiring simulation gain information and simulation deviation information under the input signals with different frequencies when the TIADC receives the input signals with different frequencies so as to establish a corresponding relation between the frequency of the input signals and the simulation gain information and a corresponding relation between the frequency of the input signals and the simulation deviation information.

14. The method according to claim 13, wherein the obtaining the estimation parameter at the nth time according to the first estimation information and the second estimation information comprises:

15. The method according to claim 14, wherein the obtaining the estimation parameter at the nth time according to the first estimation information and the second estimation information further comprises:

16. The method according to any one of claims 9 to 15, wherein the gain information at the time n-a and the gain information at the time n-b are equal to each other; the deviation information at the n-a th time and the deviation information at the n-b th time are equal to each other.

17. A compensation arrangement for use in a time-interleaved analog-to-digital converter, TIADC, configured to receive an input signal and to output an output signal; the device comprises:

18. A storage medium, in which a computer program is stored, wherein the computer program is arranged to perform the method of any of claims 9 to 16 when executed.

19. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and wherein the processor is arranged to execute the computer program to perform the method of any of claims 9 to 16.