CN103312329B - Bearing calibration and corrector for time-interleaved ADC sampling time mismatch - Google Patents

Abstract

The present invention relates to microelectric technique, particularly relate to a kind of time-interleaved analog-digital converter (ADC), particularly relate to the bearing calibration for time-interleaved ADC sampling time mismatch and corrector.Method of the present invention: mainly by difference is done in the numeral output of time-interleaved ADC adjacency channel, try to achieve residual quantity E_i[k], average A after suing for peace with its absolute value_iCharacterize the actual samples time slot between adjacency channel,Characterize the standard sample time slot between adjacency channel, pass throughObtain each channel sample time mismatch amount, finally relative error Bi is eliminated statistical error through AAR filtering, feed back to clock generating unit regulation channel sample clock after summation, thus realize the negative-feedback regu-lation of sampling time mismatch.Beneficial effects of the present invention is, it is possible to is effectively improved and ensures the performance of the time-interleaved analog-digital converter of multichannel, and have the advantage that complexity is low, hardware spending is little and is easily achieved.Present invention is particularly suitable for high-speed low-power-consumption analog digital conversion.

Description

Bearing calibration and corrector for time-interleaved ADC sampling time mismatch

Technical field

The present invention relates to microelectric technique, particularly relate to a kind of time-interleaved analog-digital converter (ADC), particularly Relate to bearing calibration and the corrector of time-interleaved ADC sampling time mismatch.

Background technology

Continuous progressive along with integrated circuit fabrication process, at a high speed, the digital circuit of high integration advanced by leaps and bounds Development, digital signal processing capability constantly strengthens.In order to meet the demand of high-speed digital circuit, how to improve analog-digital converter Speed become IC designer's focus of attention.

A kind of multiple analog-digital converters are together in parallel, and utilize the A/D conversion system that staggered clock makes it take turns to operate By extensive concern.Its feature is in the case of maintaining each sub-adc converter to be operated in lower frequency so that overall Speed gets a promotion, and is therefore referred to as time-interleaved analog-digital converter (Time-interleaved ADC).

The basic structure of one M channel time intertexture analog-digital converter is as it is shown in figure 1, each passage comprises a sampling opens Closing and a sub-ADC, operating frequency is f_s/ M, is interlocked by the sampling time each channel sample switched and comes so that be whole The operating frequency of individual system is increased to f_s(working cycle T_s=1/f_s), thus improve the speed of time-interleaved analog-digital converter.

In theory, port number is the most, and the operating rate of time-interleaved analog-digital converter is the fastest.But, it practice, each passage Sampling time mismatch (Timing mismatch), gain mismatch (Gain mismatch), imbalance is there is between sub-adc converter The non-ideal factors such as mismatch (Offset mismatch) and bandwidth mismatch (Bandwidth mismatch), have had a strong impact on whole The dynamic property of individual analog-digital converter.

Summary of the invention

The technical problem to be solved is, proposes a kind of correction for time-interleaved ADC sampling time mismatch Method and corrector.

The present invention solves above-mentioned technical problem and be the technical scheme is that for time-interleaved ADC sampling time mismatch Bearing calibration, it is characterised in that comprise the following steps:

Input signal is changed by the most time-interleaved ADC；

B. the sampling time gap between adjacency channel ADC is obtained according to the numeral output of each passage of time-interleaved ADC；

C. obtain the sampling time gap between all adjacency channel ADC, and obtain phase according to gap of all of sampling time Standard sample time slot between adjacent passage ADC；

D. according to sampling time gap and the mismatch of standard sample time slot acquisition each channel sample time of each passage Amount；

E. amount of mismatch is fed back to clock generating unit, the sampling clock of regulation respective channel.

Concrete, step b also includes:

B1. the adjacency channel ADC digital output to collecting asks poor.Assume collection is f for incoming frequency_inSinusoidal letter Number x (t), produces each passage numeral and is output as: Y=[y₁[k],y₂[k],…,y_M[k]], k=1,2, P, wherein M is The total number of channels of time-interleaved ADC, P represents single channel sampling number, then the output of adjacency channel ADC digital asks difference be:

$\left\{\begin{array}{c}{E}_1\[k\]=y_2\[k\]-y_1\[k\]\\ E_2\[k\]=y_3\[k\]-y_2\[k\]\\ ......\\ E_M\[k\]=y_1\[k+1\]-y_M\[k\]\end{array}\right.,k=1,2...,P;$

B2. to difference E obtained_iThe absolute value summation of [k] is averaged and obtains A_i, A_iIt is characterized as adopting between adjacency channel ADC Sample time slot, $A_i=\stackrel{\‾}{\left|E_i\right|}=\frac{1}{P}\underset{K=1}{\overset{P}{\Σ}}|E_i\[K\]|,i=1,2,...,M.$

Concrete, step c also includes: to all of A_iSummation is averaged and obtains The standard sample time slot being characterized as between adjacency channel ADC.

Concrete, step d also includes: to all of A_iWithDo difference, obtain:

$\begin{array}{c}{B}_i=A_i-\stackrel{\‾}{A}\\ =\stackrel{\‾}{\left|E_i\right|}-\frac{1}{4}\underset{i=1}{\overset{4}{\mathrm{\Σ}}}\stackrel{\‾}{\left|E_i\right|}\end{array}$

B_iFor the relative error in sampling time gap between adjacency channel ADC Yu standard sample time slot, the most each passage is adopted Sample time mismatch amount.

Concrete, step e also includes: by relative error B_iAccumulated and replacement module filtered eliminates statistical error, summation After feed back to vairable delay line regulation channel sample clock, it is achieved the negative-feedback regu-lation of sampling time mismatch.

For the corrector of the bearing calibration of time-interleaved ADC sampling time mismatch, at time-interleaved ADC, data Reason unit, feedback unit and clock unit, described data processing unit is connected with time-interleaved ADC and feedback unit respectively,

The output data of time-interleaved ADC are processed by described data processing unit in real time, and will process after data Output is to feedback unit；

The data that described feedback unit transmits according to data processing unit, carry out feedback operation, signal are fed back to clock Unit.

Beneficial effects of the present invention is, it is possible to be effectively improved and ensure the performance of the time-interleaved analog-digital converter of multichannel, And there is the advantage that complexity is low, hardware spending is little and is easily achieved.

Accompanying drawing explanation

Fig. 1 is the schematic diagram of tradition M channel time intertexture analog-digital converter；

Fig. 2 is the schematic flow sheet of the method for the present invention；

Fig. 3 is M channel time intertexture ADC sample graph；

Fig. 4 is the schematic diagram of the tradition time-interleaved analog-digital converter of four-way；

Fig. 5 is four-way time-interleaved ADC transformation curve；

E when Fig. 6 is to there is not sampling time mismatch_i(i=1,2,3,4) scattergram；

E when Fig. 7 is to there is sampling time mismatch_i(i=1,2,3,4) scattergram；

Fig. 8 is A_i(i=1,2,3,4) with Δ T/T_sFunctional relationship；

The sampling time mismatch repair loop that Fig. 9 designs for the present invention；

Figure 10 is B_iThe analogous diagram of convergence after corrected；

Figure 11 is the SNR figure before correction；

Figure 12 is the SNR figure after correction.

Detailed description of the invention

Below according to drawings and Examples, the present invention is described in further detail:

The present invention, by the numeral output of time-interleaved ADC adjacency channel is done difference, tries to achieve residual quantity E_i[k], absolute with it Average A after value summation_iCharacterize the actual samples time slot between adjacency channel,When characterizing the standard sample between adjacency channel Between gap, thereforeObtain each channel sample time mismatch amount, finally by relative error B_iSystem is eliminated through AAR filtering Meter error, feeds back to clock generating unit regulation channel sample clock, thus realizes the negative feedback of sampling time mismatch after summation Regulation.

The key step of method of the present invention is as shown in Figure 2:

1, incoming frequency is f_inSinusoidal signal x (t), time-interleaved ADC carries out normal conversion to x (t), produces each port number Word output Y=[y₁[k],y₂[k],…,y_M[k]] (k=1,2, P) as shown in Figure 3.Wherein M is time-interleaved ADC's Total number of channels, P represents single channel sampling number.

2, difference is done in the output of adjacency channel ADC digital, $\left\{\begin{array}{c}{E}_1\[k\]=y_2\[k\]-y_1\[k\]\\ E_2\[k\]=y_3\[k\]-y_2\[k\]\\ ......\\ E_M\[k\]=y_1\[k+1\]-y_M\[k\]\end{array}\right.$ $(k=1,2,...,P);$

3, to difference E_iThe absolute value summation of [k] is averaged and obtains A_i, in order to characterize the sampling time between adjacency channel ADC Gap, $A_i=\stackrel{\‾}{\left|E_i\right|}=\frac{1}{P}\underset{K=1}{\overset{P}{\Σ}}|E_i\[K\]|\left(i=1,2,...,M\right);$

4, to all of A_iSummation is averaged and obtainsIn order to characterize phase Standard sample time slot between adjacent passage ADC；

5, according to the above-mentioned A tried to achieve_iWithBy all of A_iWithDo difference, i.e.

$\begin{array}{c}{B}_i=A_i-\stackrel{\‾}{A}\\ =\stackrel{\‾}{\left|E_i\right|}-\frac{1}{4}\underset{i=1}{\overset{4}{\mathrm{\Σ}}}\stackrel{\‾}{\left|E_i\right|}\end{array}$

Obtain actual samples time slot and relative error B of standard sample time slot between adjacency channel ADC_i, thus Symbolize each channel sample time mismatch amount.

6, by relative error B_iEliminate statistical error through AAR (cumulative and replacement) module filtered, finally feed back to after summation Vairable delay line regulation channel sample clock, thus realize the negative-feedback regu-lation of sampling time mismatch.

Embodiment:

As a example by the time-interleaved ADC of four-way, as shown in Figure 4, its operation principle is: four clocks produced by DLL divide Do not give the sampling of four passages and keep module, and make the sampling of each passage keep working time of module staggered to come. It is f that sampling is kept the output of module to be converted into frequency by passage ADC_s/ 8, digital word (wherein, the f of N position_sHand over for the whole time Knit the sample frequency of ADC).The output of passage ADC is delivered in multiplexer, by defeated by each passage ADC of multiplexer Going out to be converted into frequency is f_sThe N bit digital output of/2.

When interchannel does not exist sampling time mismatch, such as vertical line shown in solid in Fig. 5.

Order:

$\left\{\begin{array}{c}{E}_1\[k\]=y_2\[k\]-y_1\[k\]\\ E_2\[k\]=y_3\[k\]-y_2\[k\]\\ E_3\[k\]=y_4\[k\]-y_3\[k\]\\ E_4\[k\]=y_1\[k+1\]-y_4\[k\]\end{array}\right.$

Owing to there is not time mismatch, E_i(i=1,2,3,4) distribution should be as shown in Figure 6.According to Statistics, it is put down Average $A_i=\stackrel{\‾}{\left|E_i\right|},(i=1,2,3,4)$ Should be equal.

Between when it is present during mismatch Δ T, situation the most shown in dotted lines in Figure 5.The actual samples time ratio of second channel Ideal time advance so that the one or two interchannel sampling interval T₁Reduce, the sampling interval T between the second triple channel₂Increase Greatly, and the sampling interval of other two adjacency channels is constant.Due to T₁Reduce, E₁Will reduce, and cause its meansigma methods A₁Also subtract Little.In contrast, T₂Increase can make E₂Increase, and cause its meansigma methods A₂Also increase.And E₃、E₄Because its sampling interval is constant, its Meansigma methods A₃、A₄Do not change.

Simulation result when second channel exists sampling time mismatch Δ T is as shown in Figure 7.Comparison diagram 6 and Fig. 7 can be sent out Existing, owing to there is time mismatch Δ T, E₁And E₂Relative to E₃With E₄Occur in that skew.

Fig. 8 is by A_i(i=1,2,3,4) Δ T/T it is depicted as_sFunction, wherein T_sSampling period for time-interleaved ADC.By In the time mismatch of second channel to A₃、A₄Not impact, A₃、A₄Keep constant.And A₁And A₂Respectively along with the change of Δ T, single The increase adjusted and reduction.BecauseKeep constant,Less than zero,More than zero, | B₁| and | B₂| all increase with the increase of | Δ T |.Visible, sampling time mismatch can pass through B_iCharacterized and quantified.

According to above-mentioned principle, we have proposed a kind of digital Background calibration method of time-interleaved ADC sampling time mismatch.

As it is shown in figure 9, produced four phase clocks by DLL, deliver on each passage ADC via delay cell respectively.Passage ADC Simulation output is carried out sample conversion and obtains numeral output y₁[k] (i=1,2,3,4).Adjacency channel numeral is exported and does difference:

$\left\{\begin{array}{c}{E}_1\[k\]=y_2\[k\]-y_1\[k\]\\ E_2\[k\]=y_3\[k\]-y_2\[k\]\\ E_3\[k\]=y_4\[k\]-y_3\[k\]\\ E_4\[k\]=y_1\[k+1\]-y_4\[k\]\end{array}\right.$

K is the sampling period.To E_iIt is averaging and obtainsIn order to characterize interchannel actual samples Time slot.BecauseKeep constant, so in order to characterize interchannel standard sample time slot.Therefore, relatively miss Residual quantityCharacterize and quantified interchannel relative sample times mismatch.Followed by AAR (cumulative and replacement) mould Block, filters statistical error to B_iImpact.Carry out adding up and keeping to error through ACC (cumulative summation) module again, output numeral Code C_i(i=1,2,3,4) carrys out the time delay of feedback regulation respective channel delay cell, thus reduces sampling time mismatch.

In order to verify this figure adjustment algorithm, Matlab is utilized to build behavioral scaling model.Utilize Gauss distribution (u=0, σ =0.01 T_s), four-way sampling time mismatch is set and is followed successively by 9.6ps ,-8.2ps, 12.5ps and 5.5ps.

Figure 10 show the convergence process of each channel sample mismatch time.At initial time, each passage has the mistake of maximum Dosage, along with the carrying out of correction, mismatch is gradually reduced, and finally goes to zero.

Figure 11, Figure 12 are respectively the signal noise harmonic ratio (SNDR) of the time-interleaved ADC before and after correction.Such as Figure 11 institute Show, before correction,WithAt frequency, because sampling time mismatch causes high-octane harmonic wave, SNDR is only 59.7dB, number of significant digit (ENOB) is 9.62bits；As shown in figure 12, after correction, above-mentioned harmonic wave is totally constrained, and SNDR increases It is 11.96bits to 73.8dB, ENOB.

Claims (6)

1. for the bearing calibration of time-interleaved ADC sampling time mismatch, it is characterised in that comprise the following steps:

Input signal is changed by the most time-interleaved ADC；

B. the sampling time gap between adjacency channel ADC is obtained according to the numeral output of each passage of time-interleaved ADC；

C. obtain the sampling time gap between all adjacency channel ADC, and obtain according to gap of all of sampling time adjacent logical Standard sample time slot between road ADC；

D. according to sampling time gap and the amount of mismatch of standard sample time slot acquisition each channel sample time of each passage；

E. amount of mismatch is fed back to clock generating unit, the sampling clock of regulation respective channel.

Bearing calibration for time-interleaved ADC sampling time mismatch the most according to claim 1, it is characterised in that step Rapid b also includes:

B1. the adjacency channel ADC digital output to collecting asks poor, it is assumed that collection is f for incoming frequency_inSinusoidal signal x T (), produces each passage numeral and is output as: Y=[y₁[k],y₂[k],…,y_M[k]], k=1,2, P, wherein M is the time The total number of channels of intertexture ADC, P represents single channel sampling number, then the output of adjacency channel ADC digital asks difference be:

$\left\{\begin{array}{c}{E}_1\[k\]=y_2\[k\]-y_1\[k\]\\ E_2\[k\]=y_3\[k\]-y_2\[k\]\\ \mathrm{......}\\ E_M\[k\]=y_1\[k+1\]-y_M\[k\]\end{array}\right.,k=1,2,\mathrm{...},P;$

B2. to difference E obtained_iThe absolute value summation of [k] is averaged and obtains A_i, A_iWhen being characterized as the sampling between adjacency channel ADC Between gap, $A_i=\stackrel{\‾}{\left|E_i\right|}=\frac{1}{P}\underset{K=1}{\overset{P}{\Σ}}|E_i\[K\]|,$ I=1,2, M.

Bearing calibration for time-interleaved ADC sampling time mismatch the most according to claim 2, it is characterised in that step Rapid c also includes: to all of A_iSummation is averaged and obtains I=1,2, M；It is characterized as adjacent Standard sample time slot between passage ADC.

Bearing calibration for time-interleaved ADC sampling time mismatch the most according to claim 3, it is characterised in that step Rapid d also includes: to all of A_iWithDo difference, obtain:

$\begin{array}{c}{B}_i=A_i-\stackrel{\‾}{A}\\ =\stackrel{\‾}{\left|E_i\right|}-\frac{1}{4}\underset{i=1}{\overset{4}{\Σ}}\stackrel{\‾}{\left|E_i\right|}\end{array}$

B_iFor the relative error in sampling time gap between adjacency channel ADC Yu standard sample time slot, the most each channel sample time Amount of mismatch.

Bearing calibration for time-interleaved ADC sampling time mismatch the most according to claim 4, it is characterised in that step Rapid e also includes: by relative error B_iAccumulated and replacement module filtered eliminates statistical error, feeds back to vairable delay line after summation Regulation channel sample clock.

6. it is used for the corrector of the bearing calibration of time-interleaved ADC sampling time mismatch as claimed in claim 1, including the time Intertexture ADC, data processing unit, feedback unit and clock unit, described data processing unit respectively with time-interleaved ADC and anti- Feedback unit connects,

The output data of time-interleaved ADC are processed by described data processing unit in real time, and will process after data output To feedback unit；

The data that described feedback unit transmits according to data processing unit, carry out feedback operation, signal are fed back to clock unit.