WO2021081753A1 - 显示基板及其制作方法、驱动方法、显示装置 - Google Patents

显示基板及其制作方法、驱动方法、显示装置 Download PDF

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Publication number
WO2021081753A1
WO2021081753A1 PCT/CN2019/113989 CN2019113989W WO2021081753A1 WO 2021081753 A1 WO2021081753 A1 WO 2021081753A1 CN 2019113989 W CN2019113989 W CN 2019113989W WO 2021081753 A1 WO2021081753 A1 WO 2021081753A1
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Prior art keywords
sub
pixel
substrate
transistor
gate
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PCT/CN2019/113989
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English (en)
French (fr)
Inventor
袁粲
李永谦
袁志东
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/971,550 priority Critical patent/US11877482B2/en
Priority to CN201980002187.XA priority patent/CN113272963B/zh
Priority to PCT/CN2019/113989 priority patent/WO2021081753A1/zh
Publication of WO2021081753A1 publication Critical patent/WO2021081753A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, a driving method, and a display device.
  • AMOLED Active-matrix organic light-emitting diode
  • AMOLED Active-matrix organic light-emitting diode
  • the display device of this structure may specifically include a driving circuit film layer, a light-emitting unit, and a color resist.
  • the driving circuit film layer is used to provide a driving signal for the light-emitting unit to make the light-emitting unit emit light, and the light emitted by the light-emitting unit passes through the color resistance unit to realize the display function of the AMOLED display device.
  • the purpose of the present disclosure is to provide a display substrate, a manufacturing method thereof, a driving method, and a display device.
  • a first aspect of the present disclosure provides a display substrate including a substrate, and a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels provided on the substrate;
  • the gate line and the data line are arranged crosswise;
  • the plurality of sub-pixels includes a plurality of sub-pixel columns corresponding to the plurality of data lines one-to-one, and each of the sub-pixel columns includes a plurality of the sub-pixels arranged along an extension direction of the data line;
  • the plurality of sub-pixels include a plurality of sub-pixel rows corresponding to the plurality of gate lines one-to-one, and each of the sub-pixel rows includes a plurality of the sub-pixels arranged along an extension direction of the gate lines;
  • Each of the sub-pixels includes a sub-pixel driving circuit that includes a driving transistor, a data writing transistor, and a sensing transistor, and the driving transistor and the data writing transistor are located in the opening area of the sub-pixel
  • the sensing transistor is located on the second side of the opening area of the sub-pixel, and the first side and the second side are opposite along the extension direction of the data line; the data writing transistor The second electrode is coupled to the corresponding data line; the gates of the sensing transistors located in the sub-pixel row of the same row and the gates of the data writing transistors in the adjacent sub-pixel row of the next row are both The gate line corresponding to the next row of sub-pixel rows is coupled;
  • the sub-pixel driving circuit further includes a storage capacitor coupled between the gate of the driving transistor and the first electrode of the driving transistor, and the storage capacitor includes a first electrode plate and a second electrode plate arranged oppositely ,
  • the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the second electrode plate on the substrate have a first overlap area, and the first overlap area is on the substrate
  • the orthographic projection and the corresponding orthographic projection of the opening area of the sub-pixel on the substrate at least partially overlap.
  • the first pole of the data writing transistor is located on the third side of the corresponding gate line
  • the second pole of the data writing transistor is located on the fourth side of the corresponding gate line.
  • the third side and The fourth side is opposite along the extending direction of the data line;
  • the orthographic projection of the channel portion of the data writing transistor on the substrate is located inside the orthographic projection of the corresponding gate line on the substrate;
  • the first electrode of the sensing transistor is located on the third side of the gate line corresponding to the next adjacent sub-pixel row, and the second electrode of the sensing transistor is located on the gate corresponding to the next adjacent sub-pixel row.
  • the gate lines are multiplexed at the same time as the gates of the data writing transistors in the corresponding sub-pixel row and the gates of the sensing transistors in the sub-pixels of the previous row adjacent to the sub-pixel row.
  • the first plate of the storage capacitor includes a first transparent plate
  • the second plate of the storage capacitor includes a second transparent plate
  • the sub-pixel driving circuit further includes:
  • a first conductive connection portion a first end of the first conductive connection portion is coupled to the first electrode of the driving transistor, and a second end of the first conductive connection portion is connected to the second electrode of the sensing transistor Coupled, the first conductive connection portion is multiplexed as the second transparent plate.
  • the display substrate further includes a buffer layer disposed on the surface of the base, the first transparent plate of the storage capacitor is located between the buffer layer and the base, and the second transparent plate of the storage capacitor is located between the buffer layer and the base.
  • the transparent electrode plate is located on the surface of the buffer layer facing away from the substrate.
  • the orthographic projection of the first overlap area on the substrate and the orthographic projection of the corresponding sub-pixel opening area on the substrate have a fifth overlap area, and the fifth overlap area
  • the area of the overlap area is between 1/4 to 3/4 of the area of the corresponding opening area.
  • the first conductive connection portion, the first electrode of the driving transistor, and the second electrode of the sensing transistor are arranged in the same layer, and all are made of a transparent oxide conductor material.
  • the sub-pixel driving circuit further includes:
  • a second conductive connection part, the second conductive connection part is respectively coupled with the first electrode of the data writing transistor, the first transparent plate and the gate of the driving transistor.
  • the second conductive connection portion passes through
  • the first via hole provided in the second overlapping area is coupled to the gate of the driving transistor
  • the orthographic projection of the second conductive connection portion on the substrate and the orthographic projection of the first transparent electrode plate on the substrate have a fourth overlapping area, and the second conductive connection portion is disposed on the The third via hole in the fourth overlapping area is coupled to the first transparent plate.
  • the sub-pixel driving circuit further includes:
  • the third conductive connection portion, the orthographic projection of the third conductive connection portion on the substrate and the orthographic projection of the first conductive connection portion on the substrate have a sixth overlapping area, the third conductive connection Part is coupled to the first conductive connection part through a fourth via provided in the sixth overlap region;
  • the sub-pixel further includes a light-emitting unit disposed on a side of the sub-pixel driving circuit facing away from the substrate, and the light-emitting unit includes an anode, a light-emitting layer, and a cathode that are sequentially stacked in a direction away from the substrate.
  • the light-emitting unit includes an anode, a light-emitting layer, and a cathode that are sequentially stacked in a direction away from the substrate.
  • the hole is coupled to the third conductive connection portion.
  • the orthographic projection of the anode on the substrate overlaps the orthographic projection of the corresponding second transparent plate of the storage capacitor on the substrate.
  • the display substrate further includes a light-shielding layer disposed on the surface of the base, and the orthographic projection of the light-shielding layer on the base covers all the positive projections of the driving transistors on the base.
  • the first electrode plate and the light shielding layer are provided in the same layer.
  • the light-shielding layer on the substrate there is an eighth overlapping area between the orthographic projection of the light-shielding layer on the substrate and the orthographic projection of the first electrode of the driving transistor on the substrate, and the light-shielding layer is disposed on the second
  • the sixth via hole in the eight-overlap area is coupled to the first pole of the driving transistor.
  • the display substrate further includes:
  • the color group pattern corresponding to the sub-pixels one-to-one, the color resist pattern is located between the corresponding sub-pixel drive circuit and the light-emitting unit, and the orthographic projection of the color group pattern on the substrate Overlap with the orthographic projection of the opening area of the corresponding sub-pixel on the substrate;
  • the adjacent power signal line and the sensing signal line include two columns of the sub-pixel columns, and the two data lines corresponding to the two columns of the sub-pixel columns are located between the two columns of the sub-pixel columns. In between, the two columns of the sub-pixel columns correspond to the adjacent power signal lines;
  • the plurality of sub-pixels constitute a plurality of pixel units, each of the pixel units includes at least three adjacent sub-pixels located in the same sub-pixel row, and the colors of the color group graphics corresponding to the at least three sub-pixels are different ,
  • the plurality of pixel units includes a plurality of pixel unit columns, each of the pixel unit columns includes a plurality of the pixel units arranged along the extension direction of the data line, and the plurality of pixel unit columns are The multiple sensing signal lines are in one-to-one correspondence;
  • the gate of the driving transistor is coupled to the first electrode of the data writing transistor; the second electrode of the driving transistor is connected to the corresponding power signal Line coupling; the second pole of the sensing transistor is coupled to the corresponding sensing signal line.
  • the display substrate further includes a fourth conductive connection part corresponding to the power signal line one-to-one, and the orthographic projection of the fourth conductive connection part on the base is in a position with the corresponding power signal line.
  • the orthographic projection on the substrate has a ninth overlapping area, and the fourth conductive connecting portion is coupled to the corresponding power signal line through at least one seventh via provided in the ninth overlapping area.
  • the fourth conductive connecting portion and the gate electrode of the driving transistor are provided with the same layer and the same material.
  • the color group graphics corresponding to the at least three sub-pixels included in each pixel unit specifically include: a red color group graphic, a white color group graphic, a blue color group graphic, and a green color group graphic .
  • a second aspect of the present disclosure provides a display device including the above display substrate.
  • a third aspect of the present disclosure provides a manufacturing method of a display substrate, including:
  • the plurality of sub-pixels includes a plurality of sub-pixel columns corresponding to the plurality of data lines one-to-one, and each of the sub-pixel columns includes a plurality of the sub-pixels arranged along an extension direction of the data line;
  • the plurality of sub-pixels include a plurality of sub-pixel rows corresponding to the plurality of gate lines one-to-one, and each of the sub-pixel rows includes a plurality of the sub-pixels arranged along an extension direction of the gate lines;
  • Each of the sub-pixels includes a sub-pixel driving circuit that includes a driving transistor, a data writing transistor, and a sensing transistor, and the driving transistor and the data writing transistor are located in the opening area of the sub-pixel
  • the sensing transistor is located on the second side of the opening area of the sub-pixel, and the first side and the second side are opposite along the extension direction of the data line; the data writing transistor
  • the second electrode is coupled to the corresponding data line; the gate of the sensing transistor and the gate of the data writing transistor in the next row of sub-pixel rows adjacent to it are all connected to the next row of sub-pixel rows. Corresponding gate line coupling;
  • the sub-pixel driving circuit further includes a storage capacitor coupled between the gate of the driving transistor and the first electrode of the driving transistor, and the storage capacitor includes a first electrode plate and a second electrode plate arranged oppositely ,
  • the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the second electrode plate on the substrate have a first overlap area, and the first overlap area is on the substrate
  • the orthographic projection and the corresponding orthographic projection of the opening area of the sub-pixel on the substrate at least partially overlap.
  • the first plate of the storage capacitor includes a first transparent plate
  • the second plate of the storage capacitor includes a second transparent plate
  • the step of manufacturing the sub-pixel driving circuit specifically includes:
  • a buffer layer is fabricated on the side of the light-shielding layer facing away from the substrate, and a sixth via hole and a transition hole are formed on the buffer layer, and the sixth via hole exposes a part of the light-shielding layer, and the transition hole exposes Part of the first transparent plate;
  • the first electrode of the driving transistor, the second electrode of the sensing transistor, and a first conductive connection part are fabricated on the side of the buffer layer facing away from the substrate.
  • the first electrode of the driving transistor is coupled, the second end of the first conductive connection portion is coupled to the second electrode of the sensing transistor, and the first conductive connection portion is multiplexed as the second transparent electrode Plate;
  • the first electrode of the driving transistor is coupled to the light shielding layer through the sixth via;
  • An interlayer insulating layer is formed on the side of the gate of the driving transistor facing away from the substrate, and a first via hole, a third via hole, and a fourth via hole are formed on the interlayer insulating layer, and the first A via hole exposes a portion of the gate of the driving transistor, the third via hole exposes a portion of the first transparent plate, and the orthographic projection of the third via hole on the substrate surrounds the transition hole in the Orthographic projection on the substrate, where the fourth via hole exposes a part of the second transparent electrode plate;
  • a second conductive connection portion and a third conductive connection portion are formed at the same time, the second conductive connection portion is coupled to the gate through the first via hole, and the second conductive connection portion passes through the The third via hole is coupled to the first transparent plate, and the second conductive connection part is also coupled to the first electrode of the data writing transistor in the sub-pixel driving circuit; the third conductive connection part passes through The fourth via is coupled to the second transparent plate.
  • the step of manufacturing the light-emitting unit in the sub-pixel specifically includes:
  • a cathode is fabricated on the side of the light-emitting layer facing away from the substrate.
  • a fourth aspect of the present disclosure provides a driving method of a display substrate, including a power-on period and a power-off period:
  • the power-on period includes a plurality of display periods, and in each display period,
  • the first scan signals are written to the plurality of gate lines in the display substrate one by one, and the effective level period part of the first scan signals input from adjacent to the gate lines overlapping;
  • the first scan signal written by the gate line corresponding to the previous row of sub-pixels is at an effective level, and the first scan signal written by the gate line corresponding to the next row of sub-pixels is at
  • the data writing transistor included in each sub-pixel drive circuit in the previous row of sub-pixels is turned on, and the data signal written by each data writing transistor correspondingly coupled to the data line is transmitted to its correspondingly coupled drive transistor
  • the sensing transistor included in each sub-pixel driving circuit in the previous row of sub-pixels is turned on, and the reset signal written by each sensing transistor correspondingly coupled to the sensing signal line is transmitted to its correspondingly coupled
  • the first scan signal written by the gate line corresponding to the previous row of sub-pixels is at an inactive level, and the first scan signal written by the gate line corresponding to the next row of sub-pixels When it is at an effective level, the driving transistor and the sensing transistor in the sub-pixels in the previous row are both turned on to charge the sensing signal line coupled to the sensing transistor;
  • the first scan signal written by the gate line corresponding to the previous row of sub-pixels is at an inactive level, and the first scan signal written by the gate line corresponding to the next row of sub-pixels At the inactive level, the driving transistors in the sub-pixels in the previous row are turned on, the sensing transistors in the sub-pixels in the previous row are turned off, and the light-emitting units in the sub-pixels in the previous row emit light.
  • a second scan signal is written to the plurality of gate lines in the display substrate one by one, and the second scan signal includes a first effective level period and a second interval arranged at intervals. Effective level period; among the adjacent gate lines, the second effective level period of the second scan signal input from the previous gate line coincides with the first effective level period of the second scan signal input from the next gate line ;
  • the data writing transistor and the sensing transistor included in the sub-pixel row corresponding to the previous gate line are all in the on state ;
  • the data writing transistor transmits the initialization signal written by the correspondingly coupled data line to the gate of its correspondingly coupled driving transistor, and the sensing transistor will The reset signal written in the correspondingly coupled sensing signal line is transmitted to the first pole of the correspondingly coupled driving transistor;
  • the sensing signal line stops writing the initialization signal, and the data writing transistor continues to transmit the initialization signal written by the corresponding coupled data line to it Corresponding to the gate of the coupled driving transistor, turning on the driving transistor to charge the sensing signal line until the gate-source voltage of the driving transistor is equal to the threshold voltage of the driving transistor;
  • the sensing transistor transmits the voltage signal of the first electrode of the driving transistor to which it is coupled to the sensing signal line to which it is coupled.
  • FIG. 1 is a schematic structural diagram of a sub-pixel driving circuit provided by the present disclosure
  • FIG. 2 is a schematic diagram of a layout of a pixel unit in a display substrate provided by an embodiment of the disclosure
  • FIG. 3 is a schematic diagram of the layout of the light shielding layer and the first transparent plate provided by the embodiments of the disclosure;
  • FIG. 4 is a schematic diagram of the layout of an active film layer provided by an embodiment of the disclosure.
  • FIG. 5 is a schematic diagram of the layout of a gate metal layer provided by an embodiment of the disclosure.
  • FIG. 6 is a schematic diagram of the layout of source and drain metal layers provided by an embodiment of the disclosure.
  • FIG. 7 is a schematic diagram of the layout of an anode provided by an embodiment of the disclosure.
  • FIG. 8 is a schematic diagram of forming a via hole on the buffer layer provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of forming an active film layer and a gate provided by an embodiment of the disclosure.
  • FIG. 10 is a schematic diagram of forming a via hole on an interlayer insulating layer provided by an embodiment of the present disclosure
  • FIG. 11 is a schematic cross-sectional view along the AA direction in FIG. 2;
  • FIG. 12 is a schematic diagram of the overall layout of a display substrate provided by an embodiment of the disclosure.
  • FIG. 13 is a schematic diagram of a gate driving sequence during a startup period of a display substrate according to an embodiment of the disclosure
  • FIG. 14 is a schematic diagram of a gate driving sequence during a shutdown period of a display substrate provided by an embodiment of the disclosure.
  • the display substrate provided by the present disclosure includes a transparent substrate and a plurality of sub-pixels arranged on the substrate.
  • Each sub-pixel includes a sub-pixel driving circuit and a light-emitting unit.
  • the sub-pixel driving circuit includes a variety of structures, for example, As shown in FIG.
  • the sub-pixel driving circuit includes a driving transistor T1, a data writing transistor T2, a sensing transistor T3, and a storage capacitor Cst;
  • the second electrode D1 of the driving transistor T1 is coupled to the power signal line VDD, and
  • the gate G1 of the driving transistor T1 is coupled to the first plate of the storage capacitor Cst, the first electrode S1 of the driving transistor T1 is coupled to the second plate of the storage capacitor Cst;
  • the data writing transistor T2 The gate G2 is coupled to the corresponding gate line (such as G(n) and G(n+1)), the second electrode D2 of the data writing transistor T2 is coupled to the data line Data, and the data writing
  • the first electrode S2 of the input transistor T2 is coupled to the gate G1 of the driving transistor T1;
  • the gate G3 of the sensing transistor T3 is coupled to the corresponding gate line, and the first electrode S3 of the sensing transistor T3 It is coupled to the sensing signal line SL, and the second pole D3 of the sensing transistor
  • Each sub-pixel includes an opening area and a non-aperture area located at the periphery of the opening area.
  • the non-aperture area is generally laid out with the sub-pixel driving circuit included in the sub-pixel, and the open area is generally laid out to emit light.
  • the sub-pixel drive circuit provides driving signals to the light-emitting unit to make the light-emitting unit emit light, and the light emitted by the light-emitting unit passes through the color-resist unit and exits the display substrate, so that all The display substrate realizes the display function.
  • the driving transistor T1, the sensing transistor T3, the data writing transistor T2 and the storage capacitor Cst included in each sub-pixel driving circuit are all located in the non-opening area of the sub-pixel, resulting in the required
  • the layout space of the non-opening area is relatively large, and because the actual layout space of the non-opening area is limited, the orthographic projection of the plate of the storage capacitor Cst on the substrate and the signal line (such as the gate line) in the display substrate are on the substrate. There is overlap between the orthographic projections on the upper side, which causes the storage capacitor Cst to cross the line. This situation is likely to increase the risk of crosstalk.
  • the transistors included in the sub-pixel driving circuit generally use oxide transistors, and the oxide transistors require a large layout space, which will result in the area of the non-opening area of the sub-pixels. Further increase will affect the aperture ratio and service life of the display substrate.
  • the inventors of the present disclosure have discovered through research that the above-mentioned problems can be solved by setting the storage capacitor Cst in the sub-pixel driving circuit as a transparent structure and arranging it in the opening area of the sub-pixel.
  • an embodiment of the present disclosure provides a display substrate, including a base 10, and a plurality of gate lines (such as G(n) and G(n+1) provided on the base 10 )), multiple data lines (such as: DR, DW, DB, DG) and multiple sub-pixels; the gate line and the data line are arranged crosswise; the multiple sub-pixels include one-to-one with the multiple data lines A plurality of corresponding sub-pixel columns, each of the sub-pixel columns includes a plurality of the sub-pixels arranged along the extension direction of the data line; the plurality of sub-pixels includes one-to-one correspondence with the plurality of gate lines A plurality of sub-pixel rows, each of the sub-pixel rows includes a plurality of the sub-pixels arranged along the extending direction of the gate line;
  • Each of the sub-pixels includes a sub-pixel driving circuit that includes a driving transistor T1, a data writing transistor T2, and a sensing transistor T3, and the driving transistor T1 and the data writing transistor T2 are located here
  • the sensing transistor T3 is located on the second side of the opening area of the sub-pixel, and the first side and the second side are opposite along the extending direction of the data line;
  • the second electrode D2 of the data writing transistor T2 is coupled to the corresponding data line;
  • the gate G3 of the sensing transistor T3 located in the same row of sub-pixel rows is connected to all of the adjacent sub-pixel rows in the next row.
  • the gate G2 of the data writing transistor T2 is coupled to the gate line corresponding to the sub-pixel row in the next row;
  • the sub-pixel driving circuit further includes a storage capacitor Cst coupled between the gate G1 of the driving transistor T1 and the first electrode S1 of the driving transistor T1, and the storage capacitor Cst includes first electrodes disposed oppositely.
  • Plate 30 and a second electrode plate, the orthographic projection of the first electrode plate 30 on the substrate 10 and the orthographic projection of the second electrode plate on the substrate 10 have a first overlapping area, and the second The orthographic projection of an overlapping area on the substrate 10 and the orthographic projection of the corresponding opening area 97 of the sub-pixel on the substrate 10 at least partially overlap.
  • the display substrate adopts a bottom emission structure
  • the base 10 included in the display substrate may adopt a transparent base.
  • the plurality of sub-pixels included in the display substrate may be distributed in an array, and the plurality of sub-pixels may be divided into a plurality of sub-pixel rows and a plurality of sub-pixel columns, and each of the sub-pixel rows includes arrays arranged along the second direction.
  • Each of the sub-pixel columns includes a plurality of the sub-pixels arranged along the first direction.
  • the first direction is the Y direction
  • the second The direction is the X direction.
  • the plurality of sub-pixel columns can be arranged in a one-to-one correspondence with the data lines, so that each sub-pixel in the same column of sub-pixel columns Multiplexing the same corresponding data line; setting the multiple sub-pixel rows to correspond to the gate lines one-to-one, so that each sub-pixel in the same row of sub-pixel rows multiplexes the same corresponding gate line.
  • the gate G2 of the data writing transistor T2 is coupled to the corresponding gate line, and the second of the data writing transistor T2 is The electrode D2 is coupled to the corresponding data line, the first electrode S2 of the data writing transistor T2 is coupled to the gate G1 of the driving transistor T1; the gate G3 of the sensing transistor T3 is adjacent to The gate line corresponding to the next sub-pixel row is coupled, the first electrode S3 of the sensing transistor T3 is coupled to the first electrode S1 of the driving transistor T1, and the first electrode S1 of the sensing transistor T3 is coupled The diode D3 is coupled to the corresponding sensing signal line SL.
  • the storage capacitor Cst may include a first electrode plate 30 and a second electrode plate disposed opposite to each other.
  • the first electrode plate 30 is coupled to the gate G1 of the driving transistor T1, and the second electrode
  • the plate is coupled to the gate G1 of the driving transistor T1; at least part of the first plate 30 and at least part of the second plate can be arranged in the opening area 97 of the sub-pixel, for example ,
  • the orthographic projection of the first electrode plate 30 on the substrate 10 and the orthographic projection of the second electrode plate on the substrate 10 form a first overlapping area, and the first overlapping area is on the substrate
  • the orthographic projection on 10 and the corresponding orthographic projection of the opening area 97 of the sub-pixel on the substrate 10 at least partially overlap; or, the orthographic projection of the first overlapping area on the substrate 10 is located at the corresponding The opening area 97 of the sub-pixel is inside the orthographic projection on the substrate 10.
  • the driving transistor T1 and The data writing transistor T2 is arranged on the first side of the opening area of the sub-pixel, and the sensing transistor T3 is arranged on the second side of the opening area of the sub-pixel, so that in adjacent sub-pixel rows,
  • the sensing transistor T3 included in the sub-pixels of the previous row can be close to the data writing transistor T2 included in the sub-pixels of the next row, and the gate of the sensing transistor T3 included in the sub-pixels of the previous row G3, and the gate G2 of the data writing transistor T2 included in the next row of sub-pixels are both coupled to the gate line corresponding to the next row of sub-pixels, so that the gate line can be used in the previous row of sub-pixels at the same time.
  • the gate G3 of the sensing transistor T3 included and the gate G2 of the data writing transistor T2 included in the next row of sub-pixels provide scanning signals; therefore, in the display substrate provided by the embodiment of the present disclosure, the above-mentioned
  • the layout is such that the sensing transistor T3 included in each sub-pixel of the same sub-pixel row can share the same gate line with the data writing transistor T2 included in each sub-pixel of the next adjacent sub-pixel row, thereby The layout number of signal lines is reduced, and the pixel aperture ratio is improved.
  • the storage capacitor Cst in the sub-pixel driving circuit is laid out in the opening area 97 of the sub-pixel, which not only avoids all the storage capacitors Cst being laid out in the non-open area 97
  • the cross-line condition that exists at the time ensures the stable working performance of the sub-pixel drive circuit.
  • the storage capacitor Cst since the storage capacitor Cst has a large enough layout space, it is more conducive to the improvement of the capacitance value of the storage capacitor Cst, thereby helping to improve the display of the display substrate. Uniformity of picture quality.
  • arranging at least part of the storage capacitor Cst in the sub-pixel driving circuit in the opening area 97 of the sub-pixel can also effectively reduce the area of the non-aperture area 97 of the sub-pixel, thereby increasing the aperture ratio of the sub-pixel.
  • the 8K high-resolution display substrate can achieve an average aperture ratio of about 12% according to the conventional design.
  • the average aperture ratio can be increased to about 30%. Therefore, compared with the traditional design, the display substrate provided by the embodiments of the present disclosure can increase the aperture ratio by about 150%, which significantly improves the life of the product and is a high-PPI bottom emission display field. , Provides technical support.
  • the first electrode S2 of the data writing transistor T2 is located on the third side of the corresponding gate line, and the second electrode D2 of the data writing transistor T2 is located on the fourth side of the corresponding gate line, The third side and the fourth side are opposite along the extension direction of the data line; the orthographic projection of the channel portion of the data writing transistor T2 on the substrate 10 is located on the corresponding gate line in the The interior of the orthographic projection on the substrate 10;
  • the first electrode S3 of the sensing transistor T3 is located on the third side of the gate line corresponding to the next row of sub-pixels adjacent to it, and the second electrode D3 of the sensing transistor T3 is located on the next row of sub-pixels adjacent to it.
  • the fourth side of the gate line corresponding to the row; the orthographic projection of the channel portion of the sensing transistor T3 on the substrate 10, and the gate line corresponding to the next row of sub-pixel rows adjacent to the sensing transistor T3 is in the The inside of the orthographic projection on the substrate 10;
  • the gate line is simultaneously multiplexed as the gate of each data writing transistor T2 in the corresponding sub-pixel row, and the gate of the sensing transistor T3 in the sub-pixel of the previous row adjacent to the sub-pixel row.
  • the first pole S2 of the data writing transistor T2 can be arranged on the third side of the corresponding gate line, and the data writing transistor T2
  • the second electrode D2 is arranged on the fourth side of the corresponding gate line, so that the data writing transistor T2 is connected to the first electrode S2 of the data writing transistor T2 and the second electrode S2 of the data writing transistor T2.
  • the channel portion of T2 of the pole D2 can be located near the gate line corresponding to the data writing transistor T2.
  • the orthographic projection of the channel portion of the data writing transistor T2 on the substrate 10 By further setting the orthographic projection of the channel portion of the data writing transistor T2 on the substrate 10, it is located at the corresponding Inside the orthographic projection of the gate line on the substrate 10, the corresponding gate line can be directly multiplexed into the gate of the data writing transistor T2.
  • the first electrode S3 of the sensing transistor T3 can be arranged on the third side of the gate line corresponding to the next row of sub-pixels adjacent to it, and the sensing transistor T3
  • the second electrode D3 of the sensing transistor T3 is arranged on the fourth side of the gate line corresponding to the next row of sub-pixel rows adjacent thereto, so that the sensing transistor T3 is connected to the first electrode S3 of the sensing transistor T3
  • the channel part of the second electrode D3 of the sensing transistor T3 can be located near the gate line corresponding to the next row of sub-pixel rows adjacent to the sensing transistor T3, and the channel portion of the sensing transistor T3 can be further provided.
  • the orthographic projection of the channel portion on the substrate 10 is located inside the orthographic projection of the gate line on the substrate 10, so that the gate line can be directly multiplexed as the gate of the sensing transistor T3.
  • the sensing transistor T3 and the data writing transistor T2 are laid out in the above-mentioned manner, so that both the sensing transistor T3 and the data writing transistor T2 can be formed in a structure that spans the gate line.
  • the first plate 30 of the storage capacitor includes a first transparent plate
  • the second plate of the storage capacitor includes a second transparent plate
  • the sub-pixel driving circuit further includes:
  • a first conductive connection portion 60 a first end of the first conductive connection portion 60 is coupled to the first pole S1 of the driving transistor T1, and a second end of the first conductive connection portion 60 is connected to the sensing
  • the second electrode D3 of the transistor T3 is coupled, and the first conductive connection portion 60 is multiplexed as the second transparent electrode plate.
  • the gate G3 of the sensing transistor T3 can be coupled to the first scanning signal input terminal, the first electrode S3 of the sensing transistor T3 can be coupled to the sensing signal output terminal, and the sensing transistor The second pole D3 of T3 can be coupled to the first pole S1 of the driving transistor T1.
  • the specific layout of the sensing transistor T3 is various.
  • the driving transistor T1 is located on the first side of the corresponding opening area
  • the sensing transistor T3 is located on the second side of the corresponding opening area, and the first side and the second side are opposite; in this layout, the sub-pixel driving circuit can be provided to further include the first conductive connection portion 60,
  • the first terminal of the first conductive connecting portion 60 is coupled to the first electrode S1 of the driving transistor T1
  • the second terminal of the first conductive connecting portion 60 is connected to the second electrode of the sensing transistor T3.
  • the D3 coupling realizes the coupling of the first pole S1 of the driving transistor T1 and the second pole D3 of the sensing transistor T3.
  • the orthographic projection of the first conductive connection portion 60 on the substrate 10 and the orthographic projection of the corresponding sub-pixel opening area 97 on the substrate 10 may at least partially overlap, because the storage capacitor
  • the second transparent electrode plate of Cst is respectively coupled to the first electrode S1 of the driving transistor T1 and the second electrode D3 of the sensing transistor T3. Therefore, the first conductive connection portion 60 can be multiplexed as all Mentioned second transparent polar plate.
  • the driving transistor T1 and the sensing transistor T3 are disposed on opposite sides of the opening area 97, and can pass through the opening area 97 for coupling to the second side of the driving transistor T1.
  • One pole S1 and the first conductive connecting portion 60 of the second pole D3 of the sensing transistor T3 are multiplexed as the second transparent plate of the storage capacitor Cst, so that the space occupied by the sub-pixel drive circuit is Effectively shrink, thereby effectively increasing the aperture ratio of the display substrate.
  • the first plate 30 of the storage capacitor includes a first transparent plate
  • the second plate of the storage capacitor includes a second transparent plate, so that the storage capacitor
  • the first plate 30 and the second plate of the capacitor will not affect the light output of the opening area, so that the display substrate is lifted.
  • the aperture ratio of the sub-pixels can also ensure a good light-emitting effect.
  • the display substrate further includes a buffer layer 40 disposed on the surface of the base 10, and the first transparent plate of the storage capacitor Cst is located on the buffer layer 40 and the buffer layer 40. Between the substrates 10, the second transparent plate of the storage capacitor Cst is located on the surface of the buffer layer 40 facing away from the substrate 10.
  • the specific layout positions of the first transparent electrode plate and the second transparent electrode plate are various.
  • the display substrate further includes a buffer layer 40 provided on the surface of the base 10
  • the first transparent electrode plate can be arranged between the buffer layer 40 and the substrate 10
  • the second transparent electrode plate can be arranged on the surface of the buffer layer 40 facing away from the substrate 10; Since the buffer layer 40 is thinner in the direction perpendicular to the substrate 10, this layout makes the distance between the first transparent electrode plate and the second transparent electrode plate shorter, which is beneficial to increase
  • the capacitance value of the storage capacitor Cst improves the uniformity of the image quality of the display substrate.
  • an orthographic projection of the first overlapping area on the substrate 10 may be set, and there is a fifth overlapping area with the corresponding orthographic projection of the opening area of the sub-pixel on the substrate 10
  • the area of the fifth overlapping area is between 1/4 to 3/4 of the area of the corresponding opening area.
  • the area of the first transparent electrode plate and the second transparent electrode plate can be appropriately reduced.
  • the first transparent electrode plate can be set The orthographic projection of the overlapping area on the substrate 10 and the corresponding orthographic projection of the opening area of the sub-pixel on the substrate 10 have a fifth overlapping area, and the area of the fifth overlapping area is in the corresponding The area of the opening area is between 1/4 to 3/4; this arrangement ensures that the capacitance of the storage capacitor Cst is sufficient, so that the first transparent electrode plate and the second The two transparent plates only occupy a part of the opening area, thereby increasing the luminous flux of short-wavelength light passing through the opening area, and guaranteeing the transmittance of the opening area to a certain extent. It is a high-resolution bottom emission display substrate Provide basic support.
  • the first conductive connecting portion 60, the first electrode S1 of the driving transistor T1 and the second electrode D3 of the sensing transistor T3 are arranged in the same layer, And all use transparent oxide conductor materials.
  • an oxide semiconductor material may be used to form an active pattern first, and the active pattern includes an active pattern for forming the channel region of the driving transistor T1.
  • the first part, and the second part for forming the channel region of the sensing transistor T3, dope other parts of the active pattern except the first part and the second part to Make other parts become transparent oxide conductors.
  • the other parts include the first electrode S1 and the second electrode D1 of the driving transistor T1, the first electrode S3 and the second electrode D3 of the sensing transistor T3, and the first conductive connection portion 60 .
  • the first conductive connecting portion 60, the first electrode S1 of the driving transistor T1 and the second electrode D3 of the sensing transistor T3 are arranged in the same layer and the same material, so that the The first conductive connecting portion 60, the first electrode S1 of the driving transistor T1 and the second electrode D3 of the sensing transistor T3 can be formed in the same patterning process, thereby effectively simplifying the manufacturing process of the display substrate , Saving production costs.
  • the sub-pixel driving circuit further includes:
  • the second conductive connection portion 82 is respectively coupled to the first electrode S2 of the data writing transistor T2, the first transparent electrode plate and the gate G1 of the driving transistor T1.
  • the sub-pixel driving circuit may further include a data writing transistor T2, the gate G2 of the data writing transistor T2 is coupled to the second scan signal input terminal, and the first electrode of the data writing transistor T2 S2 is coupled to the gate G1 of the driving transistor T1, and the second pole D2 of the data writing transistor T2 is coupled to the data signal input terminal.
  • the data write transistor T2 is used to turn on under the control of the second scan type input from the second scan signal input terminal during the data write stage to write the data signal input from the data signal input terminal
  • the specific layout positions of the data writing transistor T2 are various.
  • the data writing transistor T2 is located in the driving transistor T1 away from the corresponding opening area
  • the sub-pixel drive circuit can be provided to include the second conductive connection portion 82, through the second conductive connection portion 82 to write the data into the first electrode S2 of the transistor T2 , The first transparent plate and the gate G1 of the driving transistor T1 are coupled together.
  • the data writing transistor T2 is arranged on the side of the driving transistor T1 away from the corresponding opening area, and the data is realized through the second conductive connection portion 82
  • the first electrode S2 of the writing transistor T2, the first transparent plate and the gate G1 of the driving transistor T1 are coupled, so that the space occupied by the sub-pixel driving circuit is effectively reduced, thereby effectively improving the
  • the description shows the aperture ratio of the substrate.
  • the orthographic projection of the second conductive connection portion 82 on the substrate 10 and the orthographic projection of the first transparent plate on the substrate 10 have a fourth overlap area, and the second conductive connection portion 82 passes The third via 72 provided in the fourth overlapping area is coupled to the first transparent plate.
  • the specific coupling manner of the second conductive connecting portion 82 and the first electrode S2 of the data writing transistor T2, the first transparent electrode plate and the gate G1 of the driving transistor T1 can be determined according to The specific layout position of the second conductive connection portion 82 is determined. For example, when the second conductive connection portion 82 is connected to the first electrode S2 of the data writing transistor T2, the first transparent electrode plate and the When the gate G1 of the driving transistor T1 is of different layers, it can be arranged in a direction perpendicular to the substrate 10, and the second conductive connection portion 82 can be connected to the first electrode S2 of the data writing transistor T2, respectively.
  • the first transparent plate and the gate G1 of the driving transistor T1 form an overlapping area, so that the second conductive connection portion 82 can write the data by forming a via in the corresponding overlapping area.
  • the first electrode S2 of the input transistor T2, the first transparent plate and the gate G1 of the driving transistor T1 are coupled.
  • the second conductive connection portion 82, the first electrode S2 of the data writing transistor T2, the first transparent plate and the driving transistor may not be arranged in the same layer.
  • the data can be written to the first electrode S2 of the transistor T2, the first transparent plate, and the gate of the driving transistor T1 in the above-mentioned manner.
  • the poles G1 are coupled together.
  • the sub-pixel driving circuit further includes:
  • the third conductive connection portion 81, the orthographic projection of the third conductive connection portion 81 on the substrate 10 and the orthographic projection of the first conductive connection portion 60 on the substrate 10 have a sixth overlapping area, so The third conductive connection portion 81 is coupled to the first conductive connection portion 60 through a fourth via 71 provided in the sixth overlapping area;
  • the sub-pixel also includes a light-emitting unit disposed on the side of the sub-pixel driving circuit facing away from the substrate.
  • the light-emitting unit includes an anode 92, a light-emitting layer 94, and a light-emitting layer 94 that are sequentially stacked in a direction away from the substrate 10.
  • the cathode 95, the orthographic projection of the anode 92 on the substrate 10 and the orthographic projection of the third conductive connecting portion 81 on the substrate 10 have a seventh overlapping area, and the anode 92 is disposed on the The fifth via hole in the seventh overlapping area is coupled to the third conductive connection portion 81.
  • the light-emitting unit may specifically include an anode 92, a light-emitting layer 94, and a cathode 95 that are sequentially stacked in a direction away from the substrate 10.
  • the anode 92 needs to be coupled to the first electrode S1 of the corresponding driving transistor T1.
  • the light-emitting layer 94 can be made of organic light-emitting material, and the light-emitting layer 94 can be formed between the anode 92 and the cathode 95 White light is emitted under the action of electric field.
  • the anode 92 of the light-emitting unit and the first electrode S1 of the driving transistor T1 are far apart, the anode 92 and the first electrode S1 of the driving transistor T1 are directly coupled to At the same time, there are difficulties. Therefore, it can be considered that the anode 92 is directly coupled to the first conductive connection portion 60 (that is, the second transparent electrode plate), so that the anode 92 can pass through the first conductive connection portion 60. It is coupled to the gate G1 of the driving transistor T1; however, since there is a thicker film between the anode 92 and the first conductive connection portion 60 in the direction perpendicular to the substrate 10, if The coupling of the two is realized directly through a via hole. On the one hand, the process is difficult and accuracy cannot be guaranteed. On the other hand, the anode 92 is deposited in a deeper via hole, which is prone to fracture at the hole wall, and reliability cannot be guaranteed. .
  • the third conductive connection portion 81 is provided so that the orthographic projection of the third conductive connection portion 81 on the base 10 is consistent with the first conductive connection portion 60
  • the orthographic projection of the anode 92 on the substrate 10 and the orthographic projection of the third conductive connection portion 81 on the substrate 10 can form a seventh overlapping area, and the anode 92 is provided by The fifth via hole in the seventh overlapping area is coupled to the third conductive connection portion 81, so that the anode 92 passes through the fifth via hole, the third conductive connection portion 81 and the The fourth via 71 is coupled to the first conductive connection portion 60.
  • the coupling manner of the anode 92 and the first conductive connecting portion 60 provided by the above-mentioned embodiment not only has a simple implementation process and high accuracy of via holes, but also ensures that the anode 92 has high reliability.
  • the orthographic projection of the anode 92 on the substrate 10 intersects the orthographic projection of the corresponding second transparent plate of the storage capacitor Cst on the substrate 10. Stacked.
  • the orthographic projection of the anode 92 on the substrate 10 can be further arranged to overlap the orthographic projection of the corresponding second transparent plate of the storage capacitor Cst on the substrate 10, so that the
  • the storage capacitor Cst can be formed as a structure including a first transparent electrode plate, the second transparent electrode plate, and the anode 92 that are stacked, which is more advantageous for adjusting the capacitance value of the storage capacitor Cst.
  • the capacitance adjustment of the storage capacitor Cst is mainly between the first transparent electrode plate and the second transparent electrode plate.
  • the capacitance value of the storage capacitor Cst can be adjusted Adjusted to 0.12pf, the storage capacitor Cst of this capacitance can be applied to a high-resolution pixel circuit architecture to ensure the normal operation of the pixel driving circuit.
  • the display substrate further includes a light-shielding layer 20 disposed on the surface of the base 10.
  • the orthographic projection of the light-shielding layer 20 on the base 10 covers The orthographic projection of all the driving transistors T1 on the substrate 10.
  • the display substrate may further include the light-shielding layer 20, and by setting the orthographic projection of the light-shielding layer 20 on the substrate 10, all the orthographic projections of the driving transistor T1 on the substrate 10 are covered. , So that the light shielding layer 20 can completely shield the driving transistor T1, and prevent external light from passing through the substrate 10 to illuminate the driving transistor T1, thereby ensuring the stable working performance of the driving transistor T1.
  • the first electrode plate 30 and the light shielding layer 20 may be arranged in the same layer.
  • the specific layout position of the first electrode plate 30 can be set according to actual needs.
  • the first electrode plate 30 and the light-shielding layer 20 are arranged in the same layer; because the light-shielding layer 20 occupies The layout space is small, so that the area on the same layer as the light-shielding layer 20 has a larger layout space. Therefore, arranging the first plate 30 and the light-shielding layer 20 in the same layer can not only achieve the desired
  • the first electrode plate 30 provides a larger layout space and is more conducive to the thinner development of the display electrode plate.
  • the orthographic projection of the light shielding layer 20 on the substrate 10 and the first electrode S1 of the driving transistor T1 on the substrate 10 There is an eighth overlap region in the orthographic projection, and the light shielding layer 20 is coupled to the first electrode S1 of the driving transistor T1 through a sixth via 41 provided in the eighth overlap region.
  • the light-shielding layer 20 By coupling the light-shielding layer 20 to the first electrode S1 of the driving transistor T1 in the above manner, the light-shielding layer 20 is prevented from being in a floating state, which affects the stability of the sub-pixel driving circuit.
  • the display substrate further includes:
  • the orthographic projection of the above overlaps the orthographic projection of the corresponding sub-pixel opening area on the substrate 10;
  • the adjacent power signal line VDD and the sensing signal line SL include two columns of the sub-pixel columns, and two data lines corresponding to the two columns of the sub-pixel columns are located in the two columns of the sub-pixels. Between the columns, the sub-pixel columns of the two columns correspond to the adjacent power signal line VDD;
  • the plurality of sub-pixels constitute a plurality of pixel units, each of the pixel units includes at least three adjacent sub-pixels located in the same sub-pixel row, and the colors of the color group graphics corresponding to the at least three sub-pixels are different ,
  • the plurality of pixel units includes a plurality of pixel unit columns, each of the pixel unit columns includes a plurality of the pixel units arranged along the extension direction of the data line, and the plurality of pixel unit columns are
  • the multiple sensing signal lines SL have a one-to-one correspondence;
  • the gate of the driving transistor is coupled to the first electrode of the data writing transistor; the second electrode D1 of the driving transistor T1 is connected to the corresponding The power signal line VDD is coupled; the second pole D3 of the sensing transistor T3 is coupled to the corresponding sensing signal line SL.
  • the power supply signal line VDD and the sensing signal line SL may be alternately arranged, and the power supply signal line SL may be placed on the adjacent power signal line.
  • Two columns of the sub-pixel columns are arranged between VDD and the sensing signal line SL, the sub-pixel columns of the two columns correspond to the adjacent power signal line VDD, and the sub-pixel columns of the two columns Each of the sub-pixels multiplexes the same corresponding power signal line VDD.
  • the plurality of sub-pixels may form a plurality of pixel units.
  • each of the pixel units includes at least three adjacent sub-pixels located in the same sub-pixel row, and color groups corresponding to the at least three sub-pixels The colors of the graphics are different;
  • the plurality of pixel units can be divided into a plurality of pixel unit columns, and each of the pixel unit columns includes a plurality of the pixel units arranged along the first direction, and the plurality of pixel units
  • the pixel unit column may correspond to the plurality of sensing signal lines SL one-to-one, and the sub-pixels included in each pixel unit in the same column of pixel unit columns multiplex the same corresponding sensing signal line SL.
  • Layout of various signal lines and sub-pixels in the display substrate in the above-mentioned manner can not only ensure the normal use of the display substrate, but also minimize the number of signal lines and increase the pixel aperture ratio; moreover, it can satisfy The large size and high resolution requirements of the display substrate.
  • the color group graphics corresponding to the at least three sub-pixels included in each pixel unit specifically include: a red color group graphic, a white color group graphic, a blue color group graphic, and a green color group Graphics.
  • each of the pixel units may include four adjacent sub-pixels located in the same sub-pixel row, and the four sub-pixels are related to the red color group graphic, the white color group graphic, The blue color group graphics and the green color group graphics have a one-to-one correspondence.
  • the color resist pattern can be arranged between the sub-pixel driving circuit and the light-emitting unit, and the white light emitted by the light-emitting unit in the sub-pixel can pass through the corresponding The color resist pattern is finally shot out of the display substrate.
  • the display substrate further includes a fourth conductive connection part G100 corresponding to the power signal line VDD in a one-to-one manner, and the fourth conductive connection part G100 is in the There is a ninth overlapping area between the orthographic projection on the substrate 10 and the corresponding orthographic projection of the power signal line VDD on the substrate 10, and the fourth conductive connecting portion G100 passes through the At least one seventh via 75 is coupled to the corresponding power signal line VDD.
  • the extension direction of the fourth conductive connection part G100 is the same as the extension direction of the power signal line VDD, and the fourth conductive connection part G100 may be arranged in a different layer from the power signal line VDD, and is perpendicular to A ninth overlap region is formed in the direction of the substrate 10, and the fourth conductive connection portion G100 is coupled to the corresponding power signal line VDD through at least one seventh via 75 provided in the ninth overlap region. It can effectively reduce the voltage drop generated on the power signal line VDD.
  • the fourth conductive connecting portion G100 and the gate G1 of the driving transistor T1 are provided in the same layer and the same material.
  • the fourth conductive connecting portion G100 and the gate G1 of the driving transistor T1 are arranged in the same layer and the same material, so that the fourth conductive connecting portion G100 and the gate G1 of the driving transistor T1 can be in the same layer. It is formed in the sub-patterning process, thereby avoiding the addition of an additional process flow dedicated to making the fourth conductive connection part G100.
  • the embodiments of the present disclosure also provide a display device, including the display substrate provided in the above-mentioned embodiments.
  • the sensing transistor T3 included in each sub-pixel in the same sub-pixel row can be shared with the data writing transistor T2 included in each sub-pixel in the next adjacent sub-pixel row
  • the same gate line reduces the layout number of signal lines and improves the pixel aperture ratio.
  • at least part of the storage capacitor Cst in the sub-pixel drive circuit is laid out in the opening area of the sub-pixel, which not only avoids the problem when the storage capacitor Cst is all laid out in the non-open area.
  • the cross-line condition ensures the stable working performance of the sub-pixel drive circuit.
  • the storage capacitor Cst since the storage capacitor Cst has a large enough layout space, it is more conducive to the improvement of the capacitance value of the storage capacitor Cst, and thus is conducive to improving the display quality of the display substrate. Uniformity.
  • at least part of the storage capacitor Cst in the sub-pixel driving circuit is arranged in the opening area of the sub-pixel, which can also effectively reduce the area of the non-aperture area of the sub-pixel, thereby improving The aperture ratio of the sub-pixel.
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned display substrate, it also has the above-mentioned beneficial effects, which will not be repeated here.
  • the display device may be any product or component with a display function, such as a TV, a monitor, a digital photo frame, a mobile phone, a tablet computer, and the like.
  • the embodiments of the present disclosure also provide a manufacturing method of a display substrate, which is used to manufacture the display substrate provided in the above-mentioned embodiments, and the manufacturing method includes:
  • a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels are fabricated on the substrate 10, and the gate lines and the data lines are arranged crosswise;
  • the plurality of sub-pixels include a plurality of sub-pixels corresponding to the plurality of data lines one-to-one Pixel columns, each of the sub-pixel columns includes a plurality of the sub-pixels arranged along the extending direction of the data line;
  • the plurality of sub-pixels includes a plurality of sub-pixels corresponding to the plurality of gate lines one-to-one Rows, each of the sub-pixel rows includes a plurality of the sub-pixels arranged along the extending direction of the gate line;
  • Each of the sub-pixels includes a sub-pixel driving circuit that includes a driving transistor T1, a data writing transistor T2, and a sensing transistor T3, and the driving transistor T1 and the data writing transistor T2 are located here
  • the sensing transistor T3 is located on the second side of the opening area of the sub-pixel, and the first side and the second side are opposite along the extending direction of the data line;
  • the second electrode D2 of the data writing transistor T2 is coupled to the corresponding data line;
  • the gate G3 of the sensing transistor T3 located in the same row of sub-pixel rows is connected to all of the adjacent sub-pixel rows in the next row.
  • the gate G2 of the data writing transistor T2 is coupled to the gate line corresponding to the sub-pixel row in the next row;
  • the sub-pixel driving circuit further includes a storage capacitor Cst coupled between the gate G1 of the driving transistor T1 and the first electrode S1 of the driving transistor T1, and the storage capacitor Cst includes first electrodes disposed oppositely.
  • Plate 30 and a second electrode plate, the orthographic projection of the first electrode plate 30 on the substrate 10 and the orthographic projection of the second electrode plate on the substrate 10 have a first overlapping area, and the second The orthographic projection of an overlapping area on the substrate 10 and the orthographic projection of the corresponding opening area of the sub-pixel on the substrate 10 at least partially overlap.
  • the driving transistor T1 and the data are laid out, the driving transistor T1 and the data
  • the writing transistor T2 is laid out on the first side of the opening area of the sub-pixel, and the sensing transistor T3 is laid out on the second side of the opening area of the sub-pixel, so that in the adjacent sub-pixel row, the previous row is
  • the sensing transistor T3 included in the pixel can be close to the data writing transistor T2 included in the subsequent row of sub-pixels, and at the same time, the gate G3 of the sensing transistor T3 included in the previous row of sub-pixels is connected to
  • the gate G2 of the data writing transistor T2 included in the next row of sub-pixels is all coupled to the gate line corresponding to the next row of sub-pixels, so that the gate line can be used for all the sub-pixels included in the previous row at the same time.
  • the gate G3 of the sensing transistor T3 and the gate G2 of the data writing transistor T2 included in the next row of sub-pixels provide scanning signals; therefore, in the display substrate manufactured by the manufacturing method provided by the embodiment of the present disclosure, Through the above layout method, the sensing transistor T3 included in each sub-pixel in the same sub-pixel row can share the same gate line with the data writing transistor T2 included in each sub-pixel in the next adjacent sub-pixel row. , Thereby reducing the layout number of signal lines and improving the pixel aperture ratio.
  • the display substrate manufactured by the manufacturing method provided by the embodiment of the present disclosure at least a part of the storage capacitor Cst in the sub-pixel driving circuit is laid out in the opening area of the sub-pixel, which not only avoids all the storage capacitors Cst being laid out in the open area.
  • the cross-line condition existing in the open area ensures the stable working performance of the sub-pixel drive circuit.
  • the storage capacitor Cst has a large enough layout space, it is more conducive to the improvement of the capacitance value of the storage capacitor Cst, which is further conducive to the improvement.
  • the display substrate shows the uniformity of image quality.
  • the storage capacitor Cst in the sub-pixel drive circuit is laid out in the opening area of the sub-pixel, which can also effectively reduce the non-aperture of the sub-pixel.
  • the area of the region thereby increasing the aperture ratio of the sub-pixel.
  • the first plate 30 of the storage capacitor includes a first transparent plate
  • the second plate of the storage capacitor includes a second transparent plate
  • the step of manufacturing the sub-pixel driving circuit specifically includes :
  • the first transparent electrode plate is fabricated on the surface of the substrate 10;
  • a light-shielding layer 20 provided in the same layer as the first transparent plate is made;
  • a buffer layer 40 is fabricated on the side of the light shielding layer 20 facing away from the substrate 10, and a sixth via 41 and a transition hole 42 are formed on the buffer layer 40.
  • the sixth via 41 exposes a part of the light-shielding layer 20, and the transition hole 42 exposes a part of the first transparent electrode plate;
  • the first electrode S1 of the driving transistor T1, the second electrode D3 of the sensing transistor T3, and the first conductive connection are made on the side of the buffer layer 40 facing away from the substrate 10.
  • Part 60 the first terminal of the first conductive connecting part 60 is coupled to the first electrode S1 of the driving transistor T1, and the second terminal of the first conductive connecting part 60 is connected to the first terminal of the sensing transistor T3.
  • the two poles D3 are coupled, the first conductive connecting portion 60 is multiplexed as the second transparent plate; the first pole S1 of the driving transistor T1 is coupled to the light shielding layer 20 through the sixth via 41 Connect
  • a gate insulating layer 50 is formed on the side of the first electrode S1 of the driving transistor T1 facing away from the substrate 10;
  • the gate of the driving transistor is fabricated on the side of the gate insulating layer 50 facing away from the substrate 10;
  • an interlayer insulating layer 70 is formed on the side of the gate of the driving transistor facing away from the substrate 10, and a first via 73 and a third via hole 73 are formed on the interlayer insulating layer 70.
  • the orthographic projection of 72 on the substrate 10 surrounds the orthographic projection of the transition hole 42 on the substrate 10, and the fourth via 71 exposes a part of the second transparent plate;
  • the second conductive connection portion 82 and the third conductive connection portion 81 are simultaneously formed through a patterning process, and the second conductive connection portion 82 is connected to the gate through the first via 73
  • the second conductive connection portion 82 is coupled to the first transparent plate through the third via 72, and the second conductive connection portion 82 is also connected to the data writing transistor in the sub-pixel drive circuit.
  • the first pole S2 of T2 is coupled; the third conductive connection portion 81 is coupled to the second transparent pole plate through the fourth via 71.
  • an indium tin oxide (ITO) material can be used to fabricate a first transparent film on the surface of the substrate 10, and then the first transparent film can be patterned to form the first transparent electrode plate; After a transparent electrode plate, a patterning process is used to continue to fabricate a light-shielding layer 20 on the surface of the substrate 10.
  • the material of the light-shielding layer 20 can be metal materials, but is not limited to secondary materials.
  • the etching liquid used in the etching process is generally oxalic acid, and in the process of forming the light shielding layer 20, the etching liquid used in the etching process is generally It is hydrogen peroxide. Since hydrogen peroxide has no effect on the indium tin oxide material, the first transparent electrode plate is generally manufactured first, and then the light-shielding layer 20 is manufactured.
  • a buffer layer 40 can be deposited on the side of the light-shielding layer 20 facing away from the substrate 10, and the buffer layer 40 covers the surface of the substrate 10 All areas.
  • the buffer layer 40 is deposited to form the buffer layer 40, and the buffer layer 40 may be subjected to a dry etching process to form the sixth via 41 and the transition hole 42.
  • the sixth via 41 can include at least part of the light shielding layer 20, so The transition hole 42 can expose at least part of the first transparent electrode.
  • an active layer film can be made on the side of the buffer layer 40 that faces away from the substrate 10, and the active layer film can be patterned to form a contact with the driving transistor T1.
  • the first active pattern corresponding to the channel region of the data writing transistor T2, the channel region of the data writing transistor T2, and the channel region of the sensing transistor T3 are formed simultaneously with the first electrode S1 and the first electrode S1 of the driving transistor T1.
  • the specific material of the active layer film can be selected according to actual needs.
  • an oxide conductor material such as indium gallium zinc oxide
  • the first active pattern can be doped so that the material of the first active pattern becomes an oxide semiconductor material; or, an oxide semiconductor material manufacturing company is selected.
  • the second active pattern may be doped to make the material of the second active pattern become oxidized Material conductor material.
  • the fabricated first conductive connection portion 60 can be multiplexed as the second transparent plate; the first electrode S1 of the driving transistor T1 can be coupled to the light shielding layer 20 through the sixth via 41 .
  • the gate insulating layer 50 can be continuously formed, and the driving device can be fabricated on the surface of the gate insulating layer 50 facing away from the substrate 10.
  • the gate G1 of the transistor T1, the gate G2 of the data writing transistor T2, and the gate G3 of the sensing transistor T3, and the gate G1 of the driving transistor T1 covers the channel corresponding to the driving transistor T1
  • the gate G2 of the data writing transistor T2 covers the channel region corresponding to the data writing transistor T2
  • the gate G3 of the sensing transistor T3 covers the channel region corresponding to the sensing transistor T3.
  • the interlayer insulating layer 70 covering the entire area of the substrate 10 can be continuously formed, and the first via hole 73, the third via hole 72 and the first via hole 72 and the second via hole can be formed on the interlayer insulating layer 70.
  • the first via hole 73 can expose at least part of the gate G1 of the driving transistor T1
  • the third via hole 72 can expose at least part of the first transparent plate
  • the The orthographic projection of the third via 72 on the substrate 10 surrounds the orthographic projection of the transition hole 42 on the substrate 10
  • the fourth via 71 can expose at least part of the second transparent plate.
  • the thickness of the interlayer insulating layer 70 is relatively thick, generally twice the thickness of the buffer layer 40. Therefore, the buffer layer 40 can be pre-etched to form the transition hole 42 and then The third via 72 is formed on the interlayer insulating layer 70, which is more conducive to the realization of the drilling process.
  • a metal film can be formed on the side of the interlayer insulating layer 70 away from the substrate 10, and then the metal film can be etched to form at the same time
  • the second conductive connection portion 82 and the third conductive connection portion 81, the second conductive connection portion 82 is coupled to the gate through the first via 73, and the second conductive connection portion 82
  • the third via 72 is coupled to the first transparent plate, and the second conductive connection portion 82 is also coupled to the first electrode S2 of the data writing transistor T2 in the sub-pixel driving circuit;
  • the three conductive connecting portion 81 is coupled to the second transparent plate through the fourth via 71.
  • the step of manufacturing the light-emitting unit specifically includes:
  • An anode 92 is fabricated on the side of the flat layer 91 facing away from the substrate 10, and the anode 92 is coupled to the third conductive connection portion 81 through the fifth via;
  • a cathode 95 is fabricated on the side of the light-emitting layer 94 facing away from the substrate 10.
  • a passivation layer 90 can be fabricated on the side of the sub-pixel driving circuit layer facing away from the substrate 10, and the passivation layer 90 may be facing away from the substrate 10.
  • a flat layer 91 is formed on one side of the substrate 10, and a fifth via hole capable of penetrating the passivation layer 90 and the flat layer 91 is formed, and the fifth via hole exposes at least of the third conductive connecting portion 81 section.
  • the anode 92 can be continuously fabricated on the surface of the flat layer 91 facing away from the substrate 10, and a part of the anode 92 is formed in the fifth via hole and can be It is coupled to the third conductive connecting portion 81 through the fifth via hole.
  • an evaporation process can be used to continue to form a pixel defining layer 93 and a light-emitting layer 94 on the side of the anode 92 that faces away from the substrate 10, and finally the light-emitting layer 94 faces away from the A cathode 95 is formed on one side of the substrate 10.
  • the following film layers are sequentially manufactured: the first transparent plate, the light shielding layer 20, the buffer layer 40, the active layer (as shown in FIG. 4), and the gate electrode.
  • the first transparent electrode plate and the light-shielding layer 20 are arranged in the same layer, and both are arranged on the surface of the substrate 10, and the first transparent electrode plate and the light-shielding layer 20 are made by two patterning processes.
  • the buffer layer 40 covers the first transparent electrode plate and the light-shielding layer 20, and a patterning process needs to be performed to perforate the buffer layer 40.
  • the active layer is used to form the active pattern of the channel region of each transistor, the first electrode and the second electrode of each transistor, and the first conductive connection portion 60, and these structures are formed by using the active layer Need a patterning process.
  • the gate metal layer is used to form the gate of each transistor, the gate line in the display substrate and the fourth conductive connection part G100, and forming these structures requires a patterning process.
  • the interlayer insulating layer 70 covers the gates of the transistors, the gate lines in the display substrate, and the fourth conductive connection portion G100, and a patterning process needs to be performed to perforate the interlayer insulating layer 70.
  • the source and drain metal layers are used to form the second conductive connection portion 82 and the third conductive connection portion 81, and the process of forming the second conductive connection portion 82 and the third conductive connection portion 81 requires one patterning Craft.
  • Each of the passivation layer 90 and the flat layer 91 requires a patterning process to achieve perforation, and the production of the anode 92 and the pixel defining layer 93 each requires a patterning process.
  • the embodiment of the present disclosure also provides a driving method of a display substrate, including a power-on period and a power-off period:
  • the power-on period includes multiple display periods, and in each display period,
  • first gate lines such as: G(N), G(N+1) and G(N+2)
  • Scanning signals, and the effective level periods of the first scanning signals input from adjacent gate lines partially overlap (for example: P1 and P2);
  • the first scan signal written by the gate line corresponding to the previous row of sub-pixels is at an effective level (high level), and the gate line corresponding to the next row of sub-pixels is written
  • the first scan signal is at a valid level, such as during the P1 period
  • the data writing transistor T2 included in each sub-pixel driving circuit in the previous row of sub-pixels is turned on, and each data writing transistor T2 is written to the data line corresponding to the coupled data line.
  • the data signal is transmitted to the gate G1 of its corresponding driving transistor T1; at the same time, the sensing transistor T3 included in each sub-pixel driving circuit in the previous row of sub-pixels is turned on, and each sensing transistor T3 is correspondingly coupled to the sensing transistor.
  • the reset signal written in the test signal line is transmitted to the first pole S1 of the driving transistor T1 to which it is correspondingly coupled;
  • the first scan signal written by the gate line corresponding to the previous row of sub-pixels is at an inactive level, and the first scan signal written by the gate line corresponding to the next row of sub-pixels
  • the driving transistor T1 and the sensing transistor T3 in the sub-pixels of the previous row are both turned on to charge the sensing signal line SL coupled to the sensing transistor T3;
  • the first scan signal written by the gate line corresponding to the previous row of sub-pixels is at an inactive level
  • the first scan signal written by the gate line corresponding to the next row of sub-pixels When it is at an inactive level, the driving transistor T1 in the sub-pixels in the previous row is turned on, the sensing transistor T3 in the sub-pixels in the previous row is turned off, and the light-emitting units in the sub-pixels in the previous row emit light.
  • the first scan signal written by the gate line corresponding to the sub-pixel in the Nth row is at an effective level
  • the first scan signal written by the gate line corresponding to the sub-pixel in the N+1th row is at an effective level
  • the data writing transistor T2 included in the Nth row of sub-pixels is turned on, so that the data signal written by each data writing transistor T2 correspondingly coupled to the data line is transmitted to the gate of its corresponding driving transistor T1 G1;
  • the reset signal written in each sensing signal line in the display substrate, each sensing transistor T3 included in each sub-pixel driving circuit in the Nth row of sub-pixels is turned on, turning each sensing transistor
  • the reset signal written in the correspondingly coupled sensing signal line SL of T3 is transmitted to the first pole S1 of the correspondingly coupled driving transistor T1 to reset the first pole S1 of the driving transistor T1.
  • the first scan signal written by the gate line corresponding to the sub-pixel in the Nth row is at an inactive level, and the first scan signal written by the gate line corresponding to the sub-pixel in the N+1th row is at an effective level, so
  • Each sensing signal line SL in the display substrate stops writing the reset signal, and each driving transistor T1 and each sensing transistor T3 in the sub-pixels in the Nth row are all turned on, which is a sense that each sensing transistor T3 is coupled to.
  • the test signal line SL is charged.
  • the first scan signal written by the gate line corresponding to the sub-pixel in the Nth row is at an inactive level
  • the first scan signal written by the gate line corresponding to the sub-pixel in the N+1th row is at an inactive level
  • the driving transistors T1 in the sub-pixels in the Nth row are all turned on, and the sensing transistors T3 in the sub-pixels in the Nth row are all turned off, so that the driving signals generated by the driving transistors T1 in the sub-pixels in the Nth row all flow to the corresponding The light-emitting unit to drive each light-emitting unit to emit light.
  • one gate line can be used to simultaneously control the on-off conditions of the sensing transistors T3 included in the sub-pixels in the same sub-pixel row, as well as the phases.
  • the on-off conditions of the data writing transistors T2 included in the sub-pixels of the next sub-pixel row ensure that the display substrate realizes the normal display function, while reducing the layout number of signal lines and increasing the pixel aperture ratio.
  • the gate lines (such as G(N), G (N+1) and G(N+2)) write the second scan signal one by one, and the second scan signal includes a first effective level period and a second effective level period arranged at intervals; adjacent to the gate In the line, the second effective level period of the second scan signal input from the previous gate line coincides with the first effective level period of the second scan signal input from the next gate line (eg: P4, P5, P6 period) ;
  • the data writing transistor T2 transmits the initialization signal written by the correspondingly coupled data line to the gate G1 of the correspondingly coupled driving transistor T1, the The sensing transistor T3 transmits the reset signal written in the correspondingly coupled sensing signal line SL to the first pole S1 of the correspondingly coupled driving transistor T1;
  • the sensing signal line SL stops writing the initialization signal
  • the data writing transistor T2 continues to write the initialization signal corresponding to the coupled data line It is transmitted to the gate G1 of the driving transistor T1 to which it is coupled to turn on the driving transistor T1 to charge the sensing signal line SL until the gate-source voltage Vgs of the driving transistor T1 is equal to the driving transistor T1
  • the threshold voltage Vth
  • the sensing transistor T3 transmits the voltage signal of the first pole S1 of the driving transistor T1 to which it is coupled to the sensing signal line SL.
  • the data line is written with an initialization signal
  • the sensing signal line SL is written with a reset signal
  • the data write transistor T2 can correspond to the coupled data line
  • the written initialization signal is transmitted to the gate G1 of its correspondingly coupled driving transistor T1
  • the sensing transistor T3 transmits the reset signal written by the correspondingly coupled sensing signal line SL to its correspondingly coupled driving transistor T1
  • the first pole S1 of the driving transistor T1 resets the first pole S1 of the driving transistor T1.
  • the sensing signal line SL stops writing the initialization signal
  • the data writing transistor T2 continues to write the initialization signal corresponding to the coupled data line It is transmitted to the gate G1 of the driving transistor T1 to which it is correspondingly coupled, turning on the driving transistor T1, charging the sensing signal line SL, and making the first electrode S1 of the driving transistor T1 in the Nth row of sub-pixels ( The potential of N) continues to rise until the gate-source voltage Vgs of the driving transistor T1 is equal to the threshold voltage Vth of the driving transistor T1;
  • the data writing transistor T2 continues to transmit the initialization signal written by the correspondingly coupled data line to the gate G1 of the correspondingly coupled driving transistor T1
  • the sensing transistor T3 transmits the voltage signal corresponding to the first pole S1 of the driving transistor T1 to the sensing signal line SL coupled thereto, so as to collect the voltage signal of the first pole S1 of the driving transistor T1.
  • the collected signal can be used to compensate the driving transistor in the display substrate, so that the display quality of the display substrate More evenly.
  • the on-off conditions of the sensing transistor T3 included in each sub-pixel in the same sub-pixel row can be simultaneously controlled through a gate line, and the adjacent sub-pixel row in the next row
  • the on-off condition of the data writing transistor T2 included in each sub-pixel of the display substrate realizes the collection of the voltage signal of the first pole S1 of each drive transistor T1 in the display substrate, while reducing the layout number of signal lines and improving The pixel aperture ratio.

Abstract

一种显示基板及其制作方法、驱动方法、显示装置。所述显示基板包括基底（10）、栅线、数据线和多个子像素，多个子像素包括与栅线一一对应的多个子像素行；在子像素包括的子像素驱动电路中，驱动晶体管（T1）和数据写入晶体管（T2）位于该子像素的开口区的第一侧，感测晶体管（T3）位于该子像素的开口区的第二侧，第一侧和第二侧沿数据线的延伸方向相对；位于同一行的感测晶体管（T3）的栅极（G3）与相邻的下一行子像素行中的数据写入晶体管（T2）的栅极（G2），均与该下一行子像素行对应的栅线耦接；存储电容（Cst）的第一极板（30）在基底（10）上的正投影与第二极板在基底（10）上的正投影存在第一交叠区域，第一交叠区域在基底（10）上的正投影与对应的子像素的开口区域在基底（10）上的正投影至少部分交叠。

Description

显示基板及其制作方法、驱动方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其制作方法、驱动方法、显示装置。
背景技术
有源矩阵有机发光二极管(英文：Active-matrix organic light-emitting diode，以下简称：AMOLED)显示器件，以其低功耗、广色域、能够实现大尺寸等优势，受到人们的广泛关注。这种显示器件存在多种布局方式，例如：可布局为底发射结构，即实现从显示器件的基底所在一侧出光，这种结构的显示器件可具体包括驱动电路膜层、发光单元和色阻单元，驱动电路膜层用于为所述发光单元提供驱动信号，使发光单元发光，发光单元发出的光穿过所述色阻单元，实现AMOLED显示器件的显示功能。
发明内容
本公开的目的在于提供一种显示基板及其制作方法、驱动方法、显示装置。
本公开的第一方面提供一种显示基板，包括基底，以及设置在所述基底上的多条栅线、多条数据线和多个子像素；
所述栅线和所述数据线交叉设置；
所述多个子像素包括与所述多条数据线一一对应的多个子像素列，每个所述子像素列中均包括沿所述数据线的延伸方向排列的多个所述子像素；
所述多个子像素包括与所述多条栅线一一对应的多个子像素行，每个所述子像素行中均包括沿所述栅线的延伸方向排列的多个所述子像素；
每个所述子像素均包括子像素驱动电路，所述子像素驱动电路包括驱动晶体管、数据写入晶体管和感测晶体管，所述驱动晶体管和所述数据写入晶体管位于该子像素的开口区的第一侧，所述感测晶体管位于该子像素的开口区的第二侧，所述第一侧和所述第二侧沿所述数据线的延伸方向相对；所述 数据写入晶体管的第二极与对应的数据线耦接；位于同一行子像素行中的所述感测晶体管的栅极，与相邻的下一行子像素行中的所述数据写入晶体管的栅极，均与该下一行子像素行对应的栅线耦接；
所述子像素驱动电路还包括耦接在所述驱动晶体管的栅极和所述驱动晶体管的第一极之间的存储电容，所述存储电容包括相对设置的第一极板和第二极板，所述第一极板在所述基底上的正投影与所述第二极板在所述基底上的正投影存在第一交叠区域，所述第一交叠区域在所述基底上的正投影与对应的所述子像素的开口区域在所述基底上的正投影至少部分交叠。
可选的，所述数据写入晶体管的第一极位于对应的栅线的第三侧，所述数据写入晶体管的第二极位于对应的栅线的第四侧，所述第三侧和所述第四侧沿所述数据线的延伸方向相对；所述数据写入晶体管的沟道部分在所述基底上的正投影，位于对应的栅线在所述基底上的正投影的内部；
所述感测晶体管的第一极位于与其相邻的下一行子像素行对应的栅线的第三侧，所述感测晶体管的第二极位于与其相邻的下一行子像素行对应的栅线的第四侧；所述感测晶体管的沟道部分在所述基底上的正投影，位于与该感测晶体管相邻的下一行子像素行对应的栅线在所述基底上的正投影的内部；
所述栅线同时复用为对应的子像素行中的各数据写入晶体管的栅极，以及该子像素行相邻的上一行子像素中的感测晶体管的栅极。
可选的，所述存储电容的第一极板包括第一透明极板，所述存储电容的第二极板包括第二透明极板；
所述子像素驱动电路还包括：
第一导电连接部，所述第一导电连接部的第一端与所述驱动晶体管的第一极耦接，所述第一导电连接部的第二端与所述感测晶体管的第二极耦接，所述第一导电连接部复用为所述第二透明极板。
可选的，所述显示基板还包括设置在所述基底的表面的缓冲层，所述存储电容的第一透明极板位于所述缓冲层和所述基底之间，所述存储电容的第二透明极板位于所述缓冲层背向所述基底的表面。
可选的，所述第一交叠区域在所述基底上的正投影，与对应的所述子像 素的开口区域在所述基底上的正投影存在第五交叠区域，所述第五交叠区域的面积在对应的所述开口区域的面积的1/4～3/4之间。
可选的，所述第一导电连接部、所述驱动晶体管的第一极和所述感测晶体管的第二极同层设置，且均采用透明氧化物导体材料。
可选的，所述子像素驱动电路还包括：
第二导电连接部，所述第二导电连接部分别与所述数据写入晶体管的第一极、所述第一透明极板和所述驱动晶体管的栅极耦接。
可选的，所述第二导电连接部在所述基底上的正投影与所述驱动晶体管的栅极在所述基底上的正投影存在第二交叠区域，所述第二导电连接部通过设置在所述第二交叠区域的第一过孔与所述驱动晶体管的栅极耦接；
所述第二导电连接部在所述基底上的正投影与所述写入晶体管的第一极在所述基底上的正投影存在第三交叠区域，所述第二导电连接部通过设置在所述第三交叠区域的第二过孔与所述数据写入晶体管的第一极耦接；
所述第二导电连接部在所述基底上的正投影与所述第一透明极板在所述基底上的正投影存在第四交叠区域，所述第二导电连接部通过设置在所述第四交叠区域的第三过孔与所述第一透明极板耦接。
可选的，所述子像素驱动电路还包括：
第三导电连接部，所述第三导电连接部在所述基底上的正投影与所述第一导电连接部在所述基底上的正投影存在第六交叠区域，所述第三导电连接部通过设置在所述第六交叠区域的第四过孔与所述第一导电连接部耦接；
所述子像素还包括设置在所述子像素驱动电路背向所述基底的一侧的发光单元，所述发光单元包括沿远离所述基底的方向依次层叠设置的阳极、发光层和阴极，所述阳极在所述基底上的正投影与所述第三导电连接部在所述基底上的正投影存在第七交叠区域，所述阳极通过设置在所述第七交叠区域的第五过孔与所述第三导电连接部耦接。
可选的，所述阳极在所述基底上的正投影，与对应的所述存储电容的第二透明极板在所述基底上的正投影交叠。
可选的，所述显示基板还包括设置在所述基底的表面的遮光层，所述遮光层在所述基底上的正投影，覆盖全部所述驱动晶体管在所述基底上的正投 影。
可选的，所述第一极板与所述遮光层同层设置。
可选的，所述遮光层在所述基底上的正投影与所述驱动晶体管的第一极在所述基底上的正投影存在第八交叠区域，所述遮光层通过设置在所述第八交叠区域的第六过孔与所述驱动晶体管的第一极耦接。
可选的，所述显示基板还包括：
与所述子像素一一对应的色组图形，所述色阻图形位于对应的所述子像素驱动电路和所述发光单元之间，所述色组图形在所述基底上的正投影与对应的子像素的开口区域在所述基底上的正投影交叠；
多条感测信号线和多条电源信号线，所述多条感测信号线和所述多条电源信号线均与所述数据线的延伸方向相同；
相邻的所述电源信号线和所述感测信号线之间包括两列所述子像素列，该两列所述子像素列对应的两条数据线位于该两列所述子像素列之间，该两列所述子像素列与该相邻的所述电源信号线对应；
所述多个子像素组成多个像素单元，每个所述像素单元包括位于同一个所述子像素行中相邻的至少三个子像素，所述至少三个子像素对应的色组图形的颜色不同，所述多个像素单元包括多个像素单元列，每个所述像素单元列中均包括沿所述数据线的延伸方向排列的多个所述像素单元，所述多个像素单元列与所述多条感测信号线一一对应；
每个所述子像素包括的子像素驱动电路中，所述驱动晶体管的栅极与所述数据写入晶体管的第一极耦接；所述驱动晶体管的第二极与对应的所述电源信号线耦接；所述感测晶体管的第二极与对应的感测信号线耦接。
可选的，所述显示基板还包括与所述电源信号线一一对应的第四导电连接部，所述第四导电连接部在所述基底上的正投影与对应的所述电源信号线在所述基底上的正投影存在第九交叠区域，所述第四导电连接部通过设置在所述第九交叠区域的至少一个第七过孔与对应的所述电源信号线耦接。
可选的，所述第四导电连接部与所述驱动晶体管的栅极同层同材料设置。
可选的，每个所述像素单元包括的所述至少三个子像素对应的色组图形具体包括：红色色组图形、白色色组图形、蓝色色组图形和绿色色组图形。
基于上述显示基板的技术方案，本公开的第二方面提供一种显示装置，包括上述显示基板。
基于上述显示基板的技术方案，本公开的第三方面提供一种显示基板的制作方法，包括：
在基底上制作多条栅线、多条数据线和多个子像素，所述栅线和所述数据线交叉设置；
所述多个子像素包括与所述多条数据线一一对应的多个子像素列，每个所述子像素列中均包括沿所述数据线的延伸方向排列的多个所述子像素；
所述多个子像素包括与所述多条栅线一一对应的多个子像素行，每个所述子像素行中均包括沿所述栅线的延伸方向排列的多个所述子像素；
每个所述子像素均包括子像素驱动电路，所述子像素驱动电路包括驱动晶体管、数据写入晶体管和感测晶体管，所述驱动晶体管和所述数据写入晶体管位于该子像素的开口区的第一侧，所述感测晶体管位于该子像素的开口区的第二侧，所述第一侧和所述第二侧沿所述数据线的延伸方向相对；所述数据写入晶体管的第二极与对应的数据线耦接；所述感测晶体管的栅极，以及与其相邻的下一行子像素行中的所述数据写入晶体管的栅极，均与该下一行子像素行对应的栅线耦接；
所述子像素驱动电路还包括耦接在所述驱动晶体管的栅极和所述驱动晶体管的第一极之间的存储电容，所述存储电容包括相对设置的第一极板和第二极板，所述第一极板在所述基底上的正投影与所述第二极板在所述基底上的正投影存在第一交叠区域，所述第一交叠区域在所述基底上的正投影与对应的所述子像素的开口区域在所述基底上的正投影至少部分交叠。
可选的，所述存储电容的第一极板包括第一透明极板，所述存储电容的第二极板包括第二透明极板；制作所述子像素驱动电路的步骤具体包括：
在所述基底的表面制作所述第一透明极板；
制作与所述第一透明极板同层设置的遮光层；
在所述遮光层背向所述基底的一侧制作缓冲层，在所述缓冲层上形成第六过孔和过渡孔，所述第六过孔暴露部分所述遮光层，所述过渡孔暴露部分所述第一透明极板；
在所述缓冲层背向所述基底的一侧制作所述驱动晶体管的第一极、感测晶体管的第二极和第一导电连接部，所述第一导电连接部的第一端与所述驱动晶体管的第一极耦接，所述第一导电连接部的第二端与所述感测晶体管的第二极耦接，所述第一导电连接部复用为所述第二透明极板；所述驱动晶体管的第一极通过所述第六过孔与所述遮光层耦接；
在所述驱动晶体管的第一极背向所述基底的一侧制作栅极绝缘层；
在所述栅极绝缘层背向所述基底的一侧制作所述驱动晶体管的栅极；
在所述驱动晶体管的栅极背向所述基底的一侧制作层间绝缘层，在所述层间绝缘层上形成第一过孔、第三过孔和第四过孔，所述第一过孔暴露部分所述驱动晶体管的栅极，所述第三过孔暴露部分所述第一透明极板，所述第三过孔在所述基底上的正投影包围所述过渡孔在所述基底上的正投影，所述第四过孔暴露部分所述第二透明极板；
通过一次构图工艺，同时形成第二导电连接部和第三导电连接部，所述第二导电连接部通过所述第一过孔与所述栅极耦接，所述第二导电连接部通过所述第三过孔与所述第一透明极板耦接，所述第二导电连接部还与子像素驱动电路中中数据写入晶体管的第一极耦接；所述第三导电连接部通过所述第四过孔与所述第二透明极板耦接。
可选的，制作所述子像素中的发光单元的步骤具体包括：
在所述子像素驱动电路背向所述基底的一侧制作钝化层；
在所述钝化层背向所述基底的一侧制作平坦层；
形成贯穿所述钝化层和所述平坦层的第五过孔，所述第五过孔暴露部分所述第三导电连接部；
在所述平坦层背向所述基底的一侧制作阳极，所述阳极通过所述第五过孔与所述第三导电连接部耦接；
在所述阳极背向所述基底的一侧制作发光层；
在所述发光层背向所述基底的一侧制作阴极。
基于上述显示基板的技术方案，本公开的第四方面提供一种显示基板的驱动方法，包括开机时段和关机时段：
所述开机时段包括多个显示周期，在每个显示周期中，
沿所述显示基板中数据线的延伸方向，向所述显示基板中的多条栅线逐条写入第一扫描信号，且相邻所述栅线输入的第一扫描信号的有效电平时段部分重叠；
在所述显示基板的相邻两行子像素中，前一行子像素对应的栅线写入的第一扫描信号处于有效电平，后一行子像素对应的栅线写入的第一扫描信号处于有效电平时，前一行子像素中各子像素驱动电路中包括的数据写入晶体管导通，将各数据写入晶体管对应耦接的数据线写入的数据信号传输至其对应耦接的驱动晶体管的栅极；同时，前一行子像素中各子像素驱动电路中包括的感测晶体管导通，将各感测晶体管对应耦接的感测信号线写入的复位信号传输至其对应耦接的驱动晶体管的第一极；
在所述显示基板的相邻两行子像素中，前一行子像素对应的栅线写入的第一扫描信号处于非有效电平，后一行子像素对应的栅线写入的第一扫描信号处于有效电平时，前一行子像素中的驱动晶体管和感测晶体管均导通，为该感测晶体管耦接的感测信号线充电；
在所述显示基板的相邻两行子像素中，前一行子像素对应的栅线写入的第一扫描信号处于非有效电平，后一行子像素对应的栅线写入的第一扫描信号处于非有效电平时，前一行子像素中的驱动晶体管导通，前一行子像素中的感测晶体管截止，前一行子像素中的发光单元发光。
可选的，在所述关机时段，
沿所述显示基板中数据线的延伸方向，向所述显示基板中的多条栅线逐条写入第二扫描信号，所述第二扫描信号包括间隔设置的第一有效电平时段和第二有效电平时段；相邻所述栅线中，前一条栅线输入的第二扫描信号的第二有效电平时段，与后一条栅线输入的第二扫描信号的第一有效电平时段重合；
在前一条栅线输入的第二扫描信号处于所述第二有效电平时段时，与所述前一条栅线对应的子像素行中包括的数据写入晶体管和感测晶体管均处于导通状态；
在该第二有效电平时段中的第一子时段：该数据写入晶体管将对应耦接的数据线写入的初始化信号传输至其对应耦接的驱动晶体管的栅极，该感测 晶体管将对应耦接的感测信号线写入的复位信号传输至其对应耦接的驱动晶体管的第一极；
在该第二有效电平时段中的第二子时段：所述感测信号线停止写入所述初始化信号，该数据写入晶体管继续将对应耦接的数据线写入的初始化信号传输至其对应耦接的驱动晶体管的栅极，使所述驱动晶体管导通，为所述感测信号线充电，直至所述驱动晶体管的栅源电压等于该驱动晶体管的阈值电压；
在该第二有效电平时段中的第三子时段：该感测晶体管将其对应耦接的驱动晶体管的第一极的电压信号传输至其耦接的感测信号线。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开提供的子像素驱动电路的结构示意图；
图2为本公开实施例提供的显示基板中一个像素单元的布局示意图；
图3为本公开实施例提供的遮光层和第一透明极板的布局示意图；
图4为本公开实施例提供的有源膜层的布局示意图；
图5为本公开实施例提供的栅金属层的布局示意图；
图6为本公开实施例提供的源漏金属层的布局示意图；
图7为本公开实施例提供的阳极的布局示意图；
图8为本公开实施例提供的在缓冲层上形成过孔的示意图；
图9为本公开实施例提供的形成有源膜层和栅极的示意图；
图10为本公开实施例提供的在层间绝缘层上形成过孔的示意图；
图11为图2中沿AA方向的截面示意图；
图12为本公开实施例提供的显示基板的整体布局示意图；
图13为本公开实施例提供的显示基板开机时段栅极的驱动时序示意图；
图14为本公开实施例提供的显示基板关机时段栅极的驱动时序示意图。
具体实施方式
为了进一步说明本公开实施例提供的显示基板及其制作方法、驱动方法、显示装置，下面结合说明书附图进行详细描述。
本公开提供的显示基板中，包括透明的基底和设置在所述基底上的多个子像素，每个子像素均包括子像素驱动电路和发光单元，子像素驱动电路包括多种结构，示例性的，如图1所示，子像素驱动电路包括驱动晶体管T1、数据写入晶体管T2、感测晶体管T3和存储电容Cst；所述驱动晶体管T1的第二极D1与电源信号线VDD耦接，所述驱动晶体管T1的栅极G1与存储电容Cst的第一极板耦接，所述驱动晶体管T1的第一极S1与所述存储电容Cst的第二极板耦接；所述数据写入晶体管T2的栅极G2与对应的栅线(如：G(n)和G(n+1))耦接，所述数据写入晶体管T2的第二极D2与数据线Data耦接，所述数据写入晶体管T2的第一极S2与所述驱动晶体管T1的栅极G1耦接；所述感测晶体管T3的栅极G3与对应的栅线耦接，所述感测晶体管T3的第一极S3与感测信号线SL耦接，所述感测晶体管T3的第二极D3与所述驱动晶体管T1的第一极S1耦接。所述发光单元OLED的阳极与所述驱动晶体管T1的第一极S1耦接，所述发光单元OLED的阴极与电源负极VSS耦接。
每个子像素均包括开口区和位于该开口区周边的非开口区，在布局所述显示基板时，所述非开口区一般布局该子像素包括的子像素驱动电路，所述开口区域一般布局发光单元和色阻单元，实际应用时，子像素驱动电路为所述发光单元提供驱动信号，使所述发光单元发光，发光单元发出的光线穿过所述色阻单元射出所述显示基板，使所述显示基板实现显示功能。
所述显示基板按照上述布局方式进行布局时，各子像素驱动电路中包括的驱动晶体管T1、感测晶体管T3、数据写入晶体管T2和存储电容Cst均位于子像素的非开口区域，导致所需要的非开口区域的布局空间较大，而由于非开口区域的实际布局空间有限，会使得存储电容Cst的极板在基底上的正投影与显示基板中的信号线(如：栅线)在基底上的正投影之间有交叠，使存储电容Cst存在跨线的情况，这种情况容易导致串扰的风险增加。
而且，为了提升所述子像素驱动电路的驱动性能，子像素驱动电路中包 括的晶体管一般选用氧化物晶体管，而氧化物晶体管所需的版图空间较大，会导致子像素的非开口区域的面积进一步增加，影响显示基板的开口率和使用寿命。
另外，由于非开口区域的布局空间有限，当晶体管占用的空间较大时，会使得存储电容Cst占用的空间较小，从而使得存储电容Cst的容值较小，对显示基板的画质均匀性产生不良影响。
基于上述问题的存在，本公开的发明人经研究发现，可通过将所述子像素驱动电路中的存储电容Cst设置为透明结构，并将其布局在子像素的开口区域，来解决上述问题。
如图2和图11所示，本公开实施例提供了一种显示基板，包括基底10，以及设置在所述基底10上的多条栅线(如：G(n)和G(n+1))、多条数据线(如：DR、DW、DB、DG)和多个子像素；所述栅线和所述数据线交叉设置；所述多个子像素包括与所述多条数据线一一对应的多个子像素列，每个所述子像素列中均包括沿所述数据线的延伸方向排列的多个所述子像素；所述多个子像素包括与所述多条栅线一一对应的多个子像素行，每个所述子像素行中均包括沿所述栅线的延伸方向排列的多个所述子像素；
每个所述子像素均包括子像素驱动电路，所述子像素驱动电路包括驱动晶体管T1、数据写入晶体管T2和感测晶体管T3，所述驱动晶体管T1和所述数据写入晶体管T2位于该子像素的开口区的第一侧，所述感测晶体管T3位于该子像素的开口区的第二侧，所述第一侧和所述第二侧沿所述数据线的延伸方向相对；所述数据写入晶体管T2的第二极D2与对应的数据线耦接；位于同一行子像素行中的所述感测晶体管T3的栅极G3，与相邻的下一行子像素行中的所述数据写入晶体管T2的栅极G2，均与该下一行子像素行对应的栅线耦接；
所述子像素驱动电路还包括耦接在所述驱动晶体管T1的栅极G1和所述驱动晶体管T1的第一极S1之间的存储电容Cst，所述存储电容Cst包括相对设置的第一极板30和第二极板，所述第一极板30在所述基底10上的正投影与所述第二极板在所述基底10上的正投影存在第一交叠区域，所述第一交叠区域在所述基底10上的正投影与对应的所述子像素的开口区域97在所述基 底10上的正投影至少部分交叠。
具体地，所述显示基板采用底发射结构，显示基板中包括的基底10可采用透明基底。
所述显示基板中包括的多个子像素可呈阵列分布，且所述多个子像素可划分为多个子像素行和多个子像素列，每个所述子像素行均包括沿所述第二方向排列的多个所述子像素，每个所述子像素列中均包括沿所述第一方向排列的多个所述子像素，示例性的，所述第一方向为Y方向，所述第二方向为X方向。
由于所述显示基板的布局空间有限，为了减少所述显示基板中信号的设置数量，可设置所述多个子像素列与所述数据线一一对应，使位于同一列子像素列中的各子像素复用同一条对应的数据线；设置所述多个子像素行与所述栅线一一对应，使位于同一行子像素行中的各子像素复用同一条对应的栅线。
更详细地说，每个所述子像素包括的子像素驱动电路中，所述数据写入晶体管T2的栅极G2与对应的所述栅线耦接，所述数据写入晶体管T2的第二极D2与对应的所述数据线耦接，所述数据写入晶体管T2的第一极S2与所述驱动晶体管T1的栅极G1耦接；所述感测晶体管T3的栅极G3与相邻的下一个所述子像素行对应的所述栅线耦接，所述感测晶体管T3的第一极S3与所述驱动晶体管T1的第一极S1耦接，所述感测晶体管T3的第二极D3与对应的感测信号线SL耦接。
所述子像素驱动电路中，存储电容Cst可包括相对设置的第一极板30和第二极板，所述第一极板30与驱动晶体管T1的栅极G1耦接，所述第二极板与所述驱动晶体管T1的栅极G1耦接；所述第一极板30的至少部分和所述第二极板的至少部分可布局在所述子像素的开口区域97中，示例性的，所述第一极板30在所述基底10上的正投影与所述第二极板在所述基底10上的正投影形成第一交叠区域，该第一交叠区域在所述基底10上的正投影与对应的所述子像素的开口区域97在所述基底10上的正投影至少部分交叠；或者，该第一交叠区域在所述基底10上的正投影位于对应的所述子像素的开口区域97在所述基底10上的正投影的内部。
根据上述显示基板的具体结构可知，本公开实施例提供的显示基板中，在布局所述驱动晶体管T1、所述数据写入晶体管T2和所述感测晶体管T3时，将所述驱动晶体管T1和所述数据写入晶体管T2布局在该子像素的开口区的第一侧，将所述感测晶体管T3布局在该子像素的开口区的第二侧，以使相邻的子像素行中，前一行子像素中包括的所述感测晶体管T3，能够与后一行子像素中包括的所述数据写入晶体管T2靠近，同时将前一行子像素中包括的所述感测晶体管T3的栅极G3，与后一行子像素中包括的所述数据写入晶体管T2的栅极G2，均与该后一行子像素行对应的栅线耦接，使得通过该栅线能够同时为前一行子像素中包括的所述感测晶体管T3的栅极G3，以及后一行子像素中包括的所述数据写入晶体管T2的栅极G2提供扫描信号；因此，本公开实施例提供的显示基板中，通过上述布局方式，使得位于同一子像素行的各子像素中包括的感测晶体管T3，能够与相邻的下一行子像素行的各子像素中包括的数据写入晶体管T2共用同一条栅线，从而减少了信号线的布局数量，提升了像素开口率。
另外，本公开实施例提供的显示基板中，将子像素驱动电路中的存储电容Cst的至少部分布局在子像素的开口区域97中，不仅避免了将存储电容Cst全部布局在非开口区域97中时存在的跨线情况，保证了子像素驱动电路稳定性的工作性能，而且，由于存储电容Cst具有足够大的布局空间，更有利于存储电容Cst容值的提升，进而有利于提升显示基板显示画质的均匀性。另外，将子像素驱动电路中的存储电容Cst的至少部分布局在子像素的开口区域97中，还能够有效缩小所述子像素的非开口区域97的面积，从而提升子像素的开口率。
更详细地说，传统设计中，8K高分辨率显示基板按照常规的设计，能够实现的平均开口率为12％左右，而本公开实施例提供的显示基板在制作为8K高分辨率显示基板时，可将平均开口率提升至30％左右，因此，相比传统设计，本公开实施例提供的显示基板能够将开口率提升150％左右，显著提高了产品的寿命，为高PPI底发射显示领域，提供了技术支持。
在一些实施例中，所述数据写入晶体管T2的第一极S2位于对应的栅线的第三侧，所述数据写入晶体管T2的第二极D2位于对应的栅线的第四侧， 所述第三侧和所述第四侧沿所述数据线的延伸方向相对；所述数据写入晶体管T2的沟道部分在所述基底10上的正投影，位于对应的栅线在所述基底10上的正投影的内部；
所述感测晶体管T3的第一极S3位于与其相邻的下一行子像素行对应的栅线的第三侧，所述感测晶体管T3的第二极D3位于与其相邻的下一行子像素行对应的栅线的第四侧；所述感测晶体管T3的沟道部分在所述基底10上的正投影，位于与该感测晶体管T3相邻的下一行子像素行对应的栅线在所述基底10上的正投影的内部；
所述栅线同时复用为对应的子像素行中的各数据写入晶体管T2的栅极，以及该子像素行相邻的上一行子像素中的感测晶体管T3的栅极。
具体地，在布局所述数据写入晶体管T2时，可将所述数据写入晶体管T2的第一极S2设置在对应的栅线的所述第三侧，将所述数据写入晶体管T2的第二极D2设置在对应的栅线的第四侧，从而使得所述数据写入晶体管T2中，连接所述数据写入晶体管T2的第一极S2和所述数据写入晶体管T2的第二极D2的T2的沟道部分，能够位于该数据写入晶体管T2对应的栅线附近，通过进一步设置所述数据写入晶体管T2的沟道部分在所述基底10上的正投影，位于对应的栅线在所述基底10上的正投影的内部，可实现将对应的栅线直接复用为该数据写入晶体管T2的栅极。
同样的，在布局所述感测晶体管T3时，可将所述感测晶体管T3的第一极S3设置在与其相邻的下一行子像素行对应的栅线的第三侧，将所述感测晶体管T3的第二极D3设置在与其相邻的下一行子像素行对应的栅线的第四侧，从而使得所述感测晶体管T3中，连接所述感测晶体管T3的第一极S3和所述感测晶体管T3的第二极D3的沟道部分，能够位于与该感测晶体管T3相邻的下一行子像素行对应的栅线附近，通过进一步设置所述感测晶体管T3的沟道部分在所述基底10上的正投影，位于该栅线在所述基底10上的正投影的内部，可实现将该栅线直接复用为该感测晶体管T3的栅极。
将所述感测晶体管T3和所述数据写入晶体管T2按照上述方式布局，使所述感测晶体管T3和所述数据写入晶体管T2均能够形成为跨越所述栅线的结构，这样就能够实现将栅线直接复用为所述感测晶体管T3的栅极和所述数 据写入晶体管T2的栅极，从而缩小了所述感测晶体管T3和所述数据写入晶体管T2占用的空间，提升了像素开口率。
在一些实施例中，所述存储电容的第一极板30包括第一透明极板，所述存储电容的第二极板包括第二透明极板；所述子像素驱动电路还包括：
第一导电连接部60，所述第一导电连接部60的第一端与所述驱动晶体管T1的第一极S1耦接，所述第一导电连接部60的第二端与所述感测晶体管T3的第二极D3耦接，所述第一导电连接部60复用为所述第二透明极板。
具体地，所述感测晶体管T3的栅极G3可与第一扫描信号输入端耦接，所述感测晶体管T3的第一极S3可与感测信号输出端耦接，所述感测晶体管T3的第二极D3可与所述驱动晶体管T1的第一极S1耦接。
在布局所述感测晶体管T3时，所述感测晶体管T3的具体布局方式多种多样，示例性的，所述驱动晶体管T1位于对应的所述开口区域的第一侧，所述感测晶体管T3位于对应的开口区域的第二侧，所述第一侧和所述第二侧相对；在这种布局方式下，可设置所述子像素驱动电路还包括所述第一导电连接部60，通过所述第一导电连接部60的第一端与所述驱动晶体管T1的第一极S1耦接，所述第一导电连接部60的第二端与所述感测晶体管T3的第二极D3耦接，实现将所述驱动晶体管T1的第一极S1与所述感测晶体管T3的第二极D3耦接。
进一步地，可设置所述第一导电连接部60在所述基底10上的正投影与对应的子像素的开口区域97在所述基底10上的正投影至少部分交叠，由于所述存储电容Cst的第二透明极板分别与所述驱动晶体管T1的第一极S1和所述感测晶体管T3的第二极D3耦接，因此，可将所述第一导电连接部60复用为所述第二透明极板。
上述实施例提供的显示基板中，将驱动晶体管T1和感测晶体管T3设置在开口区域97相对的两侧，并将能够穿过所述开口区域97，用于耦接所述驱动晶体管T1的第一极S1和所述感测晶体管T3的第二极D3的所述第一导电连接部60复用为所述存储电容Cst的第二透明极板，使得所述子像素驱动电路占用的空间被有效缩小，从而有效提升了所述显示基板的开口率。
另外，上述实施例提供的显示基板中，通过设置所述存储电容的第一极 板30包括第一透明极板，所述存储电容的第二极板包括第二透明极板，使得在将存储电容的第一极板30和第二极板设置在子像素的开口区时，第一极板30和第二极板不会对开口区的出光情况产生影响，从而使得所述显示基板在提升子像素的开口率的同时，能够保证良好的出光效果。
如图11所示，在一些实施例中，所述显示基板还包括设置在所述基底10的表面的缓冲层40，所述存储电容Cst的第一透明极板位于所述缓冲层40和所述基底10之间，所述存储电容Cst的第二透明极板位于所述缓冲层40背向所述基底10的表面。
具体地，所述第一透明极板和所述第二透明极板的具体布局位置多种多样，示例性的，当所述显示基板还包括设置在所述基底10的表面的缓冲层40时，可将所述第一透明极板设置在所述缓冲层40和所述基底10之间，并将所述第二透明极板设置在所述缓冲层40背向所述基底10的表面；由于所述缓冲层40在垂直于所述基底10的方向上厚度较薄，这种布局方式使得所述第一透明极板和所述第二透明极板之间距离较近，从而有利于增加存储电容Cst的容值，提升显示基板画质的均匀性。
在一些实施例中，可设置所述第一交叠区域在所述基底10上的正投影，与对应的所述子像素的开口区域在所述基底10上的正投影存在第五交叠区域，所述第五交叠区域的面积在对应的所述开口区域的面积的1/4～3/4之间。
具体地，在保证所述存储电容Cst的容值充裕的情况下，可适当缩小所述第一透明极板和所述第二透明极板的面积，示例性的，可设置所述第一交叠区域在所述基底10上的正投影，与对应的所述子像素的开口区域在所述基底10上的正投影存在第五交叠区域，所述第五交叠区域的面积在对应的所述开口区域的面积的1/4～3/4之间；这种设置方式，在保证了所述存储电容Cst的容值充裕的情况下，使得所述第一透明极板和所述第二透明极板只占用了开口区域的一部分，从而提升了短波长的光线穿过所述开口区域的光通量，对开口区域的透过率具有一定的保障，为高分辨率的底发射型显示基板提供基础支持。
如图2和图4所示，在一些实施例中，所述第一导电连接部60、所述驱动晶体管T1的第一极S1和所述感测晶体管T3的第二极D3同层设置，且均 采用透明氧化物导体材料。
具体地，在制作所述驱动晶体管T1和所述感测晶体管T3时，可先利用氧化物半导体材料形成有源图形，所述有源图形包括用于形成所述驱动晶体管T1的沟道区域的第一部分，以及用于形成所述感测晶体管T3的沟道区域的第二部分，对所述有源图形中除所述第一部分和所述第二部分之外的其它部分进行掺杂，以使其它部分变为透明氧化导体。
值得注意，所述其它部分包括所述驱动晶体管T1的第一极S1和第二极D1，所述感测晶体管T3的第一极S3和第二极D3，以及所述第一导电连接部60。
上述实施例提供的显示基板中，将所述第一导电连接部60、所述驱动晶体管T1的第一极S1和所述感测晶体管T3的第二极D3同层同材料设置，使得所述第一导电连接部60、所述驱动晶体管T1的第一极S1和所述感测晶体管T3的第二极D3能够在同一次构图工艺中形成，从而有效简化了所述显示基板的制作工艺流程，节约了生产成本。
如图2和图6所示，在一些实施例中，所述子像素驱动电路还包括：
第二导电连接部82，所述第二导电连接部82分别与所述数据写入晶体管T2的第一极S2、所述第一透明极板和所述驱动晶体管T1的栅极G1耦接。
具体地，所述子像素驱动电路还可以包括数据写入晶体管T2，所述数据写入晶体管T2的栅极G2与第二扫描信号输入端耦接，所述数据写入晶体管T2的第一极S2与所述驱动晶体管T1的栅极G1耦接，所述数据写入晶体管T2的第二极D2与数据信号输入端耦接。所述数据写入晶体管T2用于在数据写入阶段，在所述第二扫描信号输入端输入的第二扫描型号的控制下导通，以将所述数据信号输入端输入的数据信号写入所述驱动晶体管T1的栅极G1。
在布局所述数据写入晶体管T2时，所述数据写入晶体管T2的具体布局位置多种多样，示例性的，所述数据写入晶体管T2位于所述驱动晶体管T1远离对应的所述开口区域的一侧；在这种布局方式下，可设置所述子像素驱动电路包括所述第二导电连接部82，通过该第二导电连接部82将所述数据写入晶体管T2的第一极S2、所述第一透明极板和所述驱动晶体管T1的栅极 G1耦接在一起。
上述实施例提供的显示基板中，将所述数据写入晶体管T2设置在所述驱动晶体管T1远离对应的所述开口区域的一侧，并通过所述第二导电连接部82实现将所述数据写入晶体管T2的第一极S2、所述第一透明极板和所述驱动晶体管T1的栅极G1相耦接，使得所述子像素驱动电路占用的空间被有效缩小，从而有效提升了所述显示基板的开口率。
如图2和图10所示，在一些实施例中，所述第二导电连接部82在所述基底10上的正投影与所述驱动晶体管T1的栅极G1在所述基底10上的正投影存在第二交叠区域，所述第二导电连接部82通过设置在所述第二交叠区域的第一过孔73与所述驱动晶体管T1的栅极G1耦接；
所述第二导电连接部82在所述基底10上的正投影与所述写入晶体管的第一极在所述基底10上的正投影存在第三交叠区域，所述第二导电连接部82通过设置在所述第三交叠区域的第二过孔74与所述数据写入晶体管T2的第一极S2耦接；
所述第二导电连接部82在所述基底10上的正投影与所述第一透明极板在所述基底10上的正投影存在第四交叠区域，所述第二导电连接部82通过设置在所述第四交叠区域的第三过孔72与所述第一透明极板耦接。
具体地，所述第二导电连接部82与所述数据写入晶体管T2的第一极S2、所述第一透明极板和所述驱动晶体管T1的栅极G1的具体耦接方式，可根据所述第二导电连接部82的具体布局位置确定，示例性的，当所述第二导电连接部82与所述数据写入晶体管T2的第一极S2、所述第一透明极板和所述驱动晶体管T1的栅极G1均不同层时，可设置在垂直于所述基底10的方向上，所述第二导电连接部82能够分别与所述数据写入晶体管T2的第一极S2、所述第一透明极板和所述驱动晶体管T1的栅极G1形成交叠区域，这样可通过在相应的交叠区域形成过孔，来实现所述第二导电连接部82将所述数据写入晶体管T2的第一极S2、所述第一透明极板和所述驱动晶体管T1的栅极G1相耦接。
需要说明，由于显示基板的布局空间有限，在实际布局时，所述第二导电连接部82、所述数据写入晶体管T2的第一极S2、所述第一透明极板和所 述驱动晶体管T1的栅极G1可能无法同层设置，在这种情况下，可按照上述方式将所述数据写入晶体管T2的第一极S2、所述第一透明极板和所述驱动晶体管T1的栅极G1耦接在一起。
如图2、图10和图11所示，在一些实施例中，所述子像素驱动电路还包括：
第三导电连接部81，所述第三导电连接部81在所述基底10上的正投影与所述第一导电连接部60在所述基底10上的正投影存在第六交叠区域，所述第三导电连接部81通过设置在所述第六交叠区域的第四过孔71与所述第一导电连接部60耦接；
所述子像素还包括设置在所述子像素驱动电路背向所述基底的一侧的发光单元，所述发光单元包括沿远离所述基底10的方向依次层叠设置的阳极92、发光层94和阴极95，所述阳极92在所述基底10上的正投影与所述第三导电连接部81在所述基底10上的正投影存在第七交叠区域，所述阳极92通过设置在所述第七交叠区域的第五过孔与所述第三导电连接部81耦接。
具体地，所述发光单元可具体包括沿远离所述基底10的方向依次层叠设置的阳极92、发光层94和阴极95，所述阳极92需要与对应的驱动晶体管T1的第一极S1耦接，以接收所述驱动晶体管T1的第一极S1输出的驱动信号，所述发光层94可采用有机发光材料制作，所述发光层94能够在所述阳极92和所述阴极95之间形成的电场的作用下发出白光。
由于在实际布局时，所述发光单元的阳极92与所述驱动晶体管T1的第一极S1之间相距较远，将所述阳极92与所述驱动晶体管T1的第一极S1直接耦接在一起存在困难，因此可考虑将所述阳极92与所述第一导电连接部60(即所述第二透明极板)直接耦接，从而实现所述阳极92通过所述第一导电连接部60与所述驱动晶体管T1的栅极G1实现耦接；然而由于在垂直于所述基底10的方向上，所述阳极92与所述第一导电连接部60之间具有较厚的膜层，若直接通过一个过孔实现二者的耦接，一方面工艺难度较高，无法保证精度，另一方面，阳极92沉积在较深的过孔中，容易在孔壁处发生断裂，无法保证信赖性。
基于此，上述实施例提供的显示基板中，通过设置所述第三导电连接部 81，使所述第三导电连接部81在所述基底10上的正投影与所述第一导电连接部60在所述基底10上的正投影存在第六交叠区域，所述第三导电连接部81能够通过设置在所述第六交叠区域的第四过孔71与所述第一导电连接部60耦接；同时设置所述阳极92在所述基底10上的正投影与所述第三导电连接部81在所述基底10上的正投影能够形成第七交叠区域，所述阳极92通过设置在所述第七交叠区域的第五过孔与所述第三导电连接部81耦接，从而使得所述阳极92通过所述第五过孔、所述第三导电连接部81和所述第四过孔71与所述第一导电连接部60耦接。
上述实施例提供的所述阳极92与所述第一导电连接部60的耦接方式，不仅实现工艺简单，过孔精度较高，而且还保证了阳极92具有较高的信赖性。
如图11所示，在一些实施例中，所述阳极92在所述基底10上的正投影，与对应的所述存储电容Cst的第二透明极板在所述基底10上的正投影交叠。
具体地，可进一步设置所述阳极92在所述基底10上的正投影，与对应的所述存储电容Cst的第二透明极板在所述基底10上的正投影交叠，这样就使得所述存储电容Cst能够形成为包括层叠设置的第一透明极板、所述第二透明极板和所述阳极92的结构，从而更有利于对存储电容Cst容值的调节。
值得注意，所述存储电容Cst的容值调节主要在所述第一透明极板和所述第二透明极板之间，对于上述结构的存储电容Cst，可将所述存储电容Cst的容值调节至0.12pf，这个容值的存储电容Cst可适用于高分辨率的像素电路架构，保证像素驱动电路正常工作。
如图2和图3所示，在一些实施例中，所述显示基板还包括设置在所述基底10的表面的遮光层20，所述遮光层20在所述基底10上的正投影，覆盖全部所述驱动晶体管T1在所述基底10上的正投影。
具体地，所述显示基板中还可以包括所述遮光层20，通过设置所述遮光层20在所述基底10上的正投影，覆盖全部所述驱动晶体管T1在所述基底10上的正投影，使得所述遮光层20能够对所述驱动晶体管T1进行完全遮挡，避免外界光线穿过所述基底10照射所述驱动晶体管T1，从而保证了所述驱动晶体管T1稳定的工作性能。
在一些实施例中，可将所述第一极板30与所述遮光层20同层设置。
具体地，所述第一极板30的具体布局位置可根据实际需要设置，示例性的，将所述第一极板30与所述遮光层20同层设置；由于所述遮光层20占用的布局空间较小，使得与所述遮光层20同层的区域还具有较大的可布局空间，因此，将所述第一极板30与所述遮光层20同层设置，不仅能够实现为所述第一极板30提供较大的布局空间，而且更有利于显示极板的薄型化发展。
如图2、图8和图10所示，在一些实施例中，所述遮光层20在所述基底10上的正投影与所述驱动晶体管T1的第一极S1在所述基底10上的正投影存在第八交叠区域，所述遮光层20通过设置在所述第八交叠区域的第六过孔41与所述驱动晶体管T1的第一极S1耦接。
通过上述方式将所述遮光层20与所述驱动晶体管T1的第一极S1耦接，避免了所述遮光层20处于悬空状态，对所述子像素驱动电路工作的稳定性产生影响。
如图11和图12所示，在一些实施例中，所述显示基板还包括：
与所述子像素一一对应的色组图形96，所述色阻图形96位于对应的所述子像素驱动电路和所述发光单元之间，所述色组图形96在所述基底10上的正投影与对应的子像素的开口区域在所述基底10上的正投影交叠；
多条感测信号线SL和多条电源信号线VDD；所述多条感测信号线SL和所述多条电源信号线VDD均与所述数据线的延伸方向相同；
相邻的所述电源信号线VDD和所述感测信号线SL之间包括两列所述子像素列，该两列所述子像素列对应的两条数据线位于该两列所述子像素列之间，该两列所述子像素列与该相邻的所述电源信号线VDD对应；
所述多个子像素组成多个像素单元，每个所述像素单元包括位于同一个所述子像素行中相邻的至少三个子像素，所述至少三个子像素对应的色组图形的颜色不同，所述多个像素单元包括多个像素单元列，每个所述像素单元列中均包括沿所述数据线的延伸方向排列的多个所述像素单元，所述多个像素单元列与所述多条感测信号线SL一一对应；
每个所述子像素包括的子像素驱动电路中，所述驱动晶体管的栅极与所述数据写入晶体管的第一极耦接；所述驱动晶体管T1的第二极D1与对应的 所述电源信号线VDD耦接；所述感测晶体管T3的第二极D3与对应的感测信号线SL耦接。
具体地，在布局所述电源信号线VDD和所述感测信号线SL时，可将所述电源信号线VDD和所述感测信号线SL交替设置，并在相邻的所述电源信号线VDD和所述感测信号线SL之间布局两列所述子像素列，该两列所述子像素列与该相邻的所述电源信号线VDD对应，该两列所述子像素列中的各子像素均复用同一条对应的电源信号线VDD。
所述多个子像素可组成多个像素单元，示例性的，每个所述像素单元包括位于同一个所述子像素行中相邻的至少三个子像素，所述至少三个子像素对应的色组图形的颜色不同；所述多个像素单元可划分为多个像素单元列，每个所述像素单元列中均包括沿所述第一方向排列的多个所述像素单元，所述多个像素单元列可与所述多条感测信号线SL一一对应，位于同一列像素单元列中的各像素单元包括的子像素均复用同一条对应的感测信号线SL。
将所述显示基板中的各种信号线和子像素按照上述方式布局，不仅能够在保证所述显示基板正常使用的同时，最大限度的减少信号线的布局数量，提升像素开口率；而且，能够满足显示基板的大尺寸，高分辨率的要求。
在一些实施例中，每个所述像素单元包括的所述至少三个子像素对应的色组图形具体包括：红色色组图形、白色色组图形、蓝色色组图形和绿色色组图形。
具体地，每个所述像素单元可均包括位于同一个所述子像素行中相邻的四个子像素，所述四个子像素与所述红色色组图形、所述白色色组图形、所述蓝色色组图形和所述绿色色组图形一一对应。
当所述显示基板采用底发射设计时，所述色阻图形可设置在所述子像素驱动电路和所述发光单元之间，由所述子像素中的发光单元发出的白色光线能够穿过对应的所述色阻图形，并最终射出所述显示基板。
如图2和图5所示，在一些实施例中，所述显示基板还包括与所述电源信号线VDD一一对应的第四导电连接部G100，所述第四导电连接部G100在所述基底10上的正投影与对应的所述电源信号线VDD在所述基底10上的正投影存在第九交叠区域，所述第四导电连接部G100通过设置在所述第九 交叠区域的至少一个第七过孔75与对应的所述电源信号线VDD耦接。
具体地，所述第四导电连接部G100的延伸方向与所述电源信号线VDD的延伸方向相同，所述第四导电连接部G100可与所述电源信号线VDD异层设置，且在垂直于所述基底10的方向上形成第九交叠区域，所述第四导电连接部G100通过设置在所述第九交叠区域的至少一个第七过孔75与对应的所述电源信号线VDD耦接，能够有效降低所述电源信号线VDD上产生的压降。
如图4所示，在一些实施例中，所述第四导电连接部G100与所述驱动晶体管T1的栅极G1同层同材料设置。
具体地，将所述第四导电连接部G100与所述驱动晶体管T1的栅极G1同层同材料设置，使得所述第四导电连接部G100能够与所述驱动晶体管T1的栅极G1在同一次构图工艺中形成，从而避免了增加额外的专门用于制作所述第四导电连接部G100的工艺流程。
本公开实施例还提供了一种显示装置，包括上述实施例提供的显示基板。
上述实施例提供的显示基板中，使得位于同一子像素行的各子像素中包括的感测晶体管T3，能够与相邻的下一行子像素行的各子像素中包括的数据写入晶体管T2共用同一条栅线，从而减少了信号线的布局数量，提升了像素开口率。而且，上述实施例提供的显示基板中，将子像素驱动电路中的存储电容Cst的至少部分布局在子像素的开口区域中，不仅避免了将存储电容Cst全部布局在非开口区域中时存在的跨线情况，保证了子像素驱动电路稳定性的工作性能，而且，由于存储电容Cst具有足够大的布局空间，更有利于存储电容Cst容值的提升，进而有利于提升显示基板显示画质的均匀性。另外，上述实施例提供的显示基板中，将子像素驱动电路中的存储电容Cst的至少部分布局在子像素的开口区域中，还能够有效缩小所述子像素的非开口区域的面积，从而提升子像素的开口率。
因此，本公开实施例提供的显示装置在包括上述显示基板时，同样具有上述有益效果，此处不再赘述。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
本公开实施例还提供了一种显示基板的制作方法，用于制作上述实施例 提供的显示基板，所述制作方法包括：
在基底10上制作多条栅线、多条数据线和多个子像素，所述栅线和所述数据线交叉设置；所述多个子像素包括与所述多条数据线一一对应的多个子像素列，每个所述子像素列中均包括沿所述数据线的延伸方向排列的多个所述子像素；所述多个子像素包括与所述多条栅线一一对应的多个子像素行，每个所述子像素行中均包括沿所述栅线的延伸方向排列的多个所述子像素；
每个所述子像素均包括子像素驱动电路，所述子像素驱动电路包括驱动晶体管T1、数据写入晶体管T2和感测晶体管T3，所述驱动晶体管T1和所述数据写入晶体管T2位于该子像素的开口区的第一侧，所述感测晶体管T3位于该子像素的开口区的第二侧，所述第一侧和所述第二侧沿所述数据线的延伸方向相对；所述数据写入晶体管T2的第二极D2与对应的数据线耦接；位于同一行子像素行中的所述感测晶体管T3的栅极G3，与相邻的下一行子像素行中的所述数据写入晶体管T2的栅极G2，均与该下一行子像素行对应的栅线耦接；
所述子像素驱动电路还包括耦接在所述驱动晶体管T1的栅极G1和所述驱动晶体管T1的第一极S1之间的存储电容Cst，所述存储电容Cst包括相对设置的第一极板30和第二极板，所述第一极板30在所述基底10上的正投影与所述第二极板在所述基底10上的正投影存在第一交叠区域，所述第一交叠区域在所述基底10上的正投影与对应的所述子像素的开口区域在所述基底10上的正投影至少部分交叠。
由于采用本公开实施例提供的制作方法制作的显示基板中，在布局所述驱动晶体管T1、所述数据写入晶体管T2和所述感测晶体管T3时，将所述驱动晶体管T1和所述数据写入晶体管T2布局在该子像素的开口区的第一侧，将所述感测晶体管T3布局在该子像素的开口区的第二侧，以使相邻的子像素行中，前一行子像素中包括的所述感测晶体管T3，能够与后一行子像素中包括的所述数据写入晶体管T2靠近，同时将前一行子像素中包括的所述感测晶体管T3的栅极G3，与后一行子像素中包括的所述数据写入晶体管T2的栅极G2，均与该后一行子像素行对应的栅线耦接，使得通过该栅线能够同时为前一行子像素中包括的所述感测晶体管T3的栅极G3，以及后一行子像素中包 括的所述数据写入晶体管T2的栅极G2提供扫描信号；因此，采用本公开实施例提供的制作方法制作的显示基板中，通过上述布局方式，使得位于同一子像素行的各子像素中包括的感测晶体管T3，能够与相邻的下一行子像素行的各子像素中包括的数据写入晶体管T2共用同一条栅线，从而减少了信号线的布局数量，提升了像素开口率。
另外，采用本公开实施例提供的制作方法制作的显示基板中，将子像素驱动电路中的存储电容Cst的至少部分布局在子像素的开口区域中，不仅避免了将存储电容Cst全部布局在非开口区域中时存在的跨线情况，保证了子像素驱动电路稳定性的工作性能，而且，由于存储电容Cst具有足够大的布局空间，更有利于存储电容Cst容值的提升，进而有利于提升显示基板显示画质的均匀性。另外，采用本公开实施例提供的制作方法制作的显示基板中，将子像素驱动电路中的存储电容Cst的至少部分布局在子像素的开口区域中，还能够有效缩小所述子像素的非开口区域的面积，从而提升子像素的开口率。
在一些实施例中，所述存储电容的第一极板30包括第一透明极板，所述存储电容的第二极板包括第二透明极板；制作所述子像素驱动电路的步骤具体包括：
如图2、图3和图8所示，在所述基底10的表面制作所述第一透明极板；
如图2、图3和图8所示，制作与所述第一透明极板同层设置的遮光层20；
如图8所示，在所述遮光层20背向所述基底10的一侧制作缓冲层40，在所述缓冲层40上形成第六过孔41和过渡孔42，所述第六过孔41暴露部分所述遮光层20，所述过渡孔42暴露部分所述第一透明极板；
如图4和图9所示，在所述缓冲层40背向所述基底10的一侧制作所述驱动晶体管T1的第一极S1、感测晶体管T3的第二极D3和第一导电连接部60，所述第一导电连接部60的第一端与所述驱动晶体管T1的第一极S1耦接，所述第一导电连接部60的第二端与所述感测晶体管T3的第二极D3耦接，所述第一导电连接部60复用为所述第二透明极板；所述驱动晶体管T1的第一极S1通过所述第六过孔41与所述遮光层20耦接；
如图9所示，在所述驱动晶体管T1的第一极S1背向所述基底10的一侧 制作栅极绝缘层50；
如图9所示，在所述栅极绝缘层50背向所述基底10的一侧制作所述驱动晶体管的栅极；
如图9和10所示，在所述驱动晶体管的栅极背向所述基底10的一侧制作层间绝缘层70，在所述层间绝缘层70上形成第一过孔73、第三过孔72和第四过孔71，所述第一过孔73暴露部分所述驱动晶体管的栅极，所述第三过孔72暴露部分所述第一透明极板，所述第三过孔72在所述基底10上的正投影包围所述过渡孔42在所述基底10上的正投影，所述第四过孔71暴露部分所述第二透明极板；
如图6和图11所示，通过一次构图工艺，同时形成第二导电连接部82和第三导电连接部81，所述第二导电连接部82通过所述第一过孔73与所述栅极耦接，所述第二导电连接部82通过所述第三过孔72与所述第一透明极板耦接，所述第二导电连接部82还与子像素驱动电路中数据写入晶体管T2的第一极S2耦接；所述第三导电连接部81通过所述第四过孔71与所述第二透明极板耦接。
具体地，可利用氧化铟锡(ITO)材料在所述基底10的表面制作第一透明薄膜，然后对所述第一透明薄膜进行构图，形成所述第一透明极板；在制作所述第一透明极板后，利用构图工艺，在所述基底10的表面继续制作遮光层20，遮光层20的材料可选用金属材料，但不仅限于次。
值得注意，在形成所述第一透明电极的过程中，刻蚀工艺所采用的刻蚀液一般为草酸，而在形成所述遮光层20的过程中，刻蚀工艺所采用的刻蚀液一般为双氧水，由于双氧水对氧化铟锡材料无影响，因此，在制作时，一般先制作所述第一透明极板，后制作所述遮光层20。
在制作所述第一透明电极和所述遮光层20之后，可继续在所述遮光层20背向所述基底10的一侧沉积形成缓冲层40，所述缓冲层40覆盖所述基底10的全部区域。沉积形成缓冲层40，可对所述缓冲层40进行干刻工艺，形成所述第六过孔41和过渡孔42，所述第六过孔41能够包括所述遮光层20的至少部分，所述过渡孔42能够暴露所述第一透明电极的至少部分。
在完成所述缓冲层40的制作后，可继续在所述缓冲层40背向所述基底 10的一侧制作有源层薄膜，对该有源层薄膜进行构图，形成与所述驱动晶体管T1的沟道区域、所述数据写入晶体管T2的沟道区域以及所述感测晶体管T3的沟道区域对应的第一有源图形，同时形成与所述驱动晶体管T1的第一极S1和第二极、所述数据写入晶体管T2的第一极S2和第二极、所述感测晶体管T3的第一极S3和第二极、以及所述第一导电连接部60对应的第二有源图形。
值得注意，所述有源层薄膜的具体材料可根据实际需要选择，示例性的，选用氧化物导体材料(如：氧化铟镓锌)制作所述有源层薄膜，在构图形成所述第一有源图形和第二有源图形后，可对所述第一有源图形进行掺杂，使所述第一有源图形的材质变为氧化物半导体材料；或者，选用氧化物半导体材料制作所述有源层薄膜，在构图形成所述第一有源图形和第二有源图形后，可对所述第二有源图形进行掺杂，使所述第二有源图形的材质变为氧化物导体材料。
所制作的所述第一导电连接部60可复用为所述第二透明极板；所述驱动晶体管T1的第一极S1可通过所述第六过孔41与所述遮光层20耦接。
在完成各晶体管的沟道区、第一极和第二极的制作后，可继续形成栅极绝缘层50，并在所述栅极绝缘层50背向所述基底10的表面制作所述驱动晶体管T1的栅极G1、所述数据写入晶体管T2的栅极G2、以及所述感测晶体管T3的栅极G3，所述驱动晶体管T1的栅极G1覆盖所述驱动晶体管T1对应的沟道区域，所述数据写入晶体管T2的栅极G2覆盖所述数据写入晶体管T2对应的沟道区域，所述感测晶体管T3的栅极G3覆盖所述感测晶体管T3对应的沟道区域。
在制作各晶体管的栅极后，可继续形成覆盖所述基底10的全部区域的层间绝缘层70，并在该层间绝缘层70上形成第一过孔73、第三过孔72和第四过孔71，所述第一过孔73能够暴露所述驱动晶体管T1的栅极G1的至少部分，所述第三过孔72能够暴露所述第一透明极板的至少部分，且所述第三过孔72在所述基底10上的正投影包围所述过渡孔42在所述基底10上的正投影，所述第四过孔71能够暴露所述第二透明极板的至少部分。
值得注意，所述层间绝缘层70的厚度较厚，一般为缓冲层40厚度的二 倍，因此可先对所述缓冲层40进行预刻，形成所述过渡孔42，然后再在所述层间绝缘层70上形成所述第三过孔72，这样更利于打孔工艺的实现。
在完成所述层间绝缘层70上的过孔制作后，可继续在所述层间绝缘层70背向所述基底10一侧形成金属薄膜，然后对该金属薄膜进行刻蚀工艺，同时形成所述第二导电连接部82和所述第三导电连接部81，所述第二导电连接部82通过所述第一过孔73与所述栅极耦接，所述第二导电连接部82通过所述第三过孔72与所述第一透明极板耦接，所述第二导电连接部82还与子像素驱动电路中数据写入晶体管T2的第一极S2耦接；所述第三导电连接部81通过所述第四过孔71与所述第二透明极板耦接。
如图11所示，在一些实施例中，制作所述发光单元的步骤具体包括：
在所述子像素驱动电路背向所述基底10的一侧制作钝化层90；
在所述钝化层90背向所述基底10的一侧制作平坦层91；
形成贯穿所述钝化层90和所述平坦层91的第五过孔，所述第五过孔暴露部分所述第三导电连接部81；
在所述平坦层91背向所述基底10的一侧制作阳极92，所述阳极92通过所述第五过孔与所述第三导电连接部81耦接；
在所述阳极92背向所述基底10的一侧制作发光层94；
在所述发光层94背向所述基底10的一侧制作阴极95。
具体地，在制作完所述子像素驱动电路层后，可继续在所述子像素驱动电路层背向所述基底10的一侧制作钝化层90，在所述钝化层90背向所述基底10的一侧制作平坦层91，并形成能够贯穿所述钝化层90和所述平坦层91的第五过孔，所述第五过孔暴露所述第三导电连接部81的至少部分。
在形成所述第五过孔后，可继续在所述平坦层91背向所述基底10的表面制作所述阳极92，所述阳极92的一部分形成在所述第五过孔中，并能够通过所述第五过孔与所述第三导电连接部81耦接。
制作所述阳极92后，可采用蒸镀工艺，在所述阳极92背向所述基底10的一侧继续形成像素界定层93和发光层94，并最后在所述发光层94背向所述基底10的一侧制作阴极95。
上述实施例提供的显示基板的制作方法中，依次制作了如下膜层：所述 第一透明极板、所述遮光层20、所述缓冲层40、有源层(如图4)、栅极绝缘层50、栅金属层(如图5)、层间绝缘层70、源漏金属层(如图6)、钝化层90、平坦层91、阳极92、像素界定层93、发光层94和阴极95。
所述第一透明极板和所述遮光层20同层设置，且均设置在所述基底10的表面，制作所述第一透明极板和所述遮光层20采用了两次构图工艺。
所述缓冲层40覆盖所述第一透明极板和所述遮光层20，需要通过一次构图工艺实现在所述缓冲层40上打孔。
所述有源层用于形成各晶体管的沟道区域的有源图形，以及各晶体管的第一极和第二极，以及所述第一导电连接部60，利用所述有源层形成这些结构需要一次构图工艺。
所述栅金属层用于形成各晶体管的栅极、显示基板中的栅线和第四导电连接部G100，形成这些结构需要一次构图工艺。
所述层间绝缘层70覆盖所述各晶体管的栅极、显示基板中的栅线和第四导电连接部G100，需要通过一次构图工艺实现在所述层间绝缘层70上打孔。
所述源漏金属层用于形成所述第二导电连接部82和所述第三导电连接部81，形成所述第二导电连接部82和所述第三导电连接部81的过程需要一次构图工艺。
所述钝化层90和所述平坦层91上各需要一次构图工艺实现打孔，制作所述阳极92和所述像素界定层93各需要采用一次构图工艺。
因此，从上述制作方法的流程能够看出，上述实施例提供的制作方法中需要进行十一次构图。
本公开实施例还提供了一种显示基板的驱动方法，包括开机时段和关机时段：
如图13所示，所述开机时段包括多个显示周期，在每个显示周期中，
沿所述显示基板中数据线的延伸方向，向所述显示基板中的多条栅线(如：G(N)、G(N+1)和G(N+2))逐条写入第一扫描信号，且相邻所述栅线输入的第一扫描信号的有效电平时段部分重叠(如：P1和P2)；
在所述显示基板的相邻两行子像素中，前一行子像素对应的栅线写入的第一扫描信号处于有效电平(高电平)，后一行子像素对应的栅线写入的第一 扫描信号处于有效电平时，如P1时段，前一行子像素中各子像素驱动电路中包括的数据写入晶体管T2导通，将各数据写入晶体管T2对应耦接的数据线写入的数据信号传输至其对应耦接的驱动晶体管T1的栅极G1；同时，前一行子像素中各子像素驱动电路中包括的感测晶体管T3导通，将各感测晶体管T3对应耦接的感测信号线写入的复位信号传输至其对应耦接的驱动晶体管T1的第一极S1；
在所述显示基板的相邻两行子像素中，前一行子像素对应的栅线写入的第一扫描信号处于非有效电平，后一行子像素对应的栅线写入的第一扫描信号处于有效电平时，前一行子像素中的驱动晶体管T1和感测晶体管T3均导通，为该感测晶体管T3耦接的感测信号线SL充电；
在所述显示基板的相邻两行子像素中，前一行子像素对应的栅线写入的第一扫描信号处于非有效电平，后一行子像素对应的栅线写入的第一扫描信号处于非有效电平时，前一行子像素中的驱动晶体管T1导通，前一行子像素中的感测晶体管T3截止，前一行子像素中的发光单元发光。
具体地，在P1时段，第N行子像素对应的栅线写入的第一扫描信号处于有效电平，第N+1行子像素对应的栅线写入的第一扫描信号处于有效电平，使得第N行子像素中包括的数据写入晶体管T2导通，从而将各数据写入晶体管T2对应耦接的数据线写入的数据信号传输至其对应耦接的驱动晶体管T1的栅极G1；在该P1时段，显示基板中的各感测信号线均写入的复位信号，第N行子像素中各子像素驱动电路中包括的各感测晶体管T3导通，将各感测晶体管T3对应耦接的感测信号线SL写入的复位信号传输至其对应耦接的驱动晶体管T1的第一极S1，实现对驱动晶体管T1的第一极S1的复位。
在P2时段，第N行子像素对应的栅线写入的第一扫描信号处于非有效电平，第N+1行子像素对应的栅线写入的第一扫描信号处于有效电平，所述显示基板中的各感测信号线SL停止写入所述复位信号，第N行子像素中的各驱动晶体管T1和各感测晶体管T3均导通，为各感测晶体管T3耦接的感测信号线SL充电。
在P3时段，第N行子像素对应的栅线写入的第一扫描信号处于非有效电平，第N+1行子像素对应的栅线写入的第一扫描信号处于非有效电平，使 得第N行子像素中的各驱动晶体管T1均导通，第N行子像素中的各感测晶体管T3均截止，从而使得第N行子像素中各驱动晶体管T1产生的驱动信号均流向对应的发光单元，以驱动各发光单元发光。
在采用本公开实施例提供的驱动方法驱动上述实施例提供的显示基板时，可通过一条栅线同时控制位于同一子像素行的各子像素中包括的感测晶体管T3的通断情况，以及相邻的下一行子像素行的各子像素中包括的数据写入晶体管T2的通断情况，在保证了显示基板实现正常显示功能的同时，减少了信号线的布局数量，提升了像素开口率。
在一些实施例中，在所述关机时段，如图14所示，沿所述显示基板中数据线的延伸方向，向所述显示基板中的多条栅线(如：G(N)、G(N+1)和G(N+2))逐条写入第二扫描信号，所述第二扫描信号包括间隔设置的第一有效电平时段和第二有效电平时段；相邻所述栅线中，前一条栅线输入的第二扫描信号的第二有效电平时段，与后一条栅线输入的第二扫描信号的第一有效电平时段重合(如：P4、P5、P6时段)；
在前一条栅线输入的第二扫描信号处于所述第二有效电平时段时，与所述前一条栅线对应的子像素行中包括的数据写入晶体管T2和感测晶体管T3均处于导通状态；
在该第二有效电平时段中的第一子时段P4：该数据写入晶体管T2将对应耦接的数据线写入的初始化信号传输至其对应耦接的驱动晶体管T1的栅极G1，该感测晶体管T3将对应耦接的感测信号线SL写入的复位信号传输至其对应耦接的驱动晶体管T1的第一极S1；
在该第二有效电平时段中的第二子时段P5：所述感测信号线SL停止写入所述初始化信号，该数据写入晶体管T2继续将对应耦接的数据线写入的初始化信号传输至其对应耦接的驱动晶体管T1的栅极G1，使所述驱动晶体管T1导通，为所述感测信号线SL充电，直至所述驱动晶体管T1的栅源电压Vgs等于该驱动晶体管T1的阈值电压Vth；
在该第二有效电平时段中的第三子时段P6：该感测晶体管T3将其对应耦接的驱动晶体管T1的第一极S1的电压信号传输至其耦接的感测信号线SL。
具体地，在该第二有效电平时段中的第一子时段P4：数据线写入初始化信号，感测信号线SL写入复位信号，该数据写入晶体管T2能够将对应耦接的数据线写入的初始化信号传输至其对应耦接的驱动晶体管T1的栅极G1，该感测晶体管T3将对应耦接的感测信号线SL写入的复位信号传输至其对应耦接的驱动晶体管T1的第一极S1，对驱动晶体管T1的第一极S1进行复位，具体参见图14中第N行子像素中驱动晶体管T1的第一极S1(N)在P4处的电压信号；
在该第二有效电平时段中的第二子时段P5：所述感测信号线SL停止写入所述初始化信号，该数据写入晶体管T2继续将对应耦接的数据线写入的初始化信号传输至其对应耦接的驱动晶体管T1的栅极G1，使所述驱动晶体管T1导通，为所述感测信号线SL充电，使第N行子像素中驱动晶体管T1的第一极S1(N)的电位不断上升，直至所述驱动晶体管T1的栅源电压Vgs等于该驱动晶体管T1的阈值电压Vth；
在该第二有效电平时段中的第三子时段P6：该数据写入晶体管T2继续将对应耦接的数据线写入的初始化信号传输至其对应耦接的驱动晶体管T1的栅极G1，该感测晶体管T3将其对应耦接的驱动晶体管T1的第一极S1的电压信号传输至其耦接的感测信号线SL，实现对驱动晶体管T1的第一极S1的电压信号的采集。
在所述第三子时段P6对驱动晶体管T1的第一极S1的电压信号进行采集后，可利用该采集的信号对显示基板中的驱动晶体管进行补偿，以使所述显示基板显示的画质更加均匀。
采用上述实施例提供的驱动方法驱动显示基板时，可通过一条栅线同时控制位于同一子像素行的各子像素中包括的感测晶体管T3的通断情况，以及相邻的下一行子像素行的各子像素中包括的数据写入晶体管T2的通断情况，在实现了对显示基板中各驱动晶体管T1的第一极S1的电压信号进行采集的同时，减少了信号线的布局数量，提升了像素开口率。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施 例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (23)

  1. 一种显示基板，其特征在于，包括基底，以及设置在所述基底上的多条栅线、多条数据线和多个子像素；
    所述栅线和所述数据线交叉设置；
    所述多个子像素包括与所述多条数据线一一对应的多个子像素列，每个所述子像素列中均包括沿所述数据线的延伸方向排列的多个所述子像素；
    所述多个子像素包括与所述多条栅线一一对应的多个子像素行，每个所述子像素行中均包括沿所述栅线的延伸方向排列的多个所述子像素；
    每个所述子像素均包括子像素驱动电路，所述子像素驱动电路包括驱动晶体管、数据写入晶体管和感测晶体管，所述驱动晶体管和所述数据写入晶体管位于该子像素的开口区的第一侧，所述感测晶体管位于该子像素的开口区的第二侧，所述第一侧和所述第二侧沿所述数据线的延伸方向相对；所述数据写入晶体管的第二极与对应的数据线耦接；位于同一行子像素行中的所述感测晶体管的栅极，与相邻的下一行子像素行中的所述数据写入晶体管的栅极，均与该下一行子像素行对应的栅线耦接；
    所述子像素驱动电路还包括耦接在所述驱动晶体管的栅极和所述驱动晶体管的第一极之间的存储电容，所述存储电容包括相对设置的第一极板和第二极板，所述第一极板在所述基底上的正投影与所述第二极板在所述基底上的正投影存在第一交叠区域，所述第一交叠区域在所述基底上的正投影与对应的所述子像素的开口区域在所述基底上的正投影至少部分交叠。
  2. 根据权利要求1所述的显示基板，其特征在于，所述数据写入晶体管的第一极位于对应的栅线的第三侧，所述数据写入晶体管的第二极位于对应的栅线的第四侧，所述第三侧和所述第四侧沿所述数据线的延伸方向相对；所述数据写入晶体管的沟道部分在所述基底上的正投影，位于对应的栅线在所述基底上的正投影的内部；
    所述感测晶体管的第一极位于与其相邻的下一行子像素行对应的栅线的第三侧，所述感测晶体管的第二极位于与其相邻的下一行子像素行对应的栅线的第四侧；所述感测晶体管的沟道部分在所述基底上的正投影，位于与该 感测晶体管相邻的下一行子像素行对应的栅线在所述基底上的正投影的内部；
    所述栅线同时复用为对应的子像素行中的各数据写入晶体管的栅极，以及该子像素行相邻的上一行子像素中的感测晶体管的栅极。
  3. 根据权利要求1所述的显示基板，其特征在于，所述存储电容的第一极板包括第一透明极板，所述存储电容的第二极板包括第二透明极板；
    所述子像素驱动电路还包括：
    第一导电连接部，所述第一导电连接部的第一端与所述驱动晶体管的第一极耦接，所述第一导电连接部的第二端与所述感测晶体管的第二极耦接，所述第一导电连接部复用为所述第二透明极板。
  4. 根据权利要求3所述的显示基板，其特征在于，所述显示基板还包括设置在所述基底的表面的缓冲层，所述存储电容的第一透明极板位于所述缓冲层和所述基底之间，所述存储电容的第二透明极板位于所述缓冲层背向所述基底的表面。
  5. 根据权利要求4所述的显示基板，其特征在于，所述第一交叠区域在所述基底上的正投影，与对应的所述子像素的开口区域在所述基底上的正投影存在第五交叠区域，所述第五交叠区域的面积在对应的所述开口区域的面积的1/4～3/4之间。
  6. 根据权利要求3所述的显示基板，其特征在于，所述第一导电连接部、所述驱动晶体管的第一极和所述感测晶体管的第二极同层设置，且均采用透明氧化物导体材料。
  7. 根据权利要求3所述的显示基板，其特征在于，所述子像素驱动电路还包括：
    第二导电连接部，所述第二导电连接部分别与所述数据写入晶体管的第一极、所述第一透明极板和所述驱动晶体管的栅极耦接。
  8. 根据权利要求7所述的显示基板，其特征在于，所述第二导电连接部在所述基底上的正投影与所述驱动晶体管的栅极在所述基底上的正投影存在第二交叠区域，所述第二导电连接部通过设置在所述第二交叠区域的第一过孔与所述驱动晶体管的栅极耦接；
    所述第二导电连接部在所述基底上的正投影与所述写入晶体管的第一极在所述基底上的正投影存在第三交叠区域，所述第二导电连接部通过设置在所述第三交叠区域的第二过孔与所述数据写入晶体管的第一极耦接；
    所述第二导电连接部在所述基底上的正投影与所述第一透明极板在所述基底上的正投影存在第四交叠区域，所述第二导电连接部通过设置在所述第四交叠区域的第三过孔与所述第一透明极板耦接。
  9. 根据权利要求3所述的显示基板，其特征在于，所述子像素驱动电路还包括：
    第三导电连接部，所述第三导电连接部在所述基底上的正投影与所述第一导电连接部在所述基底上的正投影存在第六交叠区域，所述第三导电连接部通过设置在所述第六交叠区域的第四过孔与所述第一导电连接部耦接；
    所述子像素还包括设置在所述子像素驱动电路背向所述基底的一侧的发光单元，所述发光单元包括沿远离所述基底的方向依次层叠设置的阳极、发光层和阴极，所述阳极在所述基底上的正投影与所述第三导电连接部在所述基底上的正投影存在第七交叠区域，所述阳极通过设置在所述第七交叠区域的第五过孔与所述第三导电连接部耦接。
  10. 根据权利要求9所述的显示基板，其特征在于，所述阳极在所述基底上的正投影，与对应的所述存储电容的第二透明极板在所述基底上的正投影交叠。
  11. 根据权利要求1所述的显示基板，其特征在于，所述显示基板还包括设置在所述基底的表面的遮光层，所述遮光层在所述基底上的正投影，覆盖全部所述驱动晶体管在所述基底上的正投影。
  12. 根据权利要求11所述的显示基板，其特征在于，所述第一极板与所述遮光层同层设置。
  13. 根据权利要求11所述的显示基板，其特征在于，所述遮光层在所述基底上的正投影与所述驱动晶体管的第一极在所述基底上的正投影存在第八交叠区域，所述遮光层通过设置在所述第八交叠区域的第六过孔与所述驱动晶体管的第一极耦接。
  14. 根据权利要求9所述的显示基板，其特征在于，所述显示基板还包 括：
    与所述子像素一一对应的色组图形，所述色阻图形位于对应的所述子像素驱动电路和所述发光单元之间，所述色组图形在所述基底上的正投影与对应的子像素的开口区域在所述基底上的正投影交叠；
    多条感测信号线和多条电源信号线，所述多条感测信号线和所述多条电源信号线均与所述数据线的延伸方向相同；
    相邻的所述电源信号线和所述感测信号线之间包括两列所述子像素列，该两列所述子像素列对应的两条数据线位于该两列所述子像素列之间，该两列所述子像素列与该相邻的所述电源信号线对应；
    所述多个子像素组成多个像素单元，每个所述像素单元包括位于同一个所述子像素行中相邻的至少三个子像素，所述至少三个子像素对应的色组图形的颜色不同，所述多个像素单元包括多个像素单元列，每个所述像素单元列中均包括沿所述数据线的延伸方向排列的多个所述像素单元，所述多个像素单元列与所述多条感测信号线一一对应；
    每个所述子像素包括的子像素驱动电路中，所述驱动晶体管的栅极与所述数据写入晶体管的第一极耦接；所述驱动晶体管的第二极与对应的所述电源信号线耦接；所述感测晶体管的第二极与对应的感测信号线耦接。
  15. 根据权利要求14所述的显示基板，其特征在于，所述显示基板还包括与所述电源信号线一一对应的第四导电连接部，所述第四导电连接部在所述基底上的正投影与对应的所述电源信号线在所述基底上的正投影存在第九交叠区域，所述第四导电连接部通过设置在所述第九交叠区域的至少一个第七过孔与对应的所述电源信号线耦接。
  16. 根据权利要求15所述的显示基板，其特征在于，所述第四导电连接部与所述驱动晶体管的栅极同层同材料设置。
  17. 根据权利要求14所述的显示基板，其特征在于，每个所述像素单元包括的所述至少三个子像素对应的色组图形具体包括：红色色组图形、白色色组图形、蓝色色组图形和绿色色组图形。
  18. 一种显示装置，其特征在于，包括如权利要求1～17中任一项所述的显示基板。
  19. 一种显示基板的制作方法，其特征在于，包括：
    在基底上制作多条栅线、多条数据线和多个子像素，所述栅线和所述数据线交叉设置；
    所述多个子像素包括与所述多条数据线一一对应的多个子像素列，每个所述子像素列中均包括沿所述数据线的延伸方向排列的多个所述子像素；
    所述多个子像素包括与所述多条栅线一一对应的多个子像素行，每个所述子像素行中均包括沿所述栅线的延伸方向排列的多个所述子像素；
    每个所述子像素均包括子像素驱动电路，所述子像素驱动电路包括驱动晶体管、数据写入晶体管和感测晶体管，所述驱动晶体管和所述数据写入晶体管位于该子像素的开口区的第一侧，所述感测晶体管位于该子像素的开口区的第二侧，所述第一侧和所述第二侧沿所述数据线的延伸方向相对；所述数据写入晶体管的第二极与对应的数据线耦接；所述感测晶体管的栅极，以及与其相邻的下一行子像素行中的所述数据写入晶体管的栅极，均与该下一行子像素行对应的栅线耦接；
    所述子像素驱动电路还包括耦接在所述驱动晶体管的栅极和所述驱动晶体管的第一极之间的存储电容，所述存储电容包括相对设置的第一极板和第二极板，所述第一极板在所述基底上的正投影与所述第二极板在所述基底上的正投影存在第一交叠区域，所述第一交叠区域在所述基底上的正投影与对应的所述子像素的开口区域在所述基底上的正投影至少部分交叠。
  20. 根据权利要求19所述的显示基板的制作方法，其特征在于，所述存储电容的第一极板包括第一透明极板，所述存储电容的第二极板包括第二透明极板；制作所述子像素驱动电路的步骤具体包括：
    在所述基底的表面制作所述第一透明极板；
    制作与所述第一透明极板同层设置的遮光层；
    在所述遮光层背向所述基底的一侧制作缓冲层，在所述缓冲层上形成第六过孔和过渡孔，所述第六过孔暴露部分所述遮光层，所述过渡孔暴露部分所述第一透明极板；
    在所述缓冲层背向所述基底的一侧制作所述驱动晶体管的第一极、感测晶体管的第二极和第一导电连接部，所述第一导电连接部的第一端与所述驱 动晶体管的第一极耦接，所述第一导电连接部的第二端与所述感测晶体管的第二极耦接，所述第一导电连接部复用为所述第二透明极板；所述驱动晶体管的第一极通过所述第六过孔与所述遮光层耦接；
    在所述驱动晶体管的第一极背向所述基底的一侧制作栅极绝缘层；
    在所述栅极绝缘层背向所述基底的一侧制作所述驱动晶体管的栅极；
    在所述驱动晶体管的栅极背向所述基底的一侧制作层间绝缘层，在所述层间绝缘层上形成第一过孔、第三过孔和第四过孔，所述第一过孔暴露部分所述驱动晶体管的栅极，所述第三过孔暴露部分所述第一透明极板，所述第三过孔在所述基底上的正投影包围所述过渡孔在所述基底上的正投影，所述第四过孔暴露部分所述第二透明极板；
    通过一次构图工艺，同时形成第二导电连接部和第三导电连接部，所述第二导电连接部通过所述第一过孔与所述栅极耦接，所述第二导电连接部通过所述第三过孔与所述第一透明极板耦接，所述第二导电连接部还与子像素驱动电路中中数据写入晶体管的第一极耦接；所述第三导电连接部通过所述第四过孔与所述第二透明极板耦接。
  21. 根据权利要求20所述的显示基板的制作方法，其特征在于，制作所述子像素中的发光单元的步骤具体包括：
    在所述子像素驱动电路背向所述基底的一侧制作钝化层；
    在所述钝化层背向所述基底的一侧制作平坦层；
    形成贯穿所述钝化层和所述平坦层的第五过孔，所述第五过孔暴露部分所述第三导电连接部；
    在所述平坦层背向所述基底的一侧制作阳极，所述阳极通过所述第五过孔与所述第三导电连接部耦接；
    在所述阳极背向所述基底的一侧制作发光层；
    在所述发光层背向所述基底的一侧制作阴极。
  22. 一种显示基板的驱动方法，其特征在于，包括开机时段和关机时段：
    所述开机时段包括多个显示周期，在每个显示周期中，
    沿所述显示基板中数据线的延伸方向，向所述显示基板中的多条栅线逐条写入第一扫描信号，且相邻所述栅线输入的第一扫描信号的有效电平时段 部分重叠；
    在所述显示基板的相邻两行子像素中，前一行子像素对应的栅线写入的第一扫描信号处于有效电平，后一行子像素对应的栅线写入的第一扫描信号处于有效电平时，前一行子像素中各子像素驱动电路中包括的数据写入晶体管导通，将各数据写入晶体管对应耦接的数据线写入的数据信号传输至其对应耦接的驱动晶体管的栅极；同时，前一行子像素中各子像素驱动电路中包括的感测晶体管导通，将各感测晶体管对应耦接的感测信号线写入的复位信号传输至其对应耦接的驱动晶体管的第一极；
    在所述显示基板的相邻两行子像素中，前一行子像素对应的栅线写入的第一扫描信号处于非有效电平，后一行子像素对应的栅线写入的第一扫描信号处于有效电平时，前一行子像素中的驱动晶体管和感测晶体管均导通，为该感测晶体管耦接的感测信号线充电；
    在所述显示基板的相邻两行子像素中，前一行子像素对应的栅线写入的第一扫描信号处于非有效电平，后一行子像素对应的栅线写入的第一扫描信号处于非有效电平时，前一行子像素中的驱动晶体管导通，前一行子像素中的感测晶体管截止，前一行子像素中的发光单元发光。
  23. 根据权利要求22所述的显示基板的驱动方法，其特征在于，在所述关机时段，
    沿所述显示基板中数据线的延伸方向，向所述显示基板中的多条栅线逐条写入第二扫描信号，所述第二扫描信号包括间隔设置的第一有效电平时段和第二有效电平时段；相邻所述栅线中，前一条栅线输入的第二扫描信号的第二有效电平时段，与后一条栅线输入的第二扫描信号的第一有效电平时段重合；
    在前一条栅线输入的第二扫描信号处于所述第二有效电平时段时，与所述前一条栅线对应的子像素行中包括的数据写入晶体管和感测晶体管均处于导通状态；
    在该第二有效电平时段中的第一子时段：该数据写入晶体管将对应耦接的数据线写入的初始化信号传输至其对应耦接的驱动晶体管的栅极，该感测晶体管将对应耦接的感测信号线写入的复位信号传输至其对应耦接的驱动晶 体管的第一极；
    在该第二有效电平时段中的第二子时段：所述感测信号线停止写入所述初始化信号，该数据写入晶体管继续将对应耦接的数据线写入的初始化信号传输至其对应耦接的驱动晶体管的栅极，使所述驱动晶体管导通，为所述感测信号线充电，直至所述驱动晶体管的栅源电压等于该驱动晶体管的阈值电压；
    在该第二有效电平时段中的第三子时段：该感测晶体管将其对应耦接的驱动晶体管的第一极的电压信号传输至其耦接的感测信号线。
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