WO2021079510A1 - 光半導体装置 - Google Patents
光半導体装置 Download PDFInfo
- Publication number
- WO2021079510A1 WO2021079510A1 PCT/JP2019/042003 JP2019042003W WO2021079510A1 WO 2021079510 A1 WO2021079510 A1 WO 2021079510A1 JP 2019042003 W JP2019042003 W JP 2019042003W WO 2021079510 A1 WO2021079510 A1 WO 2021079510A1
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- WIPO (PCT)
- Prior art keywords
- conductive pattern
- capacitor
- semiconductor device
- optical semiconductor
- submount
- Prior art date
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- 230000003287 optical effect Effects 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 239000003990 capacitor Substances 0.000 claims abstract description 56
- 229910000679 solder Inorganic materials 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims description 13
- 230000003071 parasitic effect Effects 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 238000007689 inspection Methods 0.000 description 3
- 230000035945 sensitivity Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 244000126211 Hericium coralloides Species 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
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Definitions
- the present invention relates to an optical semiconductor device.
- the optical semiconductor device has a light emitting element, a capacitor, and a terminating resistor (see, for example, Patent Document 1).
- the bottom electrode of the capacitor is connected to the conductive pattern provided on the top surface of the submount via solder.
- the conductive pattern has been made larger than that of a capacitor. This makes it possible to visually inspect the wettability of the solder by observing the solder protruding from the capacitor from above.
- the present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain an optical semiconductor device capable of performing an appearance inspection of solder and improving signal sensitivity.
- the optical semiconductor device includes a submount, a first conductive pattern provided on the upper surface of the submount, a GND pattern provided on the lower surface side of the submount, a light emitting element, and the first.
- the first conductive pattern includes a capacitor having a lower surface electrode bonded to the conductive pattern of the above by solder, a top electrode connected to the light emitting element, and a termination resistor connected to the first conductive pattern. Is characterized in that it has a protruding portion protruding from the capacitor in a plan view, and the width of the protruding portion is narrower than the width of the capacitor.
- the conductive pattern has a protruding portion protruding from the capacitor in a plan view.
- the appearance of the solder can be inspected by observing the solder on the protruding portion from above.
- the width of the protruding portion of the conductive pattern is narrower than the width of the capacitor. As a result, the parasitic capacitance between the GND pattern on the lower surface side of the submount and the conductive pattern on the upper surface side is reduced, so that the high frequency performance can be improved.
- FIG. It is a circuit diagram of the optical semiconductor device which concerns on Embodiment 1.
- FIG. It is a perspective view which shows the optical semiconductor device which concerns on Embodiment 1.
- FIG. It is a top view which shows the optical semiconductor device which concerns on Embodiment 1.
- FIG. It is a side view which shows the optical semiconductor device which concerns on Embodiment 1.
- FIG. It is a top view which shows the optical semiconductor device which concerns on a comparative example. This is a simulation result showing the relationship between the signal attenuation and the frequency.
- It is a top view which shows the optical semiconductor device which concerns on Embodiment 2.
- It is a top view which shows the optical semiconductor device which concerns on Embodiment 3.
- It is a side view which shows the optical semiconductor device which concerns on Embodiment 4.
- FIG. It is a top view which shows the conductive pattern provided between the carrier substrate and the submount of the optical semiconductor device which concerns on Embodiment 4.
- optical semiconductor device will be described with reference to the drawings.
- the same or corresponding components may be designated by the same reference numerals and the description may be omitted.
- FIG. 1 is a circuit diagram of an optical semiconductor device according to the first embodiment.
- the optical semiconductor device 1 is a TOSA (Transmitter Optical Sub-Assembly) and has a light emitting element 2, a capacitor 3, and a terminating resistor 4.
- the anode of the light emitting element 2 is connected to the drive circuit 5, and the cathode is connected to the GND.
- the capacitor 3 and the terminating resistor 4 are connected in parallel with the light emitting element 2.
- the light emitting element 2 is, for example, an EML-LD (Electro-absorption Modulator Laser Diode).
- the light emitting element 2 emits light in response to a high-frequency modulated electric signal supplied from the drive circuit 5.
- the capacitor 3 and the terminating resistor 4 are connected in order from the drive circuit 5 toward GND, but the present invention is not limited to this, and the terminating resistor 4 and the capacitor 3 may be connected in this order from the drive circuit 5 side. ..
- FIG. 2 is a perspective view showing the optical semiconductor device according to the first embodiment.
- FIG. 3 is a plan view showing the optical semiconductor device according to the first embodiment.
- FIG. 4 is a side view showing the optical semiconductor device according to the first embodiment.
- a sub mount 7 is provided on the carrier board 6.
- the carrier substrate 6 and the submount 7 are made of, for example, AlN.
- a conductive pattern 8 is provided on the lower surface of the carrier substrate 6.
- a conductive pattern 9 which is a GND pattern is provided on the upper surface of the carrier substrate 6.
- the conductive patterns 8 and 9 on the upper and lower surfaces of the carrier substrate 6 are made conductive with each other by through-hole vias or the like.
- a conductive pattern 10 is provided on the lower surface of the submount 7.
- the conductive pattern 9 of the carrier substrate 6 and the conductive pattern 10 of the submount 7 are joined by solder or the like.
- Conductive patterns 11 to 13 separated from each other are provided on the upper surface of the submount 7.
- the surfaces of the conductive patterns 9 to 13 are gold-plated.
- the conductive pattern 11 is connected to the modulation electric signal wiring 15 by the wire 14.
- the conductive pattern 12 is connected to the GND wiring 17 by a wire 16.
- the GND wiring 17 is provided on both sides of the modulation electric signal wiring 15, and the conductive pattern 12 is provided on both sides of the conductive pattern 11, and each constitutes a coplanar waveguide.
- the modulated electric signal wiring 15 and the conductive pattern 11 transmit the modulated electric signal from the drive circuit 5.
- the light emitting element 2 is provided on the conductive pattern 12.
- the bottom electrode 18 of the light emitting element 2 and the conductive pattern 12 are joined by solder or the like.
- the upper surface electrode 19 of the light emitting element 2 and the conductive pattern 11 are connected by a wire 20.
- the capacitor 3 is provided on the conductive pattern 13.
- the bottom electrode 21 of the capacitor 3 is joined to the conductive pattern 13 by solder 22.
- the upper surface electrode 23 of the capacitor 3 is connected to the upper surface electrode 19 of the light emitting element 2 by a wire 24.
- the lower surface electrode 21 is provided on the entire lower surface of the dielectric of the capacitor 3, and the upper surface electrode 23 is provided on the entire upper surface.
- a terminating resistor 4 is provided on the upper surface of the submount 7 and is connected between the conductive pattern 12 and the conductive pattern 13.
- the resistance value of the terminating resistor 4 is set to 50 ⁇ for impedance matching. However, the resistance value of the terminating resistor 4 may be set to other than 50 ⁇ .
- the wires 14, 16, 20, and 24 are, for example, gold wires, but may be ribbon-shaped gold wires or the like.
- the planar shape of the conductive pattern 13 is rectangular, and the planar shape of the capacitor 3 is quadrangular.
- the long side of the conductive pattern 13 is 550 ⁇ m, which is longer than the side of the capacitor 3. Therefore, the conductive pattern 13 has a protruding portion 25 protruding outward from the lower region of the capacitor 3 in a plan view viewed from a direction perpendicular to the upper surface of the submount 7. As a result, the appearance of the solder 22 can be inspected by observing the solder 22 protruding from the capacitor 3 onto the protruding portion 25 from above.
- the short side of the conductive pattern 13 is 290 ⁇ m, which is shorter than the side of the capacitor 3. Therefore, at the boundary between the protruding portion 25 and the capacitor 3, the width of the protruding portion 25 of the conductive pattern 13 is narrower than the width of the capacitor 3.
- FIG. 5 is a plan view showing an optical semiconductor device according to a comparative example.
- the short side of the conductive pattern 13 is 430 ⁇ m, and the conductive pattern 13 is larger than the width of the capacitor 3. Therefore, the conductive pattern 13 protrudes from all four sides of the outer circumference of the capacitor 3. Therefore, the appearance of the solder 22 can be inspected.
- the conductive pattern 13 since the conductive pattern 13 is large, the parasitic capacitance between the conductive pattern 9 which is the GND pattern on the lower surface side of the submount 7 and the conductive pattern 13 on the upper surface side is large.
- the width of the protruding portion 25 of the conductive pattern 13 is narrower than the width of the capacitor 3.
- the parasitic capacitance between the conductive pattern 9 and the conductive pattern 13 is reduced. Therefore, the amplitude response at the frequency used by the optical semiconductor device is expanded. Therefore, noise is reduced and signal sensitivity is improved, so that high frequency performance can be improved.
- FIG. 6 is a simulation result showing the relationship between the amount of signal attenuation and the frequency.
- the resistance value of the terminating resistor 4 was set to 50 ⁇ , and the capacitance of the capacitor 3 was set to 10nF.
- the horizontal axis indicates the frequency of the signal input to the optical semiconductor device.
- the vertical axis shows the amount of attenuation when the optical semiconductor device transmits a signal. For example, if the value on the vertical axis is -3 dB, the signal strength is halved.
- there is a roll-off around 10 to 20 GHz which is the frequency used by the optical semiconductor device.
- the present embodiment it was confirmed that the attenuation amount is close to 0 dB even in the vicinity of 10 to 20 GHz, and the high frequency performance is high.
- the planar shape of the conductive pattern 13 is rectangular, and the protruding portion 25 of the conductive pattern 13 protrudes from the two opposite sides of the capacitor 3. In this way, it is preferable that the protruding portion 25 protrudes from two or more locations on the outer circumference of the capacitor 3. As a result, the appearance of the solder 22 can be inspected at two or more places, so that the inspection is highly reliable.
- the conductive pattern 13 is rectangular, and the protruding portion 25 does not protrude from the side of the capacitor 3 orthogonal to the short side direction of the conductive pattern 13. Therefore, the width of the submount 7 of each set can be reduced in the short side direction of the conductive pattern 13. Therefore, the device can be miniaturized by arranging a plurality of sets side by side in the direction of the short side of the conductive pattern 13.
- FIG. 7 is a plan view showing the optical semiconductor device according to the second embodiment.
- the planar shape of the conductive pattern 13 is L-shaped, and the protruding portion 25 of the conductive pattern 13 protrudes from two adjacent sides of the capacitor 3. Similar to the first embodiment, at the boundary between the protruding portion 25 and the capacitor 3, the width of the protruding portion 25 of the conductive pattern 13 is narrower than the width of the capacitor 3. As a result, the parasitic capacitance between the conductive pattern 9 and the conductive pattern 13 is reduced, so that the high frequency performance can be improved.
- the protruding portion 25 protrudes from two places on the outer circumference of the capacitor 3, the appearance inspection of the solder 22 can be performed at the two places. Further, by making the conductive pattern 13 L-shaped, the vertical length of the drawing of the submount 7 can be shortened. Therefore, the resonance frequency of the submount 7 can be increased to improve the high frequency characteristics. Other configurations and effects are the same as those in the first embodiment.
- FIG. 8 is a plan view showing the optical semiconductor device according to the third embodiment.
- the protruding portion 25 of the conductive pattern 13 is comb-shaped.
- the area of the protruding portion 25 is reduced, and the parasitic capacitance between the GND pattern 8 and the conductive pattern 13 is reduced, so that the high frequency performance can be improved.
- the width of each comb tooth needs to be 100 ⁇ m or more.
- Other configurations and effects are the same as those in the first embodiment.
- FIG. 9 is a side view showing the optical semiconductor device according to the fourth embodiment.
- FIG. 10 is a plan view showing a conductive pattern provided between the carrier substrate and the submount of the optical semiconductor device according to the fourth embodiment. In this plan view, the submount 7 and the configuration above it are omitted.
- the conductive patterns 9 and 10 provided between the carrier substrate 6 and the submount 7 are present below the light emitting element 2, but not below the capacitor 3. Since the conductive patterns 9 and 10 are bonded to each other below the light emitting element 2, the heat generated by the light emitting element 2 can be dissipated to the carrier substrate 6 side.
- the conductive patterns 9 and 10 which are GND patterns are provided below the capacitor 3, there is a parasitic capacitance between the conductive patterns 13 and the conductive patterns 9 and 10.
- the conductive patterns 9 and 10 are not provided below the capacitor 3, the conductive pattern interval can be widened and the parasitic capacitance can be reduced. Therefore, the high frequency performance can be improved as compared with the first embodiment.
- Other configurations and effects are the same as those in the first embodiment.
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Abstract
第1の導電パターン(13)がサブマウント(7)の上面に設けられている。GNDパターン(9)がサブマウント(7)の下面側に設けられている。コンデンサ(3)の下面電極(21)が第1の導電パターン(13)にはんだ(22)により接合されている。コンデンサ(3)の上面電極(23)が発光素子(2)に接続されている。終端抵抗(4)が第1の導電パターン(13)に接続されている。第1の導電パターン(13)は、平面視でコンデンサ(3)からはみ出したはみ出し部(25)を有する。はみ出し部(25)の横幅はコンデンサ(3)の横幅よりも狭い。
Description
本発明は、光半導体装置に関する。
光半導体装置は発光素子とコンデンサと終端抵抗を有する(例えば、特許文献1参照)。コンデンサの下面電極は、サブマウントの上面に設けられた導電パターンにはんだを介して接続されている。従来は、導電パターンをコンデンサよりも大きくしていた。これにより、コンデンサからはみ出したはんだを上方から観察して、はんだの濡れ性の外観検査を行うことができる。
しかし、導電パターンを大きくすることで、サブマウントの下面側のGNDパターンと上面側の導電パターンとの間の寄生容量が増大する。このため、光半導体装置の使用周波数での振幅応答が減少し、ノイズが増えて信号の感度が低減するという問題があった。
本発明は、上述のような課題を解決するためになされたもので、その目的ははんだの外観検査を行うことができ、信号の感度を向上することができる光半導体装置を得るものである。
本発明に係る光半導体装置は、サブマウントと、前記サブマウントの上面に設けられた第1の導電パターンと、前記サブマウントの下面側に設けられたGNDパターンと、発光素子と、前記第1の導電パターンにはんだにより接合された下面電極と、前記発光素子に接続された上面電極とを有するコンデンサと、前記第1の導電パターンに接続された終端抵抗とを備え、前記第1の導電パターンは、平面視で前記コンデンサからはみ出したはみ出し部を有し、前記はみ出し部の横幅は前記コンデンサの横幅よりも狭いことを特徴とする。
本発明では、導電パターンは、平面視でコンデンサからはみ出したはみ出し部を有する。これにより、はみ出し部の上のはんだを上方から観察して、はんだの外観検査を行うことができる。また、導電パターンのはみ出し部の横幅はコンデンサの横幅よりも狭い。これにより、サブマウントの下面側のGNDパターンと上面側の導電パターンとの間の寄生容量が低減するため、高周波性能を向上することができる。
実施の形態に係る光半導体装置について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。
実施の形態1.
図1は、実施の形態1に係る光半導体装置の回路図である。光半導体装置1はTOSA(Transmitter Optical Sub-Assembly)であり、発光素子2、コンデンサ3及び終端抵抗4を有する。発光素子2のアノードは駆動回路5に接続され、カソードはGNDに接続されている。コンデンサ3及び終端抵抗4は発光素子2と並列に接続されている。発光素子2は、例えばEML-LD(Electro-absorption Modulator Laser Diode)である。駆動回路5から供給された高周波の変調電気信号に応じて発光素子2が発光する。なお、図1ではコンデンサ3と終端抵抗4が駆動回路5からGNDに向かって順に接続されているが、これに限らず、駆動回路5側から終端抵抗4、コンデンサ3の順に接続してもよい。
図1は、実施の形態1に係る光半導体装置の回路図である。光半導体装置1はTOSA(Transmitter Optical Sub-Assembly)であり、発光素子2、コンデンサ3及び終端抵抗4を有する。発光素子2のアノードは駆動回路5に接続され、カソードはGNDに接続されている。コンデンサ3及び終端抵抗4は発光素子2と並列に接続されている。発光素子2は、例えばEML-LD(Electro-absorption Modulator Laser Diode)である。駆動回路5から供給された高周波の変調電気信号に応じて発光素子2が発光する。なお、図1ではコンデンサ3と終端抵抗4が駆動回路5からGNDに向かって順に接続されているが、これに限らず、駆動回路5側から終端抵抗4、コンデンサ3の順に接続してもよい。
図2は、実施の形態1に係る光半導体装置を示す斜視図である。図3は、実施の形態1に係る光半導体装置を示す平面図である。図4は、実施の形態1に係る光半導体装置を示す側面図である。
キャリア基板6の上にサブマウント7が設けられている。キャリア基板6とサブマウント7は例えばAlNからなる。キャリア基板6の下面に導電パターン8が設けられている。キャリア基板6の上面にGNDパターンである導電パターン9が設けられている。本実施の形態ではキャリア基板6の上下面の導電パターン8,9はスルーホールビア等により互いに導通させている。サブマウント7の下面に導電パターン10が設けられている。キャリア基板6の導電パターン9とサブマウント7の導電パターン10ははんだなどにより接合されている。サブマウント7の上面に互いに分離した導電パターン11~13が設けられている。なお、導電パターン9~13の表面には金めっきが施されている。
導電パターン11はワイヤ14により変調電気信号用配線15に接続されている。導電パターン12はワイヤ16によりGND配線17に接続されている。なお、GND配線17は変調電気信号用配線15の両サイドに設けられ、導電パターン12は導電パターン11の両サイドに設けられ、それぞれコプレーナ導波路を構成している。変調電気信号用配線15及び導電パターン11は駆動回路5からの変調電気信号を伝達する。
発光素子2が導電パターン12の上に設けられている。発光素子2の下面電極18と導電パターン12がはんだなどにより接合されている。発光素子2の上面電極19と導電パターン11がワイヤ20により接続されている。
コンデンサ3が導電パターン13の上に設けられている。コンデンサ3の下面電極21は導電パターン13にはんだ22により接合されている。コンデンサ3の上面電極23は発光素子2の上面電極19にワイヤ24により接続されている。なお、下面電極21はコンデンサ3の誘電体の下面全面に設けられ、上面電極23は上面全面に設けられている。
終端抵抗4がサブマウント7の上面に設けられ、導電パターン12と導電パターン13との間に接続されている。インピーダンス整合をとるため、終端抵抗4の抵抗値は50Ωに設定されている。ただし、終端抵抗4の抵抗値を50Ω以外に設定してもよい。なお、ワイヤ14,16,20,24は例えば金ワイヤであるが、リボン状金線などでもよい。
導電パターン13の平面形状は長方形であり、コンデンサ3の平面形状は四角形である。導電パターン13の長辺は550μmであり、コンデンサ3の辺よりも長い。このため、導電パターン13は、サブマウント7の上面に対して垂直方向から見た平面視でコンデンサ3の下方領域から外側にはみ出したはみ出し部25を有する。これにより、コンデンサ3からはみ出し部25の上に出たはんだ22を上方から観察することで、はんだ22の外観検査を行うことができる。
一方、導電パターン13の短辺は290μmであり、コンデンサ3の辺よりも短い。このため、はみ出し部25とコンデンサ3の境界において、導電パターン13のはみ出し部25の横幅はコンデンサ3の横幅よりも狭い。
続いて、本実施の形態の効果を比較例と比較して説明する。図5は、比較例に係る光半導体装置を示す平面図である。比較例では、導電パターン13の短辺が430μmであり、導電パターン13がコンデンサ3の幅よりも大きい。従って、導電パターン13がコンデンサ3の外周の四辺全てからはみ出している。このため、はんだ22の外観検査を行うことができる。しかし、比較例では導電パターン13が大きいため、サブマウント7の下面側のGNDパターンである導電パターン9と上面側の導電パターン13との間の寄生容量が大きい。
一方、本実施の形態では、導電パターン13のはみ出し部25の横幅はコンデンサ3の横幅よりも狭い。これにより、導電パターン9と導電パターン13との間の寄生容量が低減する。このため、光半導体装置の使用周波数での振幅応答が拡大する。従って、ノイズが減って信号の感度が良くなるため、高周波性能を向上することができる。
図6は、信号の減衰量と周波数の関係を示すシミュレーション結果である。シミュレーションにおいて終端抵抗4の抵抗値を50Ω、コンデンサ3の容量を10nFと設定した。横軸は光半導体装置に入力された信号の周波数を示す。縦軸は光半導体装置が信号を伝えた時に減衰する量を示す。例えば縦軸の値が-3dBであると信号の強度が半分になる。比較例では光半導体装置の使用周波数である10~20GHz付近にロールオフがある。一方、本実施の形態では、10~20GHz付近でも減衰量が0dBに近く、高周波性能が高いことが確認された。
また、導電パターン13の平面形状は長方形であり、導電パターン13のはみ出し部25はコンデンサ3の対向する2辺からはみ出している。このようにはみ出し部25は、コンデンサ3の外周の2箇所以上からはみ出していることが好ましい。これにより、2箇所以上ではんだ22の外観検査を行うことができるため、検査の信頼性が高い。
また、サブマウント7、導電パターン13、発光素子2、コンデンサ3及び終端抵抗4を含むセットが複数ある場合には装置の更なる小型化が要求される。これに対して、本実施の形態では、導電パターン13が長方形であり、はみ出し部25は導電パターン13の短辺方向に直交するコンデンサ3の辺からはみ出していない。従って、導電パターン13の短辺方向において各セットのサブマウント7の幅を小さくできる。そこで、複数のセットを導電パターン13の短辺の方向に横並びに配置することで、装置を小型化することができる。
実施の形態2.
図7は、実施の形態2に係る光半導体装置を示す平面図である。導電パターン13の平面形状はL字形であり、導電パターン13のはみ出し部25はコンデンサ3の隣接する2辺からはみ出している。実施の形態1と同様に、はみ出し部25とコンデンサ3の境界において、導電パターン13のはみ出し部25の横幅はコンデンサ3の横幅よりも狭い。これにより、導電パターン9と導電パターン13との間の寄生容量が低減するため、高周波性能を向上することができる。
図7は、実施の形態2に係る光半導体装置を示す平面図である。導電パターン13の平面形状はL字形であり、導電パターン13のはみ出し部25はコンデンサ3の隣接する2辺からはみ出している。実施の形態1と同様に、はみ出し部25とコンデンサ3の境界において、導電パターン13のはみ出し部25の横幅はコンデンサ3の横幅よりも狭い。これにより、導電パターン9と導電パターン13との間の寄生容量が低減するため、高周波性能を向上することができる。
また、はみ出し部25がコンデンサ3の外周の2箇所からはみ出しているため、2箇所ではんだ22の外観検査を行うことができる。また、導電パターン13をL字形にすることで、サブマウント7の図面の上下方向の長さを短くすることができる。このため、サブマウント7の共振周波数を増加させ、高周波特性を向上させることができる。その他の構成及び効果は実施の形態1と同様である。
実施の形態3.
図8は、実施の形態3に係る光半導体装置を示す平面図である。導電パターン13のはみ出し部25は櫛歯状である。これにより、はみ出し部25の面積が小さくなり、GNDパターン8と導電パターン13との間の寄生容量が低減するため、高周波性能を向上することができる。ただし、はんだ22の外観検査を行うために、各櫛歯の横幅を100μm以上にする必要がある。その他の構成及び効果は実施の形態1と同様である。
図8は、実施の形態3に係る光半導体装置を示す平面図である。導電パターン13のはみ出し部25は櫛歯状である。これにより、はみ出し部25の面積が小さくなり、GNDパターン8と導電パターン13との間の寄生容量が低減するため、高周波性能を向上することができる。ただし、はんだ22の外観検査を行うために、各櫛歯の横幅を100μm以上にする必要がある。その他の構成及び効果は実施の形態1と同様である。
実施の形態4.
図9は、実施の形態4に係る光半導体装置を示す側面図である。図10は、実施の形態4に係る光半導体装置のキャリア基板とサブマウントの間に設けられた導電パターンを示す平面図である。この平面図においてサブマウント7及びその上の構成は省略している。
図9は、実施の形態4に係る光半導体装置を示す側面図である。図10は、実施の形態4に係る光半導体装置のキャリア基板とサブマウントの間に設けられた導電パターンを示す平面図である。この平面図においてサブマウント7及びその上の構成は省略している。
キャリア基板6とサブマウント7の間に設けられた導電パターン9,10は、発光素子2の下方には存在するが、コンデンサ3の下方には存在しない。発光素子2の下方で導電パターン9,10が互いに接合されているため、発光素子2で発生した熱をキャリア基板6側に放熱することができる。
実施の形態1ではコンデンサ3の下方にGNDパターンである導電パターン9,10が有るため、導電パターン13と導電パターン9,10との間の寄生容量が存在する。これに対して、本実施の形態ではコンデンサ3の下方に導電パターン9,10が無いため、導電パターン間隔を広げることができ、寄生容量を低減することができる。従って、実施の形態1よりも高周波性能を向上することができる。その他の構成及び効果は実施の形態1と同様である。
1 光半導体装置、2 発光素子、3 コンデンサ、4 終端抵抗、6 キャリア基板、7 サブマウント、8 導電パターン(GNDパターン)、9 導電パターン(GNDパターン、第2の導電パターン)、10 導電パターン(第3の導電パターン)、13 導電パターン(第1の導電パターン)、22 はんだ、21 下面電極、23 上面電極、25 はみ出し部
Claims (7)
- サブマウントと、
前記サブマウントの上面に設けられた第1の導電パターンと、
前記サブマウントの下面側に設けられたGNDパターンと、
発光素子と、
前記第1の導電パターンにはんだにより接合された下面電極と、前記発光素子に接続された上面電極とを有するコンデンサと、
前記第1の導電パターンに接続された終端抵抗とを備え、
前記第1の導電パターンは、平面視で前記コンデンサからはみ出したはみ出し部を有し、
前記はみ出し部の横幅は前記コンデンサの横幅よりも狭いことを特徴とする光半導体装置。 - 前記はみ出し部は、前記コンデンサの外周の2箇所以上からはみ出していることを特徴とする請求項1に記載の光半導体装置。
- 前記第1の導電パターンの平面形状は長方形であり、
前記コンデンサの平面形状は四角形であり、
前記第1の導電パターンの長辺は前記コンデンサの辺よりも長く、
前記第1の導電パターンの短辺は前記コンデンサの辺よりも短く、
前記はみ出し部は前記コンデンサの対向する2辺からはみ出していることを特徴とする請求項2に記載の光半導体装置。 - 前記サブマウント、前記第1の導電パターン、前記発光素子、前記コンデンサ及び前記終端抵抗を含むセットが複数あり、前記複数のセットが前記第1の導電パターンの前記短辺の方向に横並びに配置されていることを特徴とする請求項3に記載の光半導体装置。
- 前記第1の導電パターンの平面形状はL字形であり、
前記コンデンサの平面形状は四角形であり、
前記はみ出し部は前記コンデンサの隣接する2辺からはみ出していることを特徴とする請求項2に記載の光半導体装置。 - 前記はみ出し部は櫛歯状であることを特徴とする請求項1又は2に記載の光半導体装置。
- キャリア基板と、
前記キャリア基板の上面に設けられた第2の導電パターンと、
前記サブマウントの下面に設けられた第3の導電パターンとを更に備え、
前記サブマウントは前記キャリア基板の上に設けられ、
前記GNDパターンは前記キャリア基板の下面に設けられ、
前記第2の導電パターンと前記第3の導電パターンは、互いに接合され、前記発光素子の下方には存在するが、前記コンデンサの下方には存在しないことを特徴とする請求項1~6の何れか1項に記載の光半導体装置。
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