WO2021077491A1 - 一种显示面板的走线结构、显示面板走线方法及显示面板 - Google Patents

一种显示面板的走线结构、显示面板走线方法及显示面板 Download PDF

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Publication number
WO2021077491A1
WO2021077491A1 PCT/CN2019/118205 CN2019118205W WO2021077491A1 WO 2021077491 A1 WO2021077491 A1 WO 2021077491A1 CN 2019118205 W CN2019118205 W CN 2019118205W WO 2021077491 A1 WO2021077491 A1 WO 2021077491A1
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Prior art keywords
scan
display panel
scan line
line
metal layer
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PCT/CN2019/118205
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English (en)
French (fr)
Inventor
徐洪远
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Tcl华星光电技术有限公司
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Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US16/622,914 priority Critical patent/US20220244593A1/en
Publication of WO2021077491A1 publication Critical patent/WO2021077491A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present application relates to the field of panel manufacturing technology, and in particular to a wiring structure of a display panel, a wiring method of a display panel, and a display panel.
  • LCD(Liquid Crystal display (liquid crystal display) is a widely used flat panel display, which mainly realizes picture display by modulating the intensity of the light field of the backlight source through liquid crystal switches.
  • Large size, high resolution, and high refresh rate are the current development trends of high-end TFT-LCD (Thin Film Transistor-Liquid Crystal Display) products.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the impact of the increase in the panel size is the extension of the metal traces, which causes the capacitance delay to be more serious.
  • the purpose of the embodiments of the present application is to provide a wiring structure of a display panel, a wiring method of a display panel, and a display panel, which can solve the technical problem of capacitance delay in the prior art.
  • the embodiment of the present application provides a wiring structure for a display panel, including:
  • the first metal layer includes a number of first scan lines and second scan lines.
  • the first scan lines are arranged horizontally, the second scan lines are arranged vertically, the second scan lines have a number of intervals, and the first scan lines are arranged vertically.
  • the scan line is set within the interval;
  • the second metal layer is disposed on the first metal layer and corresponds to the first metal layer, the second metal layer includes a plurality of first data lines and second data lines, and the first data lines are vertical Setting, the second data line is arranged laterally, the second data line has a plurality of gaps, and the first data line is arranged in the gap;
  • the second scan line is connected in series with the first data line, and the second data line is connected in series with the first scan line.
  • the first data line is located at both ends of the space and extends toward the second scan line with a first protrusion, and the first protrusion is connected to the second scan line.
  • the second data line is located at both ends of the gap and extends toward the first scan line with second protrusions, and the second protrusions are connected to the first scan line.
  • an insulating layer is provided on the first metal layer, a via hole is provided on the insulating layer, and the first bump passes through the via hole and is connected to the second scan line.
  • the second protrusion passes through the via hole and is connected to the first scan line.
  • a thin film transistor is further included, and the thin film transistor is connected to the first scan line and the first data line.
  • the shape of the via hole is adapted to the shape of the first protrusion and the second protrusion.
  • the first data line and the second data line and the first scan line and the second scan line are copper wires.
  • the embodiment of the present application also provides a wiring method for a display panel, including:
  • a number of second data lines are vertically arranged, the second data lines have a number of gaps, the first data lines are arranged in the gaps to form a second metal layer, and the second metal layer is arranged on the first On the metal layer and corresponding to the first metal layer;
  • the second scan line is connected in series with the first data line, and the second data line is connected in series with the first scan line.
  • the first bumps of the first data line at both ends of the gap are connected to the second scan line, and the second data lines are connected to the second bumps at both ends of the gap. It is connected with the first scan line.
  • the first bump is connected to the second scan line through the via hole of the insulating layer, and the second bump is connected to the first scan line through the via hole of the insulating layer.
  • the thin film transistor is connected to the first scan line and the first data line.
  • the shape of the via hole is adapted to the shape of the first protrusion and the second protrusion.
  • the first data line and the second data line and the first scan line and the second scan line are copper wires.
  • An embodiment of the present application further provides a display panel, which includes a wiring structure, and the wiring structure includes:
  • the first metal layer includes a number of first scan lines and second scan lines.
  • the first scan lines are arranged horizontally, the second scan lines are arranged vertically, the second scan lines have a number of intervals, and the first scan lines are arranged vertically.
  • the scan line is set within the interval;
  • the second metal layer is disposed on the first metal layer and corresponds to the first metal layer, the second metal layer includes a plurality of first data lines and second data lines, and the first data lines are vertical Setting, the second data line is arranged laterally, the second data line has a plurality of gaps, and the first data line is arranged in the gap;
  • the second scan line is connected in series with the first data line, and the second data line is connected in series with the first scan line.
  • the first data line is located at both ends of the space and extends toward the second scan line with a first protrusion, and the first protrusion is connected to the second scan line.
  • the second data line is located at both ends of the gap and extends toward the first scan line with second protrusions, and the second protrusions are connected to the first scan line.
  • an insulating layer is provided on the first metal layer, a via hole is provided on the insulating layer, and the first bump passes through the via hole and is connected to the second scan line.
  • the second protrusion passes through the via hole and is connected to the first scan line.
  • a thin film transistor is further included, and the thin film transistor is connected to the first scan line and the first data line.
  • the shape of the via hole is adapted to the shape of the first protrusion and the second protrusion.
  • the first data line and the second data line and the first scan line and the second scan line are copper wires.
  • the wiring structure of the display panel includes a first metal layer and a second metal layer.
  • the first metal layer includes a plurality of first scan lines and second scan lines.
  • the two scan lines are arranged vertically, the second scan line has a number of intervals, and the first scan line is arranged in the interval.
  • the second metal layer is arranged on the first metal layer and corresponds to the first metal layer, the second metal layer includes a plurality of first data lines and second data lines, and the first data lines are vertically arranged ,
  • the second data line is arranged laterally, the second data line has a plurality of gaps, and the first data line is arranged in the gaps.
  • the second scan line is connected in series with the first data line, and the second data line is connected in series with the first scan line. Since the present application adopts a double-layer wiring structure, the copper thickness is reduced, the production cost is reduced, and the capacitance delay can be reduced to meet the needs of large-size and high-specification panels.
  • FIG. 1 is a schematic structural diagram of a wiring structure of a display panel provided by an embodiment of the application.
  • FIG. 2 is a schematic diagram of the structure of the first metal layer in the wiring structure of the display panel provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of the structure of the second metal layer in the wiring structure of the display panel provided by an embodiment of the application.
  • FIG. 4 is a schematic structural diagram of a related display panel wiring structure provided by an embodiment of the application.
  • FIG. 5 is another schematic structural diagram of the wiring structure of the display panel provided by the embodiment of the application.
  • FIG. 6 is another schematic structural diagram of the wiring structure of the display panel provided by the embodiment of the application.
  • FIG. 7 is a schematic flowchart of a wiring method for a display panel provided by an embodiment of the application.
  • the embodiment of the present application provides a display panel wiring structure 100, a display panel wiring and a display panel.
  • the wiring structure 100 of the display panel will be described in detail below.
  • FIG. 1 is a schematic structural diagram of a display panel wiring structure 100 provided by an embodiment of the application.
  • a display panel wiring structure 100 provided by an embodiment of the present application includes a first metal layer 10 and a second metal layer 20.
  • the second metal layer 20 is disposed on the first metal layer 10 and corresponds to the first metal layer 10.
  • FIG. 2 is a schematic structural diagram of the first metal layer 10 in the display panel wiring structure 100 provided by an embodiment of the application.
  • the first metal layer 10 includes a number of first scan lines 11 and second scan lines 12, the first scan lines 11 are arranged horizontally, the second scan lines 12 are arranged vertically, and the second scan lines 12 have A number of intervals 121, and the first scan line 11 is arranged in the interval 121.
  • FIG. 3 is a schematic structural diagram of the second metal layer 20 in the display panel wiring structure 100 provided by an embodiment of the application.
  • the second metal layer 20 includes a plurality of first data lines 21 and second data lines 22.
  • the first data lines 21 are arranged vertically
  • the second data lines 22 are arranged horizontally
  • the second data lines are arranged horizontally.
  • 22 has a plurality of gaps 221, and the first data line 21 is arranged in the gaps 221.
  • the second scan line 12 is connected in series with the first data line 21, and the second data line 22 is connected in series with the first scan line 11.
  • data lines and scan lines in the embodiments of the present application may be copper wires. Data lines and scan lines using copper wire process can reduce impedance.
  • a display panel wiring structure 100 made of copper wires is shown in FIG. 4.
  • the related wiring structure 100 forms a pixel area by staggering scan lines arranged horizontally and data lines arranged vertically.
  • This structure is usually a single-layer metal wiring.
  • the wiring structure 100 needs to be very thick (greater than 8000A) to meet the requirements. Since the present application adopts the double-layer wiring structure 100, reducing the copper thickness (less than 8000A) can also meet the requirements of a large-size display panel, so that the production cost can be reduced, and the capacitance delay can be reduced at the same time.
  • FIG. 5 is another structural diagram of the display panel wiring structure 100 provided by an embodiment of the application.
  • the first data line 21 is located at both ends of the space 121 and extends toward the second scan line 12 to extend a first protrusion 30, and the first protrusion 30 is connected to the second scan line.
  • the second data line 22 is located at both ends of the gap 221 and extends toward the first scan line 11 with second protrusions, and the second protrusions are connected to the first scan line 11.
  • first protrusion 30 and the second protrusion may be the same, and of course the shape of the first protrusion 30 and the second protrusion may also be different.
  • shape of the protrusion is trapezoidal.
  • the protrusion gradually narrows from the first data line 21 toward the second scan line 12. It is understandable that the first protrusion and the second protrusion may also have other shapes. In the embodiment of the present application, the specific shapes of the first protrusion 30 and the second protrusion are not described in detail.
  • the first metal layer 10 is provided with an insulating layer 40
  • the insulating layer 40 is provided with a via 41
  • the first protrusion 30 passes through the via 41 and the second scan line 12 Connected, the second protrusion passes through the via 41 and is connected to the first scan line 11.
  • the shape of the via 41 in the embodiment of the present application is compatible with the shape of the first protrusion 30 and the second protrusion.
  • FIG. 6 is another structural diagram of the display panel wiring structure 100 provided by an embodiment of the application.
  • the wiring structure 100 further includes a thin film transistor 50 connected to the first scan line 11 and the first data line 21.
  • the thin film transistor 50 changes the voltage to control the rotation of the liquid crystal so that the liquid crystal produces a picture.
  • the second scan line 12 is connected in series with the first data line 21
  • the second data line 22 is connected in series with the first scan line 11. This reduces the capacitance delay and meets the requirements of large-size panels.
  • the display panel wiring structure 100 includes a first metal layer 10 and a second metal layer 20.
  • the first metal layer 10 includes a plurality of first scan lines 11 and second scan lines 12, and the first scan line 11 is arranged horizontally, the second scan line 12 is arranged vertically, the second scan line 12 has a number of intervals 121, and the first scan line 11 is arranged in the interval 121.
  • the second metal layer 20 is disposed on the first metal layer 10 and corresponds to the first metal layer 10.
  • the second metal layer 20 includes a plurality of first data lines 21 and second data lines 22.
  • a data line 21 is arranged vertically, the second data line 22 is arranged horizontally, the second data line 22 has a plurality of gaps 221, and the first data line 21 is arranged in the gaps 221.
  • the second scan line 12 is connected in series with the first data line 21, and the second data line 22 is connected in series with the first scan line 11. Since the present application adopts the double-layer wiring structure 100, the copper thickness is reduced, the production cost is reduced, the capacitance delay can be reduced, and the requirements for large-size and high-specification panels can be met.
  • FIG. 7 is a schematic flowchart of a wiring method for a display panel according to an embodiment of the application.
  • an embodiment of the present application provides a wiring method for a display panel, including:
  • a number of second scan lines are vertically arranged, the second scan lines have a number of intervals, and the first scan lines are arranged in the intervals to form a first metal layer.
  • the second data lines Arrange several second data lines vertically, the second data lines have several gaps, and the first data lines are arranged in the gaps to form a second metal layer, and the second metal layer is arranged on the On and corresponding to the first metal layer.
  • the second scan line is connected in series with the first data line, and the second data line is connected in series with the first scan line.
  • first bumps 30 of the first data line located at both ends of the gap are connected to the second scan line
  • second bumps of the second data line located at both ends of the gap are connected to the second scan line.
  • the first scan line is connected.
  • the first bump 30 is connected to the second scan line through the via hole of the insulating layer, and the second bump is connected to the first scan line through the via hole of the insulating layer.
  • a thin film transistor is connected to the first scan line and the first data line .
  • An embodiment of the present application also provides a display panel, which includes the above-mentioned wiring structure of the display panel. Since the display structure of the display panel has been described in detail in the above embodiments. Here, I won't repeat them too much.

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Abstract

本申请显示面板走线结构包括第一金属层，包括若干第一扫描线和第二扫描线，第一扫描线横向设置，第二扫描线竖直设置，第二扫描线具有若干间隔，第一扫描线设置在间隔内；第二金属层，设置在第一金属层上且与第一金属层对应，第二金属层包括若干第一数据线和第二数据线，第一数据线竖直设置，第二数据线横向设置，第二数据线具有若干间隙，第一数据线设置在间隙内；第二扫描线与所述第一数据线串联，第二数据线与第一扫描线串。

Description

一种显示面板的走线结构、显示面板走线方法及显示面板 技术领域
本申请涉及面板制造技术领域，特别涉及一种显示面板的走线结构、显示面板走线方法及显示面板。
 背景技术
LCD(Liquid crystal displays，液晶显示器)是一种被广泛应用的平板显示器，主要是通过液晶开关调制背光源光场强度来实现画面显示。大尺寸、高解析度、高刷新频率是目前高阶TFT-LCD（Thin Film Transistor-Liquid Crystal Display，薄膜晶体管液晶显示器）产品的发展趋势。随着面板尺寸越来越大，解析度越来越高，刷新频率越来越快，薄膜晶体管的充电时间也越来越短。其中，面板尺寸的增大带来的影响则是金属走线的延长，导致电容延迟更加严重。
因此，提供一种新的显示面板走线结构以降低电容延迟成为本领域技术人员亟待解决的技术问题。
 技术问题
本申请实施例的目的在于提供一种显示面板的走线结构、显示面板走线方法及显示面板，能够解决现有技术中电容延迟的技术问题。
 技术解决方案
本申请实施例提供一种显示面板走线结构，包括：
第一金属层，包括若干第一扫描线和第二扫描线，所述第一扫描线横向设置，所述第二扫描线竖直设置，所述第二扫描线具有若干间隔，所述第一扫描线设置在所述间隔内；
第二金属层，设置在所述第一金属层上且与所述第一金属层对应，所述第二金属层包括若干第一数据线和第二数据线，所述第一数据线竖直设置，所述第二数据线横向设置，所述第二数据线具有若干间隙，所述第一数据线设置在所述间隙内；
所述第二扫描线与所述第一数据线串联，所述第二数据线与所述第一扫描线串联。
在一些实施例中，所述第一数据线位于所述间隔的两端朝向所述第二扫描线延伸出第一凸起，所述第一凸起与所述第二扫描线连接。
在一些实施例中，所述第二数据线位于所述间隙的两端朝向所述第一扫描线延伸出第二凸起，所述第二凸起与所述第一扫描线连接。
在一些实施例中，所述第一金属层上设有绝缘层，所述绝缘层上设有过孔，所述第一凸起穿过所述过孔与所述第二扫描线连接，所述第二凸起穿过所述过孔与所述第一扫描线连接。
在一些实施例中，还包括薄膜晶体管，所述薄膜晶体管连接所述第一扫描线和第一数据线。
在一些实施例中，所述过孔的形状与所述第一凸起和所述第二凸起的形状相适应。
在一些实施例中，所述第一数据线和第二数据线以及第一扫描线和第二扫描线采用铜线。
本申请实施例还提供一种显示面板走线方法，包括：
将若干第二扫描线竖直设置，所述第二扫描线具有若干间隔，将第一扫描线设置在所述间隔内以形成第一金属层；
将若干第二数据线竖直设置，所述第二数据线具有若干间隙，将第一数据线设置在所述间隙内以形成第二金属层，所述第二金属层设置在所述第一金属层上且与所述第一金属层对应；
所述第二扫描线与所述第一数据线串联，所述第二数据线与所述第一扫描线串联。
在一些实施例中，将所述第一数据线位于所述间隔的两端的第一凸起与所述第二扫描线连接，将所述第二数据线位于所述间隙的两端的第二凸起与所述第一扫描线连接。
在一些实施例中，所述第一凸起穿过绝缘层的过孔与所述第二扫描线连接，所述第二凸起穿过绝缘层的过孔与所述第一扫描线连接。
在一些实施例中，将薄膜晶体管与所述第一扫描线和第一数据线连接。
在一些实施例中，所述过孔的形状与所述第一凸起和所述第二凸起的形状相适应。
在一些实施例中，所述第一数据线和第二数据线以及第一扫描线和第二扫描线采用铜线。
本申请实施例还提供一种显示面板，其中，包括走线结构，所述走线结构包括：
第一金属层，包括若干第一扫描线和第二扫描线，所述第一扫描线横向设置，所述第二扫描线竖直设置，所述第二扫描线具有若干间隔，所述第一扫描线设置在所述间隔内；
第二金属层，设置在所述第一金属层上且与所述第一金属层对应，所述第二金属层包括若干第一数据线和第二数据线，所述第一数据线竖直设置，所述第二数据线横向设置，所述第二数据线具有若干间隙，所述第一数据线设置在所述间隙内；
所述第二扫描线与所述第一数据线串联，所述第二数据线与所述第一扫描线串联。
在一些实施例中，所述第一数据线位于所述间隔的两端朝向所述第二扫描线延伸出第一凸起，所述第一凸起与所述第二扫描线连接。
在一些实施例中，所述第二数据线位于所述间隙的两端朝向所述第一扫描线延伸出第二凸起，所述第二凸起与所述第一扫描线连接。
在一些实施例中，所述第一金属层上设有绝缘层，所述绝缘层上设有过孔，所述第一凸起穿过所述过孔与所述第二扫描线连接，所述第二凸起穿过所述过孔与所述第一扫描线连接。
在一些实施例中，还包括薄膜晶体管，所述薄膜晶体管连接所述第一扫描线和第一数据线。
在一些实施例中，所述过孔的形状与所述第一凸起和所述第二凸起的形状相适应。
在一些实施例中，所述第一数据线和第二数据线以及第一扫描线和第二扫描线采用铜线。
 有益效果
本申请实施例中，显示面板走线结构包括第一金属层和第二金属层，第一金属层包括若干第一扫描线和第二扫描线，所述第一扫描线横向设置，所述第二扫描线竖直设置，所述第二扫描线具有若干间隔，所述第一扫描线设置在所述间隔内。第二金属层设置在所述第一金属层上且与所述第一金属层对应，所述第二金属层包括若干第一数据线和第二数据线，所述第一数据线竖直设置，所述第二数据线横向设置，所述第二数据线具有若干间隙，所述第一数据线设置在所述间隙内。所述第二扫描线与所述第一数据线串联，所述第二数据线与所述第一扫描线串联。由于本申请采用双层走线结构，从而降低铜厚，使得生产成本降低，同时能够降低电容延迟，满足大尺寸、高规格的面板需求。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的显示面板走线结构的结构示意图。
图2为本申请实施例提供的显示面板走线结构中第一金属层的结构示意图。
图3为本申请实施例提供的显示面板走线结构中第二金属层的结构示意图。
图4为本申请实施例提供的相关显示面板走线结构的结构示意图。
图5为本申请实施例提供的显示面板走线结构的另一个结构示意图。
图6为本申请实施例提供的显示面板走线结构的又一个结构示意图。
图7为本申请实施例提供的显示面板走线方法的流程示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例提供一种显示面板走线结构100、显示面板走线以及显示面板。以下对显示面板走线结构100做详细介绍。
请参阅图1所示，图1为本申请实施例提供的显示面板走线结构100的结构示意图。其中，本申请实施例提供的一种显示面板走线结构100包括第一金属层10和第二金属层20。第二金属层20设置在所述第一金属层10上且与所述第一金属层10对应。
请参阅图2，图2为本申请实施例提供的显示面板走线结构100中第一金属层10的结构示意图。其中，第一金属层10包括若干第一扫描线11和第二扫描线12，所述第一扫描线11横向设置，所述第二扫描线12竖直设置，所述第二扫描线12具有若干间隔121，所述第一扫描线11设置在所述间隔121。
请参阅图3，图3为本申请实施例提供的显示面板走线结构100中第二金属层20的结构示意图。其中，所述第二金属层20包括若干第一数据线21和第二数据线22，所述第一数据线21竖直设置，所述第二数据线22横向设置，所述第二数据线22具有若干间隙221，所述第一数据线21设置在所述间隙221内。所述第二扫描线12与所述第一数据线21串联，所述第二数据线22与所述第一扫描线11串联。
需要说明的是，本申请实施例数据线和扫描线可以采用铜线。采用铜线制程的数据线和扫描线可以降低阻抗。
相关实施例中，采用铜线的制造的显示面板走线结构100如图4所示。相关的走线结构100通过横向设置的扫描线和纵向设置的数据线交错设置形成像素区域。这种结构通常是单层的金属走线，当该走线结构100应用到大尺寸的显示面板中时，走线结构100需要很厚（大于8000A）才能满足要求。由于本申请采用双层走线结构100，从而降低铜厚（小于8000A）也能满足大尺寸显示面板的要求，使得生产成本降低，同时能够降低电容延迟。
请参阅图5，图5为本申请实施例提供的显示面板走线结构100的另一个结构示意图。其中，所述第一数据线21位于所述间隔121的两端朝向所述第二扫描线12延伸出第一凸起30，所述第一凸起30与所述第二扫描线连接。所述第二数据线22位于所述间隙221的两端朝向所述第一扫描线11延伸出第二凸起，所述第二凸起与所述第一扫描线11连接。
需要说明的是，第一凸起30和第二凸起的形状可以是一样的，当然第一凸起30和第二凸起的形状也可以是不一样的。另外的，凸起的形状为呈梯形。既凸起从第一数据线21朝向第二扫描线12逐渐变窄。可以理解的是，第一凸起和第二凸起也可以是其他形状。本申请实施例中，对第一凸起30和第二凸起的具体形状不做过多赘述。
其中，所述第一金属层10上设有绝缘层40，所述绝缘层40上设有过孔41，所述第一凸起30穿过所述过孔41与所述第二扫描线12连接，所述第二凸起穿过所述过孔41与所述第一扫描线11连接。
需要说明的是，本申请实施例中过孔41的形状与第一凸起30和第二凸起的形状相适应。
请参阅图6，图6为本申请实施例提供的显示面板走线结构100的又一个结构示意图。其中，走线结构100还包括薄膜晶体管50，所述薄膜晶体管50连接所述第一扫描线11和第一数据线21。
需要说明的是，薄膜晶体管50改变电压控制液晶转向以使得液晶产生画面。本申请实施例中，由于所述第二扫描线12与所述第一数据线21串联，所述第二数据线22与所述第一扫描线11串联。从而降低了电容延迟，满足了大尺寸面板的要求。
本申请实施例中，显示面板走线结构100包括第一金属层10和第二金属层20，第一金属层10包括若干第一扫描线11和第二扫描线12，所述第一扫描线11横向设置，所述第二扫描线12竖直设置，所述第二扫描线12具有若干间隔121，所述第一扫描线11设置在所述间隔121内。第二金属层20设置在所述第一金属层10上且与所述第一金属层10对应，所述第二金属层20包括若干第一数据线21和第二数据线22，所述第一数据线21竖直设置，所述第二数据线22横向设置，所述第二数据线22具有若干间隙221，所述第一数据线21设置在所述间隙221内。所述第二扫描线12与所述第一数据线21串联，所述第二数据线22与所述第一扫描线11串联。由于本申请采用双层走线结构100，从而降低铜厚，是生产成本降低，同时能够降低电容延迟，满足大尺寸、高规格的面板需求。
请参阅图7，图7为本申请实施例提供的显示面板走线方法的流程示意图。其中，本申请实施例提供一种显示面板走线方法，包括：
101、将若干第二扫描线竖直设置，所述第二扫描线具有若干间隔，将第一扫描线设置在所述间隔内以形成第一金属层。
102、将若干第二数据线竖直设置，所述第二数据线具有若干间隙，将第一数据线设置在所述间隙内以形成第二金属层，所述第二金属层设置在所述第一金属层上且与所述第一金属层对应。
103、所述第二扫描线与所述第一数据线串联，所述第二数据线与所述第一扫描线串联。
其中，将所述第一数据线位于所述间隔的两端的第一凸起30与所述第二扫描线连接，将所述第二数据线位于所述间隙的两端的第二凸起与所述第一扫描线连接。
其中，所述第一凸起30穿过绝缘层的过孔与所述第二扫描线连接，所述第二凸起穿过绝缘层的过孔与所述第一扫描线连接。
其中，在所述第二扫描线与所述第一数据线串联，所述第二数据线与所述第一扫描线串联之后：将薄膜晶体管与所述第一扫描线和第一数据线连接。
本申请实施例还提供一种显示面板，显示面板包括上述所述的显示面板的走线结构。由于显示面板的显示结构已经在上述实施例中做了详细描述。在此，不再过多赘述。
以上对本申请实施例提供的一种液晶显示电路、液晶显示电路驱动方法及显示面板。进行了详细介绍。本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请。同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板走线结构，其中，包括：
    第一金属层，包括若干第一扫描线和第二扫描线，所述第一扫描线横向设置，所述第二扫描线竖直设置，所述第二扫描线具有若干间隔，所述第一扫描线设置在所述间隔内；
    第二金属层，设置在所述第一金属层上且与所述第一金属层对应，所述第二金属层包括若干第一数据线和第二数据线，所述第一数据线竖直设置，所述第二数据线横向设置，所述第二数据线具有若干间隙，所述第一数据线设置在所述间隙内；
    所述第二扫描线与所述第一数据线串联，所述第二数据线与所述第一扫描线串联。
  2. 根据权利要求1所述的显示面板走线结构，其中，所述第一数据线位于所述间隔的两端朝向所述第二扫描线延伸出第一凸起，所述第一凸起与所述第二扫描线连接。
  3. 根据权利要求2所述的显示面板走线结构，其中，所述第二数据线位于所述间隙的两端朝向所述第一扫描线延伸出第二凸起，所述第二凸起与所述第一扫描线连接。
  4. 根据权利要求3所述的显示面板走线结构，其中，所述第一金属层上设有绝缘层，所述绝缘层上设有过孔，所述第一凸起穿过所述过孔与所述第二扫描线连接，所述第二凸起穿过所述过孔与所述第一扫描线连接。
  5. 根据权利要求4所述的显示面板走线结构，其中，还包括薄膜晶体管，所述薄膜晶体管连接所述第一扫描线和第一数据线。
  6. 根据权利要求4所述的显示面板走线结构，其中，所述过孔的形状与所述第一凸起和所述第二凸起的形状相适应。
  7. 根据权利要求1所述的显示面板走线结构，其中，所述第一数据线和第二数据线以及第一扫描线和第二扫描线采用铜线。
  8. 一种显示面板走线方法，其中，包括：
    将若干第二扫描线竖直设置，所述第二扫描线具有若干间隔，将第一扫描线设置在所述间隔内以形成第一金属层；
    将若干第二数据线竖直设置，所述第二数据线具有若干间隙，将第一数据线设置在所述间隙内以形成第二金属层，所述第二金属层设置在所述第一金属层上且与所述第一金属层对应；
    所述第二扫描线与所述第一数据线串联，所述第二数据线与所述第一扫描线串联。
  9. 根据权利要求8所述的显示面板走线方法，其中，将所述第一数据线位于所述间隔的两端的第一凸起与所述第二扫描线连接，将所述第二数据线位于所述间隙的两端的第二凸起与所述第一扫描线连接。
  10. 根据权利要求8所述的显示面板走线方法，其中，所述第一凸起穿过绝缘层的过孔与所述第二扫描线连接，所述第二凸起穿过绝缘层的过孔与所述第一扫描线连接。
  11. 根据权利要求9所述的显示面板走线方法，其中，在所述第二扫描线与所述第一数据线串联，所述第二数据线与所述第一扫描线串联之后：
    将薄膜晶体管与所述第一扫描线和第一数据线连接。
  12. 根据权利要求10所述的显示面板走线方法，其中，所述过孔的形状与所述第一凸起和所述第二凸起的形状相适应。
  13. 根据权利要求8所述的显示面板走线方法，其中，所述第一数据线和第二数据线以及第一扫描线和第二扫描线采用铜线。
  14. 一种显示面板，其中，包括走线结构，所述走线结构包括：
    第一金属层，包括若干第一扫描线和第二扫描线，所述第一扫描线横向设置，所述第二扫描线竖直设置，所述第二扫描线具有若干间隔，所述第一扫描线设置在所述间隔内；
    第二金属层，设置在所述第一金属层上且与所述第一金属层对应，所述第二金属层包括若干第一数据线和第二数据线，所述第一数据线竖直设置，所述第二数据线横向设置，所述第二数据线具有若干间隙，所述第一数据线设置在所述间隙内；
    所述第二扫描线与所述第一数据线串联，所述第二数据线与所述第一扫描线串联。
  15. 根据权利要求14所述的显示面板，其中，所述第一数据线位于所述间隔的两端朝向所述第二扫描线延伸出第一凸起，所述第一凸起与所述第二扫描线连接。
  16. 根据权利要求15所述的显示面板，其中，所述第二数据线位于所述间隙的两端朝向所述第一扫描线延伸出第二凸起，所述第二凸起与所述第一扫描线连接。
  17. 根据权利要求16所述的显示面板，其中，所述第一金属层上设有绝缘层，所述绝缘层上设有过孔，所述第一凸起穿过所述过孔与所述第二扫描线连接，所述第二凸起穿过所述过孔与所述第一扫描线连接。
  18. 根据权利要求17所述的显示面板，其中，还包括薄膜晶体管，所述薄膜晶体管连接所述第一扫描线和第一数据线。
  19. 根据权利要求17所述的显示面板，其中，所述过孔的形状与所述第一凸起和所述第二凸起的形状相适应。
  20. 根据权利要求14所述的显示面板，其中，所述第一数据线和第二数据线以及第一扫描线和第二扫描线采用铜线。
PCT/CN2019/118205 2019-10-22 2019-11-13 一种显示面板的走线结构、显示面板走线方法及显示面板 WO2021077491A1 (zh)

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