WO2021075531A1 - トレース回路、半導体装置、トレーサ、トレースシステム - Google Patents

トレース回路、半導体装置、トレーサ、トレースシステム Download PDF

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Publication number
WO2021075531A1
WO2021075531A1 PCT/JP2020/039036 JP2020039036W WO2021075531A1 WO 2021075531 A1 WO2021075531 A1 WO 2021075531A1 JP 2020039036 W JP2020039036 W JP 2020039036W WO 2021075531 A1 WO2021075531 A1 WO 2021075531A1
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Prior art keywords
trace
program counter
destination address
output value
data
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PCT/JP2020/039036
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English (en)
French (fr)
Japanese (ja)
Inventor
高浩 西山
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to CN202080072402.6A priority Critical patent/CN114556306A/zh
Priority to JP2021552457A priority patent/JP7489398B2/ja
Priority to US17/761,713 priority patent/US12086042B2/en
Publication of WO2021075531A1 publication Critical patent/WO2021075531A1/ja
Anticipated expiration legal-status Critical
Priority to JP2024077940A priority patent/JP7690088B2/ja
Priority to US18/782,146 priority patent/US20240378126A1/en
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/362—Debugging of software
    • G06F11/3636—Debugging of software by tracing the execution of the program
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/27—Built-in tests
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/362—Debugging of software
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/362—Debugging of software
    • G06F11/3648—Debugging of software using additional hardware
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/321—Program or instruction counter, e.g. incrementing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/324—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address using program counter relative addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]

Definitions

  • the invention disclosed herein relates to a trace circuit.
  • the reason is to find the cause of the problem that the program is not working as expected, or to investigate the code coverage (whether the test covers all the code) in the test of the program operation. To do.
  • Patent Document 1 and Patent Document 2 can be mentioned.
  • Patent Document 2 since only a part of the information is output to the outside of the LSI when the branch instruction is executed, it is necessary to analyze the branch destination address outside the LSI. Therefore, if the branch destination address cannot be narrowed down to one from the branch destination address candidates, tracing becomes impossible.
  • the invention disclosed in the present specification provides a tracing circuit for simply and completely tracing the read address of the program memory from the outside of the semiconductor device in view of the above problems found by the inventor of the present application.
  • the purpose is.
  • the trace circuit disclosed in the present specification is integrated in a semiconductor device together with a microprocessor equipped with an m-bit program counter, and externally outputs a trace clock and n-bit (where 2 ⁇ n ⁇ m) bit trace data.
  • the trace data when the program counter does not change, the trace data is set as the first output value in synchronization with the trace clock, and when the program counter is incremented, the trace data is synchronized with the trace clock.
  • the trace data is set to the third output value in synchronization with the trace clock, the state machine of the microprocessor is temporarily stopped, and then the data is loaded into the program counter.
  • the branch destination address or the interrupt destination address is divided and output as the trace data (first configuration).
  • the trace circuit having the first configuration becomes the first output value when the program counter does not change, becomes the second output value when the program counter is incremented, and becomes the third output when loaded into the program counter.
  • a status generator that generates a status signal to be a value; when the operation is started when the status signal reaches the third output value and the divided output period of the branch destination address or the interrupt destination address has expired.
  • the status signal is selected as the trace data while the counter is stopped, and a part of the branch destination address or the interrupt destination address is selected as the trace data during the operation of the counter. It is preferable to have a configuration (second configuration) having a selector selected as and;
  • the status generator may monitor the internal control signal of the microprocessor and generate the status signal (third configuration).
  • the trace clock may be configured to be the drive clock of the microprocessor (fourth configuration).
  • the semiconductor device disclosed in the present specification includes a trace circuit having the above-mentioned first to fourth configurations; the instruction code is read from the program memory using the output value of the program counter as a read address, and the instruction code thereof is read. It has a configuration (fifth configuration) in which a microprocessor that decodes and executes an instruction code and; are integrated.
  • the microprocessor may have a pipeline structure (sixth configuration).
  • the tracer disclosed in the present specification is externally attached to the semiconductor device having the fifth or sixth configuration, monitors the trace data in synchronization with the trace clock, and simulates the program counter. By doing so, the configuration is such that the trace result of the read address is output (seventh configuration).
  • the tracer having the seventh configuration includes a simulated program counter; the simulated program counter is invariant when the trace data is the first output value, and the trace data is the second output value when the trace data is the second output value.
  • a decoder that increments the mock program counter and sequentially stores the branch destination address or the interrupt destination address, which is subsequently divided and input when the trace data is the third output value, in the mock program counter;
  • a latch that takes in the output value of the simulated program counter as a definite value in synchronization with the trace clock except for the split input period of the branch destination address or the interrupt destination address; It is preferable to have a configuration (eighth configuration) having a trace memory to be stored as a result and;
  • the trace system disclosed in the present specification includes a semiconductor device having the fifth or sixth configuration; a tracer having the seventh or eighth configuration; and displaying and storing the trace results. It is configured to have a host for analysis and a; (9th configuration).
  • the trace program disclosed in the present specification is executed on a computer, and the input unit, display unit, storage unit, and arithmetic unit of the computer are input, display means, and display means of the trace result, respectively.
  • the computer By operating as a storage means and an analysis means, the computer functions as the host in the trace system having the ninth configuration (tenth configuration).
  • Diagram showing the overall configuration of the trace system The figure which shows one configuration example of LSI
  • the figure which shows an example of a trace operation (LSI) Diagram showing a configuration example of a tracer
  • LSI trace operation
  • trace operation (tracer) Diagram showing an example of tracing operation (entire system)
  • program code Diagram showing split input operation of branch destination address Diagram showing the execution result of the program code
  • FIG. 1 is a diagram showing an overall configuration of a trace system.
  • the trace system X of this configuration example includes an LSI 100, a tracer 200, and a host 300.
  • the LSI 100 is an example of a semiconductor device equipped with a CPU 110.
  • the tracer 200 is an example of an adapter (debugging tool) externally attached to the LSI 100.
  • an adapter debugging tool
  • the trace result trace_result is acquired and output to the host 300 (details will be described later).
  • USB universal serial bus
  • the host 300 receives the input of the trace result trace_result from the tracer 200, and displays, stores, analyzes, and the like.
  • a trace program 310 to be executed on the personal computer is prepared, and an input unit (USB port, etc.) and a display unit (LCD [liquid crystal display]) of the personal computer are prepared.
  • Etc. storage unit
  • HDD hard disc drive
  • SSD solid state drive
  • arithmetic unit CPU, DSP [digital signal processor], etc.
  • the tracer 200 and the trace program 310 are provided together with the LSI 100.
  • FIG. 2 is a diagram showing a configuration example of the LSI 100.
  • the trace circuit 120 is integrated together with the CPU 110 described above.
  • the CPU 110 is an example of a microprocessor that performs a program operation in synchronization with the drive clock CLK (for example, 100 MHz), and includes a state machine 111, a decoding / execution unit 112, an increment unit 113, a branch destination address storage unit 114, and the like. It has a selector 115, a program counter (PC [program counter]) 116, and a program memory 117.
  • CLK drive clock
  • the state machine 111 is a 3-bit sequential circuit (logic circuit) that controls the state transition of the CPU 110, and can take up to eight operating state states (FETCH, WAIT_KEEP, TRACE, PRE_FETCH, etc.).
  • the TRACE state is one of the operating state states newly introduced with the implementation of the trace circuit 120. Although the details will be described later, the state machine 111 is suspended in the TRACE state while the trace circuit 120 divides and outputs the branch destination address or the interrupt destination address loaded in the program counter 116 as trace data trace_data.
  • the decoding / execution unit 112 reads an instruction code from the program memory 117 with the output value pc_reg of the program counter 116 as a read address, decodes the instruction code, and executes the instruction code.
  • the increment unit 113 increases the output value pc_reg of the program counter 116 by a predetermined increment value and outputs it.
  • the branch destination address storage unit 114 holds the branch destination address or the interrupt destination address output from the decoding / execution unit 112 when the program counter 116 is loaded.
  • the selector 115 programs the output of either the increment unit 113 or the branch destination address storage unit 114 in response to the internal control signals (for example, the PC load instruction pc_load and the PC increment instruction pc_inc) output from the decode / execute unit 112. Selectively output to the counter 116.
  • the internal control signals for example, the PC load instruction pc_load and the PC increment instruction pc_inc
  • the output of the increment unit 113 is selectively output to the program counter 116.
  • the program counter 116 is incremented in parallel with the decoding / execution of the instruction code.
  • the program counter 116 is incremented after decoding / executing the instruction code.
  • the output of the branch destination address storage unit 114 is selectively output to the program counter 116. Therefore, for example, when any of the interrupt instructions NMI [non-maskable interrupt] and IRQ [interrupt request], the jump instruction JMP (absolute / relative), the subroutine call instruction CALL, and the return instructions RET and RETI are executed.
  • the output value pc_reg of the program counter 116 is used as the read address of the program memory 117.
  • the program memory 117 is a storage means for storing the instruction code of the CPU 110.
  • the instruction code read according to the read address (pc_reg) is decoded / executed by the above-mentioned decoding / execution unit 112.
  • the drive clock CLK of the CPU 110 may be used as it is.
  • the status generation unit 121 operates in synchronization with the trace clock trace_clk, monitors the internal control signals of the CPU 110 (for example, the PC load instruction pc_load and the PC increment instruction pc_inc), and generates a 2-bit status signal status.
  • the fourth output value "3d (11b)" of the status signal status may be set as a reserve value (unused value).
  • the counter 122 is a 4-bit pulse counter.
  • the counter 122 starts the pulse counting operation of the trace clock trace_clk when the status signal status becomes the third output value “2d (10b)”, that is, when the program counter 116 is loaded. Further, the counter 122 receives when the count value trace_count reaches a predetermined value (for example, 8d (1000b)), that is, when the split output period (details will be described later) of the branch destination address or the interrupt destination address has expired.
  • the pulse count operation is stopped and the count value trace_count is reset to 0.
  • the selector 123 selects one of the status signal status and the output value pc_reg (of which the maximum n bits) of the program counter 116 according to the operating state of the counter 122 (whether or not the count value trace_count is 0), and trace data. Output as trace_data.
  • the state machine 111 of the CPU 110 is set to the paused state (TRACE state) while the counter 122 is operating (trace_count ⁇ 0). Is desirable.
  • the trace data trace_data is set to the first output value "0d (00b)" in synchronization with the trace clock trace_clk when the program counter 116 does not change due to the extremely simple circuit configuration.
  • the trace data trace_data is set to the second output value "1d (01b)" in synchronization with the trace clock trace_clk, and when loading to the program counter 116, the trace data trace_data is set to the third in synchronization with the trace clock trace_clk.
  • FIG. 3 is a flowchart showing an example of a trace operation in the LSI 100 (particularly the trace circuit 120).
  • step S12 If no determination is made in step S12, it is necessary to inform the tracer 200 that the program counter 116 is invariant. Therefore, in step S13, the trace data trace_data is set to the first output value "0d (00b)". After that, the flow is returned to step S11.
  • step S11 determines whether a yes determination is made in step S11, it is necessary to inform the tracer 200 that the program counter 116 has been incremented. Therefore, in step S14, the trace data trace_data is set to the second output value "1d (01b)". After that, the flow is returned to step S11.
  • step S12 when a yes judgment is made in step S12, it is necessary to inform the tracer 200 that the program counter 116 has been loaded. Therefore, in step S15, the trace data trace_data is set to the third output value "2d (10b)".
  • step S16 the pulse count operation of the trace clock trace_clk by the counter 122 is started, and the state machine 111 of the CPU 110 is put into the paused state (TRACE state).
  • step S17 a part of the branch destination address or the interrupt destination address is divided and output as trace data trace_data in synchronization with the trace clock trace_clk.
  • step S18 it is determined whether or not the count value trace_count of the counter 122 has reached a predetermined value, that is, whether or not the count of the divided output period has expired.
  • step S18 If no determination is made in step S18, the flow is returned to step S17, and the split output of the branch destination address or the interrupt destination address is continued. On the other hand, if a yes judgment is made, the flow proceeds to step S19.
  • step S19 the count value trace_count of the counter 122 is reset to 0, and the state machine 111 of the CPU 110 is returned from the paused state (TRACE state). After that, the flow is returned to step S11, and the above series of operations is repeated.
  • FIG. 4 is a diagram showing a configuration example of the tracer 200.
  • the tracer 200 of this configuration example includes a decoder 201, an increment unit 202, a selector 203, a simulated program counter 204, a latch 205, and a trace memory 206.
  • the decoder 201 monitors the trace data trace_data in synchronization with the trace clock trace_clk, and controls each part of the tracer 200 (selector 203, latch 205, etc.).
  • the decoder 201 makes the simulated program counter 204 invariant when the trace data trace_data is the first output value "0d (00b)", and the trace data trace_data is the second output value "1d (01b)".
  • the mock program counter 204 is incremented, and when the trace data trace_data is the third output value "2d (10b)", the branch destination address or the interrupt destination address which is subsequently divided and input is sequentially input to the mock program counter 204.
  • the selector 203 is controlled so as to be stored.
  • the decoder 201 generates a fixed value fetch instruction signal fetch_inst based on the monitoring result of the trace data trace_data, and determines whether or not the output value pc_count of the simulated program counter 204 should be fetched by the latch 205 as the simulated PC fixed value dump_pc. Control.
  • the increment unit 202 increases the output value pc_count of the simulated program counter 204 by a predetermined increment value and outputs it.
  • the selector 203 selects and outputs one of the trace data trace_data, the output value of the increment unit 113, and the output value pc_count of the simulated program counter 204 to the simulated program counter 204.
  • the output value pc_count of the simulated program counter 204 is selected as the simulated program counter 204 in order to make the simulated program counter 204 invariant. It is output.
  • the simulated program counter 204 may be immutable by prohibiting the fetch operation of the simulated program counter 204.
  • the output value of the increment unit 113 is selectively output to the simulated program counter 204 in order to increment the simulated program counter 204.
  • the trace trace_data is the third output value "2d (10b)"
  • the trace trace_data is stored in the simulated program counter 204 in order to sequentially store the branch destination address or the interrupt destination address to be input separately thereafter. Is selected and output to the simulated program counter 204.
  • the trace memory 206 stores the simulated PC fixed value dump_pc that is sequentially taken into the latch 205 as the trace result trace_result.
  • the output operation of the trace result trace_result for example, it may be output at any time in response to a request from the host 300, or it may be output periodically every time a certain amount is buffered.
  • the configuration is such that the program counter 116 of the CPU 110 is simulated by using the trace memory, it is not necessary to mount the trace memory on the LSI 100. Therefore, the program operation (read address) of the CPU 110 can be easily and completely traced with a small number of pins without increasing the overhead of the LSI 100.
  • FIG. 5 is a flowchart showing an example of the tracing operation in the tracer 200.
  • the trace operation starts, in step S21, the output value pc_count of the simulated program counter 204 is first initialized.
  • the output value pc_reg of the program counter 116 usually starts from 0, so the output value pc_count of the simulated program counter 204 may also be initialized to 0.
  • the program operation may be temporarily broken at the address where the tracing is to be started, and the trace data may be recorded after the program operation is restarted. Therefore, the output of the simulated program counter 204 is output.
  • the value pc_count may be initialized to the address at the time of the break.
  • step S22 it is determined whether or not the trace data trace_data input from the LSI 100 has the second output value "1d (01b)".
  • step S23 it is determined whether or not the trace data trace_data input from the LSI 100 has the second output value "1d (01b)".
  • step S23 it is determined whether or not the trace data trace_data input from the LSI 100 is the third output value "2d (10b)".
  • step S24 it is determined whether or not the trace data trace_data input from the LSI 100 is the third output value "2d (10b)".
  • step S23 If no determination is made in step S23, it is considered that the trace data trace_data input from the LSI 100 is the first output value "0d (00b)". Therefore, in step S24, the flow is returned to step S22 after the simulated program counter 204 is made immutable.
  • step S22 if a yes determination is made in step S22, the flow is returned to step S22 after the simulated program counter 204 is incremented in step S25.
  • step S23 If a yes determination is made in step S23, it is necessary to load the branch destination address or the interrupt destination address into the simulated program counter 204. Therefore, in steps S26 and S27, the branch destination address or the interrupt destination address is divided and input.
  • step S26 a part (2 bits) of the branch destination address or the interrupt destination address that is dividedly input as the trace data trace_data is stored in the corresponding bit of the simulated program counter 204.
  • step S27 whether or not all the bit values of the branch destination address or the interrupt destination address are stored in the simulated program counter 204, that is, whether or not the division input of the branch destination address or the interrupt destination address is completed. Is determined.
  • step S27 If no determination is made in step S27, the flow is returned to step S26, and the split input of the branch destination address or the interrupt destination address is continued. On the other hand, if a yes determination is made, the flow proceeds to step S28.
  • step S28 the output value pc_count of the simulated program counter 204 is fixed as the simulated PC fixed value dump_pc. After that, the flow is returned to step S22, and the above series of operations is repeated.
  • FIG. 6 is a timing chart showing a specific example of the trace operation in the entire trace system X. From the top, the PC load instruction pc_load, the PC increment instruction pc_inc, the output value pc_reg of the program counter 116, the trace clock trace_clk, and the trace data. The trace_data, the count value trace_count of the counter 122, the operating state state of the state machine 111, the output value pc_count of the simulated program counter 204, the fixed value fetch instruction signal fetch_inst, and the simulated PC fixed value dump_pc are described.
  • FIG. 6 assumes a case where the CPU 110 has a three-stage pipeline structure. That is, in the CPU 110, the signal processing for one instruction code is decomposed into three unit signal processing (fetch (F), decode (D), execution (E)), and each of them is independently processed in parallel at the same time. ..
  • the number of stages of the pipeline structure may be two stages or four or more stages.
  • the CPU 110 does not have to have a pipeline structure.
  • the CPU 110 is an 8-bit CPU and the instruction code is for 16 bits.
  • the number of bits of the CPU 110 and the number of bits of the instruction code are not limited to this.
  • FIG. 7 is a diagram showing an example (partial excerpt) of the program code provided for the trace operation of FIG.
  • various instructions JMPC, HLT, STR, LDR, SDR, CALL, RET, OR, etc.
  • the increment value of the program counter 116 is "+2" because the CPU 110 is an 8-bit CPU and the instruction code is for 16 bits, so that the read address of the program memory 117 is incremented by 2 bytes. .. In this way, the increment value of the program counter 116 is determined according to the number of bits of the CPU 110 and the number of bits of the instruction code.
  • the CPU 110 has a three-stage pipeline structure. Therefore, for example, the LDR instruction at address 0x000C fetched at time t1 is decoded at time t2 and executed at time t3. The same applies to other commands as described above. However, due to the execution of a branch instruction or an interrupt instruction, an instruction that has been fetched or decoded in parallel may be discarded without being executed. Of course, this does not apply to CPUs that do not have a pipeline structure and CPUs that have a large number of pipeline stages.
  • the output value pc_count of the simulated program counter 204 is incremented by "+2" one clock later than the output value pc_reg of the program counter 116 (0A ⁇ 0C ⁇ 0E ⁇ 10 ⁇ 12 ⁇ 14).
  • fetch_inst "H”. Therefore, the simulated PC fixed value dump_pc is incremented by "+2" one clock later than the output value pc_count of the simulated program counter 204 (08 ⁇ 0A ⁇ 0C ⁇ 0E ⁇ 10 ⁇ 12).
  • the destination address 0x004C is divided and output as trace data trace_data by 2 bits (see the hatch area in the figure).
  • the operating state state of the state machine 111 is set to the TRACE state (paused state).
  • the mock program counter 204 sequentially stores the branch destination address 0x004C, which is divided and input by 2 bits as trace data trace_data.
  • FIG. 8 is a diagram showing the split input operation of the branch destination address, and shows the transitions of the count value trace_counter of the counter 122, the output value pc_counter of the simulated program counter 204, and the trace data trace_data.
  • trace_counter "3"
  • pc_counter "0000 0000 0000 1100b (0x000C)" (see time t10 in FIG. 6).
  • trace_counter "4"
  • pc_counter "0000 0000 0100 1100b (0x004C)" (see time t11 in FIG. 6).
  • trace_counter "8"
  • pc_counter "0000 0000 0100 1100b (0x004C)" (see time t15 in FIG. 6).
  • the 16-bit branch destination address 0x004C is divided and input to the simulated program counter 204 by dividing it into 8 times by 2 bits each.
  • the simulated PC fixed value dump_pc is incremented by "+2" one clock later than the output value pc_count of the simulated program counter 204 (4C ⁇ 4E ⁇ ).
  • FIG. 9 is a diagram showing the execution result of the program code (FIG. 7). As shown in this figure, the CPU 110 executes the instruction code of each address in the order of... ⁇ 0x0008 ⁇ 0x000A ⁇ 0x000C ⁇ 0x000E ⁇ 0x0010 ⁇ 0x0012 ⁇ 0x004C ⁇ 0x004E ⁇ 0x0050 ⁇ ....
  • the simulated PC fixed value dump_pc changes in the order of ... ⁇ 0x0008 ⁇ 0x000A ⁇ 0x000C ⁇ 0x000E ⁇ 0x0010 ⁇ 0x0012 ⁇ 0x004C ⁇ 0x004E ⁇ 0x0050 ⁇ ... I will go. That is, the simulated PC fixed value dump_pc obtained by the tracer 200 completely matches the execution result of the above-mentioned program code.
  • the invention disclosed in the present specification can be used, for example, for debugging a microprocessor implemented in various information processing devices (smartphones, game devices, car navigation systems, etc.).

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  • General Engineering & Computer Science (AREA)
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PCT/JP2020/039036 2019-10-18 2020-10-16 トレース回路、半導体装置、トレーサ、トレースシステム Ceased WO2021075531A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN202080072402.6A CN114556306A (zh) 2019-10-18 2020-10-16 跟踪电路、半导体装置、跟踪器及跟踪系统
JP2021552457A JP7489398B2 (ja) 2019-10-18 2020-10-16 トレース回路、半導体装置、トレーサ、トレースシステム
US17/761,713 US12086042B2 (en) 2019-10-18 2020-10-16 Tracing circuit, semiconductor device, tracer, and tracing system
JP2024077940A JP7690088B2 (ja) 2019-10-18 2024-05-13 トレース回路、半導体装置、トレーサ、トレースシステム、トレース方法
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