WO2021070367A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2021070367A1
WO2021070367A1 PCT/JP2019/040259 JP2019040259W WO2021070367A1 WO 2021070367 A1 WO2021070367 A1 WO 2021070367A1 JP 2019040259 W JP2019040259 W JP 2019040259W WO 2021070367 A1 WO2021070367 A1 WO 2021070367A1
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WO
WIPO (PCT)
Prior art keywords
power supply
supply line
semiconductor device
power
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2019/040259
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English (en)
French (fr)
Japanese (ja)
Inventor
岡本　淳
ウェンゼン ワン
紘宜 武野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Socionext Inc
Original Assignee
Socionext Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Socionext Inc filed Critical Socionext Inc
Priority to JP2021551078A priority Critical patent/JP7315016B2/ja
Priority to PCT/JP2019/040259 priority patent/WO2021070367A1/ja
Priority to CN201980101203.0A priority patent/CN114514603B/zh
Publication of WO2021070367A1 publication Critical patent/WO2021070367A1/ja
Priority to US17/714,683 priority patent/US12154904B2/en
Anticipated expiration legal-status Critical
Priority to US18/929,016 priority patent/US20250056879A1/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/427—Power or ground buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/481—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes on the rear surfaces of the wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/856—Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/968—Macro-architecture
    • H10D84/974—Layout specifications, i.e. inner core regions
    • H10D84/981—Power supply lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/992—Noise prevention, e.g. preventing crosstalk

Definitions

  • the present invention relates to a semiconductor device.
  • Semiconductor devices include various circuit areas, and there is a standard cell area as an example of the circuit area.
  • the standard cell area includes various logic circuits and power switch circuits.
  • the power switch circuit is provided between, for example, a power supply line having a potential of VDD supplied to a semiconductor device and a power supply line supplying a power supply of V VDD to a transistor of a logic circuit, and supplies the power supply potential of V VDD to the transistor. Switch on / off.
  • the power supply is turned off when it is not necessary to operate the logic circuit, the leakage current generated in the transistors constituting the logic circuit is suppressed, and the power consumption can be reduced.
  • a technique has been proposed in which a subordinate semiconductor chip including wiring is attached to the back side of the main semiconductor chip, and a power supply potential is supplied to a transistor of the main semiconductor chip via the wiring of the subordinate semiconductor chip.
  • Such a technology is sometimes called BS-PDN (backside-power delivery network).
  • An object of the present invention is to provide a semiconductor device to which a power switch circuit can be appropriately provided.
  • the semiconductor device has a first chip having a substrate, a first wiring layer formed on the first surface of the substrate, and the opposite of the first surface of the substrate. It has a second wiring layer formed on the second surface on the side, and the second wiring layer has a first power supply line to which a first power supply potential is supplied and a second power supply.
  • the first chip has a second power supply line to which an electric potential is supplied and a first switch connected between the first power supply line and the second power supply line. It has a ground wire, a third power supply line to which the second power supply potential is supplied, and a first region in which the first ground wire and the third power supply line are arranged. In plan view, the first switch overlaps the first region.
  • a power switch circuit can be appropriately provided.
  • FIG. 1 is a cross-sectional view showing an outline of the semiconductor device according to the first embodiment.
  • FIG. 2 is a diagram showing the layout of the first chip in the first embodiment.
  • FIG. 3 is a circuit diagram showing a configuration of a circuit included in the semiconductor device according to the first embodiment.
  • FIG. 4 is a circuit diagram showing a buffer configuration.
  • FIG. 5 is a schematic view showing a planar configuration of the buffer.
  • FIG. 6 is a circuit diagram showing the configuration of the inverter.
  • FIG. 7 is a schematic view showing a planar configuration of the inverter.
  • FIG. 8 is a schematic diagram showing an outline of the power domain in the first embodiment.
  • FIG. 9 is a schematic view (No. 1) showing a planar configuration of the semiconductor device according to the first embodiment.
  • FIG. 1 is a cross-sectional view showing an outline of the semiconductor device according to the first embodiment.
  • FIG. 2 is a diagram showing the layout of the first chip in the first embodiment.
  • FIG. 10 is a schematic view (No. 2) showing a planar configuration of the semiconductor device according to the first embodiment.
  • FIG. 11 is a cross-sectional view (No. 1) showing the semiconductor device according to the first embodiment.
  • FIG. 12 is a cross-sectional view (No. 2) showing the semiconductor device according to the first embodiment.
  • FIG. 13 is a cross-sectional view (No. 3) showing the semiconductor device according to the first embodiment.
  • FIG. 14 is a schematic view (No. 1) showing a planar configuration of the semiconductor device according to the second embodiment.
  • FIG. 15 is a schematic view (No. 2) showing a planar configuration of the semiconductor device according to the second embodiment.
  • FIG. 16 is a cross-sectional view (No. 1) showing the semiconductor device according to the second embodiment.
  • FIG. 17 is a cross-sectional view (No. 2) showing the semiconductor device according to the second embodiment.
  • FIG. 18 is a schematic view (No. 1) showing a planar configuration of the semiconductor device according to the third embodiment.
  • FIG. 19 is a schematic view (No. 2) showing a planar configuration of the semiconductor device according to the third embodiment.
  • FIG. 20 is a schematic view showing a planar configuration of the semiconductor device according to the fourth embodiment.
  • FIG. 21 is a cross-sectional view (No. 1) showing the semiconductor device according to the fourth embodiment.
  • FIG. 22 is a cross-sectional view (No. 2) showing the semiconductor device according to the fourth embodiment.
  • FIG. 23 is a cross-sectional view (No. 3) showing the semiconductor device according to the fourth embodiment.
  • FIG. 24 is a schematic view showing a planar configuration of the semiconductor device according to the fifth embodiment.
  • FIG. 25 is a cross-sectional view (No. 1) showing the semiconductor device according to the fifth embodiment.
  • FIG. 26 is a cross-sectional view (No. 2) showing the semiconductor device according to the fifth embodiment.
  • FIG. 27 is a schematic view showing a planar configuration of the semiconductor device according to the sixth embodiment.
  • FIG. 28 is a schematic view showing a planar configuration of the semiconductor device according to the seventh embodiment.
  • FIG. 29 is a cross-sectional view showing the semiconductor device according to the eighth embodiment.
  • FIG. 30 is a cross-sectional view showing the semiconductor device according to the ninth embodiment.
  • FIG. 31 is a schematic diagram showing an outline of the power domain according to the tenth embodiment.
  • FIG. 32 is a schematic view showing a planar configuration of the semiconductor device according to the tenth embodiment.
  • FIG. 33 is a schematic view showing a planar configuration of the semiconductor device according to the eleventh embodiment.
  • FIG. 34 is a schematic view showing a planar configuration of the semiconductor device according to the twelfth embodiment.
  • FIG. 35 is a cross-sectional view (No. 1) showing an example of the cross-sectional configuration of the switch transistor.
  • FIG. 36 is a cross-sectional view (No. 2) showing an example of the cross-sectional configuration of the switch transistor.
  • FIG. 37 is a cross-sectional view (No. 3) showing an example of the cross-sectional configuration of the switch transistor.
  • FIG. 1 is a cross-sectional view showing an outline of the semiconductor device according to the first embodiment.
  • the semiconductor device according to the first embodiment includes a first chip 10 and a second chip 20.
  • the first chip 10 is, for example, a semiconductor chip, and includes a substrate 11 and a first wiring layer 12.
  • the substrate 11 is, for example, a silicon substrate, and a semiconductor element such as a transistor is formed on the surface side of the substrate 11.
  • the transistor is, for example, a FinFET with fins 13 in the source, drain and channels.
  • the first wiring layer 12 is formed on the surface of the substrate 11 and includes the wiring 14 and the insulating layer 15. A part of the wiring 14 is connected to the fin 13.
  • a power supply line 16 connected to the wiring 14 is formed on the front surface side of the substrate 11, and the substrate 11 is provided with a via 17 extending from the power supply line 16 to the back surface of the substrate 11.
  • the via 17 is, for example, a through-silicon via (TSV).
  • TSV through-silicon via
  • the second chip 20 is, for example, a semiconductor chip, and is arranged so as to face the back surface of the substrate 11 of the first chip 10.
  • the second chip 20 includes, for example, a second wiring layer 22 and a pad 23.
  • the second wiring layer 22 includes the wiring 24 and the insulating layer 25.
  • the upper surface of the second wiring layer 22 faces, for example, the back surface of the substrate 11 of the first chip 10. That is, the substrate 11 is located between the first wiring layer 12 and the second wiring layer 22.
  • the second wiring layer 22 may have a plurality of wirings 24.
  • the plurality of wirings 24 may be connected via vias 28 provided in the second wiring layer 22.
  • the pad 23 is an external connection terminal connected to, for example, a wiring board or a board. A part of the wiring 24 is connected to the via 17.
  • the pad 23 is provided on the back surface of the second wiring layer 22, and is connected to the wiring 24 through the via 28.
  • the power supply potential is supplied and the signal is transmitted to the second wiring layer 22 via the
  • the second chip 20 may have a size similar to that of the first chip 10, or may have a size larger than that of the first chip 10. Further, the pad 23 may be provided on the surface of the second chip 20 on the side facing the first chip 10 and outside the first chip 10 in a plan view.
  • the plan view means the plan view of the surface of the first chip 10.
  • the second wiring layer 22 may be provided by forming the wiring 24, the insulating layer 25, and the like on the back surface of the substrate 11.
  • the second wiring layer 22 may be formed on the second substrate on which the TSV is formed, or the pad 23 may be provided on the back surface of the second substrate.
  • FIG. 1 shows an outline of the semiconductor device, and the details are shown in FIGS. 9 to 13.
  • FIG. 2 is a diagram showing the layout of the first chip 10.
  • the first chip 10 includes a first power domain 31A, a second power domain 31B, and an input / output (I / O) cell area 32.
  • the I / O cell region 32 is arranged, for example, around the first power domain 31A and the second power domain 31B.
  • the number of the first power domain 31A and the number of the second power domain 31B may be 2 or more.
  • FIG. 3 is a circuit diagram showing a configuration of a circuit included in the semiconductor device according to the first embodiment.
  • the semiconductor device includes a standard cell 41, a power switch circuit 42, and a power switch control circuit 52.
  • the power switch control circuit 52 is provided in the first power domain 31A of the first chip 10.
  • the standard cell 41 is provided in the second power domain 31B of the first chip 10.
  • the standard cell 41 includes various logic circuits such as a NAND circuit and an inverter.
  • the power switch control circuit 52 includes a buffer as described later.
  • a VSS wiring that supplies the ground potential to the power switch control circuit 52 and a VDD wiring that supplies the power potential are arranged in the second power domain 31B.
  • a VSS wiring for supplying the ground potential and a V VDD wiring for supplying the power supply potential are arranged in the standard cell 41.
  • the power switch circuit 42 is provided on the second chip 20.
  • the power switch circuit 42 includes a switch transistor 51.
  • the switch transistor 51 is, for example, a P-channel MOS transistor, and is connected between the VDD wiring and the V VDD wiring.
  • the power switch control circuit 52 is connected to the gate of the switch transistor 51 and controls the operation of the switch transistor 51.
  • the power switch control circuit 52 switches the switch transistor 51 on / off, and controls the continuity between the VDD wiring and the V VDD wiring.
  • the power switch control circuit 52 includes, for example, a buffer.
  • the switch transistor 51 may be composed of a thin film transistor (TFT), or may be a microelectromechanical systems (MEMS) switch.
  • TFT thin film transistor
  • MEMS microelectromechanical systems
  • VSS wiring that supplies the ground potential to the first power domain 31A and a VVSS wiring that supplies the ground potential to the second power domain 31B, and N as a switch transistor 51 between the VSS wiring and the VVSS wiring.
  • a channel MOS transistor may be provided.
  • FIG. 4 is a circuit diagram showing a buffer configuration.
  • FIG. 5 is a schematic view showing a planar configuration of the buffer.
  • the buffer 60 included in the power switch control circuit 52 includes an inverter 61 and an inverter 62.
  • the input signal IN is input to the inverter 61
  • the output of the inverter 61 is input to the gate of the switch transistor 51 and the inverter 62
  • the output signal OUT is output from the inverter 62.
  • the inverter 61 includes a P-channel MOS transistor 610P and an N-channel MOS transistor 610N.
  • the inverter 62 includes a P-channel MOS transistor 620P and an N-channel MOS transistor 620N.
  • a power supply line 1110 corresponding to VDD wiring and a power supply line 1120 corresponding to VSS wiring are provided.
  • the power lines 1110 and 1120 extend in the X direction.
  • a semiconductor fin 651 extending in the X direction is provided on the power supply line 1120 side of the power supply line 1110.
  • a semiconductor fin 652 extending in the X direction is provided on the power supply line 1120 side of the fin 651.
  • a local wiring 631 is provided which is connected to the power supply line 1110 via the via 681, extends in the Y direction, and is connected to the fin 651.
  • a local wiring 632 that is connected to the power supply line 1120 via the via 682, extends in the Y direction, and is connected to the fin 652 is provided.
  • Local wiring 634 connected to fins 651 and 652 is provided on the positive side in the X direction from the local wirings 631 and 632.
  • Local wiring 636 connected to fins 651 and 652 is provided on the negative side in the X direction from the local wirings 631 and 632.
  • a gate electrode 612 that intersects the fins 651 and 652 via a gate insulating film (not shown) is provided between the local wiring 631 and the local wiring 634, and between the local wiring 632 and the local wiring 634.
  • a gate electrode 622 that intersects the fins 651 and 652 via a gate insulating film (not shown) is provided between the local wiring 631 and the local wiring 636, and between the local wiring 632 and the local wiring 636.
  • the gate electrode 612 is connected to wiring 611 via local wiring 633 and via 641.
  • the gate electrode 622 is connected to the control signal line 5110 via the local wiring 635 and via 643.
  • the control signal line 5110 is also connected to the local wiring 634 via the via 642.
  • the local wiring 636 is connected to the wiring 621 via the via 644.
  • the input signal IN is input to the wiring 611, and the output signal OUT is output from the wiring 621 (see FIG. 4).
  • the control signal line 5110 is connected to the gate of the switch transistor 51. That is, the control signal line 5110 functions as a signal line for transmitting a control signal to the switch transistor 51.
  • the configurations of the inverters 61 and 62 are examples.
  • the number of pairs of P-channel MOS transistors and N-channel MOS transistors included in the inverters 61 and 62 may be two or more.
  • the wiring connected to the gate of the switch transistor 51 may be connected to the input or output of the buffer 60.
  • FIG. 6 is a circuit diagram showing the configuration of the inverter.
  • FIG. 7 is a schematic view showing a planar configuration of the inverter.
  • the inverter 70 includes a P-channel MOS transistor 710P and an N-channel MOS transistor 710N.
  • a power supply line 2110 corresponding to VSS wiring and a power supply line 2120 corresponding to VSS wiring are provided.
  • the power lines 2110 and 2120 extend in the X direction.
  • Semiconductor fins 751 extending in the X direction are provided on the power supply line 2120 side of the power supply line 2110.
  • two fins 751 are provided.
  • a semiconductor fin 752 extending in the X direction is provided on the power supply line 2120 side of the fin 751.
  • a local wiring 731 that is connected to the power supply line 2110 via the via 781, extends in the Y direction, and is connected to the fin 751 is provided.
  • a local wiring 732 connected to the power supply line 2120 via the via 782, extending in the Y direction, and connected to the fin 752 is provided.
  • Local wiring 734 connected to fins 751 and 752 is provided on the positive side in the X direction from the local wirings 731 and 732.
  • a gate electrode 712 that intersects the fins 751 and 752 via a gate insulating film (not shown) is provided between the local wiring 731 and the local wiring 734, and between the local wiring 732 and the local wiring 734.
  • the gate electrode 712 is connected to the wiring 711 via the local wiring 733 and the via 741.
  • the local wiring 734 is connected to the wiring 760 via the via 742.
  • the input signal IN is input to the wiring 711, and the output signal OUT is output from the wiring 760 (see FIG. 6).
  • the circuit included in the standard cell 41 is not limited to the inverter, and circuits such as various logic circuits may be included. Further, a memory cell of SRAM (Static Random Access Memory) may be included. Further, the circuit may be provided over the region where the power supply lines 2110 and 2120 are three or more. That is, a so-called multi-height circuit may be provided.
  • SRAM Static Random Access Memory
  • FIGS. 5 and 7 exemplify a transistor using fins (FinFET), a planar type transistor and a complementary field effect transistor (Complementary) are used in the first power domain 31A and the second power domain 31B.
  • FieldEffectTransistor (CFET), a transistor using nanowires, and the like may be provided.
  • FIG. 8 is a schematic diagram showing an outline of the power domain in the first embodiment.
  • the second power domain 31B is located on the positive side of the first power domain 31A in the X direction.
  • the first power domain 31A includes circuits connected to power lines 1110 and 1120.
  • the buffer 60 of the power switch control circuit 52 shown in FIGS. 4 and 5 is included in the first power domain 31A.
  • the second power domain 31B includes circuits connected to power lines 2110 and 2120.
  • the inverter 70 shown in FIGS. 6 and 7 is included in the second power domain 31B.
  • the power switch circuit 42 overlaps with the second power domain 31B.
  • the power line 1110 and the power line 2110 extend along the extending direction as shown in FIG. At least a part of the power domain 31A of 1 and the second power domain 31B may be arranged.
  • FIGS. 9 and 10 are schematic views showing a planar configuration of the semiconductor device according to the first embodiment.
  • 11 to 13 are cross-sectional views showing a semiconductor device according to the first embodiment.
  • FIG. 9 shows the internal configuration of the first chip 10 and the second chip 20
  • FIG. 10 shows the internal configuration of the second chip 20.
  • FIG. 11 corresponds to a cross-sectional view taken along the line X11-X21 in FIGS. 9 and 10
  • FIG. 12 corresponds to a cross-sectional view taken along the line X12-X22 in FIGS. 9 and 10.
  • the power supply lines 1110 extending in the X direction and the power supply lines 1120 extending in the X direction are alternately arranged in the Y direction.
  • the power supply line 1110 corresponds to the VDD wiring
  • the power supply line 1120 corresponds to the VSS wiring.
  • a plurality of grooves extending in the X direction are formed on the substrate 11, and the power supply lines 1110 and 1120 are formed in these grooves.
  • the power supply lines 1110 and 1120 having such a structure are sometimes called BPR (Buried Power Rail).
  • An element separation film (not shown) may be formed on the surface of the substrate 11.
  • the element separation membrane is formed by, for example, the STI (Shallow Trench Isolation) method. The surface of the element separation membrane may or may not be flush with the surface of the substrate 11.
  • Vias 1111 and 1121 that penetrate the substrate 11 to the back surface are formed on the substrate 11.
  • the via 1111 is formed below the power line 1110 and the via 1121 is formed below the power line 1120.
  • One power supply line 1110 may be provided with two or more vias 1111 or one power supply line 1120 may be provided with two or more vias 1121.
  • a circuit such as the power switch control circuit 52 shown in FIG. 5 is connected between the power supply line 1110 and the power supply line 1120.
  • the control signal line 5110 that transmits the output of the inverter 61 is located between the power supply line 1110 and the power supply line 1120 in a plan view.
  • the control signal line 5110 extends to the region between the first power domain 31A and the second power domain 31B in plan view.
  • a groove is formed in the substrate 11 below the end of the control signal line 5110 on the second power domain 31B side, and the connection layer 5190 is formed in the groove.
  • the insulating layer 15 is formed with vias 5111 that electrically connect the control signal line 5110 and the connecting layer 5190.
  • a via 5191 that penetrates the substrate 11 to the back surface is formed on the substrate 11.
  • the via 5191 is formed below the connecting layer 5190.
  • the power supply lines 2110 extending in the X direction and the power supply lines 2120 extending in the X direction are alternately arranged in the Y direction.
  • the power supply line 2110 corresponds to the VSS wiring
  • the power supply line 2120 corresponds to the VSS wiring.
  • a plurality of grooves extending in the X direction are formed on the substrate 11, and the power supply lines 2110 and 2120 are formed in these grooves.
  • Power lines 2110 and 2120 having such a structure may also be referred to as BPR.
  • An element separation film (not shown) may be formed on the surface of the substrate 11.
  • Vias 2111 and 2121 are formed on the substrate 11 so as to penetrate the substrate 11 to the back surface.
  • the via 2111 is formed below the power supply line 2110 and the via 2121 is formed below the power supply line 2120.
  • One power supply line 2110 may be provided with two or more vias 2111, or one power supply line 2120 may be provided with two or more vias 2121.
  • the circuit included in the standard cell 41 such as the inverter 70 shown in FIG. 7 is connected between the power supply line 2110 and the power supply line 2120.
  • a memory cell of the SRAM may be connected between the power supply line 2110 and the power supply line 2120.
  • the second chip 20 includes, for example, an insulating layer 25 and power supply lines 4110, 4120, 4130, 4140, and 4150 formed on the surface layer portion of the insulating layer 25.
  • the power lines 4110, 4120, 4130, 4140 and 4150 extend in the Y direction.
  • the power supply lines 4110 and 4120 are provided in an area overlapping the first power domain 31A in a plan view.
  • the power supply line 4110 corresponds to the VDD wiring
  • the power supply line 4120 corresponds to the VSS wiring.
  • the power supply line 4110 is arranged at a position overlapping a straight line in which a plurality of vias 1111 are arranged in the Y direction, and is connected to the power supply line 1110 via the vias 1111.
  • the power supply line 4120 is arranged at a position overlapping a straight line in which a plurality of vias 1121 are arranged in the Y direction, and is connected to the power supply line 1120 via the via 1121.
  • the power supply lines 4130, 4140, and 4150 are provided in an area overlapping the second power domain 31B in a plan view.
  • the power supply line 4130 corresponds to the V VDD wiring
  • the power supply line 4140 corresponds to the VSS wiring
  • the power supply line 4150 corresponds to the VDD wiring.
  • the power supply line 4130 is arranged at a position overlapping a straight line in which a plurality of vias 2111 are arranged in the Y direction, and is connected to the power supply line 2110 via the vias 2111.
  • the power lines 2110 and 4130 have a mesh structure in a plan view.
  • the power supply line 4140 is arranged at a position overlapping a straight line in which a plurality of vias 2121 are arranged in the Y direction, and is connected to the power supply line 2120 via the vias 2121.
  • the power lines 2120 and 4140 have a mesh structure in a plan view.
  • the second chip 20 includes a power supply line 4190 and a gate electrode 5120 in the insulating layer 25.
  • the power line 4190 and the gate electrode 5120 are located below the power lines 4110, 4120, 4130, 4140 and 4150.
  • the power line 4190 and the gate electrode 5120 extend in the X direction.
  • the power supply line 4190 has a portion that overlaps with the power supply line 1110 in a plan view, a portion that overlaps with the power supply line 2110 in a plan view, and a portion that connects them.
  • the power supply line 4190 corresponds to VDD wiring.
  • the insulating layer 25 is formed with vias 4191 that electrically connect the power supply line 4110 and the power supply line 4190, and vias 4192 that electrically connect the power supply line 4150 and the power supply line 4190.
  • the power lines 4150 and 4190 have a mesh structure in a plan view.
  • the gate electrode 5120 is located between the power supply line 2110 and the power supply line 2120 in a plan view. As shown in FIG. 12, the gate electrode 5120 extends to the region between the first power domain 31A and the second power domain 31B in plan view.
  • a connecting portion 5180 is formed on the surface layer portion of the insulating layer 25 above the end portion of the gate electrode 5120 on the first power domain 31A side. The connecting portion 5180 is connected to the via 5191.
  • the insulating layer 25 is formed with vias 5181 that electrically connect the gate electrode 5120 and the connecting portion 5180.
  • a control signal line 5170 extending in the Y direction is formed on the surface layer portion of the insulating layer 25.
  • the control signal line 5170 is located on the first power domain 31A side of each power supply line 4130.
  • the control signal line 5170, the power supply line 4130, the power supply line 4150, and the power supply line 4140 are repeatedly arranged in the X direction in this order.
  • the insulating layer 25 is formed with vias 5171 that electrically connect the control signal lines 5170 and the gate electrode 5120 that intersect each other.
  • the gate electrode 5120 and the control signal line 5170 have a mesh structure in a plan view.
  • a plurality of semiconductor layers 6110 are formed on the insulating layer 25 so as to overlap with a pair of adjacent power supply lines 4130 and 4150 in a plan view.
  • the semiconductor layer 6110 is located below the gate electrode 5120, and a gate insulating film 6120 is provided between the semiconductor layer 6110 and the gate electrode 5120.
  • the gate insulating film 6120 is in contact with the gate electrode 5120, and the semiconductor layer 6110 is in contact with the gate insulating film 6120.
  • the semiconductor layer 6110 has a V VDD connection portion 6111 (drain) and a VDD connection portion 6112 (source) with the center line of the semiconductor layer 6110 sandwiched in the Y direction.
  • the insulating layer 25 is formed with a via 4131 that electrically connects the V VDD connection portion 6111 and the power supply line 4130, and a via 4151 that electrically connects the VDD connection portion 6112 and the power supply line 4150.
  • the plurality of semiconductor layers 6110 are arranged in a grid pattern.
  • the power supply line 4190 is connected to the VDD connection portion 6112 via the via 4192, the power supply line 4150, and the via 4151. Further, the V VDD connection unit 6111 is connected to the power supply line 2110 via the via 4131, the power supply line 4130, and the via 2111. The potential of VDD is supplied to the power supply line 4190 via, for example, the pad 23 (see FIG. 1). Further, as described above, the power supply line 2110 corresponds to the V VDD wiring. The conduction between the V VDD connection portion 6111 and the VDD connection portion 6112 is controlled by the potential of the gate electrode 5120. That is, the gate electrode 5120 functions as a gate of the switch transistor 51 connected between the VDD wiring and the V VDD wiring.
  • the switch transistor 51 includes the semiconductor layer 6110, and the semiconductor layer 6110 overlaps with the second power domain 31B in a plan view. That is, in a plan view, the switch transistor 51 overlaps with the second power domain 31B.
  • the size of the semiconductor device is reduced as compared with the case where the power switch circuit 42 including the switch transistor 51 is arranged independently from the first power domain 31A and the second power domain 31B. Can be done. Further, a region (separation region) for power supply separation between the first power domain 31A and the second power domain 31B is used between the first power domain 31A and the second power domain 31B.
  • the control signal line is connected, and the size of the semiconductor device can be reduced in this respect as well. Since the control signal line is not the wiring of the power supply potential such as the VDD wiring and the V VDD wiring, it can be arranged in the separation region.
  • the VSS wiring such as the power supply line 1120 of the first power domain 31A and the VSS wiring such as the power supply line 2120 of the second power domain 31B may be connected to each other, and may be separated from each other to be different nodes. It may be. Further, the power supply line provided in the second power domain 31B and the power supply line provided in the second chip 20 do not have to have a mesh structure in a plan view, and the gate electrode 5120 and the control signal line 5170 do not have to have a mesh structure. Does not have to have a mesh structure in plan view.
  • each via is not particularly limited, and may be, for example, a circle, an ellipse, a square, a rectangle, or the like.
  • FIGS. 14 and 15 are schematic views showing a planar configuration of the semiconductor device according to the second embodiment.
  • 16 and 17 are cross-sectional views showing a semiconductor device according to the second embodiment.
  • FIG. 14 shows the internal configuration of the first chip 10 and the second chip 20
  • FIG. 15 shows the internal configuration of the second chip 20.
  • 16 corresponds to a cross-sectional view taken along the line X13-X23 in FIGS. 14 and 15, and
  • FIG. 17 corresponds to a cross-sectional view taken along the line Y12-Y22 in FIGS. 14 and 15.
  • the second chip 20 includes, for example, the insulating layer 25 and the power supply lines 4110, 4120, 4130, 4140 formed on the surface layer portion of the insulating layer 25. Includes 4150 and.
  • the power lines 4110, 4120, 4130, 4140 and 4150 extend in the Y direction.
  • the second chip 20 further includes power lines 4270, 4280 and 4290 in the insulating layer 25.
  • the power lines 4270, 4280 and 4290 extend in the X direction.
  • the power lines 4270, 4280 and 4290 are provided in a region overlapping the second power domain 31B in a plan view.
  • the power lines 4270, 4280 and 4290 are located below the power lines 4110, 4120, 4130, 4140 and 4150.
  • the power supply line 4280 corresponds to the V VDD wiring
  • the power supply line 4270 corresponds to the VSS wiring
  • the power supply line 4290 corresponds to the VDD wiring.
  • the power supply line 4290 has a portion that overlaps with the power supply line 1120 in a plan view, a portion that overlaps with the power supply line 2120 in a plan view, and a portion that connects them.
  • the insulating layer 25 is formed with vias 4291 that electrically connect the power supply line 4110 and the power supply line 4290, and vias 4251 that electrically connect the power supply line 4150 and the power supply line 4290.
  • the insulating layer 25 is electrically connected to the via 4231 that electrically connects the power supply line 4130 and the power supply line 4280, and the power supply line 4140 and the power supply line 4270. Via 4241 is formed.
  • the second chip 20 includes a control signal line 5270 in the insulating layer 25.
  • the control signal line 5270 is located below the power lines 4110, 4120, 4130, 4140 and 4150.
  • the control signal line 5270 extends in the X direction.
  • the control signal line 5270 is located between the power supply line 2110 and the power supply line 2120 on the negative side in the Y direction of the power supply line 2110 in a plan view.
  • the power supply line 4270, the power supply line 4280, the power supply line 4290, and the control signal line 5270 are repeatedly arranged in the Y direction in this order.
  • the control signal line 5270 extends to the region between the first power domain 31A and the second power domain 31B in plan view.
  • a connecting portion 5180 is formed on the surface layer portion of the insulating layer 25 above the end portion on the first power domain 31A side of the control signal line 5270.
  • the connecting portion 5180 is connected to the via 5191.
  • the insulating layer 25 is formed with vias 5181 that electrically connect the control signal line 5270 and the connecting portion 5180.
  • the insulating layer 25 is formed with a gate electrode 5220 extending in the Y direction and overlapping the set of the power supply line 4280, the power supply line 4290, and the control signal line 5270 in a plan view.
  • the gate electrode 5220 is located between the adjacent power supply lines 4130 and 4150 in a plan view.
  • the gate electrode 5220 is located below the power supply line 4270, the power supply line 4280, the power supply line 4290, and the control signal line 5270.
  • vias 5221 are formed in the insulating layer 25 to electrically connect the gate electrode 5220 and the control signal line 5270.
  • the insulating layer 25 is formed with a semiconductor layer 6210 that overlaps with the adjacent power supply lines 4130 and 4150 and overlaps with the adjacent power supply lines 4280 and 4290 in a plan view.
  • the semiconductor layer 6210 is located below the gate electrode 5220, and a gate insulating film 6220 is provided between the semiconductor layer 6210 and the gate electrode 5220.
  • the gate insulating film 6220 is in contact with the gate electrode 5220, and the semiconductor layer 6210 is in contact with the gate insulating film 6220.
  • the semiconductor layer 6210 has a V VDD connection portion 6211 on the negative side in the X direction from the gate electrode 5220 in a plan view, and a VDD connection portion 6212 on the positive side in the X direction from the gate electrode 5220 in a plan view.
  • the insulating layer 25 is formed with a via 4281 that electrically connects the V VDD connection portion 6211 and the power supply line 4280, and a via 4292 that electrically connects the VDD connection portion 6212 and the power supply line 4290.
  • the power supply line 4290 is connected to the VDD connection portion 6212 via the via 4292.
  • the V VDD connection portion 6211 is connected to the power supply line 2110 via the via 4281, the power supply line 4280, the via 4231, the power supply line 4130, and the via 2111.
  • the potential of VDD is supplied to the power supply line 4290 via, for example, the pad 23 (see FIG. 1).
  • the power supply line 2110 corresponds to the V VDD wiring.
  • the conduction between the V VDD connection portion 6211 and the VDD connection portion 6212 is controlled by the potential of the gate electrode 5220. That is, the gate electrode 5220 functions as a gate of the switch transistor 51 connected between the VDD wiring and the V VDD wiring.
  • the switch transistor 51 includes a semiconductor layer 6210, and the semiconductor layer 6210 overlaps with the second power domain 31B in a plan view. That is, in a plan view, the switch transistor 51 overlaps with the second power domain 31B.
  • the size of the semiconductor device can be reduced as in the first embodiment.
  • FIGS. 18 and 19 are schematic views showing a planar configuration of the semiconductor device according to the third embodiment.
  • FIG. 18 shows the internal configuration of the first chip 10 and the second chip 20
  • FIG. 19 shows the internal configuration of the second chip 20.
  • the portion corresponding to the first power domain 31A is omitted.
  • the first chip 10 includes a control signal line 2390 extending in the X direction on the negative side in the Y direction of the second power domain 31B.
  • the control signal line 2390 is, for example, a BPR.
  • a via 2391 that penetrates the substrate 11 to the back surface is formed on the substrate 11.
  • the via 2391 is formed below the control signal line 2390.
  • the control signal line 5110 is connected to the control signal line 2390 via a via 5111 formed on the insulating layer 15.
  • the second chip 20 includes, for example, power lines 4130, 4140, and 4150 in the region overlapping the second power domain 31B, as in the first embodiment.
  • the power lines 4130, 4140 and 4150 extend in the Y direction.
  • the second chip 20 includes a gate electrode 5320 extending in the Y direction in the insulating layer 25.
  • the gate electrode 5320 is located below the power lines 4130, 4140 and 4150.
  • the gate electrode 5320 is located between adjacent power lines 4130 and 4150 in plan view.
  • the gate electrode 5320 has a portion that overlaps with the control signal line 2390 in a plan view.
  • a connecting portion 5380 is formed on the surface layer portion of the insulating layer 25 above the portion overlapping the control signal line 2390 in the plan view of the gate electrode 5320.
  • the insulating layer 25 is formed with vias 5381 that electrically connect the gate electrode 5320 and the connecting portion 5380.
  • the insulating layer 25 is formed with a semiconductor layer 6210 that overlaps with the adjacent power supply lines 4130 and 4150 and overlaps with the adjacent power supply lines 2110 and 2120 in a plan view.
  • the semiconductor layer 6210 is located below the gate electrode 5320.
  • a gate insulating film 6220 is provided between the semiconductor layer 6210 and the gate electrode 5320, the gate insulating film 6220 is in contact with the gate electrode 5320, and the semiconductor layer 6210 is a gate, as in the second embodiment. It is in contact with the insulating film 6220.
  • the semiconductor layer 6210 has a V VDD connection portion 6211 on the negative side in the X direction from the gate electrode 5320 in a plan view, and a VDD connection portion 6212 on the positive side in the X direction from the gate electrode 5320 in a plan view.
  • the insulating layer 25 is formed with a via 4331 that electrically connects the V VDD connection portion 6211 and the power supply line 4130, and a via 4351 that electrically connects the VDD connection portion 6212 and the power supply line 4150.
  • the switch transistor 51 includes a semiconductor layer 6210, and the semiconductor layer 6210 overlaps with the second power domain 31B in a plan view. That is, in a plan view, the switch transistor 51 overlaps with the second power domain 31B.
  • the size of the semiconductor device can be reduced as in the first embodiment and the like. Further, since the number of control signal lines extending in the X direction can be reduced, the size of the semiconductor device can be further reduced.
  • the power supply line 4150 which is an example of VDD wiring, may be connected to the power supply line 4110 or the like in the first power domain 31A via the power supply line 4190.
  • FIG. 20 is a schematic view showing a planar configuration of the semiconductor device according to the fourth embodiment.
  • 21 to 23 are cross-sectional views showing the semiconductor device according to the fourth embodiment.
  • 21 corresponds to a cross-sectional view taken along line X14-X24 in FIG. 20
  • FIG. 22 corresponds to a cross-sectional view taken along line X15-X25 in FIG.
  • FIG. 23 corresponds to a cross-sectional view taken along line X15-X25 in FIG. It corresponds to a cross-sectional view taken along the lines Y13-Y23.
  • the portion corresponding to the first power domain 31A is omitted.
  • the control signal line 5270 is provided above the semiconductor layer 6210 and is located between the power supply line 4280 and the power supply line 4290 in a plan view.
  • the gate electrode 5220 is provided for each semiconductor layer 6210 and extends in the X direction below the control signal line 5270.
  • the via 5221 that electrically connects the gate electrode 5220 and the control signal line 5270 is located above the semiconductor layer 6210.
  • a plurality of vias 4281 may be provided for one V VDD connection portion 6211, or a plurality of vias 4292 may be provided for one VDD connection portion 6212.
  • the power supply lines 4270, 4280 and 4290 and the control signal line 5270 are located above the gate electrode 5220.
  • the gate electrode 5220 is provided for each switch transistor 51 and a plurality of gate electrodes 5220 arranged in the X direction are commonly connected to the control signal line 5270, the gate electrode 5220 and the gate insulating film 6220 can be easily formed. That is, since the gate electrode 5220 and the gate insulating film 6220 do not protrude from the semiconductor layer 6210 in a plan view, the gate electrode 5220 and the gate insulating film 6220 are likely to be formed. Also in other embodiments, the gate electrode and the gate insulating film may be configured so as not to protrude from the semiconductor layer in a plan view. Further, also in other embodiments, a plurality of gate electrodes arranged in the X direction may be configured to be commonly connected to one control signal line in a plan view.
  • FIG. 24 is a schematic view showing a planar configuration of the semiconductor device according to the fifth embodiment.
  • 25 and 26 are cross-sectional views showing the semiconductor device according to the fifth embodiment.
  • FIG. 25 corresponds to a cross-sectional view taken along the line X16-X26 in FIG. 24, and
  • FIG. 26 corresponds to a cross-sectional view taken along the line Y14-Y24 in FIG. 24.
  • the portion corresponding to the first power domain 31A is omitted.
  • the second chip 20 includes a power supply line 4190 and a gate electrode 5520 in the insulating layer 25.
  • the power line 4190 and the gate electrode 5520 are located below the power lines 4110, 4120, 4130, 4140 and 4150.
  • the power line 4190 and the gate electrode 5520 extend in the X direction.
  • the insulating layer 25 has a control signal line 5170 sandwiching between the power supply lines 2110 and the power supply line 2120 in the Y direction and the power supply lines 4130 and 4150 in the X direction in a plan view.
  • a semiconductor layer 6510 is formed between the power supply line 4140 and the power supply line 4140.
  • the semiconductor layer 6510 is located above the gate electrode 5520, and a gate insulating film 6520 is provided between the semiconductor layer 6510 and the gate electrode 5520.
  • the gate insulating film 6520 is in contact with the gate electrode 5520, and the semiconductor layer 6510 is in contact with the gate insulating film 6520.
  • the semiconductor layer 6510 has a V VDD connection portion 6511 and a VDD connection portion 6512 with the center line of the semiconductor layer 6510 interposed therebetween in a plan view.
  • the insulating layer 25 is formed with a via 4131 that electrically connects the V VDD connection portion 6511 and the power supply line 4130, and a via 4151 that electrically connects the VDD connection portion 6512 and the power supply line 4150.
  • the gate electrode 5520 may be formed in the same layer as the power supply line 4190 or the like.
  • the gate electrode 5520 may be formed of the same material as the power supply line 4190 or the like.
  • the gate electrode and the gate insulating film may be located below the semiconductor layer.
  • FIG. 27 is a schematic view showing a planar configuration of the semiconductor device according to the sixth embodiment.
  • the part corresponding to the first power domain 31A is omitted.
  • a part relating to the arrangement of control signal lines, which is a characteristic part of the sixth embodiment, is illustrated, and some power lines, vias, and the like are not shown.
  • a plurality of control signal lines 5670 are arranged in the insulating layer 25.
  • the control signal line 5670 extends in the X direction and is arranged side by side in the Y direction.
  • Each control signal line 5670 has a portion protruding from both ends of the second power domain 31B in the X direction.
  • the control signal lines 5670 adjacent to each other in the Y direction are connected to each other via the control signal lines 5610 extending in the Y direction outside the second power domain 31B.
  • the control signal line 5670 connected to the control signal line 5670 located on the positive side in the Y direction via the control signal line 5610 on the negative side in the X direction is on the negative side in the Y direction via the control signal line 5610 on the positive side in the X direction. It is connected to a located control signal line 5670.
  • the control signal line 5670 connected to the control signal line 5670 located on the positive side in the Y direction via the control signal line 5610 on the positive side in the X direction is connected to the control signal line 5670 on the negative side in the X direction via the control signal line 5610 in the Y direction. It is connected to the control signal line 5670 located on the negative side.
  • control signal lines 5670 adjacent to each other in the Y direction are connected to each other only outside the second power domain 31B.
  • a gate electrode (not shown) of the switch transistor 51 is connected to the control signal line 5670. That is, a plurality of switch transistors 51 are connected in parallel.
  • the capacitance and resistance parasitic on the control signal line 5670 are large. Then, the control signal from the power switch control circuit is sequentially transmitted to each switch transistor 51 through the control signal line 5670. Therefore, the rise of the V VDD potential in the second power domain 31B becomes gentle, and the power supply noise due to the steep rise of the potential can be reduced.
  • control signal lines 5670 adjacent to each other in the Y direction are connected outside the second power domain 31B in a plan view via a control signal line provided on the surface layer of the second chip 20 instead of the control signal line 5610. It may have been done.
  • FIG. 28 is a schematic view showing a planar configuration of the semiconductor device according to the seventh embodiment.
  • the part corresponding to the first power domain 31A is omitted.
  • a part relating to the arrangement of control signal lines, which is a characteristic part of the seventh embodiment, is illustrated, and some vias and the like are not shown.
  • the buffer 5700 is added to the control signal lines 5110 and 5610.
  • the buffer 5700 is provided on the first chip 10.
  • the buffer 5700 is supplied with voltage from the VDD wiring and the VSS wiring in the same manner as the buffer 60.
  • the buffer 5700 may be provided in the first power domain 31A in the same manner as the buffer 60.
  • Other configurations are the same as in the sixth embodiment.
  • the buffer 5700 can function as a delay circuit. Therefore, the operation timing of the switch transistor 51 can be controlled by using the delay in the transmission of the control signal by the buffer 5700.
  • FIG. 29 is a cross-sectional view showing the semiconductor device according to the eighth embodiment. In FIG. 29, a part related to a control signal line and a switch transistor, which are characteristic parts of the eighth embodiment, is shown, and some power lines and the like are not shown.
  • a gate electrode 5820 extending in the X direction is provided instead of the control signal line 5670. Further, a plurality of gate insulating films 6820 in contact with the gate electrode 5820 and a plurality of semiconductor layers 6810 in contact with each of the plurality of gate insulating films 6820 are provided.
  • the semiconductor layer 6810 parasitizes the gate electrode 5820 with a large capacitance. Therefore, the effect of suppressing the steep rise of the potential can be further enhanced.
  • FIG. 30 is a cross-sectional view showing the semiconductor device according to the ninth embodiment.
  • a part related to a control signal line and a switch transistor, which are characteristic parts of the ninth embodiment, is illustrated, and some power lines and the like are not shown.
  • a plurality of gate electrodes 5920 are connected to the control signal line 5670 via vias 5671, respectively, and a gate insulating film 6820 and a semiconductor layer 6810 are formed under the gate electrodes 5920. It is provided.
  • a wiring capacitance unit 5941 having wiring 5931 and wiring 5932 adjacent to each other is connected to the control signal line 5670 via the via 5921.
  • the wires 5931 and 5932 extend in the Y direction, and the via 5921 is connected to the wire 5931.
  • the wiring 5933 extending in the Y direction is connected to the control signal line 5670 via the via 5922.
  • An insulating film 5934 and a conductive film 5935 are formed on the wiring 5933.
  • the capacitive element 5942 is composed of the wiring 5933, the insulating film 5934, and the conductive film 5935.
  • the wiring capacitance unit 5941 and the capacitance element 5942 parasitize the control signal line 5670 with a larger capacitance. Therefore, the effect of suppressing the steep rise of the potential can be further enhanced.
  • the wiring capacitance section 5941 or the capacitance element 5942 may be provided. In other embodiments, the wiring capacitance section 5941 may be provided, the capacitance element 5942 may be provided, or both of them may be provided.
  • FIG. 31 is a schematic diagram showing an outline of the power domain according to the tenth embodiment.
  • FIG. 32 is a schematic view showing a planar configuration of the semiconductor device according to the tenth embodiment.
  • the second power domain 31B is located on the positive side in the X direction of the first power domain 31A, as in the first embodiment.
  • the third power domain 31C is provided on the negative side in the Y direction of the second power domain 31B.
  • the third power domain 31C like the first power domain 31A, includes circuits connected to power lines 1110 and 1120.
  • the power switch circuit 42 is provided so as to overlap the second power domain 31B in a plan view.
  • the power switch circuit 42 is further provided between the first power domain 31A and the second power domain 31B, and between the third power domain 31C and the second power domain 31B.
  • the plane arrangement of the first power domain 31A or the third power domain 31C is not limited to FIG. 31. In this case, at least a part of the third power domain 31C and the second power domain 31B may be arranged along a direction orthogonal to the extending direction of the power supply line 1110 and the power supply line 2110.
  • a semiconductor layer 6210 is also provided between the first power domain 31A and the second power domain 31B.
  • a gate electrode 5320 extending in the Y direction is also provided between the first power domain 31A and the second power domain 31B.
  • the power supply line 4110 located on the second power domain 31B side of the power supply lines 4110 provided in the first power domain 31A is connected to the VDD connection portion 6212 of the semiconductor layer 6210 via the via 4151.
  • the power supply line 4130 located on the first power domain 31A side is connected to the V VDD connection portion 6211 of the semiconductor layer 6210 via the via 4131.
  • the third power domain 31C is also provided with power lines 1110, 1120, 4110, 4120, and the like.
  • a semiconductor layer 6210 is also provided between the third power domain 31C and the second power domain 31B.
  • the power supply line 4110 provided in the third power domain 31C is connected to the VDD connection portion 6212 of the semiconductor layer 6210 between the third power domain 31C and the second power domain 31B via the via 4151.
  • the power supply line 4130 is connected to the V VDD connection portion 6211 of the semiconductor layer 6210 between the third power domain 31C and the second power domain 31B via the via 4131.
  • the power switch circuit 42 may be provided between the first power domain 31A and the second power domain 31B. Further, in other embodiments, a third power domain 31C may be provided, and a power switch circuit 42 may be provided between the third power domain 31C and the second power domain 31B. Good.
  • FIG. 33 is a schematic view showing a planar configuration of the semiconductor device according to the eleventh embodiment.
  • the semiconductor layer 6210 between the first power domain 31A and the second power domain 31B is configured to extend in the Y direction. Further, the semiconductor layer 6210 between the third power domain 31C and the second power domain 31B is configured to extend in the X direction.
  • FIG. 34 is a schematic view showing a planar configuration of the semiconductor device according to the twelfth embodiment.
  • power supply lines 910 and 920 extending in the X direction are provided below the semiconductor layer 6210 in the second power domain 31B.
  • the power supply line 910 corresponds to the VDD wiring
  • the power supply line 920 corresponds to the V VDD wiring.
  • the power supply line 910 is connected to the VDD connection portion 6212 of the semiconductor layer 6210 via a via 911 provided under the semiconductor layer 6210.
  • the power supply line 920 is connected to the V VDD connection portion 6211 of the semiconductor layer 6210 via a via 912 provided under the semiconductor layer 6210.
  • the power supply lines 4130 and the power supply lines 4140 are alternately arranged on the surface layer portion of the insulating layer 25.
  • the power supply line 4140 may be provided above the VDD connection portions 6212 arranged in the Y direction.
  • the same effect as that of the tenth embodiment can be obtained by the twelfth embodiment. Further, according to the twelfth embodiment, the number of power supply lines provided on the surface layer portion of the insulating layer 25 can be reduced as compared with the tenth embodiment and the eleventh embodiment.
  • 35 to 37 are cross-sectional views showing an example of the cross-sectional configuration of the switch transistor.
  • the underlying insulating film 102 is provided in the insulating layer 101, and the semiconductor layer 103, the gate insulating film 104, and the gate electrode 105 are provided on the underlying insulating film 102.
  • a control signal line 110, a power supply line 120 corresponding to VDD wiring, and a power supply line 130 corresponding to V VDD wiring are provided on the surface layer portion of the insulating layer 101.
  • the semiconductor layer 103 has a channel 103C and a source 103S and a drain 103D sandwiching the channel 103C.
  • the power supply line 120 and the source 103S are connected via the via 121, and the power supply line 130 and the drain 103D are connected via the via 131.
  • a power supply line 123 corresponding to VDD wiring and a power supply line 133 corresponding to V VDD wiring are provided under the underlying insulating film 102.
  • the power supply line 120 and the power supply line 123 are connected via the via 122, and the power supply line 130 and the power supply line 133 are connected via the via 132.
  • the control signal line 110 is connected to the gate electrode 105 via the via 111.
  • the gate insulating film 204 is provided on the underlying insulating film 102, the semiconductor layer 103 is provided on the gate insulating film 204, and the gate electrode 205 is provided under the gate insulating film 204.
  • Other configurations are the same as in the first example.
  • the power supply line 123 provided under the underlying insulating film 102 is connected to the source 103S via the via 321 penetrating the underlying insulating film 102.
  • a power supply line 140 corresponding to VSS wiring may be provided on the surface layer portion of the insulating layer 101.
  • Other configurations are the same as in the first example.
  • the material of the underlying insulating film is, for example, silicon oxide, silicon nitride, silicon carbide, silicon oxide nitride, silicon oxide carbide, or the like.
  • the material of the semiconductor layer is, for example, InGaZnO (IGZO), ZnO, ZnSnO, InZnO, or the like.
  • the material of the gate insulating film is, for example, SiO 2 , SiO x N y , SiN, Al 2 O 3, and the like.
  • the material of the gate electrode is a metal such as molybdenum, titanium, chromium, tantalum, magnesium, silver, tungsten, aluminum, copper, neodymium, ruthenium, scandium and the like.
  • the material of the gate electrode may be graphene or the like.
  • the switch transistors 51 provided in each of the above embodiments can be classified into the first to third examples from the viewpoint of the stacking relationship between the gate electrode and the semiconductor layer and the connection relationship between the semiconductor layer and the VDD wiring as follows. Become. That is, the switch transistors 51 provided in the first to fourth and sixth to eleventh embodiments are classified into the first example. The switch transistor 51 provided in the fifth embodiment is classified into the second example. The switch transistor 51 provided in the twelfth embodiment is classified into the third example.
  • the present invention has been described above based on each embodiment, the present invention is not limited to the requirements shown in the above embodiments. With respect to these points, the gist of the present invention can be changed without impairing the gist of the present invention, and can be appropriately determined according to the application form thereof.
  • First chip 20 Second chip 31A, 31B, 31C: Power domain 42: Power switch circuit 51: Switch transistor 52: Power switch control circuit

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
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CN201980101203.0A CN114514603B (zh) 2019-10-11 2019-10-11 半导体装置
US17/714,683 US12154904B2 (en) 2019-10-11 2022-04-06 Semiconductor device
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WO2023127385A1 (ja) * 2021-12-27 2023-07-06 株式会社ソシオネクスト 半導体集積回路装置
WO2023166674A1 (ja) * 2022-03-03 2023-09-07 株式会社ソシオネクスト 半導体集積回路装置
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WO2024162070A1 (ja) * 2023-01-31 2024-08-08 株式会社ソシオネクスト 半導体集積回路装置
WO2024166906A1 (ja) * 2023-02-08 2024-08-15 株式会社ソシオネクスト 半導体集積回路装置
WO2024252660A1 (ja) * 2023-06-09 2024-12-12 株式会社ソシオネクスト 半導体装置
WO2025009171A1 (ja) * 2023-07-06 2025-01-09 株式会社ソシオネクスト 半導体集積回路装置
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WO2024252660A1 (ja) * 2023-06-09 2024-12-12 株式会社ソシオネクスト 半導体装置
WO2025009171A1 (ja) * 2023-07-06 2025-01-09 株式会社ソシオネクスト 半導体集積回路装置
WO2026033396A1 (ja) * 2024-08-08 2026-02-12 株式会社半導体エネルギー研究所 半導体装置

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