JPWO2021070367A1 - - Google Patents

Info

Publication number
JPWO2021070367A1
JPWO2021070367A1 JP2021551078A JP2021551078A JPWO2021070367A1 JP WO2021070367 A1 JPWO2021070367 A1 JP WO2021070367A1 JP 2021551078 A JP2021551078 A JP 2021551078A JP 2021551078 A JP2021551078 A JP 2021551078A JP WO2021070367 A1 JPWO2021070367 A1 JP WO2021070367A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2021551078A
Other languages
Japanese (ja)
Other versions
JP7315016B2 (ja
JPWO2021070367A5 (https=
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2021070367A1 publication Critical patent/JPWO2021070367A1/ja
Publication of JPWO2021070367A5 publication Critical patent/JPWO2021070367A5/ja
Application granted granted Critical
Publication of JP7315016B2 publication Critical patent/JP7315016B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10Integrated device layouts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90Masterslice integrated circuits
    • H10D84/903Masterslice integrated circuits comprising field effect technology
    • H10D84/907CMOS gate arrays
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/20Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/427Power or ground buses
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/481Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes on the rear surfaces of the wafers or substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85Complementary IGFETs, e.g. CMOS
    • H10D84/856Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90Masterslice integrated circuits
    • H10D84/903Masterslice integrated circuits comprising field effect technology
    • H10D84/907CMOS gate arrays
    • H10D84/968Macro-architecture
    • H10D84/974Layout specifications, i.e. inner core regions
    • H10D84/981Power supply lines
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90Masterslice integrated circuits
    • H10D84/903Masterslice integrated circuits comprising field effect technology
    • H10D84/907CMOS gate arrays
    • H10D84/992Noise prevention, e.g. preventing crosstalk

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
JP2021551078A 2019-10-11 2019-10-11 半導体装置 Active JP7315016B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2019/040259 WO2021070367A1 (ja) 2019-10-11 2019-10-11 半導体装置

Publications (3)

Publication Number Publication Date
JPWO2021070367A1 true JPWO2021070367A1 (https=) 2021-04-15
JPWO2021070367A5 JPWO2021070367A5 (https=) 2022-12-07
JP7315016B2 JP7315016B2 (ja) 2023-07-26

Family

ID=75438139

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021551078A Active JP7315016B2 (ja) 2019-10-11 2019-10-11 半導体装置

Country Status (4)

Country Link
US (2) US12154904B2 (https=)
JP (1) JP7315016B2 (https=)
CN (1) CN114514603B (https=)
WO (1) WO2021070367A1 (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023112682A1 (ja) * 2021-12-17 2023-06-22 株式会社ソシオネクスト 半導体集積回路装置
JPWO2023127385A1 (https=) * 2021-12-27 2023-07-06
WO2023166674A1 (ja) * 2022-03-03 2023-09-07 株式会社ソシオネクスト 半導体集積回路装置
US12402293B2 (en) 2022-09-23 2025-08-26 Apple Inc. Stacked SRAM cell architecture
US12482750B2 (en) 2022-10-17 2025-11-25 International Business Machines Corporation Power distribution network with backside power rail
WO2024162070A1 (ja) * 2023-01-31 2024-08-08 株式会社ソシオネクスト 半導体集積回路装置
WO2024166906A1 (ja) * 2023-02-08 2024-08-15 株式会社ソシオネクスト 半導体集積回路装置
JPWO2024252660A1 (https=) * 2023-06-09 2024-12-12
WO2025009171A1 (ja) * 2023-07-06 2025-01-09 株式会社ソシオネクスト 半導体集積回路装置
WO2026033396A1 (ja) * 2024-08-08 2026-02-12 株式会社半導体エネルギー研究所 半導体装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5326689A (en) * 1976-08-25 1978-03-11 Hitachi Ltd Semiconductor integrated circuit unit
JPH05206420A (ja) * 1992-01-30 1993-08-13 Nec Ic Microcomput Syst Ltd 半導体集積回路
JPH11102910A (ja) * 1997-09-29 1999-04-13 Hitachi Ltd 半導体集積回路
JP2009302198A (ja) * 2008-06-11 2009-12-24 Elpida Memory Inc 半導体チップ、半導体チップ群および半導体装置
JP2012044042A (ja) * 2010-08-20 2012-03-01 Kawasaki Microelectronics Inc 半導体集積回路および半導体集積回路装置
JP2014165358A (ja) * 2013-02-26 2014-09-08 Panasonic Corp 半導体装置及びその製造方法
US20150187642A1 (en) * 2013-12-30 2015-07-02 International Business Machines Corporation Double-sided segmented line architecture in 3d integration

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009177200A (ja) * 1998-05-01 2009-08-06 Sony Corp 半導体記憶装置
JP2009124667A (ja) * 2007-01-25 2009-06-04 Panasonic Corp 双方向スイッチ及びその駆動方法
US8530273B2 (en) 2010-09-29 2013-09-10 Guardian Industries Corp. Method of making oxide thin film transistor array
DE102013207324A1 (de) 2012-05-11 2013-11-14 Semiconductor Energy Laboratory Co., Ltd. Halbleitervorrichtung und elektronisches Gerät
EP2884542A3 (en) 2013-12-10 2015-09-02 IMEC vzw Integrated circuit device with power gating switch in back end of line
US9754923B1 (en) 2016-05-09 2017-09-05 Qualcomm Incorporated Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs)
EP3324436B1 (en) 2016-11-21 2020-08-05 IMEC vzw An integrated circuit chip with power delivery network on the backside of the chip
US10950546B1 (en) 2019-09-17 2021-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including back side power supply circuit
US11004789B2 (en) 2019-09-30 2021-05-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including back side power supply circuit

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5326689A (en) * 1976-08-25 1978-03-11 Hitachi Ltd Semiconductor integrated circuit unit
JPH05206420A (ja) * 1992-01-30 1993-08-13 Nec Ic Microcomput Syst Ltd 半導体集積回路
JPH11102910A (ja) * 1997-09-29 1999-04-13 Hitachi Ltd 半導体集積回路
JP2009302198A (ja) * 2008-06-11 2009-12-24 Elpida Memory Inc 半導体チップ、半導体チップ群および半導体装置
JP2012044042A (ja) * 2010-08-20 2012-03-01 Kawasaki Microelectronics Inc 半導体集積回路および半導体集積回路装置
JP2014165358A (ja) * 2013-02-26 2014-09-08 Panasonic Corp 半導体装置及びその製造方法
US20150187642A1 (en) * 2013-12-30 2015-07-02 International Business Machines Corporation Double-sided segmented line architecture in 3d integration

Also Published As

Publication number Publication date
JP7315016B2 (ja) 2023-07-26
US20250056879A1 (en) 2025-02-13
US12154904B2 (en) 2024-11-26
WO2021070367A1 (ja) 2021-04-15
US20220231054A1 (en) 2022-07-21
CN114514603B (zh) 2024-10-29
CN114514603A (zh) 2022-05-17

Similar Documents

Publication Publication Date Title
BR112019017762A2 (https=)
BR112021017339A2 (https=)
BR112021018450A2 (https=)
BR112021017637A2 (https=)
BR112021017892A2 (https=)
BR112021017782A2 (https=)
JPWO2021070367A5 (https=)
BR112021016821A2 (https=)
BR112021017939A2 (https=)
BR112021017738A2 (https=)
BR112021016996A2 (https=)
BR112021008711A2 (https=)
BR112019016141A2 (https=)
BR112021017728A2 (https=)
BR112021013944A2 (https=)
BR112021018452A2 (https=)
BR112021017703A2 (https=)
BR112021018102A2 (https=)
BR112019016142A2 (https=)
BR112019016138A2 (https=)
BR112021017732A2 (https=)
BR112021017234A2 (https=)
BR112021017355A2 (https=)
BR112021018168A2 (https=)
BR112021018093A2 (https=)

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20220921

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20221121

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20230613

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20230626

R150 Certificate of patent or registration of utility model

Ref document number: 7315016

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150