WO2021068326A1 - 一种基于控制信号脉宽提取的锁相加速电路及锁相环系统 - Google Patents
一种基于控制信号脉宽提取的锁相加速电路及锁相环系统 Download PDFInfo
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Abstract
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Claims (7)
- 一种基于控制信号脉宽提取的锁相加速电路,该锁相加速电路适用的锁相环包括:鉴频鉴相器、电荷泵、低通滤波器、压控振荡器和分频器,鉴频鉴相器、电荷泵、低通滤波器、压控振荡器和分频器依次连接形成一个反馈环路,其特征在于,所述锁相加速电路包括脉宽提取控制电路和电流注入开关模块;脉宽提取控制电路设有驱动输入端、使能控制端和控制输出端;电流注入开关模块设有电流步进控制端和电流注入控制端;脉宽提取控制电路的使能控制端连接外部的使能信号源,该使能信号源用于控制锁相环开始工作;脉宽提取控制电路的控制输出端连接电流注入开关模块的电流注入控制端,同时,电流注入开关模块的电流步进控制端和脉宽提取控制电路的驱动输入端都连接于鉴频鉴相器的一个预设控制信号输出端,用于根据该预设控制信号输出端输出信号的脉冲宽度变化情况,控制电流注入开关模块向低通滤波器注入电荷,直到鉴频鉴相器输入的参考时钟信号与反馈时钟信号的相位同步;其中,该预设控制信号输出端输出的信号是鉴频鉴相器输出的用于控制电荷泵进行电流注入的控制信号的反信号;低通滤波器的信号输入端连接电荷泵的信号输出端,低通滤波器的电容输入端连接电流注入开关模块的信号输出端,用于在接收电荷泵的信号输出端提供的电荷的同时,也接收电流注入开关模块的信号输出端注入的电荷,并将接收积累的电荷生成控制电压,输出给压控振荡器,其中,低通滤波器的电容输入端是:在低通滤波器内部的阻容串联支路中,电阻及其串联的电容的连接节点。
- 根据权利要求1所述锁相加速电路,其特征在于,所述电流注入开关模块包括:供电电源、第一零NMOS管、第二零NMOS管和第一零PMOS管;第一零NMOS管的源极连接第二零NMOS管的漏极,第一零NMOS管的栅极连接第一零NMOS管的漏极,第一零NMOS管的漏极连接供电电源;第二零NMOS管的漏极连接第一零NMOS管的源极,第二零NMOS管的源极连接第一零PMOS管的源极,第二零NMOS管的栅极连接所述预设控制信号输出端,作为所述电流注入开关模块的电流步进输入控制端,用于根据所述预设控制信号输出端输出信号的跳变状态改变第二零NMOS管的导通情况,以实现所述电流注入开关模块步进式注入电流;第一零PMOS管的源极连接第二零NMOS管的源极,第一零PMOS管的栅极连接脉宽提取控制电路的控制输出端,作为所述电流注入开关模块的电流注入控制端;第一零PMOS管的漏极作为所述电流注入开关模块的信号输出端,连接所述低通滤波器的电容输入端。
- 根据权利要求1或2所述锁相加速电路,其特征在于,所述延时控制模块包括延时电平产生阵列、脉宽提取阵列和控制信号生成模块;所述驱动输入端连接延时电平产生阵列设置的时钟输入端,所述使能控制端连接延时电平产生阵列设置的数据输入端;延时电平产生阵列内部包括n+3个级联的D触发器,分别对应设置n+3个数据输出端,其中,与所述使能控制端连接的D触发器为第一级D触发器,级联的脉宽提取单元的级数与相连接的相邻级联的两个D触发器中较小的级数相同;脉宽提取阵列内部包括n+2个级联的脉宽提取单元,每个脉宽提取单元都设置配有2个脉冲输入端、1个电荷泄放控制端、1个驱动端和1个脉宽信息输出端,相邻级联的脉宽提取单元都有一个共同的脉冲输入端,n+2个级联的脉宽提取单元的驱动端都连接于延时电平产生阵列设置的时钟输入端;延时电平产生阵列中相邻级联的两个D触发器的数据输出端对应连接到脉宽提取阵列的相匹配级数的脉宽提取单元的两个脉冲输入端;在延时电平产生阵列中,与所述使能控制端连接的D触发器的反相输出端连接每个脉宽提取单元的电荷泄放控制端;控制信号生成模块内置的n个比较器,每个比较器的正反相输入端分别连接相邻级联的脉宽提取单元的脉宽信息输出端,相邻两个比较器各自只存在一个输入端连接同一脉宽提取单元的脉宽信息输出端,其中,连接同一脉宽提取单元的脉宽信息输出端的相邻两个比较器的输入端属性不同,非相邻两个比较器的输入端不连接同一脉宽提取单元的脉宽信息输出端,比较器的正输入端连接的脉宽提取单元所属的级数高于同一比较器的负输入端连接的脉宽提取单元所属的级数。
- 根据权利要求3所述锁相加速电路,其特征在于,在所述延时电平产生阵列内,n+3个级联的D触发器的连接结构为:第一级D触发器的数据输入端连接所述使能控制端;在相邻级联的两个D触发器中,后一级的D触发器的数据输入端连接前一级的D触发器的数据输出端;每一级D触发器的时钟端都连接所述驱动输入端,每一级D触发器的复位端都连接所述使能控制端。
- 根据权利要求3所述锁相加速电路,其特征在于,所述脉宽提取阵列包括供电电源和n+2个级联的脉宽提取单元,每一级脉宽提取单元包括脉宽测试NMOS管、脉宽测试PMOS管、开关PMOS管、重置控制NMOS管和电容;在第n级的脉宽提取单元中,脉宽测试NMOS管的栅极连接所述延时电平产生阵列内第n级的D触发器的数据输出端,脉宽测试PMOS管的栅极连接所述延时电平产生阵列内第n+1级的D触发器的数据输出端,其中,第n级D触发器与第n级脉宽提取单元的级数相等 ,第n+1级的D触发器与第n级的D触发器是相邻级联的连接关系,以满足所述延时电平产生阵列中相邻级联的两个D触发器的数据输出端对应连接到脉宽提取阵列的相匹配级数的脉宽提取单元的两个脉冲输入端的连接关系,其中,脉宽测试NMOS管的栅极和脉宽测试PMOS管的栅极分别作为所述2个脉冲输入端;在每一级的脉宽提取单元中,脉宽测试PMOS管的源极连接供电电源,脉宽测试PMOS管的漏极连接脉宽测试NMOS管的漏极,脉宽测试NMOS管的源极连接开关PMOS管的源极,开关PMOS管的栅极作为所述脉宽提取单元的驱动端,重置控制NMOS管的栅极作为所述电荷泄放控制端,重置控制NMOS管的漏极同时连接开关PMOS管的漏极和电容的上极板,重置控制NMOS管的漏极和电容的上极板的连接节点作为所述脉宽信息输出端,电容的下极板和重置控制NMOS管的源极都接地;其中,所有级联的脉宽提取单元的开关PMOS管的栅极都连接于所述时钟输入端,所有级联的脉宽提取单元的重置控制NMOS管的栅极都连接于第一级D触发器的反相输出端。
- 根据权利要求3所述锁相加速电路,其特征在于,所述控制信号生成模块n个比较器、或逻辑电路和一个开关D触发器;这n个比较器按照脉宽提取阵列内部的级联顺序,从第二级的脉宽提取单元开始,每个比较器的正反相输入端分别连接相邻级联的脉宽提取单元的脉宽信息输出端,比较器的反相输入端连接级数较小的脉宽提取单元的脉宽信息输出端,比较器的正相输入端连接级数较大的脉宽提取单元的脉宽信息输出端;这n个比较器的信号输出端分别连接到或逻辑电路的n个输入端,或逻辑电路的输出端连接到开关D触发器的时钟端,开关D触发器的数据输入端和复位端都连接所述使能控制端,开关D触发器的数据输出端作为所述脉宽提取控制电路的控制输出端;其中,或逻辑电路包括多个或门或其对应的组合逻辑电路。
- 一种锁相环系统,包括:鉴频鉴相器,用于检测输入时钟信号和反馈时钟信号的频差和相差,产生脉冲控制信号;电荷泵,用于根据鉴频鉴相器输出的控制信号产生充电电流和放电电流;低通滤波器,用于将电荷泵输出的电流控制信号转换成控制电压,并滤除高频噪声;压控振荡器,用于根据低通滤波器输出的控制电压控制压控振荡器输出信号的频率,在控制电压升高时提升输出信号的振荡频率,在控制电压降低时降低输出信号的振荡频率,在控制电压稳定时,输出信号的振荡频率保持在一个恒值上;分频器,用于将压控振荡器的输出信号进行分频,产生所述鉴频鉴相器的反馈时钟信号;其中,鉴频鉴相器、电荷泵、低通滤波器、压控振荡器和分频器依次连接形成一个反馈环路;其特征在于,还包括:权利要求1至6任一项所述的锁相加速电路,所述锁相加速电路的脉宽提取控制电路根据鉴频鉴相器输出的控制信号的反信号的占空比变化情况,控制所述锁相加速电路的电流注入开关模块向低通滤波器注入电荷的情况,直到鉴频鉴相器输入的参考时钟信号与反馈时钟信号的相位同步,使得所述锁相加速电路缩短反馈环路的锁相时间。
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Also Published As
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US20220294458A1 (en) | 2022-09-15 |
CN110635803B (zh) | 2024-06-14 |
EP4044437A4 (en) | 2022-12-07 |
JP2022551302A (ja) | 2022-12-08 |
CN110635803A (zh) | 2019-12-31 |
EP4044437A1 (en) | 2022-08-17 |
US11664810B2 (en) | 2023-05-30 |
JP7417718B2 (ja) | 2024-01-18 |
KR20220079633A (ko) | 2022-06-13 |
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