WO2021063053A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2021063053A1
WO2021063053A1 PCT/CN2020/099349 CN2020099349W WO2021063053A1 WO 2021063053 A1 WO2021063053 A1 WO 2021063053A1 CN 2020099349 W CN2020099349 W CN 2020099349W WO 2021063053 A1 WO2021063053 A1 WO 2021063053A1
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Prior art keywords
sub
signal line
substrate
light
pin
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PCT/CN2020/099349
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English (en)
French (fr)
Inventor
王玲
林奕呈
王国英
韩影
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京东方科技集团股份有限公司
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Priority to US17/253,093 priority Critical patent/US11730035B2/en
Publication of WO2021063053A1 publication Critical patent/WO2021063053A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K50/865—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. light-blocking layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K59/8792—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. black layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, and a display device.
  • OLED display substrates are widely used in display fields such as mobile phones, tablet computers, and digital cameras due to their advantages of low energy consumption, low production cost, self-luminescence, wide viewing angle, and fast response speed.
  • a first aspect of the present disclosure provides a display substrate including a substrate and a plurality of sub-pixels arrayed on the substrate. At least one of the sub-pixels includes: a light-emitting element, a sub-pixel drive circuit coupled to the light-emitting element, And a light-emitting detection circuit for detecting the light-emitting brightness of the light-emitting element, the light-emitting detection circuit comprising: a first control transistor and a PIN-type photodiode that are sequentially stacked in a direction away from the substrate, and a first control transistor of the first control transistor One pole is coupled to the cathode of the PIN-type photodiode, and the orthographic projection of the first control transistor on the substrate at least partially overlaps the orthographic projection of the PIN-type photodiode on the substrate.
  • the PIN-type photodiode includes a cathode, a photoelectric conversion structure, and an anode that are sequentially stacked in a direction away from the substrate;
  • the cathode adopts a light-shielding material, and the orthographic projection of the first control transistor on the substrate is located inside the orthographic projection of the cathode on the substrate.
  • the plurality of sub-pixels are divided into a plurality of sub-pixel groups distributed in an array, each of the sub-pixel groups includes at least four sub-pixels distributed in an array, and the at least four sub-pixels are located in two adjacent rows, and the same
  • the sub-pixels of the sub-pixel group multiplex the same luminescence detection circuit; the orthographic projection of the PIN-type photodiode in the luminescence detection circuit on the substrate is respectively corresponding to each of the sub-pixel groups.
  • the orthographic projections of the light-emitting elements included in the sub-pixels on the substrate overlap.
  • the display substrate further includes a reference signal line, a first sensing signal line, and a first control signal line, the reference signal line is coupled to the anode of the PIN photodiode, and the first sensing A signal line is coupled to the second electrode of the first control transistor, and the first control signal line is coupled to the gate of the first control transistor;
  • the plurality of sub-pixels includes a plurality of sub-pixel rows and a plurality of sub-pixel columns; each of the sub-pixel rows includes a plurality of the sub-pixels sequentially arranged along a first direction, and each of the sub-pixel columns includes a plurality of sub-pixel rows along a first direction. A plurality of said sub-pixels arranged sequentially in two directions, said first direction intersects said second direction;
  • the light emission detection circuits located in the same row multiplex the same first reference signal line and the same control signal line;
  • the light emission detection circuits located in the same column multiplex the same first sensing signal line.
  • the orthographic projection of the reference signal line on the substrate and the orthographic projection of each of the PIN-type photodiodes coupled to the reference signal line on the substrate overlap.
  • the reference signal line and the PIN-type photodiode are sequentially stacked in a direction away from the substrate.
  • the orthographic projection of the first control signal line on the substrate and the orthographic projection of the PIN photodiodes in each of the light-emitting detection circuits coupled to the first control signal line on the substrate overlap.
  • the first control signal line and the PIN-type photodiode are sequentially stacked in a direction away from the substrate.
  • the light emission detection circuit further includes a storage capacitor, the first plate of the storage capacitor is coupled to the anode of the PIN photodiode, and the second plate of the storage capacitor is connected to the anode of the PIN photodiode.
  • the first electrode plate and the first electrode and the second electrode of the first control transistor are arranged in the same layer and the same material;
  • the cathode of the PIN photodiode is multiplexed as the second plate of the storage capacitor coupled to it, and the orthographic projection of the first plate on the substrate is located on the second plate on the substrate. The interior of the orthographic projection.
  • the display substrate further includes: a second sensing signal line and a second control signal line;
  • the sub-pixel further includes an electrical detection circuit, the electrical detection circuit includes a second control transistor, the first electrode of the second control transistor is coupled to the anode of the light-emitting element, and the second control transistor The pole is coupled to the second sensing signal line, and the gate of the second control transistor is coupled to the second control signal line;
  • the electrical detection circuits located in the same row multiplex the same second control signal line;
  • the electrical detection circuits located in the same column multiplex the same second sensing signal line.
  • At least two adjacent rows of the electrical detection circuits multiplex the same second sensing signal line.
  • the first sensing signal lines and the second sensing signal lines are alternately arranged, and there are at least two rows between the adjacent first sensing signal lines and the second sensing signal lines The sub-pixel column.
  • the display substrate further includes a data line corresponding to each of the sub-pixel columns one-to-one, and each of the data lines is respectively coupled to a sub-pixel drive circuit included in each sub-pixel in the corresponding sub-pixel column;
  • At least one column of the sub-pixels is included between the data line and the first sensing signal line;
  • At least one column of the sub-pixels is included between the data line and the second sensing signal line.
  • the sub-pixels corresponding to the electrical detection circuits in the same row may form a pixel unit, and the light emitted by the pixel unit is white light.
  • each of the sub-pixel groups includes eight sub-pixels distributed in an array, and the eight sub-pixels are respectively located in two adjacent rows, and four sub-pixels in the same row among the eight sub-pixels constitute a display substrate
  • the light emitted by the pixel unit is white light.
  • the first control transistor includes an oxide thin film transistor.
  • the display substrate further includes a first flat layer, and the first flat layer is located between the first control transistor and the PIN photodiode.
  • a second aspect of the present disclosure provides a display device including the above display substrate.
  • a third aspect of the present disclosure provides a manufacturing method of a display substrate for manufacturing the above display substrate.
  • the manufacturing method includes a step of manufacturing a plurality of sub-pixels distributed in an array on a substrate.
  • the specific steps include:
  • the PIN-type photodiode in each of the luminescence detection circuits is fabricated on the side of the first control transistor facing away from the substrate, and the first pole of the first control transistor is corresponding to the cathode of the PIN-type photodiode Coupled, the orthographic projection of the first control transistor on the substrate at least partially overlaps the orthographic projection of the corresponding PIN-type photodiode on the substrate;
  • a light-emitting element included in each sub-pixel is fabricated on the side of the PIN-type photodiode facing away from the substrate, and the light-emitting element is coupled to the corresponding sub-pixel driving circuit.
  • a first flat layer is formed between the first control transistor and the PIN photodiode.
  • FIG. 1 is a first cross-sectional schematic diagram of a light-emitting detection element provided by an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of a second cross-section of a light-emitting detection element provided by an embodiment of the disclosure
  • FIG. 3 is a schematic top view of a light-emitting detection element provided by an embodiment of the disclosure.
  • FIG. 4 is a schematic diagram of the structure of a light-emitting detection element provided by an embodiment of the disclosure.
  • FIG. 5 is a schematic top view of a display substrate provided by an embodiment of the disclosure.
  • the OLED display substrate includes a plurality of sub-pixels distributed in an array.
  • Each sub-pixel includes a sub-pixel driving circuit and a light-emitting element coupled to each other.
  • the sub-pixel driving circuit provides a driving current for the corresponding light-emitting element to drive the light-emitting element to emit corresponding colors Light.
  • the sub-pixel is generally set to detect the brightness of light emitted by the light-emitting element Detection circuit
  • the light-emitting detection circuit mainly includes a detection switch transistor and a PIN-type photodiode.
  • the PIN-type photodiode When the light-emitting detection circuit is used to detect the intensity of the light emitted by the light-emitting element, the PIN-type photodiode receives the light emitted by the light-emitting element and will receive The light is converted into an electrical signal, so that the converted electrical signal can compensate the light emission of the light-emitting element.
  • the area of the PIN-type photodiode is generally larger.
  • setting the PIN-type photodiode with a larger area will cause the overall area of the light-emitting detection circuit to be larger, which will lead to The aperture ratio of the display substrate decreases.
  • an embodiment of the present disclosure provides a display substrate, including a substrate 10 and a plurality of sub-pixels arrayed on the substrate 10, each of the sub-pixels includes: a light-emitting element, and the light-emitting element A sub-pixel driving circuit coupled to the element, and a light-emitting detection circuit for detecting the light-emitting brightness of the light-emitting element.
  • the light-emitting detection circuit includes: a first control transistor T1 and a PIN type that are sequentially stacked in a direction away from the substrate 10
  • the photodiode 17, the first pole 151 of the first control transistor T1 is coupled to the cathode 170 of the PIN-type photodiode 17, the orthographic projection of the first control transistor T1 on the substrate 10, and the The orthographic projections of the PIN photodiodes 17 on the substrate 10 at least partially overlap.
  • the base 10 in the display substrate may include a glass base 10, but is not limited thereto.
  • the light-emitting color of the light-emitting elements included in each sub-pixel in the display substrate can be set according to actual needs.
  • the light-emitting elements included in each sub-pixel in the display substrate can be set to emit white light.
  • the display substrate further includes a color film structure, and the color film structure may include color resist patterns of at least three colors, such as a red color resist pattern, a green color resist pattern, and a blue color resist pattern. The pattern corresponds to the light-emitting element one-to-one, so that the light emitted by the light-emitting element can pass through its corresponding color resist pattern and then exit the display substrate, thereby realizing the display function of the display substrate.
  • the sub-pixels in the same column can be set to correspond to the color resist patterns of the same color. As shown in Figure 5, the first column of sub-pixels from the left corresponds to the red color resist pattern, and the corresponding data line is DR.
  • the light emitted by the pixel is red light; the second column of sub-pixels corresponds to the green color resist pattern, the corresponding data line is DG, and the second column of sub-pixels emit green light; the third column of sub-pixels corresponds to the blue color resist pattern, and the corresponding data line It is DB, the light emitted by the third column of sub-pixels is blue; the fourth column of sub-pixels corresponds to a white color resist pattern, the corresponding data line is DW, and the light from the fourth column of sub-pixels is white light.
  • each sub-pixel further includes a sub-pixel drive circuit and a light-emission detection circuit.
  • the position layout of the sub-pixel drive circuit and the light-emission detection circuit can be set according to actual needs, for example, as shown in FIG. 5
  • the first layout area 20 of the sub-pixel driving circuit and the second layout area 22 of the light-emission detection circuit are arranged oppositely, and the opening area 21 of the sub-pixel is located in the sub-pixel. Between the first layout area 20 of the driving circuit and the second layout area 22 of the light emission detection circuit.
  • the sub-pixel driving circuit may include at least one driving thin film transistor and a plurality of switching thin film transistors. These thin film transistors cooperate with each other so that the driving thin film transistor generates a driving signal and transmits it to the corresponding light-emitting element to drive the corresponding light-emitting element Realize the light-emitting function.
  • the light emission detection circuit includes the first control transistor T1 and the PIN-type photodiode 17.
  • the first pole 151 of the first control transistor T1 is coupled to the cathode 170 of the PIN-type photodiode 17.
  • the first control transistor T1 and the PIN-type photodiode 17 are laminated and arranged, and the first control transistor T1 is arranged on the substrate 10 and the PIN-type photodiode 17.
  • the orthographic projection of the first control transistor T1 on the substrate 10 at least partially overlaps the orthographic projection of the PIN-type photodiode 17 on the substrate 10, so that it is perpendicular to In the direction of the substrate 10, the PIN-type photodiode 17 can shield at least part of the first control transistor T1.
  • the display substrate provided by the embodiment of the present disclosure can be selected as bottom emission, that is, light is emitted from the side where the base 10 of the display substrate is located.
  • the display substrate is arranged on the first control transistor T1 and the PIN type photoelectric
  • the first control transistor T1 is disposed between the substrate 10 and the PIN-type photodiode 17.
  • the display substrate further includes a light-shielding layer 11, a buffer layer 120, a first insulating layer 121, a first passivation layer 122, a second passivation layer 123, a second planarization layer 125, and a gate.
  • the PIN-type photodiode 17 receives the light emitted by its corresponding light-emitting element, converts it into an electrical signal, and transmits it to the chip of the display substrate via the first control transistor T1.
  • the chip compensates the light-emitting brightness of the light-emitting element in the display substrate based on the electrical signal, so as to achieve the uniformity of the display brightness of the display substrate.
  • the first control transistor T1 and the PIN photodiode 17 included in the light-emitting detection circuit in each sub-pixel are sequentially arranged in a direction away from the base 10 Stacked arrangement, and set the orthographic projection of the first control transistor T1 on the substrate 10 to at least partially overlap the orthographic projection of the PIN-type photodiode 17 on the substrate 10, so that the PIN-type photoelectric
  • the diode 17 can shield at least part of the first control transistor T1, reducing the area occupied by the light-emitting detection circuit in a direction parallel to the substrate 10, thereby effectively increasing the aperture ratio of each sub-pixel.
  • the first control transistor T1 is disposed between the base 10 and the PIN-type photodiode 17, and the light-emitting element is disposed on the PIN-type photodiode.
  • the side of 17 facing away from the base 10 realizes that while increasing the aperture ratio of the display substrate, it also ensures the light sensing accuracy of the PIN-type photodiode 17 so as to be more conducive to improving the brightness of the display substrate. Uniformity.
  • the PIN-type photodiode 17 includes a cathode 170, a photoelectric conversion structure 171, and an anode 172 that are sequentially stacked in a direction away from the substrate 10; the cathode 170 is made of light-shielding material, and the first control The orthographic projection of the transistor T1 on the substrate 10 is located inside the orthographic projection of the cathode 170 on the substrate 10.
  • the cathode 170 of the PIN-type photodiode 17 is made of light-shielding material, and specifically, a metal material with light-shielding performance can be selected. But it is not limited to this.
  • the photoelectric conversion structure 171 specifically includes: a PN junction and a layer of I-type semiconductor with a low concentration doped in the middle of the PN junction. Because the doped I-type semiconductor has a low concentration, it is almost an Intrinsic semiconductor. It can be called the I layer. On both sides of the I layer are P-type semiconductors and N-type semiconductors with high doping concentration, which are formed into P and N layers. The P and N layers are very thin, and the proportion of absorbing incident light is small. , So that most of the incident light is absorbed in the I layer and generate a large number of electron-hole pairs, and the I layer is thicker and almost occupies the entire depletion zone, which can be achieved by increasing the width of the depletion zone. Achieve the purpose of reducing the influence of the diffusion movement and improving the response speed of the photodiode.
  • the PIN-type photodiode 17 can well receive the light emitted by the corresponding light-emitting element, thereby ensuring the detection accuracy of the light-emitting detection circuit.
  • the cathode is provided with a light-shielding material, and the orthographic projection of the first control transistor T1 on the substrate 10 is located inside the orthographic projection of the cathode on the substrate 10.
  • the first control transistor T1 is completely covered by the PIN-type photodiode 17, which not only minimizes the area occupied by the luminescence detection circuit in the direction parallel to the substrate 10, so that the luminescence detection
  • the area occupied by the circuit in the direction parallel to the substrate 10 is only the area occupied by the PIN-type photodiode 17, and the first control transistor T1 is prevented from being affected by light, which ensures that the light-emitting detection circuit
  • the smaller dark current that is, the current of the first control transistor T1 in the off state, thereby effectively improving the signal-to-noise ratio of the light-emitting detection circuit.
  • the plurality of sub-pixels are divided into a plurality of sub-pixel groups distributed in an array, each of the sub-pixel groups includes at least four sub-pixels distributed in an array, and the at least four sub-pixels are located in In two adjacent rows, sub-pixels of the same sub-pixel group multiplex the same luminescence detection circuit; the orthographic projection of the PIN-type photodiode 17 in the luminescence detection circuit on the substrate 10 is different from The orthographic projections of the light-emitting elements included in the sub-pixels in the corresponding sub-pixel groups on the substrate 10 overlap.
  • the plurality of sub-pixels may be divided into a plurality of sub-pixel groups, the plurality of sub-pixel groups are arranged in an array, and each of the sub-pixel groups includes an array distribution and is arranged adjacently
  • the at least four sub-pixels may be located in two adjacent rows; for example, the sub-pixel group includes 8 sub-pixels, the 8 sub-pixels include 4 sub-pixels located in the same row, and the at least four sub-pixels may be located in two adjacent rows. 4 sub-pixels in the next adjacent row.
  • the 4 sub-pixels located in the same row can correspond to the red color group unit, the green color group unit, the blue color group unit, and the white color group unit one by one, so that the 4 sub-pixels located in the same row constitute the whole A pixel unit in the display substrate.
  • the 4 sub-pixels located in the next adjacent row can also correspond to the red color group unit, the green color group unit, the blue color group unit, and the white color group unit one by one, so that the four sub-pixels located in the next adjacent row
  • the 4 sub-pixels also constitute a pixel unit in the display substrate.
  • the PIN-type photodiode 17 in the luminescence detection circuit can be arranged on the substrate 10
  • the orthographic projection on the corresponding sub-pixel group overlaps with the orthographic projection of the light-emitting element included in each sub-pixel in the sub-pixel group on the substrate 10, so that the luminescence detection circuit can receive its corresponding sub-pixel group
  • the light emitted by the light-emitting element included in each sub-pixel in the sub-pixel so as to realize the light-emitting detection of the light-emitting element included in each sub-pixel in the corresponding sub-pixel group.
  • sub-pixels in the same sub-pixel group multiplex the same luminescence detection circuit, so that the area occupied by the luminescence detection circuit in the display substrate is further reduced, thereby further reducing the area occupied by the luminescence detection circuit. It is beneficial to increase the aperture ratio of the display substrate.
  • the sub-pixels of the same sub-pixel group are multiplexed with the same light-emission detection circuit, which also reduces the number of vertices of the PIN-type photodiode 17 in the light-emission detection circuit included in the display substrate. Thereby, the dark current of the luminescence detection circuit is further reduced.
  • the display substrate provided by the above embodiment further includes a reference signal line REF, a first sensing signal line SL1, and a first control signal line G1, the reference signal line REF and the PIN-type photoelectric
  • the anode 172 of the diode 17 is coupled through a via0, the first sensing signal line SL1 is coupled to the second pole 150 of the first control transistor T1, and the first control signal line G1 is coupled to the first electrode 150 of the first control transistor T1.
  • the gate of the control transistor T1 is coupled; the first electrode 151 of the first control transistor T1 is coupled to the cathode 170 of the PIN photodiode 17 through the dashed frame pattern in FIG. 3.
  • the plurality of sub-pixels includes a plurality of sub-pixel rows and a plurality of sub-pixel columns; each of the sub-pixel rows includes a plurality of the sub-pixels sequentially arranged along a first direction, and each of the sub-pixels
  • Each pixel column includes a plurality of the sub-pixels arranged in sequence along a second direction, the first direction intersects the second direction; along the first direction, the light emission detection circuits located in the same row multiplex the same One reference signal line REF and the same first control signal line G1; along the second direction, the light emission detection circuits located in the same column multiplex the same first sensing signal line SL1.
  • the plurality of sub-pixels included in the display substrate are distributed in an array, and the plurality of sub-pixels may be divided into a plurality of sub-pixel rows or a plurality of sub-pixel columns; wherein each of the sub-pixel rows includes A plurality of the sub-pixels sequentially arranged along a first direction, each of the sub-pixel columns includes a plurality of the sub-pixels sequentially arranged along a second direction, and the first direction may intersect the second direction Exemplarily, the first direction is perpendicular to the second direction.
  • the display substrate further includes a plurality of reference signal lines REF, a plurality of first sensing signal lines SL1, and a plurality of first control signal lines G1.
  • the The anode 172 of the PIN photodiode 17 is coupled to the reference signal line REF corresponding to the light emission detection circuit
  • the second pole 150 of the first control transistor T1 is coupled to the first sensing signal line SL1 corresponding to the light emission detection circuit
  • the gate of the first control transistor T1 is coupled to the first control signal line G1 corresponding to the light emission detection circuit.
  • the specific layout of the plurality of reference signal lines REF, the plurality of first sensing signal lines SL1, and the plurality of first control signal lines G1 are various, for example, as shown in FIG. 5 It is shown that the luminescence detection circuits located in the same row along the first direction can be multiplexed with the same reference signal line REF and the same first control signal line G1; along the second direction, located in The luminescence detection circuits in the same column multiplex the same first sensing signal line SL1; in this arrangement, a driving method similar to the gate line and data line in the display substrate can be adopted, and the first control The signal line G1 controls the first control transistor T1 to turn on row by row, and when the first control transistor T1 is turned on in a certain row, the PIN-type photodiode 17 sensor of the row is transmitted through the plurality of first sensing signal lines SL1. Measured sensing signal.
  • the luminescence detection circuits located in the same row along the first direction multiplex the same reference signal line REF and the same first control signal line G1, and The luminescence detection circuits located in the same column along the second direction multiplex the same first sensing signal line SL1, so that the reference signal line REF provided in the display substrate, the first The number of the sensing signal line SL1 and the first control signal line G1 is greatly reduced, thereby reducing the complexity of the layout of the display substrate and further improving the resolution of the display substrate.
  • an orthographic projection of the reference signal line REF on the substrate 10 may be provided, and each of the PIN-type photodiodes 17 coupled to the reference signal line REF may be located on the substrate 10. And/or, the orthographic projection of the first control signal line G1 on the substrate 10, and the PIN-type photodiode 17 in each of the light-emitting detection circuits coupled with it is in the The orthographic projections on the substrate 10 all overlap.
  • the luminescence detection circuits located in the same row multiplex the same reference signal line REF and the same first control signal line G1, and are located along the second direction
  • the reference signal line REF and the first control signal line G1 both extend along the first direction
  • the first A sensing signal line SL1 extends along the second direction.
  • the specific layout of the reference signal line REF and the first control signal line G1 can be set according to actual needs, and only needs to satisfy that the reference signal line REF can correspond to each PIN in a row of light-emitting detection circuits respectively.
  • the anode 172 of the type photodiode 17 is coupled, and the first control signal line G1 can be coupled to the gate of each first control transistor T1 in the corresponding row of light emission detection circuit;
  • the orthographic projection of G1 on the substrate 10 and the orthographic projections of the PIN-type photodiodes 17 in each of the light-emitting detection circuits coupled with it on the substrate 10 overlap; this arrangement makes the reference signal The line REF and/or the first control signal line G1 can overlap the above-mentioned PIN-type photodiode 17 in a direction perpendicular to the substrate 10, while ensuring the normal operation of each of the light-emitting detection circuits, more It is beneficial to increase the aperture ratio of the display substrate.
  • reference signal line REF and the first control signal line G1 may both be arranged between the substrate 10 and the PIN-type photodiode to avoid the reference signal line REF and the first control signal line G1.
  • the control signal line G1 blocks the light-receiving surface of the PIN-type photodiode.
  • the light emission detection circuit further includes a storage capacitor C1, the first plate 152 of the storage capacitor C1 and the anode of the PIN photodiode 17 172, the second plate of the storage capacitor C1 is coupled to the cathode 170 of the PIN-type photodiode 17; the first plate 152 is coupled to the first electrode 151 and the first electrode of the first control transistor T1
  • the two poles 150 are arranged in the same layer and the same material; the cathode 170 of the PIN-type photodiode 17 is multiplexed as the second plate of the storage capacitor C1 coupled to it, and the first plate 152 is on the substrate 10
  • the orthographic projection of is located inside the orthographic projection of the second plate on the substrate 10.
  • each of the light-emitting detection circuits in the display substrate further includes a storage capacitor C1, which is coupled between the anode 172 and the cathode 170 of the PIN photodiode 17 for storing the PIN Type photodiode 17 converts the electrical signal.
  • the specific layout of the storage capacitor C1 can be selected according to actual needs.
  • the first electrode plate 152 of the storage capacitor C1 can be combined with the first electrode 151 and the second electrode 150 of the first control transistor T1.
  • the same layer and the same material are set; the cathode 170 of the PIN-type photodiode 17 is multiplexed as the second plate of the storage capacitor C1 coupled to it;
  • the process flow of the second electrode plate of the capacitor C1 also enables the first electrode plate 152 of the storage capacitor C1 to be formed in the same process as the first electrode 151 and the second electrode 150 of the first control transistor T1. Therefore, the manufacturing process flow of the storage capacitor C1 is well simplified, and the manufacturing cost of the display substrate is effectively saved.
  • the orthographic projection of the first electrode plate 152 on the substrate 10 can also be set to be located inside the orthographic projection of the second electrode plate on the substrate 10, so that not only the storage capacitor C1 is
  • the first electrode plate 152 and the second electrode plate can form a facing area in the direction perpendicular to the substrate 10, and also enable the storage capacitor C1 to be completely covered by the PIN photodiode 17, so that all
  • the storage capacitor C1 does not increase the occupied area of the luminescence detection circuit in the direction parallel to the substrate 10, thereby ensuring that in the direction parallel to the substrate 10, the occupancy area of the luminescence detection circuit is It includes the light-receiving area of the PIN-type photodiode 17.
  • the area of the cathode 170, the photoelectric conversion structure 171, and the anode 172 included in the PIN photodiode 17 in a direction parallel to the substrate 10 is approximately the same, and the cathode 170 is located on the substrate 10.
  • the projection, the orthographic projection of the photoelectric conversion structure 171 on the substrate 10 and the orthographic projection of the anode 172 on the substrate 10 basically coincide.
  • the light-receiving area of the PIN photodiode may be the area of the anode 172 in a direction parallel to the substrate 10 or the area of the photoelectric conversion structure 171 in a direction parallel to the substrate 10.
  • the display substrate further includes: a second sensing signal line SL2 and a second control signal line; the sub-pixel further includes an electrical detection circuit, and the electrical detection circuit includes a first Two control transistors, the first electrode of the second control transistor is coupled to the anode 180 of the light-emitting element, the second electrode of the second control transistor is coupled to the second sensing signal line SL2, the The gate of the second control transistor is coupled to the second control signal line; along the first direction, the electrical detection circuits in the same row multiplex the same second control signal line; along the first direction In both directions, the electrical detection circuits located in the same column multiplex the same second sensing signal line SL2.
  • the display substrate further includes a plurality of second sensing signal lines SL2 and a plurality of second control signal lines, each sub-pixel in the display substrate further includes an electrical detection circuit, and the electrical detection circuit may include multiple
  • the electrical detection circuit includes a second control transistor, the gate of the second control transistor is coupled to the second control signal line corresponding to the electrical detection circuit, and the first control transistor of the second control transistor One pole is coupled to the anode 180 of the light-emitting element, and the second pole of the second control transistor is coupled to the second sensing signal line SL2 corresponding to the electrical detection circuit.
  • the second sensing signal line SL2 writes a reset signal, and under the control of the second control signal input from the second control signal line, the second control transistor is turned on, and the reset signal is turned on. It is transmitted to the anode 180 of the light-emitting element to realize the reset of the light-emitting element.
  • the second control transistor In the sensing period, under the control of the second control signal input from the second control signal line, the second control transistor is turned on to transmit the voltage signal of the anode 180 of the light-emitting element to the second sensor.
  • the second sensing signal line SL2 transmits the voltage signal to the chip of the display substrate for subsequent electrical compensation.
  • the plurality of second sensing signal lines SL2 and the plurality of second control signal lines there are various specific layouts of the plurality of second sensing signal lines SL2 and the plurality of second control signal lines.
  • the electrical components located in the same row The detection circuit multiplexes the same second control signal line; along the second direction, the electrical detection circuits located in the same column multiplex the same second sensing signal line SL2; in this arrangement , A driving method similar to the gate line and data line in the display substrate can be adopted, the second control transistor is controlled row by row through the second control signal line to turn on, and when the second control transistor is turned on in a certain row, all
  • the reset signals transmitted by the plurality of second sensing signal lines SL2 are resetting the anodes 180 of the row of light-emitting elements, or the voltage signals of the anodes 180 of the row of light-emitting elements are transmitted to all through the plurality of second sensing signal lines SL2.
  • the chip of the display substrate is described.
  • the electrical detection circuits located in the same row along the first direction multiplex the same second control signal line, and along the second direction, the electrical detection circuits are located in the same column.
  • the electrical detection circuit multiplexes the same second sensing signal line SL2, so that the number of the second sensing signal line SL2 and the second control signal line provided in the display substrate is greatly reduced, Therefore, the complexity of the layout of the display substrate is reduced, and the resolution of the display substrate is further improved.
  • At least two adjacent columns of the electrical detection circuits multiplex the same second sensing signal line SL2.
  • the electrical detection circuits in four adjacent columns multiplex the same second sensing signal line SL2, and in the electrical detection circuits in the four adjacent columns, the electrical detection circuits located in the same row
  • the sub-pixels corresponding to the circuit can correspond to the red color group unit, the green color group unit, the blue color group unit, and the white color group unit one by one, so that 4 sub-pixels located in the same row constitute one pixel unit in the display substrate.
  • At least two adjacent rows of the electrical detection circuits are provided to multiplex the same second sensing signal line SL2, so that the number of the second sensing signal lines SL2 provided in the display substrate is further By reducing, the complexity of the layout of the display substrate is further reduced, and the resolution of the display substrate is improved.
  • the first sensing signal line SL1 and the second sensing signal line SL2 are alternately arranged, and the adjacent first sensing signal line SL1 and the second sensing signal line SL1 are arranged alternately. At least two rows of the sub-pixel rows are included between the two sensing signal lines SL2.
  • the first sensing signal line SL1 and the second sensing signal line SL2 both extend along the second direction, and the first sensing signal line is laid out.
  • the first sensing signal line SL1 and the second sensing signal line SL2 can be alternately arranged, and adjacent first sensing signal lines can be arranged
  • the display substrate further includes data lines (DR, DG, DB, and DW in FIG. 5) corresponding to each of the sub-pixel columns, each of which The data line and the sub-pixel driving circuit included in each sub-pixel in the corresponding sub-pixel column are respectively coupled; at least one column of the sub-pixels is included between the data line and the first sensing signal line SL1; the data line At least one column of the sub-pixels is included between the second sensing signal line SL2 and the second sensing signal line SL2.
  • data lines DR, DG, DB, and DW in FIG. 5
  • the display substrate further includes a data line corresponding to each sub-pixel column one-to-one, and the data line is used to provide a data signal to the sub-pixel driving circuit included in each sub-pixel in the corresponding sub-pixel column.
  • the sub-pixel driving circuit generates a driving signal for driving the light-emitting element to emit light based on the data signal.
  • At least one column of sub-pixels is included between the data line and the first sensing signal line SL1, and at least one column is included between the data line and the second sensing signal line SL2.
  • the sub-pixels enable the data line to be far away from the first sensing signal line SL1 and the second sensing signal line SL2, thereby avoiding the adjacent data line and the second sensing signal line SL2.
  • Crosstalk is generated between the first sensing signal line SL1, and crosstalk between the adjacent data line and the second sensing signal line SL2 is avoided, which effectively improves the working stability of the display substrate.
  • the first control transistor T1 includes an oxide thin film transistor.
  • the luminescence detection circuit has better detection performance. The performance is more conducive to improving the detection accuracy of the luminescence detection circuit.
  • the display substrate further includes a first flat layer 124, and the first flat layer 124 is located between the first control transistor T1 and the PIN photodiode 17 between.
  • the first control transistor T1 faces away from the surface of the substrate 10, there is a step difference. Therefore, in order to ensure the flatness of the PIN-type photodiode 17 produced subsequently, the first control transistor T1 and A first flat layer 124 is arranged between the PIN-type photodiodes 17, and the first flat layer 124 may be an organic insulating material SOG (Silicon On Glass, silicon-glass bonding structure material).
  • SOG Silicon On Glass, silicon-glass bonding structure material
  • the first flat layer 124 is fabricated on the side of the first control transistor T1 facing away from the substrate 10, and the PIN-type photodiode is fabricated on the side of the first flat layer 124 facing away from the substrate 10 17, so that the PIN-type photodiode 17 has a higher flatness, which is more conducive to the PIN-type photodiode 17 to achieve good working performance.
  • the embodiments of the present disclosure also provide a display device, including the display substrate provided in the above-mentioned embodiments.
  • the first control transistor T1 and the PIN photodiode 17 included in the light-emitting detection circuit in each sub-pixel are sequentially stacked in a direction away from the substrate 10, and the first control transistor is provided.
  • the orthographic projection of the transistor T1 on the substrate 10 at least partially overlaps the orthographic projection of the PIN-type photodiode 17 on the substrate 10, so that the PIN-type photodiode 17 can control the first transistor
  • At least part of T1 is shielded, which reduces the area occupied by the light-emitting detection circuit in a direction parallel to the substrate 10, thereby effectively increasing the aperture ratio of each sub-pixel.
  • the first control transistor T1 is disposed between the base 10 and the PIN photodiode 17, and the light-emitting element is disposed on the PIN photodiode 17.
  • the side facing away from the base 10 realizes that while increasing the aperture ratio of the display substrate, it ensures the light sensing accuracy of the PIN-type photodiode 17, which is more conducive to improving the uniformity of the brightness of the display substrate. Therefore, when the display device provided by the embodiment of the present disclosure includes the display substrate provided by the above-mentioned embodiment, it also has all the beneficial effects that the display substrate can achieve, and will not be repeated here.
  • the display device may be any product or component with a display function, such as a TV, a monitor, a digital photo frame, a mobile phone, a tablet computer, and the like.
  • the embodiments of the present disclosure also provide a manufacturing method of a display substrate for manufacturing the display substrate provided in the above-mentioned embodiments.
  • the manufacturing method includes a step of manufacturing a plurality of sub-pixels distributed in an array on the substrate 10, and the step specifically includes:
  • the PIN-type photodiodes 17 in each of the light-emitting detection circuits are fabricated on the side of the first control transistor T1 facing away from the substrate 10, and the first pole 151 of the first control transistor T1 corresponds to the PIN
  • the cathode 170 of the type photodiode 17 is coupled, and the orthographic projection of the first control transistor T1 on the substrate 10 at least partially overlaps the orthographic projection of the corresponding PIN-type photodiode 17 on the substrate 10 ;
  • a light-emitting element included in each sub-pixel is fabricated on the side of the PIN-type photodiode 17 facing away from the substrate 10, and the light-emitting element is coupled to the corresponding sub-pixel driving circuit.
  • the first control transistor T1 and the PIN-type photodiode 17 included in the light-emitting detection circuit in each sub-pixel are sequentially stacked in a direction away from the substrate 10, and
  • the orthographic projection of the first control transistor T1 on the substrate 10 is set to at least partially overlap with the orthographic projection of the PIN-type photodiode 17 on the substrate 10, so that the PIN-type photodiode 17 can be aligned with At least part of the first control transistor T1 is shielded, which reduces the area occupied by the light-emitting detection circuit in a direction parallel to the substrate 10, thereby effectively increasing the aperture ratio of each sub-pixel.
  • the first control transistor T1 is disposed between the base 10 and the PIN-type photodiode 17, and the light-emitting element is disposed on the substrate.
  • the PIN-type photodiode 17 faces away from the side of the substrate 10, which improves the aperture ratio of the display substrate while ensuring the accuracy of the PIN-type photodiode 17 for light sensing, which is more conducive to improving the The brightness uniformity of the display substrate is described.

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Abstract

本公开提供一种显示基板及其制作方法、显示装置。所述显示基板，包括基底以及阵列分布在该基底上的多个子像素，每个所述子像素均包括：发光元件，与该发光元件耦接的子像素驱动电路，以及用于检测该发光元件发光亮度的发光检测电路，所述发光检测电路包括：沿远离所述基底的方向依次层叠设置的第一控制晶体管和PIN型光电二极管，所述第一控制晶体管的第一极与所述PIN型光电二极管的阴极耦接，所述第一控制晶体管在所述基底上的正投影，与所述PIN型光电二极管在所述基底上的正投影至少部分交叠。本公开提供的显示基板用于显示。

Description

显示基板及其制作方法、显示装置
相关申请的交叉引用
本申请主张在2019年9月30日在中国提交的中国专利申请号No.201910941914.0的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其制作方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示基板以其低能耗、生产成本低、自发光、宽视角及响应速度快等优点，被广泛应用在手机、平板电脑、数码相机等显示领域。
发明内容
本公开的第一方面提供一种显示基板，包括基底以及阵列分布在该基底上的多个子像素，至少一个所述子像素均包括：发光元件，与该发光元件耦接的子像素驱动电路，以及用于检测该发光元件发光亮度的发光检测电路，所述发光检测电路包括：沿远离所述基底的方向依次层叠设置的第一控制晶体管和PIN型光电二极管，所述第一控制晶体管的第一极与所述PIN型光电二极管的阴极耦接，所述第一控制晶体管在所述基底上的正投影，与所述PIN型光电二极管在所述基底上的正投影至少部分交叠。
可选的，所述PIN型光电二极管包括沿远离所述基底的方向依次层叠设置的阴极、光电转换结构和阳极；
所述阴极采用遮光材料，所述第一控制晶体管在所述基底上的正投影，位于所述阴极在所述基底上的正投影的内部。
可选的，所述多个子像素分为阵列分布的多个子像素组，每个所述子像素组包括阵列分布的至少四个子像素，所述至少四个子像素位于相邻的两行，同一所述子像素组的子像素复用同一个所述发光检测电路；该发光检测电路中的所述PIN型光电二极管在所述基底上的正投影，分别与其对应的所述子像素组中各所述子像素包括的发光元件在所述基底上的正投影交叠。
可选的，所述显示基板还包括基准信号线、第一感测信号线和第一控制信号线，所述基准信号线与所述PIN型光电二极管的阳极耦接，所述第一感测信号线与所述第一控制晶体管的第二极耦接，所述第一控制信号线与所述第一控制晶体管的栅极耦接；
所述多个子像素包括多个子像素行和多个子像素列；每个所述子像素行均包括沿第一方向依次排列的多个所述子像素，每个所述子像素列均包括沿第二方向依次排列的多个所述子像素，所述第一方向与所述第二方向相交；
沿所述第一方向，位于同一行的所述发光检测电路复用同一条所述第一基准信号线和同一条所述控制信号线；
沿所述第二方向，位于同一列的所述发光检测电路复用同一条所述第一感测信号线。
可选的，所述基准信号线在所述基底上的正投影，与其耦接的各所述PIN型光电二极管在所述基底上的正投影均交叠。
可选的，所述基准信号线和所述PIN型光电二极管沿远离所述基底的方向依次层叠设置。可选的，所述第一控制信号线在所述基底上的正投影，与其耦接的各所述发光检测电路中的PIN型光电二极管在所述基底上的正投影均交叠。
可选的，所述第一控制信号线和所述PIN型光电二极管沿远离所述基底的方向依次层叠设置。
可选的，所述发光检测电路还包括存储电容，所述存储电容的第一极板与所述PIN光电二极管的阳极耦接，所述存储电容的第二极板与所述PIN光电二极管的阴极耦接；
所述第一极板与所述第一控制晶体管的第一极和第二极同层同材料设置；
所述PIN光电二极管的阴极复用为与其耦接的所述存储电容的第二极板， 所述第一极板在所述基底上的正投影，位于所述第二极板在所述基底上的正投影的内部。
可选的，所述显示基板还包括：第二感测信号线和第二控制信号线；
所述子像素还包括电学检测电路，所述电学检测电路包括第二控制晶体管，所述第二控制晶体管的第一极与所述发光元件的阳极耦接，所述第二控制晶体管的第二极与所述第二感测信号线耦接，所述第二控制晶体管的栅极与所述第二控制信号线耦接；
沿所述第一方向，位于同一行的所述电学检测电路复用同一条所述第二控制信号线；
沿所述第二方向，位于同一列的所述电学检测电路复用同一条所述第二感测信号线。
可选的，相邻的至少两列所述电学检测电路复用同一条所述第二感测信号线。
可选的，所述第一感测信号线和所述第二感测信号线交替设置，相邻的所述第一感测信号线和所述第二感测信号线之间包括至少两列所述子像素列。
可选的，所述显示基板还包括与各所述子像素列一一对应的数据线，每条所述数据线与其对应的子像素列中各子像素包括的子像素驱动电路分别耦接；
所述数据线与所述第一感测信号线之间包括至少一列所述子像素；
所述数据线与所述第二感测信号线之间包括至少一列所述子像素。
可选的，相邻的四列所述电学检测电路中，位于同一行的所述电学检测电路对应的子像素可组成像素单元，所述像素单元发出的光为白光。
可选的，每个所述子像素组包括阵列分布的八个子像素，所述八个子像素分别位于相邻的两行，所述八个子像素中位于同一行中的四个子像素组成显示基板中的一个像素单元，所述像素单元发出的光为白光。
可选的，所述第一控制晶体管包括氧化物薄膜晶体管。
可选的，所述显示基板还包括第一平坦层，所述第一平坦层位于所述第一控制晶体管和所述PIN型光电二极管之间。
基于上述显示基板的技术方案，本公开的第二方面提供了一种显示装置， 包括上述显示基板。
基于上述显示基板的技术方案，本公开的第三方面提供了一种显示基板的制作方法，用于制作上述显示基板，所述制作方法包括在基底上制作阵列分布的多个子像素的步骤，该步骤具体包括：
在基底上制作各子像素包括的子像素驱动电路和发光检测电路中的第一控制晶体管；
在所述第一控制晶体管背向所述基底的一侧制作各所述发光检测电路中的PIN型光电二极管，所述第一控制晶体管的第一极与对应的所述PIN型光电二极管的阴极耦接，所述第一控制晶体管在所述基底上的正投影，与对应的所述PIN型光电二极管在所述基底上的正投影至少部分交叠；
在所述PIN型光电二极管背向所述基底的一侧制作各子像素包括的发光元件，所述发光元件与对应的所述子像素驱动电路耦接。
可选的，在所述第一控制晶体管和所述PIN型光电二极管之间形成第一平坦层。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的发光检测元件的第一截面示意图；
图2为本公开实施例提供的发光检测元件的第二截面示意图；
图3为本公开实施例提供的发光检测元件的俯视示意图；
图4为本公开实施例提供的发光检测元件的结构示意图；
图5为本公开实施例提供的显示基板的俯视示意图。
具体实施方式
为了进一步说明本公开实施例提供的显示基板及其制作方法、显示装置，下面结合说明书附图进行详细描述。
OLED显示基板包括阵列分布的多个子像素，每个子像素包括耦接的子 像素驱动电路和发光元件，工作时，子像素驱动电路为对应的发光元件提供驱动电流，以驱动发光元件发出对应颜色的光。由于OLED显示基板在使用过程中，发光元件的发光亮度会变化，为了改善发光元件发光亮度变化对显示效果的不利影响，一般会在子像素中设置对发光元件发出的光的亮度进行检测的发光检测电路，该发光检测电路主要包括检测开关晶体管和PIN型光电二极管，在利用发光检测电路对发光元件发出的光的强度进行检测时，PIN型光电二极管接收发光元件发出的光，并将接收的光转换为电信号，以实现通过转换后的电信号对发光元件发光进行补偿。
在实际应用中，为了保证较高的补偿精度和信噪比，PIN型光电二极管的面积一般较大，但是设置PIN型光电二极管面积较大，会导致发光检测电路整体占用面积较大，进而导致显示基板的开口率降低。
请参阅图1-图3，本公开实施例提供了一种显示基板，包括基底10以及阵列分布在该基底10上的多个子像素，每个所述子像素均包括：发光元件，与该发光元件耦接的子像素驱动电路，以及用于检测该发光元件发光亮度的发光检测电路，所述发光检测电路包括：沿远离所述基底10的方向依次层叠设置的第一控制晶体管T1和PIN型光电二极管17，所述第一控制晶体管T1的第一极151与所述PIN型光电二极管17的阴极170耦接，所述第一控制晶体管T1在所述基底10上的正投影，与所述PIN型光电二极管17在所述基底10上的正投影至少部分交叠。
具体地，所述显示基板中的基底10可包括玻璃基底10，但不限于此。所述显示基板中各子像素包括的发光元件的发光颜色均可根据实际需要设置，示例性的，可设置所述显示基板中各子像素包括的发光元件均发白光，在这种情况下，可设置所述显示基板还包括彩膜结构，所述彩膜结构可包括至少三种颜色的色阻图形，例如：红色色阻图形、绿色色阻图形和蓝色色阻图形，将所述色阻图形与所述发光元件一一对应，使得所述发光元件发出的光能够穿过其对应的色阻图形后射出所述显示基板，从而实现所述显示基板的显示功能。
另外值得注意，可设置位于同一列的子像素对应同种颜色的色阻图形，如图5所示，从左边起第一列子像素对应红色色阻图形，对应的数据线为DR， 第一列子像素发出的光为红光；第二列子像素对应绿色色阻图形，对应的数据线为DG，第二列子像素发出的光为绿光；第三列子像素对应蓝色色阻图形，对应的数据线为DB，第三列子像素发出的光为蓝光；第四列子像素对应白色色阻图形，对应的数据线为DW，第四列子像素发出的光为白光。
所述显示基板中，每个子像素还包括子像素驱动电路和发光检测电路，所述子像素驱动电路和所述发光检测电路的位置布局可根据实际需要设置，示例性的，如图5所示，在每个所述子像素中，所述子像素驱动电路的第一布局区域20和所述发光检测电路的第二布局区域22相对设置，所述子像素的开口区21位于所述子像素驱动电路的第一布局区域20和所述发光检测电路的第二布局区域22之间。
所述子像素驱动电路可包括至少一个驱动薄膜晶体管和多个开关薄膜晶体管，这些薄膜晶体管相互配合工作，使所述驱动薄膜晶体管产生驱动信号并传输至对应的发光元件，以驱动对应的发光元件实现发光功能。
所述发光检测电路包括所述第一控制晶体管T1和所述PIN型光电二极管17，所述第一控制晶体管T1的第一极151与所述PIN型光电二极管17的阴极170耦接，在布局所述发光检测电路时，本公开实施例将所述第一控制晶体管T1和所述PIN型光电二极管17层叠设置，并将所述第一控制晶体管T1设置在所述基底10与所述PIN型光电二极管17之间，使得所述第一控制晶体管T1在所述基底10上的正投影，与所述PIN型光电二极管17在所述基底10上的正投影至少部分交叠，这样在垂直于所述基底10的方向上，所述PIN型光电二极管17能够对所述第一控制晶体管T1的至少部分进行遮挡。
需要说明，本公开实施例提供的显示基板可选为底发射，即从所述显示基板的基底10所在一侧出光，所述显示基板在布局所述第一控制晶体管T1和所述PIN型光电二极管17时，采用了类似顶发射的技术，即将所述第一控制晶体管T1设置在所述基底10和所述PIN型光电二极管17之间。另外，如图1所示，所述显示基板中还包括遮光层11、缓冲层120、第一绝缘层121、第一钝化层122、第二钝化层123、第二平坦层125、栅极绝缘层126和像素界定层PDL；所述第一控制晶体管T1还包括有源层13和栅极图形14；所述 发光元件包括发光元件的阳极180，发光元件的阴极19和有机发光材料层EL。
所述发光检测电路在工作时，PIN型光电二极管17接收其对应的发光元件发出的光线，并将其转化为电信号后，经所述第一控制晶体管T1传输至所述显示基板的芯片，该芯片基于所述电信号对所述显示基板中发光元件的发光亮度进行补偿，从而实现所述显示基板的显示亮度均一性。
根据上述显示基板的具体结构可知，本公开实施例提供的显示基板中，将各子像素中发光检测电路包括的第一控制晶体管T1和PIN型光电二极管17，沿远离所述基底10的方向依次层叠设置，并设置所述第一控制晶体管T1在所述基底10上的正投影，与所述PIN型光电二极管17在所述基底10上的正投影至少部分交叠，使得所述PIN型光电二极管17能够对所述第一控制晶体管T1的至少部分进行遮挡，减小了所述发光检测电路在平行于所述基底10的方向上占用的面积，从而有效提升了各子像素的开口率。而且，本公开实施例提供的显示基板中，将所述第一控制晶体管T1设置在所述基底10和所述PIN型光电二极管17之间，将所述发光元件设置在所述PIN型光电二极管17背向所述基底10的一侧，实现了在提升所述显示基板的开口率的同时，保证了PIN型光电二极管17对光线的感测精度，从而更有利于提升所述显示基板的亮度均一性。
在一些实施例中，所述PIN型光电二极管17包括沿远离所述基底10的方向依次层叠设置的阴极170、光电转换结构171和阳极172；所述阴极170采用遮光材料，所述第一控制晶体管T1在所述基底10上的正投影，位于所述阴极170在所述基底10上的正投影的内部。
具体地，所述PIN型光电二极管17的阴极170选用遮光材料，具体可选用具有遮光性能的金属材料，所述PIN型光电二极管17的阳极172选用透光材料，具体可选用氧化铟锡材料，但不仅限于此。
所述光电转换结构171具体包括：PN结和在该PN结中间掺入的一层浓度很低的I型半导体，由于掺入的I型半导体浓度低，近乎本征(Intrinsic)半导体，因此也可称为I层，在I层两侧是掺杂浓度很高的P型半导体和N型半导体，即形成为P层和N层，P层和N层很薄，吸收入射光的比例很小，使得绝大部分的入射光在I层内被吸收并产生大量的电子-空穴对，而I层较 厚，几乎占据了整个耗尽区，从而可实现通过增大耗尽区的宽度，达到减小扩散运动的影响，提高光电二极管响应速度的目的。
上述实施例中，通过设置所述阳极采用透光材料，使得PIN型光电二极管17能够很好的接收对应的发光元件发出的光线，从而保证了所述发光检测电路的检测精度。而且，上述实施例中，通过设置所述阴极采用遮光材料，以及所述第一控制晶体管T1在所述基底10上的正投影，位于所述阴极在所述基底10上的正投影的内部，使得所述第一控制晶体管T1完全被所述PIN型光电二极管17覆盖，这样不仅最大限度的缩小了所述发光检测电路在平行于所述基底10的方向上占用的面积，使得所述发光检测电路在平行于所述基底10的方向上占用的面积仅为所述PIN型光电二极管17占用的面积，而且，避免了所述第一控制晶体管T1受光照的影响，保证了所述发光检测电路较小的暗电流(即所述第一控制晶体管T1在关态下的电流)，进而有效提升了所述发光检测电路的信噪比。
如图5所示，在一些实施例中，所述多个子像素分为阵列分布的多个子像素组，每个所述子像素组包括阵列分布的至少四个子像素，所述至少四个子像素位于相邻的两行，同一所述子像素组的子像素复用同一个所述发光检测电路；该发光检测电路中的所述PIN型光电二极管17在所述基底10上的正投影，分别与其对应的所述子像素组中各所述子像素包括的发光元件在所述基底10上的正投影交叠。
具体地，所述显示基板中，可将所述多个子像素划分为多个子像素组，所述多个子像素组呈阵列分布，且每个所述子像素组中包括阵列分布、且相邻设置的至少四个子像素，所述至少四个子像素可位于相邻的两行；示例性的，所述子像素组包括8个子像素，所述8个子像素包括位于同一行的4个子像素，以及位于相邻的下一行的4个子像素。更详细地说，所述位于同一行的4个子像素可一一对应红色色组单元、绿色色组单元、蓝色色组单元和白色色组单元，使得所述位于同一行的4个子像素组成所述显示基板中的一个像素单元。同样的，所述位于相邻的下一行的4个子像素也可一一对应红色色组单元、绿色色组单元、蓝色色组单元和白色色组单元，使得所述位于相邻的下一行的4个子像素也组成所述显示基板中的一个像素单元。
上述实施例提供的显示基板中，设置同一所述子像素组的子像素复用同一个所述发光检测电路时，可设置该发光检测电路中的所述PIN型光电二极管17在所述基底10上的正投影，分别与其对应的所述子像素组中各所述子像素包括的发光元件在所述基底10上的正投影交叠，这样该发光检测电路就能够接收其对应的子像素组中各子像素包括的发光元件所发出的光线，从而实现对其对应的子像素组中各子像素包括的发光元件进行发光检测。
上述实施例提供的显示基板中，设置同一所述子像素组的子像素复用同一个所述发光检测电路，使得所述显示基板中，所述发光检测电路占用的面积进一步缩小，从而更有利于提升所述显示基板的开口率。
而且，设置同一所述子像素组的子像素复用同一个所述发光检测电路，还减少了所述显示基板中，包括的所述发光检测电路中所述PIN型光电二极管17的顶点数，从而进一步减小了所述发光检测电路的暗电流。更详细地说，以一个所述PIN型光电二极管17在所述基底10上的正投影为四边形(即对应4个顶点)为例，当所述8个子像素共用一个所述发光检测电路时，则该8个子像素对应一个PIN型光电二极管17，即对应4个顶点，而当所述8个子像素对应8个PIN型光电二极管17时，则该8个子像素对应32个顶点。
如图3和图4所示，上述实施例提供的显示基板还包括基准信号线REF、第一感测信号线SL1和第一控制信号线G1，所述基准信号线REF与所述PIN型光电二极管17的阳极172通过过孔via0耦接，所述第一感测信号线SL1与所述第一控制晶体管T1的第二极150耦接，所述第一控制信号线G1与所述第一控制晶体管T1的栅极耦接；所述第一控制晶体管T1的第一极151通过图3中的虚线框图形与所述PIN型光电二极管17的阴极170耦接。
如图5所示，所述多个子像素包括多个子像素行和多个子像素列；每个所述子像素行均包括沿第一方向依次排列的多个所述子像素，每个所述子像素列均包括沿第二方向依次排列的多个所述子像素，所述第一方向与所述第二方向相交；沿所述第一方向，位于同一行的所述发光检测电路复用同一条所述基准信号线REF和同一条所述第一控制信号线G1；沿所述第二方向，位于同一列的所述发光检测电路复用同一条所述第一感测信号线SL1。
具体地，所述显示基板包括的所述多个子像素呈阵列分布，所述多个子 像素可划分为多个子像素行，也可划分为多个子像素列；其中每个所述子像素行均包括沿第一方向依次排列的多个所述子像素，每个所述子像素列均包括沿第二方向依次排列的多个所述子像素，所述第一方向可与所述第二方向相交，示例性的，所述第一方向与所述第二方向垂直。
所述显示基板还包括多条基准信号线REF，多条第一感测信号线SL1和多条第一控制信号线G1，所述显示基板中包括的每个所述发光检测电路中，所述PIN型光电二极管17的阳极172与该发光检测电路对应的基准信号线REF耦接，所述第一控制晶体管T1的第二极150与该发光检测电路对应的第一感测信号线SL1耦接，所述第一控制晶体管T1的栅极与该发光检测电路对应的第一控制信号线G1耦接。
值得注意，所述多条基准信号线REF，所述多条第一感测信号线SL1和所述多条第一控制信号线G1的具体布局方式多种多样，示例性的，如图5所示，可将沿所述第一方向，位于同一行的所述发光检测电路复用同一条所述基准信号线REF和同一条所述第一控制信号线G1；沿所述第二方向，位于同一列的所述发光检测电路复用同一条所述第一感测信号线SL1；在这种设置方式下，可采用类似显示基板中栅线和数据线的驱动方式，通过所述第一控制信号线G1逐行控制所述第一控制晶体管T1开启，且在某一行所述第一控制晶体管T1开启时，通过所述多条第一感测信号线SL1传输该行PIN型光电二极管17感测到的感测信号。
需要说明，上述设置方式适用于多个子像素复用一个所述发光检测电路的情况，以及每个子像素包括单独的所述发光检测电路的情况。
上述实施例提供的显示基板中，通过设置沿所述第一方向，位于同一行的所述发光检测电路复用同一条所述基准信号线REF和同一条所述第一控制信号线G1，以及设置沿所述第二方向，位于同一列的所述发光检测电路复用同一条所述第一感测信号线SL1，使得所述显示基板中设置的所述基准信号线REF，所述第一感测信号线SL1和所述第一控制信号线G1的数量大大减少，从而降低了所述显示基板布局的复杂程度，进一步提升了所述显示基板的分辨率。
如图3和图5所示，在一些实施例中，可设置所述基准信号线REF在所 述基底10上的正投影，与其耦接的各所述PIN型光电二极管17在所述基底10上的正投影均交叠；和/或，所述第一控制信号线G1在所述基底10上的正投影，与其耦接的各所述发光检测电路中的PIN型光电二极管17在所述基底10上的正投影均交叠。
具体地，当沿所述第一方向，位于同一行的所述发光检测电路复用同一条所述基准信号线REF和同一条所述第一控制信号线G1，沿所述第二方向，位于同一列的所述发光检测电路复用同一条所述第一感测信号线SL1时，所述基准信号线REF和所述第一控制信号线G1均沿所述第一方向延伸，所述第一感测信号线SL1沿所述第二方向延伸。
值得注意，所述基准信号线REF和所述第一控制信号线G1的具体布局方式可根据实际需要设置，只需满足所述基准信号线REF能够分别与其对应的一行发光检测电路中的各PIN型光电二极管17的阳极172耦接，所述第一控制信号线G1能够分别与其对应的一行发光检测电路中的各第一控制晶体管T1的栅极耦接即可；示例性的，设置所述基准信号线REF在所述基底10上的正投影，与其耦接的各所述PIN型光电二极管17在所述基底10上的正投影均交叠；和/或，所述第一控制信号线G1在所述基底10上的正投影，与其耦接的各所述发光检测电路中的PIN型光电二极管17在所述基底10上的正投影均交叠；这种设置方式使得所述基准信号线REF和/或所述第一控制信号线G1，能够在垂直于所述基底10的方向上，与上述PIN型光电二极管17交叠，在保证各所述发光检测电路正常工作的同时，更有利于提升所述显示基板的开口率。
进一步地，可将所述基准信号线REF和所述第一控制信号线G1均设置在所述基底10和所述PIN型光电二极管之间，以避免所述基准信号线REF和所述第一控制信号线G1对所述PIN型光电二极管的受光面产生遮挡。
如图1、图2和图4所示，在一些实施例中，所述发光检测电路还包括存储电容C1，所述存储电容C1的第一极板152与所述PIN型光电二极管17的阳极172耦接，所述存储电容C1的第二极板与所述PIN型光电二极管17的阴极170耦接；所述第一极板152与所述第一控制晶体管T1的第一极151和第二极150同层同材料设置；所述PIN型光电二极管17的阴极170复用为 与其耦接的所述存储电容C1的第二极板，所述第一极板152在所述基底10上的正投影，位于所述第二极板在所述基底10上的正投影的内部。
具体地，所述显示基板中的各所述发光检测电路还包括存储电容C1，该存储电容C1耦接在所述PIN型光电二极管17的阳极172和阴极170之间，用于存储所述PIN型光电二极管17转换得到的电信号。
所述存储电容C1的具体布局方式可根据实际需要选择，示例性的，可将所述存储电容C1的第一极板152与所述第一控制晶体管T1的第一极151和第二极150同层同材料设置；将所述PIN型光电二极管17的阴极170复用为与其耦接的所述存储电容C1的第二极板；这种设置方式不仅避免了增加专门用于制作所述存储电容C1的第二极板的工艺流程，还使得所述存储电容C1的第一极板152能够与所述第一控制晶体管T1的第一极151和第二极150在同一次工艺中形成，从而很好的简化了所述存储电容C1的制作工艺流程，有效节约了所述显示基板的制作成本。另外，还可设置所述第一极板152在所述基底10上的正投影，位于所述第二极板在所述基底10上的正投影的内部，这样不仅使得所述存储电容C1的第一极板152和第二极板之间在垂直于所述基底10的方向上，能够形成正对面积，还使得所述存储电容C1能够完全被所述PIN型光电二极管17覆盖，使得所述存储电容C1不会增加所述发光检测电路在平行于所述基底10的方向上的占用面积，从而保证了在平行于所述基底10的方向上，所述发光检测电路的占用面积即为其包括的PIN型光电二极管17的受光面积。
需要说明，所述PIN型光电二极管17包括的阴极170、光电转换结构171和阳极172在平行于所述基底10的方向上的面积大致相同，且所述阴极170在所述基底10上的正投影、所述光电转换结构171在所述基底10上的正投影和所述阳极172在所述基底10上的正投影基本重合。所述PIN型光电二极管的受光面积可为所述阳极172在平行于所述基底10的方向上的面积，或者所述光电转换结构171在平行于所述基底10的方向上的面积。
如图5所示，在一些实施例中，所述显示基板还包括：第二感测信号线SL2和第二控制信号线；所述子像素还包括电学检测电路，所述电学检测电路包括第二控制晶体管，所述第二控制晶体管的第一极与所述发光元件的阳 极180耦接，所述第二控制晶体管的第二极与所述第二感测信号线SL2耦接，所述第二控制晶体管的栅极与所述第二控制信号线耦接；沿所述第一方向，位于同一行的所述电学检测电路复用同一条所述第二控制信号线；沿所述第二方向，位于同一列的所述电学检测电路复用同一条所述第二感测信号线SL2。
具体地，所述显示基板还包括多条第二感测信号线SL2和多条第二控制信号线，所述显示基板中的各子像素还包括电学检测电路，所述电学检测电路可包括多种结构，示例性的，所述电学检测电路包括第二控制晶体管，该第二控制晶体管的栅极与所述电学检测电路对应的第二控制信号线耦接，所述第二控制晶体管的第一极与所述发光元件的阳极180耦接，所述第二控制晶体管的第二极与所述电学检测电路对应的第二感测信号线SL2耦接，所述电学检测电路的具体工作过程如下：
在复位时段，所述第二感测信号线SL2写入复位信号，在所述第二控制信号线输入的第二控制信号的控制下，所述第二控制晶体管导通，将所述复位信号传输至所述发光元件的阳极180，实现对所述发光元件的复位。
在感测时段，在所述第二控制信号线输入的第二控制信号的控制下，所述第二控制晶体管导通，将所述发光元件的阳极180的电压信号传输至所述第二感测信号线SL2，并由所述第二感测信号线SL2将该电压信号传输至所述显示基板的芯片中，以供后续电学补偿使用。
值得注意，所述多条第二感测信号线SL2和所述多条第二控制信号线的具体布局方式多种多样，示例性的，沿所述第一方向，位于同一行的所述电学检测电路复用同一条所述第二控制信号线；沿所述第二方向，位于同一列的所述电学检测电路复用同一条所述第二感测信号线SL2；在这种设置方式下，可采用类似显示基板中栅线和数据线的驱动方式，通过所述第二控制信号线逐行控制所述第二控制晶体管开启，且在某一行所述第二控制晶体管开启时，通过所述多条第二感测信号线SL2传输的复位信号为该行发光元件的阳极180复位，或者通过所述多条第二感测信号线SL2传输该行发光元件的阳极180的电压信号至所述显示基板的芯片。
上述实施例提供的显示基板中，通过设置沿所述第一方向，位于同一行 的所述电学检测电路复用同一条所述第二控制信号线，以及沿所述第二方向，位于同一列的所述电学检测电路复用同一条所述第二感测信号线SL2，使得所述显示基板中设置的所述第二感测信号线SL2和所述第二控制信号线的数量大大减少，从而降低了所述显示基板布局的复杂程度，进一步提升了所述显示基板的分辨率。
在一些实施例中，相邻的至少两列所述电学检测电路复用同一条所述第二感测信号线SL2。
示例性的，相邻的四列所述电学检测电路复用同一条所述第二感测信号线SL2，在该相邻的四列所述电学检测电路中，位于同一行的所述电学检测电路对应的子像素可一一对应红色色组单元、绿色色组单元、蓝色色组单元和白色色组单元，使得位于同一行的4个子像素组成所述显示基板中的一个像素单元。
上述实施例中设置相邻的至少两列所述电学检测电路复用同一条所述第二感测信号线SL2，使得所述显示基板中设置的所述第二感测信号线SL2的数量进一步减少，从而进一步降低了所述显示基板布局的复杂程度，提升了所述显示基板的分辨率。
如图5所示，在一些实施例中，所述第一感测信号线SL1和所述第二感测信号线SL2交替设置，相邻的所述第一感测信号线SL1和所述第二感测信号线SL2之间包括至少两列所述子像素列。
具体地，上述实施例提供的显示基板中，所述第一感测信号线SL1和所述第二感测信号线SL2均沿所述第二方向延伸，在布局所述第一感测信号线SL1和所述第二感测信号线SL2时，可将所述第一感测信号线SL1和所述第二感测信号线SL2交替设置，并设置相邻的所述第一感测信号线SL1和所述第二感测信号线SL2之间包括至少两列所述子像素列，这种设置方式使得所述第一感测信号线SL1和所述第二感测信号线SL2之间保持较大的距离，从而很好的避免了相邻的所述第一感测信号线SL1和所述第二感测信号线SL2之间产生串扰，有效提升了所述发光检测电路和所述电学检测电路的信噪比。
如图5所示，在一些实施例中，所述显示基板还包括与各所述子像素列一一对应的数据线(如图5中的DR、DG、DB和DW)，每条所述数据线与 其对应的子像素列中各子像素包括的子像素驱动电路分别耦接；所述数据线与所述第一感测信号线SL1之间包括至少一列所述子像素；所述数据线与所述第二感测信号线SL2之间包括至少一列所述子像素。
具体地，所述显示基板还包括与各所述子像素列一一对应的数据线，该数据线用于为其对应的子像素列中各子像素包括的子像素驱动电路提供数据信号，以使所述子像素驱动电路基于该数据信号产生驱动发光元件发光的驱动信号。
上述实施例通过设置所述数据线与所述第一感测信号线SL1之间包括至少一列所述子像素，以及所述数据线与所述第二感测信号线SL2之间包括至少一列所述子像素，使得所述数据线能够与所述第一感测信号线SL1和所述第二感测信号线SL2均相距较远，从而很好的避免了相邻的所述数据线和所述第一感测信号线SL1之间产生串扰，以及避免了相邻的所述数据线和所述第二感测信号线SL2之间产生串扰，有效提升了所述显示基板的工作稳定性。
在一些实施例中，可设置所述第一控制晶体管T1包括氧化物薄膜晶体管。
具体地，由于氧化物薄膜晶体管具有迁移率高、大面积均匀性好等优点，因此，当设置所述第一控制晶体管T1包括氧化物薄膜晶体管时，使得所述发光检测电路具有更好的检测性能，更有利于提升所述发光检测电路的检测准确性。
如图1和图2所示，在一些实施例中，所述显示基板还包括第一平坦层124，所述第一平坦层124位于所述第一控制晶体管T1和所述PIN型光电二极管17之间。
具体地，由于所述第一控制晶体管T1背向所述基底10的表面存在段差，因此，为了保证后续制作的所述PIN型光电二极管17的平坦性，可在所述第一控制晶体管T1和所述PIN型光电二极管17之间设置第一平坦层124，该第一平坦层124可采用有机绝缘材料SOG(Silicon On Glass，硅-玻璃键合结构材料)。
上述在所述第一控制晶体管T1背向所述基底10的一侧制作第一平坦层124，并在所述第一平坦层124背向所述基底10的一侧制作所述PIN型光电 二极管17，使得所述PIN型光电二极管17具有较高的平坦度，从而更有利于所述PIN型光电二极管17实现良好的工作性能。
本公开实施例还提供了一种显示装置，包括上述实施例提供的显示基板。
上述实施例提供的显示基板中，将各子像素中发光检测电路包括的第一控制晶体管T1和PIN型光电二极管17，沿远离所述基底10的方向依次层叠设置，并设置所述第一控制晶体管T1在所述基底10上的正投影，与所述PIN型光电二极管17在所述基底10上的正投影至少部分交叠，使得所述PIN型光电二极管17能够对所述第一控制晶体管T1的至少部分进行遮挡，减小了所述发光检测电路在平行于所述基底10的方向上占用的面积，从而有效提升了各子像素的开口率。而且，上述实施例提供的显示基板中，将所述第一控制晶体管T1设置在所述基底10和所述PIN型光电二极管17之间，将所述发光元件设置在所述PIN型光电二极管17背向所述基底10的一侧，实现了在提升所述显示基板的开口率的同时，保证了PIN型光电二极管17对光线的感测精度，从而更有利于提升所述显示基板的亮度均一性；因此，本公开实施例提供的显示装置在包括上述实施例提供的显示基板时，同样具有该显示基板所能够实现的全部有益效果，此处不再赘述。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
本公开实施例还提供了一种显示基板的制作方法，用于制作上述实施例提供的显示基板，所述制作方法包括在基底10上制作阵列分布的多个子像素的步骤，该步骤具体包括：
在基底10上制作各子像素包括的子像素驱动电路和发光检测电路中的第一控制晶体管T1；
在所述第一控制晶体管T1背向所述基底10的一侧制作各所述发光检测电路中的PIN型光电二极管17，所述第一控制晶体管T1的第一极151与对应的所述PIN型光电二极管17的阴极170耦接，所述第一控制晶体管T1在所述基底10上的正投影，与对应的所述PIN型光电二极管17在所述基底10上的正投影至少部分交叠；
在所述PIN型光电二极管17背向所述基底10的一侧制作各子像素包括 的发光元件，所述发光元件与对应的所述子像素驱动电路耦接。
采用本公开实施例提供的制作方法制作的显示基板中，将各子像素中发光检测电路包括的第一控制晶体管T1和PIN型光电二极管17，沿远离所述基底10的方向依次层叠设置，并设置所述第一控制晶体管T1在所述基底10上的正投影，与所述PIN型光电二极管17在所述基底10上的正投影至少部分交叠，使得所述PIN型光电二极管17能够对所述第一控制晶体管T1的至少部分进行遮挡，减小了所述发光检测电路在平行于所述基底10的方向上占用的面积，从而有效提升了各子像素的开口率。而且，采用本公开实施例提供的制作方法制作的显示基板中，将所述第一控制晶体管T1设置在所述基底10和所述PIN型光电二极管17之间，将所述发光元件设置在所述PIN型光电二极管17背向所述基底10的一侧，实现了在提升所述显示基板的开口率的同时，保证了PIN型光电二极管17对光线的感测精度，从而更有利于提升所述显示基板的亮度均一性。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

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  1. 一种显示基板，包括基底以及阵列分布在该基底上的多个子像素，至少一个所述子像素均包括：发光元件，与该发光元件耦接的子像素驱动电路，以及用于检测该发光元件发光亮度的发光检测电路，所述发光检测电路包括：沿远离所述基底的方向依次层叠设置的第一控制晶体管和PIN型光电二极管，所述第一控制晶体管的第一极与所述PIN型光电二极管的阴极耦接，所述第一控制晶体管在所述基底上的正投影，与所述PIN型光电二极管在所述基底上的正投影至少部分交叠。
  2. 根据权利要求1所述的显示基板，其中，所述PIN型光电二极管包括沿远离所述基底的方向依次层叠设置的阴极、光电转换结构和阳极；
    所述阴极采用遮光材料，所述第一控制晶体管在所述基底上的正投影，位于所述阴极在所述基底上的正投影的内部。
  3. 根据权利要求2所述的显示基板，其中，所述多个子像素分为阵列分布的多个子像素组，每个所述子像素组包括阵列分布的至少四个子像素，所述至少四个子像素位于相邻的两行，同一所述子像素组的子像素复用同一个所述发光检测电路；该发光检测电路中的所述PIN型光电二极管在所述基底上的正投影，分别与其对应的所述子像素组中各所述子像素包括的发光元件在所述基底上的正投影交叠。
  4. 根据权利要求3所述的显示基板，其中，
    所述显示基板还包括基准信号线、第一感测信号线和第一控制信号线，所述基准信号线与所述PIN型光电二极管的阳极耦接，所述第一感测信号线与所述第一控制晶体管的第二极耦接，所述第一控制信号线与所述第一控制晶体管的栅极耦接；
    所述多个子像素包括多个子像素行和多个子像素列；每个所述子像素行均包括沿第一方向依次排列的多个所述子像素，每个所述子像素列均包括沿第二方向依次排列的多个所述子像素，所述第一方向与所述第二方向相交；
    沿所述第一方向，位于同一行的所述发光检测电路复用同一条所述基准信号线和同一条所述第一控制信号线；
    沿所述第二方向，位于同一列的所述发光检测电路复用同一条所述第一感测信号线。
  5. 根据权利要求4所述的显示基板，其中，
    所述基准信号线在所述基底上的正投影，与其耦接的各所述PIN型光电二极管在所述基底上的正投影均交叠。
  6. 根据权利要求5所述的显示基板，其中，所述基准信号线和所述PIN型光电二极管沿远离所述基底的方向依次层叠设置。
  7. 根据权利要求4所述的显示基板，其中，所述第一控制信号线在所述基底上的正投影，与其耦接的各所述发光检测电路中的PIN型光电二极管在所述基底上的正投影均交叠。
  8. 根据权利要求7所述的显示基板，其中，所述第一控制信号线和所述PIN型光电二极管沿远离所述基底的方向依次层叠设置。
  9. 根据权利要求4所述的显示基板，其中，所述发光检测电路还包括存储电容，所述存储电容的第一极板与所述PIN光电二极管的阳极耦接，所述存储电容的第二极板与所述PIN光电二极管的阴极耦接；
    所述第一极板与所述第一控制晶体管的第一极和第二极同层同材料设置；
    所述PIN光电二极管的阴极复用为与其耦接的所述存储电容的第二极板，所述第一极板在所述基底上的正投影，位于所述第二极板在所述基底上的正投影的内部。
  10. 根据权利要求4所述的显示基板，其中，所述显示基板还包括：第二感测信号线和第二控制信号线；
    所述子像素还包括电学检测电路，所述电学检测电路包括第二控制晶体管，所述第二控制晶体管的第一极与所述发光元件的阳极耦接，所述第二控制晶体管的第二极与所述第二感测信号线耦接，所述第二控制晶体管的栅极与所述第二控制信号线耦接；
    沿所述第一方向，位于同一行的所述电学检测电路复用同一条所述第二控制信号线；
    沿所述第二方向，位于同一列的所述电学检测电路复用同一条所述第二感测信号线。
  11. 根据权利要求10所述的显示基板，其中，相邻的至少两列所述电学检测电路复用同一条所述第二感测信号线。
  12. 根据权利要求11所述的显示基板，其中，所述第一感测信号线和所述第二感测信号线交替设置，相邻的所述第一感测信号线和所述第二感测信号线之间包括至少两列所述子像素列。
  13. 根据权利要求12所述的显示基板，其中，所述显示基板还包括与各所述子像素列一一对应的数据线，每条所述数据线与其对应的子像素列中各子像素包括的子像素驱动电路分别耦接；
    所述数据线与所述第一感测信号线之间包括至少一列所述子像素；
    所述数据线与所述第二感测信号线之间包括至少一列所述子像素。
  14. 根据权利要求13所述的显示基板，其中，相邻的四列所述电学检测电路中，位于同一行的所述电学检测电路对应的子像素可组成像素单元，所述像素单元发出的光为白光。
  15. 根据权利要求3所述的显示基板，其中，每个所述子像素组包括阵列分布的八个子像素，所述八个子像素分别位于相邻的两行，所述八个子像素中位于同一行中的四个子像素组成显示基板中的一个像素单元，所述像素单元发出的光为白光。
  16. 根据权利要求1所述的显示基板，其中，所述第一控制晶体管包括氧化物薄膜晶体管。
  17. 根据权利要求1所述的显示基板，其中，所述显示基板还包括第一平坦层，所述第一平坦层位于所述第一控制晶体管和所述PIN型光电二极管之间。
  18. 一种显示装置，包括如权利要求1～17中任一项所述的显示基板。
  19. 一种显示基板的制作方法，用于制作如权利要求1～17中任一项所述的显示基板，所述制作方法包括在基底上制作阵列分布的多个子像素的步骤，该步骤具体包括：
    在基底上制作各子像素包括的子像素驱动电路和发光检测电路中的第一控制晶体管；
    在所述第一控制晶体管背向所述基底的一侧制作各所述发光检测电路中 的PIN型光电二极管，所述第一控制晶体管的第一极与对应的所述PIN型光电二极管的阴极耦接，所述第一控制晶体管在所述基底上的正投影，与对应的所述PIN型光电二极管在所述基底上的正投影至少部分交叠；
    在所述PIN型光电二极管背向所述基底的一侧制作各子像素包括的发光元件，所述发光元件与对应的所述子像素驱动电路耦接。
  20. 根据权利要求19所述的方法，其中，在所述第一控制晶体管和所述PIN型光电二极管之间形成第一平坦层。
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