WO2021057757A1 - 显示面板及其制作方法、显示装置 - Google Patents

显示面板及其制作方法、显示装置 Download PDF

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Publication number
WO2021057757A1
WO2021057757A1 PCT/CN2020/116979 CN2020116979W WO2021057757A1 WO 2021057757 A1 WO2021057757 A1 WO 2021057757A1 CN 2020116979 W CN2020116979 W CN 2020116979W WO 2021057757 A1 WO2021057757 A1 WO 2021057757A1
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WIPO (PCT)
Prior art keywords
cathode
substrate
blocking structure
layer
groove
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PCT/CN2020/116979
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English (en)
French (fr)
Inventor
隋凯
靳倩
王小芬
薛金祥
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京东方科技集团股份有限公司
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Priority to US17/419,608 priority Critical patent/US20220085124A1/en
Publication of WO2021057757A1 publication Critical patent/WO2021057757A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/822—Cathodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/846—Passivation; Containers; Encapsulations comprising getter material or desiccants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80522—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/874—Passivation; Containers; Encapsulations including getter material or desiccant
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel, a manufacturing method thereof, and a display device.
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • LCD Liquid Crystal Display
  • OLED display devices are ultra-light, ultra-thin (the thickness can be less than 1mm), high brightness, large viewing angles (up to 170 degrees), and the pixels themselves emit light.
  • a backlight is required, with low power consumption, fast response speed, high definition, low heat generation, excellent shock resistance, flexibility and other advantages.
  • a display panel in one aspect, includes a substrate and at least one display unit disposed on the substrate.
  • One display unit has a display area and a peripheral area surrounding the display area.
  • the display unit includes a cathode, a thin film encapsulation layer, and at least one cathode blocking structure disposed on a substrate; the cathode is located in the display area and the peripheral area; the thin film encapsulation layer is disposed on the cathode away from the cathode.
  • the thin film encapsulation layer covers the cathode, and the edge of the thin film encapsulation layer extends beyond the edge of the cathode; the at least one cathode blocking structure is arranged on the cathode close to the substrate Each cathode blocking structure is configured to disconnect the cathode at the position of the cathode blocking structure.
  • each cathode blocking structure is arranged around the display area.
  • the at least one cathode blocking structure includes a plurality of cathode blocking structures, and the plurality of cathode blocking structures are arranged at intervals.
  • the substrate includes a plurality of islands separated from each other, and a plurality of bridges connecting the plurality of islands.
  • the area where each island is located is an area where the display unit is located.
  • the display panel further includes a connection electrode disposed on the substrate; the connection electrode is located in the peripheral area, the connection electrode is disposed on a side of the cathode close to the substrate, and the connection electrode is connected to the substrate.
  • the cathode is directly connected; any cathode blocking structure arranged on the same side of the display area as the connecting electrode is arranged on the side of the connecting electrode away from the display area. Any two connecting electrodes arranged on different islands are electrically connected by connecting wires arranged on a bridge.
  • each cathode blocking structure is a groove provided in at least one insulating layer; on each boundary side of the display area where the cathode blocking structure is provided, the groove The cross section cut by the vertical plane of the boundary is an inverted T shape.
  • the display unit further includes at least one first organic filling pattern, each of the first organic filling patterns is filled at a corresponding position of a cathode blocking structure, and the first organic filling pattern is The surface away from the substrate is flush with the surface of the at least one insulating layer away from the substrate.
  • the first organic filling pattern includes an organic material and a desiccant doped in the organic material.
  • the at least one insulating layer includes two insulating layers laminated.
  • the cathode blocking structure includes a first sub-groove and a second sub-groove stacked and connected along the thickness direction of the substrate, and the first sub-groove and the second sub-groove are respectively disposed on the two layers In the insulating layer.
  • the display unit further includes: a plurality of pixel driving circuits disposed on the substrate and located in the display area, and a plurality of pixel driving circuits disposed on a side of the plurality of pixel driving circuits away from the substrate.
  • the pixel driving circuit includes a plurality of thin film transistors, and at least one thin film transistor of the plurality of thin film transistors includes a semiconductor active pattern, a gate electrode, and an interlayer insulating layer sequentially disposed on the substrate.
  • the part of the region, the source electrode and the drain electrode, the source electrode and the drain electrode are respectively in contact with the semiconductor active pattern through at least the first via hole in the interlayer insulating layer.
  • Each light-emitting function layer is located between a corresponding anode and the cathode; the anode is connected to the pixel driving circuit through a second via hole in the flat layer.
  • the two insulating layers are the interlayer insulating layer and the flat layer respectively.
  • the display unit further includes a retaining wall disposed on a side of the film encapsulation layer close to the substrate, and the retaining wall is disposed in the peripheral area.
  • the blocking wall is located on the side of the cathode blocking structure away from the display area.
  • the cross section of the retaining wall cut by the vertical plane of the boundary is an inverted trapezoid.
  • the cathode blocking structure is a groove provided in at least one insulating layer.
  • the display unit further includes a recessed portion and a second organic filling pattern.
  • the recessed portion is disposed in the at least one insulating layer, and the orthographic projection of the recessed portion on the substrate overlaps the orthographic projection of the retaining wall on the substrate.
  • the second organic filling pattern is filled in the recess; the surface of the second organic filling pattern away from the substrate is flush with the surface of the at least one insulating layer away from the substrate.
  • the retaining wall is arranged on the surface of the second organic filling pattern away from the substrate.
  • the second organic filling pattern includes an organic material and a desiccant doped in the organic material.
  • a display device including the display panel.
  • a method for manufacturing a display panel including: forming at least one display unit on a substrate, each display unit including a display area and a peripheral area surrounding the display area.
  • Forming the display unit includes: forming at least one cathode blocking structure located in the peripheral area on a substrate; forming a cathode on the substrate on which the at least one cathode blocking structure is formed; the cathode Located in the display area and the peripheral area, and the cathode is disconnected at the position of the at least one cathode blocking structure; on the side of the cathode away from the substrate, a thin film encapsulation layer is formed; the thin film encapsulation The layer covers the cathode, and the edge of the thin film encapsulation layer extends beyond the edge of the cathode.
  • each cathode blocking structure is a groove formed in at least one insulating layer; on each boundary side of the display area where the cathode blocking structure is formed, the groove The cross section cut by the vertical plane of the boundary is an inverted T shape.
  • forming the display unit before forming the cathode, further includes: forming a plurality of pixel driving circuits on the substrate and located in the display area; at least one of the plurality of pixel driving circuits A pixel driving circuit includes a plurality of thin film transistors, and at least one thin film transistor of the plurality of thin film transistors includes a semiconductor active pattern, a gate electrode, and an interlayer insulating layer sequentially formed on the substrate.
  • a flat layer is formed on the substrate of the driving circuit; a plurality of anodes and a plurality of light-emitting functional layers are formed on the side of the flat layer away from the substrate, and each light-emitting functional layer is located between a corresponding anode and the cathode ;
  • the anode is connected to the pixel driving circuit through a second via hole in the flat layer.
  • the at least one insulating layer includes the interlayer insulating layer and the flat layer;
  • the cathode blocking structure includes a first sub-groove and a second sub-groove that are stacked and communicated along the thickness direction of the substrate, The first sub-groove is located in the flat layer and penetrates the flat layer, and the second sub-groove is located in the interlayer insulating layer.
  • forming the display unit further includes: filling the second sub-groove in the interlayer insulating layer with light.
  • the photoresist is made to be flush with the surface of the photoresist away from the substrate and the surface of the interlayer insulating layer away from the substrate; and the photoresist is exposed.
  • forming the display unit further includes: developing the photoresist filled in the second sub-groove.
  • forming the display unit further includes: filling a first organic filling pattern at the position of the cathode blocking structure, and curing; The surface of the first organic filling pattern away from the substrate is flush with the surface of the flat layer away from the substrate; the first organic filling pattern includes an organic material and a surface doped in the organic material Desiccant.
  • forming the display unit further includes: forming a retaining wall in the peripheral area, On the side of each boundary of the display area where the cathode blocking structure and the blocking wall are formed, the blocking wall is located on the side of the cathode blocking structure away from the display area; On one side of each boundary of the display area of the retaining wall, the cross section of the retaining wall cut by the vertical plane of the boundary is an inverted trapezoid.
  • forming the display unit further includes: filling a second organic filling pattern in the concave portion and curing; The surface of the filling pattern away from the substrate is flush with the surface of the flat layer away from the substrate; the second organic filling pattern includes an organic material and a desiccant doped in the organic material; The retaining wall is in contact with the surface of the second organic filling pattern away from the substrate.
  • FIG. 1A is a schematic diagram of a display panel according to some embodiments.
  • Fig. 1B is a cross-sectional view taken along the line A-A' in Fig. 1A according to some embodiments;
  • Fig. 1C is still another cross-sectional view along the line A-A' in Fig. 1A according to some embodiments;
  • FIG. 1D is a schematic diagram of an arrangement of at least one cathode blocking structure in a display unit according to some embodiments
  • 1E is a schematic diagram of an arrangement of at least one cathode blocking structure in another display unit according to some embodiments
  • FIG. 1F is a schematic diagram of another arrangement of at least one cathode blocking structure in a display unit according to some embodiments.
  • FIG. 1G is a schematic diagram of another arrangement of at least one cathode blocking structure in a display unit according to some embodiments.
  • FIG. 1H is a schematic diagram of another arrangement of at least one cathode blocking structure in a display unit according to some embodiments.
  • FIG. 2A is a structural diagram of still another display panel according to some embodiments.
  • Fig. 2B is a cross-sectional view taken along the line B-B' in Fig. 2A according to some embodiments;
  • 3A is a cross-sectional view of a display panel in the related art
  • 3B is a cross-sectional view of another display panel in the related art.
  • Fig. 4 is still another cross-sectional view in the direction of B-B' in Fig. 2A according to some embodiments;
  • Fig. 5 is still another cross-sectional view taken along the line C-C' in Fig. 2A according to some embodiments;
  • Fig. 6 is still another cross-sectional view taken along the line C-C' in Fig. 2A according to some embodiments;
  • Fig. 7 is a cross-sectional view taken along the line B-B' in Fig. 2A according to some embodiments;
  • Fig. 8 is still another cross-sectional view taken along the line B-B' in Fig. 2A according to some embodiments;
  • FIG. 9 is a flowchart of a manufacturing method of a display panel according to some embodiments.
  • FIG. 10 is a process diagram of manufacturing a second sub-recess and a thin film transistor according to some embodiments.
  • FIG. 11 is a process diagram of filling a second sub-groove with photoresist according to some embodiments.
  • 12-13 are diagrams of a process of fabricating a flat layer according to some embodiments.
  • FIG. 14 is a process diagram of filling a second organic filling pattern according to some embodiments.
  • Figure 15 is a process diagram of making a retaining wall according to some embodiments.
  • FIG. 16 is a process diagram of a photoresist development and production of an anode and a light-emitting functional layer according to some embodiments
  • FIG. 17 is a process diagram of manufacturing a cathode according to some embodiments.
  • FIG. 18 is a process diagram of filling a first organic filling pattern according to some embodiments.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • connection and its extensions may be used.
  • connection may be used to indicate that two or more components are in direct physical or electrical contact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • exemplary embodiments are described herein with reference to cross-sectional views and/or plan views as idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity.
  • Exemplary embodiments of the present disclosure should not be interpreted as being limited to the shape of the area shown herein, but include shape deviations due to, for example, manufacturing.
  • an etched area shown as a rectangle will generally have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the area of the device, and are not intended to limit the scope of the exemplary embodiments.
  • the display panel 1 includes a substrate 13 and at least one display unit 10 disposed on the substrate 13, and one display unit 10 has a display area 11. And the peripheral area 12 surrounding the display area 11.
  • each display unit 10 has a display area 11 and a peripheral area 12 surrounding the display area 11.
  • the display unit 10 includes a cathode 14 disposed on a substrate 13, a thin film encapsulation layer 15 and at least one cathode blocking structure 16.
  • the cathode 14 is located in the display area 11 and extends to the peripheral area 12.
  • the thin film encapsulation layer 15 is disposed on the side of the cathode 14 away from the substrate 13, the thin film encapsulation layer 15 covers the cathode 14, and the edge of the thin film encapsulation layer 15 exceeds the edge of the cathode 14.
  • At least one cathode blocking structure 16 is disposed on the side of the cathode 14 close to the substrate 13 and located in the peripheral region 12, and each cathode blocking structure 16 is configured to disconnect the cathode 14 at the position of the cathode blocking structure 16.
  • cathode blocking structure 16 there is one cathode blocking structure 16.
  • the at least one cathode blocking structure 16 includes a cathode blocking structure 16 located in the peripheral area 12 on one side of the display area 11.
  • the cathode blocking structure 16 is located on the side of the first boundary 11A of the display area 11, and along the extending direction of the first boundary 11A, the cathode blocking structure 16 extends beyond the cathode 14 or is flush with the cathode 14.
  • the cathode 14 is divided into a main portion and a first edge portion. The first edge portion is located in the peripheral area 12, the main portion is located in the display area 11 and the peripheral area 12, and the side of the main portion facing the first edge portion and the first edge Partially disconnected.
  • the at least one cathode blocking structure 16 includes two cathode blocking structures 16, and the two cathode blocking structures 16 are respectively located in the peripheral area 12 on both sides of the display area 11.
  • one of the two cathode blocking structures 16 is located on the side of the first boundary 11A of the display area 11, and along the extension direction of the first boundary 11A, the one cathode blocking structure 16 extends beyond the cathode 14 or Flush with the cathode 14.
  • the other cathode blocking structure 16 of the two cathode blocking structures 16 is located on the side of the second boundary 11B of the display area 11, and along the extension direction of the second boundary 11B, the other cathode blocking structure 16 extends beyond the cathode 14 or Flush with the cathode 14.
  • the cathode 14 is divided into a main body part, a first edge part and a second edge part.
  • the first edge part and the second edge part are located in the peripheral area 12, the main body part is located in the display area 11 and the peripheral area 12, and the main part faces The side surface of the first edge portion is disconnected from the first edge portion, and the side surface of the main body portion facing the second edge portion is disconnected from the second edge portion.
  • the first side border and the second side border of the display area 11 may be adjacent borders or opposite borders.
  • the at least one cathode blocking structure 16 includes three cathode blocking structures 16, which are respectively located in the peripheral area 12 on three sides of the display area 11. And the three cathode blocking structures 16 are connected to form an integral structure.
  • the first cathode blocking structure 16 of the three cathode blocking structures 16 is located on the side of the first boundary 11A of the display area 11, and along the extension direction of the first boundary 11A, the first cathode blocking structure 16 extends beyond The cathode 14 may be flush with the cathode 14.
  • the second cathode blocking structure 16 of the three cathode blocking structures 16 is located on the side of the second boundary 11B of the display area 11, and along the extension direction of the second boundary 11B, the second cathode blocking structure 16 extends beyond The cathode 14 may be flush with the cathode 14.
  • the third cathode blocking structure 16 of the three cathode blocking structures 16 is located on the side of the third boundary 11C of the display area 11, and along the extension direction of the third boundary 11C, the third cathode blocking structure 16 extends beyond The cathode 14 may be flush with the cathode 14.
  • the cathode 14 is divided into a main body part, a first edge part, a second edge part and a third edge part.
  • the first edge part, the second edge part and the third edge part are located in the peripheral area 12, and the main body part is located in the display area 11. And the peripheral area 12, and the side of the main body part facing the first edge part is disconnected from the first edge part, the side of the main body part facing the second edge part is disconnected from the second edge part, and the main body part faces the third edge part The side is partly disconnected from the third edge.
  • the at least one cathode blocking structure 16 includes a cathode blocking structure 16, and the cathode blocking structure 16 is disposed around the display area 11. In this way, through the cathode blocking structure 16 arranged around the display area 11, the main body part of the cathode 14 in the area enclosed by the cathode blocking structure 16 can be disconnected from the rest.
  • At least one cathode blocking structure 16 includes a plurality of cathode blocking structures 16, each cathode blocking structure 16 is disposed around the display area 11, and the at least two cathode blocking structures The break structure 16 is arranged at intervals. By arranging at least two cathode blocking structures 16 and each cathode blocking structure 16 is arranged around the display area 11, it can be ensured that the cathode 14 located on the side of the at least two cathode blocking structures 16 closest to the display area 11 The blocking structure 16 encloses the main part of the area and is completely disconnected from the rest.
  • At least one cathode blocking structure 16 includes three cathode blocking structures 16, each cathode blocking structure 16 is arranged around the display area 11, and any two adjacent cathode blocking structures among the three cathode blocking structures 16 The break structure 16 is arranged at intervals.
  • at least one cathode blocking structure 16 includes two cathode blocking structures 16, each cathode blocking structure 16 is arranged around the display area 11, and the two cathode blocking structures 16 are arranged at intervals.
  • At least one cathode blocking structure 16 includes a plurality of cathode blocking structures 16, at least one cathode blocking structure 16 of the plurality of cathode blocking structures 16 is disposed around the display area 11, and the remaining cathode blocking structures 16 do not Set around the display area 11.
  • the cathode blocking structure 16 provided around the display area 11 has a continuous ring configuration.
  • the ring of the ring structure can be a circular ring, a square ring or other special-shaped rings.
  • some embodiments of the present disclosure do not limit the specific structure of the cathode blocking structure 16, as long as the cathode 14 can be disconnected at the position of the cathode blocking structure 16.
  • the cathodes 14 located in different display units 10 are disconnected from each other.
  • the thin film encapsulation layers 15 located in different display units 10 are disconnected from each other, that is, when there are multiple display units 10, each display unit 10 is individually packaged.
  • the specific structure of the cathode blocking structure 16 is not limited.
  • FIG. 1B uses the cathode blocking structure 16 as a groove for illustration, but the embodiment of the present disclosure is not limited thereto.
  • the cathode blocking structure 16 is a protrusion, and the specific structure of the protrusion is not limited, as long as the cathode 14 can be disconnected by the protrusion.
  • the cathode 14 is disconnected at the position of the cathode blocking structure 16 to divide the cathode 14 into a main body part and an edge part. Part of it is located on the side of the cathode blocking structure 16 close to the display area 11, and the main body partly covers the display area 11.
  • the cathode blocking structure 16 is arranged so that the main part of the cathode 14 faces the cathode blocking structure 16 The distance between the side surface of the encapsulation film layer 15 and the corresponding side surface of the packaging film layer 15 is increased, thereby increasing the path of water and oxygen intruding into the main body part, and ensuring the reliability of the package.
  • the cathode 14 can be enlarged by increasing 14 evaporation area to achieve.
  • the arrangement of the cathode blocking structure 16 can ensure the reliability of the package even if the overall size of the cathode 14 is relatively large.
  • the thickness of the thin film encapsulation layer 15 ranges from 0.3 to 15 ⁇ m. In some examples, the thickness of the thin film encapsulation layer 15 ranges from 0.5 to 5 ⁇ m.
  • the thickness of the thin film encapsulation layer 15 is 0.3 ⁇ m, 0.5 ⁇ m, 1 ⁇ m, 1.5 ⁇ m, 1.8 ⁇ m, 2.0 ⁇ m, 3 ⁇ m, 5 ⁇ m, 8 ⁇ m, 10 ⁇ m, 12 ⁇ m, or 15 ⁇ m.
  • the substrate 13 includes a plurality of islands 131 separated from each other and a plurality of bridges 132 connecting the plurality of islands 131 together.
  • the area where each island 131 is located is an area where a display unit 10 is located.
  • the display panel 1 further includes a connection electrode 17 disposed on the substrate 13 and located in the peripheral area 12, and the connection electrode 17 is disposed on a side of the cathode 14 close to the substrate 13.
  • the connecting electrode 17 is directly connected to the cathode 14, that is, the surface of the cathode 14 close to the substrate 13 is in contact with the surface of the connecting electrode 17 away from the substrate 13.
  • Any one of the cathode blocking structures 16 arranged on the same side of the display area 11 as the connecting electrode 17 is arranged on the side of the connecting electrode 17 away from the display area 11.
  • Any two connecting electrodes 17 arranged on different islands 131 are electrically connected by connecting wires arranged on one bridge 132.
  • any two connecting electrodes 17 arranged on different islands 131 are electrically connected into one body by connecting wires arranged on one bridge 132.
  • the cathodes 14 on different islands 131 are independent of each other, in order to supply power to the cathodes 14 on all islands 131, the cathode 14 on each island 131 is connected to the connecting electrode 17, and any two connecting electrodes 17 are Through the electrical connection with the connecting wire, the cathodes 14 on all the islands 131 can be electrically connected.
  • the display panel 1 is a stretchable display panel. There is a hollow area in the stretchable display panel, and a certain stretch performance is achieved through the expansion and contraction of the hollow area.
  • each island 131 (that is, each display unit 10) ranges from 50 to 2000 ⁇ m.
  • the area of the display unit 10 is also small.
  • the vapor deposition position of the cathode 14 is very challenging. Due to the shadow effect and alignment accuracy problems during the evaporation process, it is easy to cause the cathode 14 and the connecting electrode 17 not to overlap (as shown in FIG. 3A), and the dot screen does not light up. Or, it is easy to occur that the overlap area between the cathode 14 and the connecting electrode 17 is small (as shown in FIG. 3B), which causes the driving voltage of the display panel to increase.
  • the cathode blocking structure 16 can be arranged to make the overall size of the cathode 14 larger, so that even if the alignment accuracy is low, it can ensure that the main part of the cathode 14 is in contact with each other.
  • the connection electrodes 17 are sufficiently overlapped, and there is no problem of package reliability.
  • each cathode blocking structure 16 is a groove 161 provided on at least one insulating layer.
  • the cross section of the groove 161 cut by the vertical plane of the boundary is an inverted T shape.
  • the cross section of the groove 161 cut by the vertical plane of the first boundary 11A is all an inverted T shape.
  • the cross section of the groove 161 cut by the vertical plane of the second boundary 11B is an inverted T shape.
  • the cross section of the groove 161 located on one side of each boundary of the display area 11 cut by the vertical plane of the boundary is an inverted T shape.
  • the depth of the inverted T-shaped groove is 0.5-7 ⁇ m along the thickness direction of the substrate 13. In some examples, the depth of the inverted T-shaped groove is 1.0-5 ⁇ m.
  • the depth of the inverted T-shaped groove is 0.5 ⁇ m, 0.8 ⁇ m, 1.4 ⁇ m, 2 ⁇ m, 4 ⁇ m, 6 ⁇ m, or 7 ⁇ m.
  • any two adjacent insulating layers of the at least two insulating layers are close to each other Surface contact.
  • the display panel 1 can be avoided while ensuring that the cathode 14 is disconnected at the position of the cathode blocking structure 16
  • the increase in thickness facilitates the thinning of the display panel 1.
  • the above-mentioned at least one insulating layer includes two insulating layers laminated.
  • the cathode blocking structure 16 includes a first sub-groove 1611 and a second sub-groove 1612 that are stacked and connected along the thickness direction of the substrate 13.
  • the first sub-groove 1611 and the second sub-groove 1612 are respectively disposed in two insulating layers in.
  • the first sub-recess 1611 is located in an insulating layer far from the substrate 13 of the two insulating layers
  • the second sub-recess 1612 is located in an insulating layer close to the substrate 13 of the two insulating layers.
  • the width of the first sub-groove 1611 is smaller than the width of the second sub-groove 1612 along the direction perpendicular to the boundary.
  • the display unit 10 further includes at least one first organic filling pattern 162, and each first organic filling pattern 162 is filled in a corresponding position of the cathode blocking structure 16, and The surface of the first organic filling pattern 162 away from the substrate 13 is flush with the surface of the aforementioned at least one insulating layer away from the substrate 13.
  • the organic material has good ductility and flexibility.
  • the first organic filling pattern 162 includes an organic material and a desiccant doped in the organic material.
  • the organic material is epoxy resin or phenolic resin.
  • the organic material is doped with a desiccant, which can improve the barrier ability of the film encapsulation layer 15 to water and oxygen, and improve the reliability of the package.
  • the display unit 10 further includes a retaining wall 18 disposed on the side of the thin film encapsulation layer 15 close to the substrate 13, and the retaining wall 18 Set in the peripheral area 12.
  • the blocking wall 18 is located on the side of the cathode blocking structure 16 away from the display area 11.
  • the cross section of the retaining wall 18 cut by the vertical plane of the boundary is an inverted trapezoid.
  • the cross section of the retaining wall 18 cut by the vertical plane of the first boundary 11A is an inverted trapezoid.
  • the cross section of the retaining wall 18 cut by the vertical plane of the second boundary 11B is an inverted trapezoid.
  • the cross section of the retaining wall 18 located on the side of each boundary of the display area 11, which is cut by the vertical plane of the boundary is an inverted trapezoid.
  • the retaining wall 18 is arranged around the display area 11, and the retaining wall 18 has a continuous or segmented ring structure.
  • the ring of the ring structure can be a circular ring, a square ring or other special-shaped rings.
  • the thin film encapsulation layer 15 includes an inorganic encapsulation layer, and the inorganic encapsulation layer covers the retaining wall 18.
  • the retaining wall 18 can block the crack when the edge of the film encapsulation layer 15 is subjected to greater stress and cracks in the display panel 1, especially the stretchable display panel. , To prevent cracks from extending to the display area 11, causing water and oxygen etc. to invade from the cracks to the display area 11, thereby affecting the performance of the display panel 1.
  • the display unit 10 further includes a recess 163 and a second organic filling pattern 164.
  • the recessed portion 163 is disposed in the above-mentioned at least one insulating layer, and the orthographic projection of the recessed portion 163 on the substrate 13 overlaps with the orthographic projection of the retaining wall 18 on the substrate 13.
  • the second organic filling pattern 164 is filled in the recess 163, and the surface of the second organic filling pattern 164 away from the substrate 13 is flush with the surface away from the substrate 13 in the at least one insulating layer.
  • the barrier wall 18 is disposed on the surface of the second organic filling pattern 164 away from the substrate 13.
  • the recess 163 is located in an insulating layer far from the substrate 13 among the two insulating layers.
  • the second organic filling pattern 164 includes an organic material, and the organic material has good ductility and flexibility. By disposing the second organic filling pattern 164 at the recess 163, the ductility and flexibility of the display panel 1 can be increased. At the same time, when organic materials are used to make the retaining wall 18, since the adhesion between the organic materials is better, the adhesion between the retaining wall 18 and the surface of the at least one insulating layer away from the substrate 13 can be improved, and avoidance of blocking The wall 18 and the surface of the at least one insulating layer away from the substrate 13 are peeled off, resulting in cracking of the thin film encapsulation layer 15, which further improves the reliability of the package.
  • the second organic filling pattern 164 includes an organic material and a desiccant doped in the organic material.
  • the organic material may be epoxy resin, phenolic resin, and the like.
  • the material of the second organic filling pattern 164 is the same as that of the first organic filling pattern 162. Doping the organic material for making the second organic filling pattern 164 with a desiccant can improve the barrier ability of the thin film encapsulation layer 15 to water and oxygen, and improve the reliability of the encapsulation.
  • the display unit 10 further includes a plurality of pixel driving circuits disposed on the substrate 13 and located in the display area 11, and the plurality of pixel driving circuits are disposed far away from the substrate.
  • the pixel driving circuit includes a plurality of thin film transistors 112. As shown in FIG. 5 and FIG. 6, at least one thin film transistor 112 of the plurality of thin film transistors 112 includes a semiconductor active pattern 1121, which is sequentially disposed on the substrate 13. 1123.
  • the interlayer insulating layer 1124 is located in the region where the thin film transistor 112 is located, the source electrode 1125 and the drain electrode 1126, and the source electrode 1125 and the drain electrode 1126 are respectively active with the semiconductor through at least the first via hole 1127 in the interlayer insulating layer 1124.
  • the pattern 1121 is in contact.
  • the thin film transistor 112 further includes a gate insulating pattern 1122 disposed between the semiconductor active pattern 1121 and the gate electrode 1123.
  • the source electrode 1125 and the drain electrode 1126 are in contact with the semiconductor active pattern 1121 through the first via hole 1127 in the interlayer insulating layer 1124, respectively.
  • the thin film transistor 112 further includes a portion of the first gate insulating layer disposed between the semiconductor active pattern 1121 and the gate electrode 1123 in the region where the thin film transistor 112 is located.
  • the source electrode 1125 and the drain electrode 1126 make contact with the semiconductor active pattern 1121 through the first via hole 1127 penetrating the interlayer insulating layer 1124 and the first gate insulating layer, respectively.
  • Each light-emitting functional layer 1113 is located between a corresponding anode 1112 and the cathode 14.
  • the anode 1112 is connected to the pixel driving circuit through the second via 1114 on the flat layer 1111.
  • the light-emitting functional layer 1113, the anode 1112 and the cathode 14 located on both sides of the light-emitting functional layer 1113 constitute a light-emitting device.
  • the light-emitting function layer 1113 includes a light-emitting layer.
  • the light-emitting function layer 1113 also includes an electron transporting layer (ETL), an electron injection layer (EIL), and a hole transporting layer (hole transporting layer). , HTL for short) and hole injection layer (HIL for short).
  • ETL electron transporting layer
  • EIL electron injection layer
  • hole transporting layer hole injection layer
  • the electron transport layer and the electron injection layer are disposed between the light-emitting layer and the cathode 14, and the electron injection layer is closer to the cathode 14 than the electron transport layer.
  • the hole transport layer and the hole injection layer are disposed between the light emitting layer and the anode 1112, and the hole injection layer is closer to the anode 1112 than the hole transport layer.
  • the electron transport layer in all light-emitting devices can be located on the same layer, the electron injection layer in all light-emitting devices can be located on the same layer, and the hole transport layer in all light-emitting devices can be located on the same layer.
  • the hole injection layer may be located on the same layer.
  • the display area 11 includes a plurality of sub-pixel areas 110, and each pixel driving circuit and a light-emitting element electrically connected therewith are disposed in a corresponding sub-pixel area 110.
  • FIG. 5 illustrates that the thin film transistor 112 is a top-gate thin film transistor, but the embodiments of the present disclosure are not limited to this, and the thin film transistor 112 may also be any one such as a bottom-gate thin film transistor or a double-gate thin film transistor.
  • the thin film transistor 112 further includes a second gate insulating layer 1128 disposed on the side of the semiconductor active pattern 1121 close to the substrate 13 in the region where the thin film transistor 112 is located, and The second gate insulating layer 1128 is close to the second gate 1129 on the side of the substrate 13.
  • the embodiment of the present disclosure does not limit the number of the plurality of thin film transistors 112 in the pixel driving circuit.
  • the number of the plurality of thin film transistors 112 is two, for example, the plurality of thin film transistors 112 is five, and for example, there are multiple thin film transistors 112. There are seven thin film transistors 112.
  • FIGS. 5 and 6 only illustrate one thin film transistor 112 in the pixel driving circuit.
  • each thin film transistor 112 in the pixel driving circuit is the structure shown in FIG. 5 and FIG. 6.
  • FIG. 5 and FIG. 6 the structure shown in FIG. 5 and FIG. 6.
  • the flat layer 1111 and the interlayer insulating layer 1124 both extend from the display area 11 to the peripheral area 12, and the above-mentioned at least one insulating layer includes the flat layer 1111 and the interlayer insulating layer 1124.
  • the two insulating layers are a flat layer 1111 and an interlayer insulating layer 1124, respectively.
  • the cathode blocking structure 16 includes a first sub-groove 1611 and a second sub-groove 1612 that are stacked and connected in the thickness direction of the substrate 13, the first sub-groove 1611 is disposed in the flat layer 1111 and Through the flat layer 1111, the second sub-groove 1612 is disposed in the interlayer insulating layer 1124.
  • the second sub-groove 1612 penetrates the interlayer insulating layer 1124. In other examples, as shown in FIGS. 5 and 6, the second sub-groove 1612 does not penetrate the interlayer insulating layer 1124. That is, along the thickness direction of the substrate 13, the depth of the second sub-groove 1612 is smaller than the thickness of the interlayer insulating layer 1124.
  • the depth of the first sub-groove 1611 ranges from 0.3 to 2 ⁇ m.
  • the depth of the first sub-groove 161 is 0.3 ⁇ m, 0.6 ⁇ m, 0.9 ⁇ m, 1 ⁇ m, 1.5 ⁇ m, or 2 ⁇ m.
  • the depth of the second sub-groove 1612 ranges from 0.2 to 5 ⁇ m, for example, the depth of the second sub-groove 1612 is 0.2 ⁇ m, 0.5 ⁇ m, 0.8 ⁇ m, 1 ⁇ m, 1.5 ⁇ m, 2 ⁇ m, 3 ⁇ m, 4 ⁇ m, or 5 ⁇ m.
  • the width of the second sub-groove 1612 is 5-50 ⁇ m, and the first sub-groove 1611 The width is 2-40 ⁇ m.
  • the width of the second sub-groove 1612 is 5 ⁇ m, 10 ⁇ m, 13 ⁇ m, 20 ⁇ m, 30 ⁇ m, 40 ⁇ m, or 50 ⁇ m.
  • the width of the first sub-groove 1611 is 2 ⁇ m, 6 ⁇ m, 10 ⁇ m, 13 ⁇ m, 20 ⁇ m, 30 ⁇ m, or 40 ⁇ m.
  • Some embodiments of the present disclosure provide a display device including a display panel 1.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator.
  • Some embodiments of the present disclosure provide a manufacturing method of the display panel 1, including: forming at least one display unit 10 on a substrate 13, each display unit 10 includes a display area 11 and a peripheral area 12 surrounding the display area 11.
  • forming the display unit 10 includes:
  • At least one cathode blocking structure 16 located in the peripheral region 12 is formed on the substrate 13.
  • the arrangement of the at least one cathode blocking structure 16 can refer to the foregoing description, and will not be repeated here.
  • a cathode 14 is formed on the substrate 13 on which the at least one cathode blocking structure 16 is formed; the cathode 14 is located in the display area 11 and the peripheral area 12, and the cathode 14 is located in the At least one cathode blocking structure is disconnected at position 16.
  • a thin film encapsulation layer 15 is formed on the side of the cathode 14 away from the substrate 13; the thin film encapsulation layer 15 covers the cathode 14, and the edge of the thin film encapsulation layer 15 exceeds the edge of the cathode 14.
  • the at least one cathode blocking structure 16 is a groove 161 formed in at least one insulating layer; one at each boundary of the display area 11 where the cathode blocking structure 16 is formed
  • the cross section of the groove 161 cut by the vertical plane of the boundary is an inverted T shape.
  • forming the display unit further includes:
  • a plurality of pixel driving circuits are formed on the substrate 13 and located in the display area 11; the pixel driving circuit includes a plurality of thin film transistors 112, and at least one thin film transistor 112 of the plurality of thin film transistors 112 includes those which are sequentially formed on the substrate 13
  • the semiconductor active pattern 1121, the gate electrode 1123, the interlayer insulating layer 1124 are located in the area where the thin film transistor 112 is located, and the source electrode 1125 and the drain electrode 1126; the source electrode 1125 and the drain electrode 1126 pass through at least the first in the interlayer insulating layer 1124 A via hole 1127 is in contact with the semiconductor active pattern 1121.
  • each light-emitting functional layer 1113 is located between a corresponding anode 1112 and the cathode 14; the anode 1112 passes through the flat layer
  • the second via 1114 in 1111 is connected to the pixel driving circuit.
  • the above-mentioned at least one insulating layer includes an interlayer insulating layer 1124 and a flat layer 1111;
  • the cathode blocking structure 16 includes a first sub-groove 1611 and a second sub-groove 1612 that are stacked and connected along the thickness direction of the substrate 13.
  • the first sub-groove 1611 is located in the flat layer 1111 and penetrates the flat layer 1111, and the second sub-groove 1612 is located in the interlayer insulating layer 1124.
  • the first sub-groove 1611 and the second sub-groove 1612 may be formed by an etching process.
  • the depth of the first sub-groove 1611 ranges from 0.3 to 2 ⁇ m, for example, 0.6 ⁇ m.
  • the depth of the second sub-groove 1612 ranges from 0.2 ⁇ m to 5 ⁇ m, for example, 0.8 ⁇ m.
  • the width of the second sub-groove 1612 ranges from 5 to 50 ⁇ m, for example, 13 ⁇ m.
  • the width of the first sub-groove 1611 ranges from 2 to 40 ⁇ m, for example, 6 ⁇ m.
  • forming the display unit further includes:
  • the second sub-groove 1612 in the interlayer insulating layer 1124 is filled with photoresist 1612a so that the photoresist 1612a is away from the surface of the substrate 13 and the surface of the interlayer insulating layer 1124 is away from the substrate.
  • the surface of 13 is flush.
  • the photoresist 1612a is exposed to light.
  • forming the display unit further includes:
  • a retaining wall 18 is formed in the peripheral area 12.
  • the retaining wall 18 is located in the cathode blocking structure 16
  • a recess 163 located in the peripheral region 12 is also formed in the flat layer 1111.
  • the orthographic projection of the recess 163 on the substrate 13 overlaps the orthographic projection of the retaining wall 18 on the substrate 13.
  • the recess 163 may be formed by an etching process.
  • forming the display unit before developing the photoresist 1612a filled in the second sub-groove 1612, forming the display unit further includes:
  • the second organic filling pattern 164 is filled in the recess 163 and cured.
  • the surface of the second organic filling pattern 164 away from the substrate 13 is flush with the surface of the flat layer 1111 away from the substrate 13;
  • the second organic filling pattern 164 includes an organic material and a desiccant doped in the organic material;
  • the surface of the second organic filling pattern 164 away from the substrate 13 contacts.
  • forming the display unit further includes:
  • the photoresist 1612a filled in the second sub-groove 1612 is developed.
  • the first sub-groove 1611 and the second sub-groove 1612 together form the cathode blocking structure 16.
  • forming the display unit further includes:
  • the first organic filling pattern 162 is filled and cured; the surface of the first organic filling pattern 162 away from the substrate 13 and the flat layer 1111 are away from the substrate The surface of 13 is flush; the first organic filling pattern 162 includes an organic material and a desiccant doped in the organic material.
  • the cathode 14 is disconnected at the position of the cathode blocking structure 16 and the cathode 14 is divided into a main part and an edge.
  • the main body part is located on the side of the cathode blocking structure 16 close to the display area 11, and the main body part covers the display area 11.
  • the cathode blocking structure 16 is arranged so that the main part of the cathode 14 faces the cathode blocking structure 16 The distance between the side surface of the encapsulation film layer 15 and the corresponding side surface of the packaging film layer 15 is increased, thereby increasing the path of water and oxygen intruding into the main body part, and ensuring the reliability of the package.
  • the cathode 14 can be enlarged by increasing 14 evaporation area to achieve.
  • the arrangement of the cathode blocking structure 16 can ensure the reliability of the package even if the overall size of the cathode 14 is relatively large.
  • the substrate 13 includes a plurality of islands 131 separated from each other and a plurality of bridges 132 connecting the plurality of islands 131.
  • the area where each island 131 is located is an area where a display unit 10 is located.
  • the manufacturing method of the display panel 1 further includes: forming a connection electrode 17 on the substrate 13 and located in the peripheral area 12, and the connection electrode 17 is located on the island 131, And it is located on the side of the cathode blocking structure 16 close to the display area 11.
  • the connecting electrode 17 is directly connected to the cathode 14, and any two connecting electrodes 17 arranged on different islands 131 are electrically connected by connecting wires located on a bridge 132.

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Abstract

一种显示面板，包括衬底和设置于所述衬底上的至少一个显示单元，一个显示单元具有显示区以及围绕所述显示区的周边区。所述显示单元包括阴极、薄膜封装层以及至少一个阴极阻断结构；所述阴极设置于所述衬底上、且位于所述显示区以及所述周边区；所述薄膜封装层设置于所述阴极远离所述衬底的一侧，所述薄膜封装层覆盖所述阴极，且所述薄膜封装层的边缘超出所述阴极的边缘；所述至少一个阴极阻断结构设置于所述阴极靠近所述衬底的一侧、且位于所述周边区，每个阴极阻断结构被配置为使所述阴极在所述阴极阻断结构位置处断开。

Description

显示面板及其制作方法、显示装置
本申请要求于2019年9月27日提交的、申请号为201910927307.9的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及其制作方法、显示装置。
背景技术
OLED(Organic Light-Emitting Diode，有机发光二极管)，是一种利用有机半导体材料和发光材料在电流驱动下而达到发光并实现显示的技术。相比于LCD(Liquid Crystal Display，液晶显示器)，OLED显示装置具有超轻、超薄(厚度可低于1mm)、亮度高、可视角度大(可达170度)、由像素本身发光而不需要背光源，功耗低、响应速度快、清晰度高、发热量低、抗震性能优异、可弯曲等优势。
发明内容
一方面，提供一种显示面板。所述显示面板包括衬底和设置于所述衬底上的至少一个显示单元，一个显示单元具有显示区以及围绕所述显示区的周边区。所述显示单元包括设置于衬底上的阴极、薄膜封装层以及至少一个阴极阻断结构；所述阴极位于所述显示区以及所述周边区；所述薄膜封装层设置于所述阴极远离所述衬底的一侧，所述薄膜封装层覆盖所述阴极，且所述薄膜封装层的边缘超出所述阴极的边缘；所述至少一个阴极阻断结构设置于所述阴极靠近所述衬底的一侧、且位于所述周边区，每个阴极阻断结构被配置为使所述阴极在所述阴极阻断结构位置处断开。
在一些实施例中，每个阴极阻断结构围绕所述显示区设置。
在一些实施例中，所述至少一个阴极阻断结构包括多个阴极阻断结构，所述多个阴极阻断结构间隔设置。
在一些实施例中，所述衬底包括彼此分隔开的多个岛、以及将多个所述多个岛中连接起来的多个桥。每个岛所在区域为一个所述显示单元所在区域。所述显示面板还包括设置于所述衬上的连接电极；所述连接电极位于所述周边区，所述连接电极设置于所述阴极靠近所述衬底的 一侧且所述连接电极与所述阴极直接连接；与所述连接电极设置于所述显示区同一侧的任一个阴极阻断结构，设置于所述连接电极远离所述显示区的一侧。设置于不同岛上的任意两个连接电极通过设置于一桥上的连接线电连接。
在一些实施例中，每个阴极阻断结构为设置于至少一层绝缘层中的凹槽；在设置有所述阴极阻断结构的所述显示区的每一边界一侧，所述凹槽被该边界的垂直面所截得的截面为倒T形。在一些实施例中，所述显示单元还包括至少一个第一有机填充图案，每个所述第一有机填充图案填充于对应的一个阴极阻断结构位置处，且所述第一有机填充图案的远离所述衬底的表面与所述至少一层绝缘层远离所述衬底的表面齐平。
在一些实施例中，所述第一有机填充图案包括有机材料和掺杂于有机材料中的干燥剂。
在一些实施例中，所述至少一层绝缘层包括层叠设置的两层绝缘层。所述阴极阻断结构包括沿所述衬底厚度方向层叠且连通的第一子凹槽和第二子凹槽，所述第一子凹槽和第二子凹槽分别设置于所述两层绝缘层中。
在一些实施例中，所述显示单元还包括：设置于所述衬底上且位于所述显示区的多个像素驱动电路、设置于所述多个像素驱动电路远离所述衬底一侧的平坦层、以及设置于所述平坦层远离所述衬底一侧的多个阳极以及多个发光功能层。所述像素驱动电路包括多个薄膜晶体管，所述多个薄膜晶体管中的至少一个薄膜晶体管包括依次设置于所述衬底上的半导体有源图案、栅极、层间绝缘层位于所述薄膜晶体管所在区域的部分、源极和漏极，所述源极和所述漏极至少通过所述层间绝缘层中的第一过孔分别与所述半导体有源图案接触。每个发光功能层位于对应的一个阳极和所述阴极之间；所述阳极通过所述平坦层中的第二过孔与所述像素驱动电路连接。所述两层绝缘层分别为所述层间绝缘层和所述平坦层。
在一些实施例中，所述显示单元还包括设置于所述薄膜封装层靠近所述衬底一侧的挡墙，所述挡墙设置于所述周边区中。在设置有所述阴极阻断结构和所述挡墙的所述显示区的每一边界一侧，所述挡墙位于所述阴极阻断结构远离所述显示区的一侧。在设置有所述挡墙的所述显示 区的每一边界的一侧，所述挡墙被该边界的垂直面所截得的截面为倒梯形。
在一些实施例中，所述阴极阻断结构为设置于至少一层绝缘层中的凹槽。所述显示单元还包括凹陷部和第二有机填充图案。所述凹陷部设置于所述至少一层绝缘层中，且所述凹陷部在所述衬底上的正投影与所述挡墙在所述衬底上的正投影重叠。所述第二有机填充图案填充在所述凹陷部中；所述第二有机填充图案的远离所述衬底的表面与所述至少一层绝缘层中远离所述衬底的表面齐平。所述挡墙设置于所述第二有机填充图案的远离所述衬底的表面上。
在一些实施例中，所述第二有机填充图案包括有机材料和掺杂于有机材料中的干燥剂。
另一方面，提供一种显示装置，包括所述显示面板。
再一方面，提供一种显示面板的制备方法，包括：在衬底上形成至少一个显示单元，每个显示单元包括显示区以及环绕所述显示区的周边区。形成所述显示单元，包括：在衬底上形成位于所述周边区的至少一个阴极阻断结构；在形成有所述至少一个阴极阻断结构的所述衬底上，形成阴极；所述阴极位于所述显示区以及所述周边区，并且所述阴极在所述至少一个阴极阻断结构位置处断开；在所述阴极远离所述衬底一侧，形成薄膜封装层；所述薄膜封装层覆盖所述阴极，且所述薄膜封装层的边缘超出所述阴极的边缘。
在一些实施例中，每个阴极阻断结构为形成于至少一层绝缘层中的凹槽；在形成有所述阴极阻断结构的所述显示区的每一边界一侧，所述凹槽被该边界的垂直面所截得的截面为倒T形。
在一些实施例中，在形成所述阴极之前，形成所述显示单元还包括：在所述衬底上且位于所述显示区形成多个像素驱动电路；所述多个像素驱动电路中的至少一个像素驱动电路包括多个薄膜晶体管，所述多个薄膜晶体管中的至少一个薄膜晶体管包括依次形成于所述衬底上的半导体有源图案、栅极、层间绝缘层位于所述薄膜晶体管所在区域的部分、源极和漏极；所述源极和所述漏极至少通过所述层间绝缘层中的第一过孔与所述半导体有源图案接触；在形成有所述多个像素驱动电路的衬底上，形成平坦层；在所述平坦层远离所述衬底一侧形成多个阳极以及多个发光功能层，每个发光功能层位于对应的一个阳极和所述阴极之间； 所述阳极通过所述平坦层中的第二过孔与所述像素驱动电路连接。所述至少一层绝缘层包括所述层间绝缘层和所述平坦层；所述阴极阻断结构包括沿所述衬底厚度方向层叠且连通的第一子凹槽和第二子凹槽，所述第一子凹槽位于所述平坦层中且贯穿所述平坦层，所述第二子凹槽位于所述层间绝缘层中。
在一些实施例中，在形成所述层间绝缘层之后，形成所述平坦层之前，形成所述显示单元还包括：在所述层间绝缘层中的所述第二子凹槽中填充光刻胶，使光刻胶远离所述衬底的表面与所述层间绝缘层的远离所述衬底的表面齐平；对光刻胶进行曝光。在此基础上，在形成所述平坦层之后，形成所述阴极之前，形成所述显示单元，还包括：将填充在所述第二子凹槽中的光刻胶进行显影。
在一些实施例中，在形成所述阴极之后，形成所述薄膜封装层之前，形成所述显示单元还包括：在所述阴极阻断结构位置处，填充第一有机填充图案，并进行固化；所述第一有机填充图案的远离所述衬底的表面与所述平坦层远离所述衬底的表面齐平；所述第一有机填充图案包括有机材料和掺杂于所述有机材料中的干燥剂。
在一些实施例中，在形成所述平坦层之后，对填充在所述第二子凹槽中的光刻胶进行显影之前，形成所述显示单元还包括：在所述周边区形成挡墙，在形成有所述阴极阻断结构和所述挡墙的所述显示区的每一边界一侧，所述挡墙位于所述阴极阻断结构远离所述显示区的一侧；在形成有所述挡墙的所述显示区的每一边界的一侧，所述挡墙被该边界的垂直面所截得的截面为倒梯形。
在一些实施例中，在所述平坦层中形成所述第一子凹槽与所述第二过孔的同时，还在所述平坦层中形成位于所述周边区的凹陷部；所述凹陷部在所述衬底上的正投影与所述挡墙在所述衬底上的正投影重叠。在将填充在所述第二子凹槽中的光刻胶进行显影之前，形成所述显示单元还包括：在所述凹陷部中填充第二有机填充图案，并进行固化；所述第二有机填充图案的远离所述衬底的表面与所述平坦层远离所述衬底的表面齐平；所述第二有机填充图案包括有机材料和掺杂于所述有机材料中的干燥剂；所述挡墙与所述第二有机填充图案的远离所述衬底的表面接触。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施 例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1A为根据一些实施例的一种显示面板的示意图；
图1B为根据一些实施例的一种图1A中A-A′向的剖视图；
图1C为根据一些实施例的再一种图1A中A-A′向的剖视图；
图1D为根据一些实施例的一种显示单元中至少一个阴极阻断结构的设置方式的示意图；
图1E为根据一些实施例的另一种显示单元中至少一个阴极阻断结构的设置方式的示意图；
图1F为根据一些实施例的又一种显示单元中至少一个阴极阻断结构的设置方式的示意图；
图1G为根据一些实施例的又一种显示单元中至少一个阴极阻断结构的设置方式的示意图；
图1H为根据一些实施例的又一种显示单元中至少一个阴极阻断结构的设置方式的示意图；
图2A为根据一些实施例的又一种显示面板的结构图；
图2B为根据一些实施例的一种图2A中B-B′向的剖视图；
图3A为相关技术中一种显示面板的剖视图；
图3B为相关技术中又一种显示面板的剖视图；
图4为根据一些实施例的又一种图2A中B-B′向的剖视图；
图5为根据一些实施例的再一种图2A中C-C′向的剖视图；
图6为根据一些实施例的又一种图2A中C-C′向的剖视图；
图7为根据一些实施例的一种图2A中B-B′向的剖视图；
图8为根据一些实施例的又一种图2A中B-B′向的剖视图；
图9为根据一些实施例的一种显示面板的制作方法的流程图；
图10为根据一些实施例的一种制作第二子凹槽以及薄膜晶体管的过程图；
图11为根据一些实施例的一种用光刻胶填充第二子凹槽的过程图；
图12-13为根据一些实施例的一种制作平坦层的过程图；
图14为根据一些实施例的一种填充第二有机填充图案的过程图；
图15为根据一些实施例的制作挡墙的过程图；
图16为根据一些实施例的一种光刻胶显影和制作阳极、发光功能层的过程图；
图17为根据一些实施例的一种制作阴极的过程图；
图18为根据一些实施例的一种填充第一有机填充图案的过程图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
本文中“被配置为”的使用意味着开放和包容性的语言，其不排除适用 于或被配置为执行额外任务或步骤的设备。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。本公开示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
如图1A-图1C所示，本公开一些实施例提供一种显示面板1，显示面板1包括衬底13和设置于衬底13上的至少一个显示单元10，一个显示单元10具有显示区11以及围绕显示区11的周边区12。在一些示例中，每个显示单元10具有显示区11以及围绕显示区11的周边区12。
如图1B和图1C所示，该显示单元10包括设置于衬底13上的阴极14、薄膜封装层15和至少一个阴极阻断结构16。阴极14位于显示区11并延伸至周边区12。薄膜封装层15设置于阴极14远离衬底13的一侧，薄膜封装层15覆盖阴极14，且薄膜封装层15的边缘超出阴极14的边缘。至少一个阴极阻断结构16设置于阴极14靠近衬底13的一侧并位于周边区12，且每个阴极阻断结构16被配置为使阴极14在该阴极阻断结构16位置处断开。
可选的，阴极阻断结构16为一个。或者，阴极阻断结构16为多个，多个阴极阻断结构16间隔设置。
在一些示例中，如图1D所示，至少一个阴极阻断结构16包括一个阴极阻断结构16，该阴极阻断结构16位于显示区11的一侧的周边区12中。例如，该阴极阻断结构16位于显示区11的第一边界11A一侧，沿该第一边界11A的延伸方向，阴极阻断结构16超出阴极14或与阴极14齐平。由此，阴极14被分成主体部分和第一边缘部分，第一边缘部分位于周边区12，主体部分位于显示区11以及周边区12，且主体部分的朝向第一边缘部分的侧面与第一边缘部分断开。
在另一些示例中，如图1E所示，至少一个阴极阻断结构16包括两个阴极阻断结构16，该两个阴极阻断结构16分别位于显示区11的两侧的周边区12中。例如，该两个阴极阻断结构16中一个阴极阻断结构16位于显示区11的第一边界11A一侧，沿该第一边界11A的延伸 方向，该一个阴极阻断结构16超出阴极14或与阴极14齐平。该两个阴极阻断结构16中另一个阴极阻断结构16位于显示区11的第二边界11B一侧，沿该第二边界11B的延伸方向，该另一个阴极阻断结构16超出阴极14或与阴极14齐平。由此，阴极14被分成主体部分、第一边缘部分和第二边缘部分，第一边缘部分和第二边缘部分位于周边区12，主体部分位于显示区11以及周边区12，且主体部分的朝向第一边缘部分的侧面与第一边缘部分断开，主体部分的朝向第二边缘部分的侧面与第二边缘部分断开。这里，显示区11的第一侧边界和第二侧边界可以是相邻的边界，也可以是相对的边界。
在另一些示例中，如图1F所示，至少一个阴极阻断结构16包括三个阴极阻断结构16，该三个阴极阻断结构16分别位于显示区11的三侧的周边区12中，且该三个阴极阻断结构16连接为一体结构。该三个阴极阻断结构16中的第一个阴极阻断结构16位于显示区11的第一边界11A一侧，沿该第一边界11A的延伸方向，该第一个阴极阻断结构16超出阴极14或与阴极14齐平。该三个阴极阻断结构16中的第二个阴极阻断结构16位于显示区11的第二边界11B一侧，沿该第二边界11B的延伸方向，该第二个阴极阻断结构16超出阴极14或与阴极14齐平。该三个阴极阻断结构16中的第三个阴极阻断结构16位于显示区11的第三边界11C一侧，沿该第三边界11C的延伸方向，该第三个阴极阻断结构16超出阴极14或与阴极14齐平。由此，阴极14被分成主体部分、第一边缘部分、第二边缘部分和第三边缘部分，第一边缘部分、第二边缘部分和第三边缘部分位于周边区12，主体部分位于显示区11以及周边区12，且主体部分的朝向第一边缘部分的侧面与第一边缘部分断开，主体部分的朝向第二边缘部分的侧面与第二边缘部分断开，主体部分的朝向第三边缘部分的侧面与第三边缘部分断开。
在另一些示例中，如图1G所示，至少一个阴极阻断结构16包括一个阴极阻断结构16，该阴极阻断结构16围绕所述显示区11设置。这样，通过围绕所述显示区11设置的阴极阻断结构16，可使阴极14中位于该阴极阻断结构16围成区域内的主体部分与其余部分断开。
在另一些示例中，如图1H所示，至少一个阴极阻断结构16包括多个阴极阻断结构16，每个阴极阻断结构16围绕所述显示区11设置，且该至少两个阴极阻断结构16间隔设置。通过设置至少两个阴极阻断 结构16，且每个阴极阻断结构16围绕显示区11设置，可保证阴极14中位于该至少两个阴极阻断结构16中最靠近显示区11一侧的阴极阻断结构16围成区域内的主体部分、与其余部分完全断开。
示例的，至少一个阴极阻断结构16包括三个阴极阻断结构16，每个阴极阻断结构16围绕所述显示区11设置，且三个阴极阻断结构16中任意相邻两个阴极阻断结构16间隔设置。又示例的，至少一个阴极阻断结构16包括两个阴极阻断结构16，每个阴极阻断结构16围绕所述显示区11设置，且两个阴极阻断结构16间隔设置。
在一些示例中，至少一个阴极阻断结构16包括多个阴极阻断结构16，多个阴极阻断结构16中至少一个阴极阻断结构16围绕显示区11设置，其余阴极阻断结构16则不围绕显示区11设置。
在一些示例中，围绕显示区11设置的阴极阻断结构16具有连续式环形构造。其中，环形构造之环形可为圆环、方形环或其他异形环。
需要说明的是，本公开的一些实施例不对阴极阻断结构16的具体结构不做限定，只要能使阴极14在该阴极阻断结构16位置处断开即可。在显示单元10为多个的情况下，位于不同显示单元10中的阴极14相互断开。位于不同显示单元10中的薄膜封装层15相互断开，即，在显示单元10为多个的情况下，每个显示单元10单独封装。
此外，对于阴极阻断结构16的具体结构不做限定，图1B以阴极阻断结构16为凹槽进行示意，但本公开实施例并不限于此。例如，如图1C所示，阴极阻断结构16为凸起，对于凸起的具体结构不做限定，只要能通过该凸起使阴极14断开即可。
在本公开一些实施例提供的显示面板1中，通过在周边区12设置阴极阻断结构16，使阴极14在阴极阻断结构16位置处断开而将阴极14分成主体部分和边缘部分，主体部分位于阴极阻断结构16靠近显示区11的一侧，且主体部分覆盖显示区11。相比于未设置阴极阻断结构16的情况下阴极14的侧面与封装薄膜层15的对应侧面之间的距离，阴极阻断结构16的设置使得阴极14中主体部分的朝向阴极阻断结构16的侧面与封装薄膜层15的对应侧面之间的距离增大，从而增加了水氧入侵到主体部分的路径，保证了封装的信赖性。在此基础上，考虑到在蒸镀形成阴极14时，存在对位精度的问题，为保证在对位精度较低的情况下，上述主体部分也能形成在预定的区域，可以通过增大阴极 14的蒸镀面积来实现。而阴极阻断结构16的设置，即使阴极14整体的尺寸较大，也可保证封装信赖性。
在一些实施例中，薄膜封装层15的厚度范围为0.3～15μm。在一些示例中，薄膜封装层15的厚度范围为0.5～5μm。
例如，薄膜封装层15的厚度为0.3μm、0.5μm、1μm、1.5μm、1.8μm、2.0μm、3μm、5μm、8μm、10μm、12μm、或15μm。
在一些实施例中，如图2A和图2B所示，衬底13包括彼此分隔开的多个岛131、以及将多个岛131连接起来的多个桥132。每个岛131所在区域为一个显示单元10所在的区域。
显示面板1还包括设置于衬底13上且位于周边区12的连接电极17，连接电极17设置于阴极14靠近衬底13的一侧。连接电极17与阴极14直接连接，即，阴极14靠近衬底13的表面与连接电极17远离衬底13的表面接触。与连接电极17设置于显示区11同一侧的任一个阴极阻断结构16，设置于连接电极17远离显示区11的一侧。设置于不同岛131上的任意两个连接电极17通过设置于一个桥132上的连接线电连接。示例的，设置于不同岛131上的任意两个连接电极17通过设置于一个桥132上的连接线电连接为一体。
由于位于不同岛131上的阴极14是相互独立的，而为了向所有岛131上的阴极14供电，通过使每个岛上131的阴极14与连接电极17连接，而任意两个连接电极17又通过连接线电连接，使得位于所有岛131上的阴极14都能电连接。
在衬底13包括彼此分隔开的多个岛131、以及将多个岛131中每个岛131连接起来的多个桥132的情况下，该显示面板1为可拉伸显示面板。在可拉伸显示面板中存在镂空区，通过镂空区的伸缩而达到一定的拉伸性能。
在一些示例中，每个岛131(也即每个显示单元10)的边长范围为50～2000μm。
在显示单元10的边长范围较小的情况下，相应的，显示单元10的面积也较小。为了实现显示面板1的高分辨率，需要尽可能的提高显示单元10内的像素数量，这样就会降低显示单元10中周边区12的面积。然而，当显示单元10中周边区12的面积较小时，在不设置本公开实施例中的阴极阻断结构16的情况下，对阴极14的蒸镀位置具有非常 大的挑战。由于蒸镀过程中阴影效应(Shadow)的存在以及对位精度的问题，很容易产生阴极14与连接电极17搭接不上的情况(如图3A所示)，从而出现点屏不亮现象。或者，容易出现阴极14与连接电极17的搭接面积较小(如图3B所示)，从而导致显示面板的驱动电压升高的现象。
而本公开一些实施例的可拉伸显示面板中，阴极阻断结构16的设置，可将阴极14的整体尺寸做的大一些，这样即使对位精度低，也能保证阴极14的主体部分与连接电极17的充分搭接，而且，也不会存在封装信赖性的问题。
可选的，如图4所示，每个阴极阻断结构16为设置于至少一层绝缘层上的凹槽161。在设置有阴极阻断结构16的显示区11的每一边界一侧，凹槽161被该边界的垂直面所截得的截面为倒T形。
例如，在凹槽161位于显示区11的第一边界11A一侧的情况下，该凹槽161被该第一边界11A的垂直面所截得的截面都是倒T形。又如，在凹槽161位于显示区11的第二边界11B一侧的情况下，该凹槽161被该第二边界11B的垂直面所截得的截面是倒T形。又如，在凹槽161围绕显示区11设置的情况下，位于显示区11的每一边界一侧的凹槽161被该边界的垂直面所截得的截面都是倒T形。
在一些实施例中，沿衬底13厚度的方向，倒T形凹槽的深度为0.5～7μm。在一些示例中，倒T形凹槽的深度为1.0～5μm。
示例的，倒T形凹槽的深度为0.5μm、0.8μm、1.4μm、2μm、4μm、6μm、或7μm。
需要说明的是，在上述至少一层绝缘层包括至少两层绝缘层的情况下，至少在阴极阻断结构16位置处，该至少两层绝缘层中任意相邻两层绝缘层的相互靠近的表面接触。
通过将阴极阻断结构16设置为凹槽161，并且将凹槽161的纵截面设置为倒T形，在保证阴极14在阴极阻断结构16位置处断开的情况下，可避免显示面板1厚度的增加，有利于显示面板1薄型化。
在一些实施例中，如图5和6所示，上述至少一层绝缘层包括层叠设置的两层绝缘层。阴极阻断结构16包括沿衬底13厚度方向层叠且连通的第一子凹槽1611和第二子凹槽1612，第一子凹槽1611和第二子凹槽1612分别设置于两层绝缘层中。例如，第一子凹槽1611位于两 层绝缘层中远离衬底13的一层绝缘层中，第二子凹槽1612位于两层绝缘层中靠近衬底13的一层绝缘层中。相应的，在设置有阴极阻断结构16的显示区11的每一边界一侧，沿垂直该边界的方向，第一子凹槽1611的宽度小于第二子凹槽1612的宽度。
在一些实施例中，如图5-8所示，显示单元10还包括至少一个第一有机填充图案162，每个第一有机填充图案162填充于对应的一个阴极阻断结构16位置处，且第一有机填充图案162的远离衬底13的表面与上述至少一层绝缘层远离衬底13的表面齐平。
通过在阴极阻断结构16位置处填充第一有机填充图案162，并使第一有机填充图案162的远离衬底13的表面与上述至少一层绝缘层远离衬底13的表面齐平，可以在后续制作薄膜封装层15时，避免薄膜封装层15在阴极阻断结构16处因为段差而断开，影响封装性能。此外，有机材料具有较好的延展性和柔韧性，通过设置第一有机填充图案162，可以增加显示面板1的延展性和柔韧性。
在一些示例中，第一有机填充图案162包括有机材料和掺杂于有机材料中的干燥剂。示例的，有机材料为环氧树脂或酚醛树脂等。在有机材料中掺杂干燥剂，可以提高薄膜封装层15对水氧的阻隔能力，提高封装的信赖性。
在一些实施例中，如图1B、图1C、图2B，图4-图8所示，显示单元10还包括设置于薄膜封装层15靠近衬底13一侧的挡墙18，该挡墙18设置于周边区12中。在设置有阴极阻断结构16和挡墙18的显示区11的每一边界一侧，挡墙18位于阴极阻断结构16远离显示区11的一侧。
在设置有挡墙18的显示区11的每一边界一侧，挡墙18被该边界的垂直面所截得的截面为倒梯形。
例如，在挡墙18位于显示区11的第一边界11A一侧的情况下，该挡墙18被该第一边界11A的垂直面所截得的截面是倒梯形。又如，在挡墙18位于显示区11的第二边界11B一侧的情况下，该挡墙18被该第二边界11B的垂直面所截得的截面是倒梯形。又如，在挡墙18围绕显示区11设置的情况下，位于显示区11的每一边界一侧的挡墙18被该边界的垂直面所截得的截面都是倒梯形。
在一些示例中，挡墙18围绕显示区11设置，且挡墙18具有连续 式或分段式环形构造。环形构造之环形可为圆环、方形环或其他异形环。
在一些示例中，薄膜封装层15包括无机封装层，无机封装层覆盖挡墙18。
通过设置截面为倒梯形的挡墙18，使得在显示面板1尤其是可拉伸显示面板中，薄膜封装层15的边缘受到较大的应力而发生开裂时，挡墙18可以对该裂纹进行阻挡，避免裂纹延伸至显示区11，导致水氧等从裂纹入侵至显示区11，而影响显示面板1的性能。
在一些实施例中，如图8所示，显示单元10还包括凹陷部163和第二有机填充图案164。凹陷部163设置于上述至少一层绝缘层中，且凹陷部163在衬底13上的正投影与挡墙18在衬底13上的正投影重叠。
第二有机填充图案164填充在凹陷部163中，第二有机填充图案164的远离衬底13的表面，与上述至少一层绝缘层中远离衬底13的表面齐平。挡墙18设置于第二有机填充图案164的远离衬底13的表面上。
在上述至少一层绝缘层包括层叠设置的两层绝缘层的情况下，在一些示例中，凹陷部163位于两层绝缘层中远离衬底13的一层绝缘层中。
第二有机填充图案164包括有机材料，有机材料具有较好的延展性和柔韧性，通过在凹陷部163处设置第二有机填充图案164，可以增加显示面板1的延展性和柔韧性。同时，当使用有机材料制作挡墙18时，由于有机材料之间的粘附性较好，可以提高挡墙18与上述至少一层绝缘层远离衬底13的表面的粘附性，避免由于挡墙18与上述至少一层绝缘层远离衬底13的表面剥离而导致薄膜封装层15的开裂，进一步提高封装的信赖性。
在一些示例中，第二有机填充图案164包括有机材料和掺杂于有机材料中的干燥剂。其中，有机材料可为环氧树脂、酚醛树脂等。示例的，第二有机填充图案164与第一有机填充图案162的材料相同。在制作第二有机填充图案164的有机材料中掺杂干燥剂，可以提高薄膜封装层15对水氧的阻隔能力，提高封装的信赖性。
在一些实施例中，如图5和图6所示，显示单元10还包括设置于衬底13上且位于显示区11的多个像素驱动电路、设置于所述多个像素驱动电路远离衬底13一侧的平坦层1111、设置于平坦层1111远离衬底13一侧的多个阳极1112以及多个发光功能层1113。
像素驱动电路包括多个薄膜晶体管112，如图5和图6所示，所述多个薄膜晶体管112中的至少一个薄膜晶体管112包括依次设置于衬底13上的半导体有源图案1121、栅极1123、层间绝缘层1124位于薄膜晶体管112所在区域的部分、源极1125和漏极1126，源极1125和漏极1126至少通过层间绝缘层1124中的第一过孔1127分别与半导体有源图案1121接触。在一些示例中，薄膜晶体管112还包括设置于半导体有源图案1121和栅极1123之间的栅绝缘图案1122。在此情况下，源极1125和漏极1126通过层间绝缘层1124中的第一过孔1127分别与半导体有源图案1121接触。在另一些示例中，薄膜晶体管112还包括设置于半导体有源图案1121和栅极1123之间的第一栅绝缘层位于薄膜晶体管112所在区域的部分。在此情况下，源极1125和漏极1126通过贯穿层间绝缘层1124和第一栅绝缘层中的第一过孔1127分别与半导体有源图案1121接触。
每个发光功能层1113位于对应的一个阳极1112和所述阴极14之间。阳极1112通过平坦层1111上的第二过孔1114与像素驱动电路连接。发光功能层1113、位于该发光功能层1113两侧的阳极1112和阴极14构成一个发光器件。
在一些示例中，该发光功能层1113包括发光层。在另一些示例中，发光功能层1113除包括发光层外，还包括电子传输层(electron transporting layer，简称ETL)、电子注入层(electron injection layer，简称EIL)、空穴传输层(hole transporting layer，简称HTL)以及空穴注入层(hole injection layer，简称HIL)。电子传输层和电子注入层设置于发光层和阴极14之间，且电子注入层相对电子传输层更靠近阴极14。空穴传输层和空穴注入层设置于发光层和阳极1112之间，且空穴注入层相对空穴传输层更靠近阳极1112。在此基础上，所有发光器件中的电子传输层可位于同一层，所有发光器件中的电子注入层可位于同一层，所有发光器件中的空穴传输层可位于同一层，所有发光器件中的空穴注入层可位于同一层。
如图2A所示，显示区11包括多个亚像素区110，每个像素驱动电路和与其电连接的一个发光元件设置于对应的一个亚像素区110中。
需要说明的是，图5以薄膜晶体管112为顶栅型薄膜晶体管进行示意，但本公开实施例并不限于此，薄膜晶体管112也可以为底栅型薄膜晶体管或双栅型薄膜晶体管等任意一种。对于双栅型薄膜晶体管，如 图6所示，薄膜晶体管112还包括设置于半导体有源图案1121靠近衬底13一侧的第二栅绝缘层1128位于薄膜晶体管112所在区域的部分、以及设置于第二栅绝缘层1128靠近衬底13一侧的第二栅极1129。
此外，本公开实施例不对像素驱动电路中多个薄膜晶体管112的数量进行限定，例如多个薄膜晶体管112的数量为2个，又例如，多个薄膜晶体管112是5个，又例如，多个薄膜晶体管112是7个。此外，图5和图6仅以像素驱动电路中的一个薄膜晶体管112进行示意。
在一些示例中，像素驱动电路中每个薄膜晶体管112的结构均为图5和图6所示的结构，具体参见上述说明，在此不再赘述。
平坦层1111和层间绝缘层1124均由显示区11延伸至周边区12，且上述至少一层绝缘层包括平坦层1111和层间绝缘层1124。在至少一层绝缘层包括两层绝缘层的情况下，该两层绝缘层分别为平坦层1111和层间绝缘层1124。相应的，在阴极阻断结构16包括沿衬底13厚度方向层叠且连通的第一子凹槽1611和第二子凹槽1612的情况下，第一子凹槽1611设置于平坦层1111中并贯穿平坦层1111，第二子凹槽1612设置于层间绝缘层1124中。
在一些示例中，第二子凹槽1612贯穿层间绝缘层1124。在另一些示例中，如图5和图6所示，第二子凹槽1612未贯穿层间绝缘层1124。即，沿衬底13的厚度方向，第二子凹槽1612的深度小于层间绝缘层1124的厚度。
在一些示例中，沿衬底13的厚度方向，第一子凹槽1611的深度范围为0.3～2μm。例如，第一子凹槽161的深度为0.3μm、0.6μm、0.9μm、1μm、1.5μm、或者2μm。
在一些示例中，沿衬底13的厚度方向，第二子凹槽1612的深度范围为0.2～5μm，例如，第二子凹槽1612的深度为0.2μm、0.5μm、0.8μm、1μm、1.5μm、2μm、3μm、4μm、或5μm。
在一些示例中，在设置有阴极阻断结构16的显示区11的每一边界一侧，沿垂直该边界的方向，第二子凹槽1612的宽度为5～50μm，第一子凹槽1611的宽度为2～40μm。
例如，第二子凹槽1612的宽度为5μm、10μm、13μm、20μm、30μm、40μm、或50μm。又例如，第一子凹槽1611的宽度为2μm、6μm、10μm、13μm、20μm、30μm、或40μm。
本公开一些实施例提供一种显示装置，包括显示面板1。
该显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
本公开一些实施例提供一种显示面板1的制备方法，包括：在衬底13上形成至少一个显示单元10，每个显示单元10包括显示区11以及环绕显示区11的周边区12。
如图9所示，形成显示单元10，包括：
S10：如图1B和图1C所示，在衬底13上形成位于周边区12的至少一个阴极阻断结构16。
至少一个阴极阻断结构16的设置方式可参考前述描述，在此不再赘述。
S11：如图1B和图1C所示，在形成有所述至少一个阴极阻断结构16的衬底13上，形成阴极14；阴极14位于显示区11以及周边区12，并且阴极14在所述至少一个阴极阻断结构位置16处断开。
S12：如图1B和图1C所示，在阴极14远离衬底13的一侧，形成薄膜封装层15；薄膜封装层15覆盖阴极14，且薄膜封装层15的边缘超出阴极14的边缘。
在一些实施例中，如图4所示，至少一个阴极阻断结构16为形成于至少一层绝缘层中的凹槽161；在形成有阴极阻断结构16的显示区11的每一边界一侧，凹槽161被该边界的垂直面所截得的截面为倒T形。
在一些实施例中，如图5和图6所示，在形成阴极14之前，形成所述显示单元，还包括：
S20：在衬底13上且位于显示区11形成多个像素驱动电路；像素驱动电路包括多个薄膜晶体管112，多个薄膜晶体管112中的至少一个薄膜晶体管112包括依次形成于衬底13上的半导体有源图案1121、栅极1123、层间绝缘层1124位于薄膜晶体管112所在区域的部分、以及源极1125和漏极1126；源极1125和漏极1126至少通过层间绝缘层1124中的第一过孔1127与半导体有源图案1121接触。
关于薄膜晶体管112以及像素驱动电路的结构可参考前述描述。
S21：在形成有多个像素驱动电路的衬底13上，形成平坦层1111。
S22：在平坦层1111远离衬底13一侧形成多个阳极1112以及多个发光功能层1113，每个发光功能层1113位于对应的一个阳极1112和所述阴极14之间；阳极1112通过平坦层1111中的第二过孔1114与像素驱动电路连接。
基于此，上述至少一层绝缘层包括层间绝缘层1124和平坦层1111；阴极阻断结构16包括沿衬底13厚度方向层叠且连通的第一子凹槽1611和第二子凹槽1612，第一子凹槽1611位于平坦层1111中且贯穿平坦层1111，第二子凹槽1612位于层间绝缘层1124中。示例的，第一子凹槽1611与第二子凹槽1612可以通过刻蚀工艺形成。
在一些示例中，沿衬底13的厚度方向，第一子凹槽1611的深度范围为0.3～2μm，例如为0.6μm。第二子凹槽1612的深度范围为0.2～5um，例如为0.8μm。
在另一些示例中，在设置有阴极阻断结构16的显示区11的每一边界一侧，沿垂直该边界的方向，第二子凹槽1612的宽度范围为5～50um，例如为13μm。第一子凹槽1611的宽度范围为2～40μm，例如为6μm。
在一些实施例中，在形成层间绝缘层1124之后，形成平坦层1111之前，形成所述显示单元，还包括：
如图10和11所示，在层间绝缘层1124中的第二子凹槽1612中填充光刻胶1612a，使光刻胶1612a远离衬底13的表面与层间绝缘层1124的远离衬底13的表面齐平。
如图11所示，对光刻胶1612a进行曝光。
在一些实施例中，在形成包括第一子凹槽1611的平坦层1111之后，对填充在第二子凹槽1612中的光刻胶1612a进行显影之前，形成显示单元，还包括：
如图13-图15所示，在周边区12形成挡墙18，在形成有阴极阻断结构16和挡墙18的显示区11的每一边界一侧，挡墙18位于阴极阻断结构16远离显示区11的一侧；在形成有挡墙18的显示区11的每一边界的一侧，挡墙18被该边界的垂直面所截得的截面为倒梯形。
在一些示例中，如图13所示，在平坦层1111中形成第一子凹槽1611与第二过孔1114的同时，还在平坦层1111中形成位于周边区12的凹陷部163。凹陷部163在衬底13上的正投影与挡墙18在衬底13 上的正投影重叠。示例的，凹陷部163可通过刻蚀工艺形成。
在一些示例中，在将填充在第二子凹槽1612中的光刻胶1612a进行显影之前，形成所述显示单元，还包括：
如图14-图16所示，在凹陷部163中填充第二有机填充图案164，并进行固化。第二有机填充图案164的远离衬底13的表面与平坦层1111远离衬底13的表面齐平；第二有机填充图案164包括有机材料和掺杂于有机材料中的干燥剂；挡墙18与第二有机填充图案164的远离衬底13的表面接触。
在上述基础上，在一些实施例中，在形成包括第一子凹槽1611的平坦层1111之后，形成阴极14之前，形成所述显示单元，还包括：
如图15和图16所示，将填充在第二子凹槽1612中的光刻胶1612a进行显影。
如图16所示，对填充在第二子凹槽1612中的光刻胶1612a进行显影后，第一子凹槽1611和第二子凹槽1612共同构成阴极阻断结构16。
在一些实施例中，在形成阴极14之后，形成薄膜封装层之前，形成所述显示单元，还包括：
如图17和图18所示，在阴极阻断结构16位置处，填充第一有机填充图案162，并进行固化；第一有机填充图案162的远离衬底13的表面与平坦层1111远离衬底13的表面齐平；第一有机填充图案162包括有机材料和掺杂于有机材料中的干燥剂。
在本公开一些实施例提供的显示面板1的制备方法中，通过在周边区12设置阴极阻断结构16，使阴极14在阴极阻断结构16位置处断开而将阴极14分成主体部分和边缘部分，主体部分位于阴极阻断结构16靠近显示区11的一侧，且主体部分覆盖显示区11。相比于未设置阴极阻断结构16的情况下阴极14的侧面与封装薄膜层15的对应侧面之间的距离，阴极阻断结构16的设置使得阴极14中主体部分的朝向阴极阻断结构16的侧面与封装薄膜层15的对应侧面之间的距离增大，从而增加了水氧入侵到主体部分的路径，保证了封装的信赖性。在此基础上，考虑到在蒸镀形成阴极14时，存在对位精度的问题，为保证在对位精度较低的情况下，上述主体部分也能形成在预定的区域，可以通过增大阴极14的蒸镀面积来实现。而阴极阻断结构16的设置，即使阴极14整体的尺寸较大，也可保证封装信赖性。
可选的，衬底13包括彼此分隔开的多个岛131、以及将多个岛131连接起来的多个桥132。每个岛131所在区域为一个显示单元10所在区域。
可选的，在形成阴极阻断结构16之后，形成阴极14之前，显示面板1的制备方法还包括：在衬底13上且位于周边区12形成连接电极17，连接电极17位于岛131上、且位于阴极阻断结构16靠近显示区11的一侧。
连接电极17与阴极14直接连接，设置于不同岛131上的任意两个连接电极17通过位于一个桥132上的连接线电连接。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种显示面板，包括：
    衬底；
    设置于所述衬底上的至少一个显示单元，一个显示单元具有显示区以及围绕所述显示区的周边区；所述显示单元，包括：
    设置于所述衬底上的阴极；所述阴极位于所述显示区以及所述周边区；
    设置于所述衬底上的薄膜封装层；所述薄膜封装层设置于所述阴极远离所述衬底的一侧，所述薄膜封装层覆盖所述阴极，且所述薄膜封装层的边缘超出所述阴极的边缘；
    设置于所述阴极靠近所述衬底一侧的至少一个阴极阻断结构；所述至少一个阴极阻断结构设置于所述周边区，每个阴极阻断结构被配置为使所述阴极在所述阴极阻断结构位置处断开。
  2. 根据权利要求1所述的显示面板，其中，每个阴极阻断结构围绕所述显示区设置。
  3. 根据权利要求1或2所述的显示面板，所述至少一个阴极阻断结构包括多个阴极阻断结构，所述多个阴极阻断结构间隔设置。
  4. 根据权利要求1所述的显示面板，其中，所述衬底包括彼此分隔开的多个岛、以及将所述多个岛连接起来的多个桥；每个岛所在区域为所述显示单元所在的区域；所述显示单元，还包括：
    设置于所述衬底上的连接电极；所述连接电极位于所述周边区，所述连接电极设置在所述阴极靠近所述衬底的一侧且所述连接电极与所述阴极直接连接；与所述连接电极设置于所述显示区同一侧的任一个阴极阻断结构，设置于所述连接电极远离所述显示区的一侧；其中，
    设置于不同岛上的任意两个连接电极通过设置于一桥上的连接线电连接。
  5. 根据权利要求1-4任一项所述的显示面板，其中，每个阴极阻断结构为设置于至少一层绝缘层中的凹槽；在设置有所述阴极阻断结构的所述显示区的每一边界一侧，所述凹槽被该边界的垂直面所截得的截面为倒T形。
  6. 根据权利要求5所述的显示面板，其中，所述显示单元还包括：
    至少一个第一有机填充图案，每个第一有机填充图案填充于对应的一个阴极阻断结构位置处，且所述第一有机填充图案的远 离所述衬底的表面与所述至少一层绝缘层远离所述衬底的表面齐平。
  7. 根据权利要求6所述的显示面板，其中，所述第一有机填充图案包括有机材料和掺杂于有机材料中的干燥剂。
  8. 根据权利要求5所述的显示面板，其中，所述至少一层绝缘层包括层叠设置的两层绝缘层；
    所述阴极阻断结构包括沿所述衬底厚度方向层叠且连通的第一子凹槽和第二子凹槽，所述第一子凹槽和所述第二子凹槽分别设置于所述两层绝缘层中。
  9. 根据权利要求8所述的显示面板，其中，所述显示单元还包括：
    设置于所述衬底上且位于所述显示区的多个像素驱动电路；所述像素驱动电路包括多个薄膜晶体管，所述多个薄膜晶体管中的至少一个薄膜晶体管包括依次设置于所述衬底上的半导体有源图案、栅极、层间绝缘层位于所述薄膜晶体管所在区域的部分、源极和漏极，所述源极和所述漏极至少通过所述层间绝缘层中的第一过孔分别与所述半导体有源图案接触；
    设置于所述多个像素驱动电路远离所述衬底一侧的平坦层；
    设置于所述平坦层远离所述衬底一侧的多个阳极以及多个发光功能层，每个发光功能层位于对应的一个阳极和所述阴极之间；所述阳极通过所述平坦层中的第二过孔与所述像素驱动电路连接；其中，
    所述两层绝缘层分别为所述层间绝缘层和所述平坦层。
  10. 根据权利要求1-9任一项所述的显示面板，其中，所述显示单元还包括：
    设置于所述薄膜封装层靠近所述衬底一侧的挡墙，所述挡墙设置于所述周边区中；在设置有所述阴极阻断结构和所述挡墙的所述显示区的每一边界一侧，所述挡墙位于所述阴极阻断结构远离所述显示区的一侧；其中，
    在设置有所述挡墙的所述显示区的每一边界的一侧，所述挡墙被该边界的垂直面所截得的截面为倒梯形。
  11. 根据权利要求10所述的显示面板，其中，所述阴极阻断结构为设置于至少一层绝缘层中的凹槽；
    所述显示单元还包括：
    设置于所述至少一层绝缘层中的凹陷部，所述凹陷部在所述衬底上的正投影与所述挡墙在所述衬底上的正投影重叠；
    第二有机填充图案，填充在所述凹陷部中；所述第二有机填充图案的远离所述衬底的表面与所述至少一层绝缘层中远离所述衬底的表面齐平；所述挡墙设置于所述第二有机填充图案的远离所述衬底的表面上。
  12. 根据权利要求11所述的显示面板，其中，所述第二有机填充图案包括有机材料和掺杂于有机材料中的干燥剂。
  13. 一种显示装置，包括如权利要求1-12任一项所述的显示面板。
  14. 一种显示面板的制备方法，包括：
    在衬底上形成至少一个显示单元，每个显示单元包括显示区以及环绕所述显示区的周边区；其中，形成所述显示单元，包括：
    在衬底上形成位于所述周边区的至少一个阴极阻断结构；
    在形成有所述至少一个阴极阻断结构的所述衬底上，形成阴极；所述阴极位于所述显示区以及所述周边区，并且所述阴极在所述至少一个阴极阻断结构位置处断开；
    在所述阴极远离所述衬底一侧，形成薄膜封装层；所述薄膜封装层覆盖所述阴极，且所述薄膜封装层的边缘超出所述阴极的边缘。
  15. 根据权利要求14所述的制备方法，其中，每个阴极阻断结构为形成于至少一层绝缘层中的凹槽；在形成有所述阴极阻断结构的所述显示区的每一边界一侧，所述凹槽被该边界的垂直面所截得的截面为倒T形。
  16. 根据权利要求15所述的制备方法，其中，在形成所述阴极之前，形成所述显示单元，还包括：
    在所述衬底上且位于所述显示区形成多个像素驱动电路；所述多个像素驱动电路中的至少一个像素驱动电路包括多个薄膜晶体管，所述多个薄膜晶体管中的至少一个薄膜晶体管包括依次形成于所述衬底上的半导体有源图案、栅极、层间绝缘层位于所述薄膜晶体管所在区域的部分、以及源极和漏极；所述源极和所述漏极至少通过所述层间绝缘层中的第一过孔与所述半导体有源图案接触；
    在形成有所述多个像素驱动电路的衬底上，形成平坦层；
    在所述平坦层远离所述衬底的一侧形成多个阳极以及多个发光功能层，每个发光功能层位于对应的一个阳极和所述阴极之间；所述阳极 通过所述平坦层中的第二过孔与所述像素驱动电路连接；其中，
    所述至少一层绝缘层包括所述层间绝缘层和所述平坦层；所述阴极阻断结构包括沿所述衬底厚度方向层叠且连通的第一子凹槽和第二子凹槽，所述第一子凹槽位于所述平坦层中且贯穿所述平坦层，所述第二子凹槽位于所述层间绝缘层中。
  17. 根据权利要求16所述的制备方法，其中，在形成所述层间绝缘层之后，形成所述平坦层之前，形成所述显示单元，还包括：
    在所述层间绝缘层中的所述第二子凹槽中填充光刻胶，使光刻胶远离所述衬底的表面与所述层间绝缘层的远离所述衬底的表面齐平；
    对光刻胶进行曝光；
    在形成所述平坦层之后，形成所述阴极之前，形成所述显示单元，还包括：
    将填充在所述第二子凹槽中的光刻胶进行显影。
  18. 根据权利要求17所述的制备方法，其中，在形成所述阴极之后，形成所述薄膜封装层之前，形成所述显示单元，还包括：
    在所述阴极阻断结构位置处，填充第一有机填充图案，并进行固化；所述第一有机填充图案的远离所述衬底的表面与所述平坦层远离所述衬底的表面齐平；所述第一有机填充图案包括有机材料和掺杂于所述有机材料中的干燥剂。
  19. 根据权利要求17所述的制备方法，其中，在形成所述平坦层之后，对填充在所述第二子凹槽中的光刻胶进行显影之前，形成所述显示单元，还包括：
    在所述周边区形成挡墙，在形成有所述阴极阻断结构和所述挡墙的所述显示区的每一边界一侧，所述挡墙位于所述阴极阻断结构远离所述显示区的一侧；其中，在形成有所述挡墙的所述显示区的每一边界的一侧，所述挡墙被该边界的垂直面所截得的截面为倒梯形。
  20. 根据权利要求19所述的显示面板的制备方法，其中，在所述平坦层中形成所述第一子凹槽与所述第二过孔的同时，还在所述平坦层中形成位于所述周边区的凹陷部；所述凹陷部在所述衬底上的正投影与所述挡墙在所述衬底上的正投影重叠；
    在将填充在所述第二子凹槽中的光刻胶进行显影之前，形成所述显示单元，还包括：
    在所述凹陷部中填充第二有机填充图案，并进行固化；所述第二有 机填充图案的远离所述衬底的表面与所述平坦层远离所述衬底的表面齐平；所述第二有机填充图案包括有机材料和掺杂于所述有机材料中的干燥剂；所述挡墙与所述第二有机填充图案的远离所述衬底的表面接触。
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