WO2021056958A1 - 反熔丝存储单元电路、阵列电路及其读写方法 - Google Patents

反熔丝存储单元电路、阵列电路及其读写方法 Download PDF

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Publication number
WO2021056958A1
WO2021056958A1 PCT/CN2020/076311 CN2020076311W WO2021056958A1 WO 2021056958 A1 WO2021056958 A1 WO 2021056958A1 CN 2020076311 W CN2020076311 W CN 2020076311W WO 2021056958 A1 WO2021056958 A1 WO 2021056958A1
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Prior art keywords
unit
switch
coupled
module
fuse
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PCT/CN2020/076311
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English (en)
French (fr)
Inventor
李新
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长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/432,808 priority Critical patent/US11887682B2/en
Priority to EP20869974.4A priority patent/EP3926634B1/en
Publication of WO2021056958A1 publication Critical patent/WO2021056958A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/06—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using diode elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory

Definitions

  • the invention relates to the field of integrated circuits, in particular to an anti-fuse memory cell circuit, an array circuit and a reading and writing method thereof.
  • OTP memory can store data in multiple OTP cells with two states: unprogrammed or programmed.
  • the OTP unit may include a fuse or an anti-fuse, and once the fuse or anti-fuse is programmed, the stored data is permanent. Because of this feature, OTP memory is used in various applications to store data.
  • OTP is used to control the opening or closing of redundancy memory cells. For example, when a memory cell corresponding to a word line is defective, the corresponding OTP cell will be programmed (the output state of the OTP cell is changed by " 0" to "1"), the DRAM control circuit will close the reading and writing of this storage unit, and open the reading and writing of a storage unit in the redundant area. At this time, the storage unit corresponding to the redundant area has completely replaced the existing storage unit. Defective memory cells, DRAM defects are repaired.
  • the current one-time programmable memory has the following problems: 1. The problem of large static power consumption of the one-time programmable memory; 2. The problem of poor reliability of the read-out circuit of the one-time programmable memory; 3. The complicated problem of the control circuit of the one-time programmable memory; 4 , One-time programmable memory layout layout is not flexible.
  • the technical problem to be solved by the present invention is to provide an anti-fuse memory cell circuit, an array circuit and a reading and writing method thereof, which have lower static power consumption, high reliability of the readout circuit, simple structure and flexible wiring.
  • an anti-fuse memory cell circuit which includes:
  • a switch module coupled to the anti-fuse device
  • a selection module coupled to the switch module
  • a control module respectively coupled to the anti-fuse device and the switch module
  • control module is configured to switch the on-off mode of the switch module according to the breakdown state of the anti-fuse device.
  • the anti-fuse device has a first end and a second end
  • the switch module includes a first switch unit and a second switch unit, and both the first switch unit and the second switch unit have a first end , A second end and a control end, and the control ends are all coupled to the control module, the second ends are all coupled to the selection module, and the first end of the first switch unit is coupled to the inverter The first end of the fuse device, and the first end of the second switch unit is coupled to the second end of the anti-fuse device.
  • the switch module further includes a third switch unit having a first end, a second end and a control end, and the first end of the third switch unit is coupled to the anti-fuse device
  • the second end of the third switch unit is coupled to the ground signal
  • the control end of the third switch unit is coupled to the control module.
  • the selection module includes a bit line selection unit and a word line selection unit. Both the bit line selection unit and the word line selection unit have a first end, a second end and a control end.
  • the control terminal is coupled to the bit line
  • the first terminal of the bit line selection unit is coupled to the second terminal of the second switch unit
  • the second terminal of the bit line selection unit is coupled to the ground signal
  • the The control end of the word line selection unit is coupled to the word line
  • the first end of the word line selection unit is coupled to the second end of the first switch unit
  • the second end of the word line selection unit is coupled to Power signal.
  • the anti-fuse memory cell circuit further includes a current supply module having a first end and a second end, the first end of the current supply module is coupled to the power signal, and the second end is coupled to the word line Select the second end of the unit.
  • control module includes a control unit, the control unit has an input end and an output end, the input end is coupled to the first end of the anti-fuse device, write enable signal, read enable signal, read The delay signal is enabled, and the output terminal is coupled to the switch module.
  • control module further includes an amplifying unit having an input terminal and an output terminal, the input terminal is coupled to the first terminal of the anti-fuse device, and the output terminal is coupled to the control The input end of the unit, and the amplifying unit is used to amplify the signal at the first end of the anti-fuse device.
  • control module further includes a delay unit, the delay unit has an input terminal and an output terminal, the read enable signal is also coupled to the input terminal of the delay unit, and the output of the delay unit The terminal is coupled to the control unit, and the delay unit is used to delay the read enable signal to form the read enable delay signal.
  • the present invention also provides an anti-fuse memory array circuit, which includes:
  • At least one control module At least one control module
  • At least one anti-fuse memory cell circuit includes:
  • a switch module coupled to the anti-fuse device
  • a selection module coupled to the switch module
  • the control module is respectively coupled to the anti-fuse device and the switch module of the anti-fuse memory unit circuit, and the control module is configured to switch the anti-fuse device according to the breakdown state of the anti-fuse device.
  • the on-off mode of the switch module is respectively coupled to the anti-fuse device and the switch module of the anti-fuse memory unit circuit, and the control module is configured to switch the anti-fuse device according to the breakdown state of the anti-fuse device.
  • the on-off mode of the switch module is respectively coupled to the anti-fuse device and the switch module of the anti-fuse memory unit circuit, and the control module is configured to switch the anti-fuse device according to the breakdown state of the anti-fuse device.
  • control module is a master control module, which is respectively coupled to the anti-fuse device and the switch module of each of the anti-fuse storage unit circuits.
  • the master control module includes a control unit having an input terminal and an output terminal, and the input terminal is respectively coupled to the first of the anti-fuse device of each of the anti-fuse memory unit circuits.
  • the output terminal is respectively coupled to the switch module of each of the anti-fuse memory cell circuits.
  • the anti-fuse memory array circuit includes a plurality of the control modules, and one control module is coupled to at least the anti-fuse device and the switch module of one of the anti-fuse memory unit circuits.
  • the anti-fuse memory array circuit further includes at least one current supply module, and at least some of the anti-fuse memory cell circuits share the same current supply module.
  • the anti-fuse memory array circuit further includes at least one word line selection unit, and at least some of the anti-fuse memory cell circuits share the same word line selection unit.
  • the present invention also provides a method for reading and writing an anti-fuse memory cell circuit as described above, which includes:
  • control module controls the switch module to be in the first state to perform a write operation on the anti-fuse device
  • control module controls the switch module to be in the second state, so as to reduce the power consumption of the anti-fuse device
  • control module controls the switch module to be in the third state to perform a read operation on the anti-fuse device.
  • the selection module is turned on, in standby, the selection module is turned off, and in normal operation, the selection module is turned on.
  • the anti-fuse device has a first end and a second end
  • the switch module includes a first switch unit and a second switch unit, and both the first switch unit and the second switch unit have a first end , A second end and a control end, and the control ends are all coupled to the control module, the second ends are all coupled to the selection module, and the first end of the first switch unit is coupled to the inverter A first end of the fuse device, and the first end of the second switch unit is coupled to the second end of the anti-fuse device;
  • the first state of the switch module is: the first switch unit and the second switch unit are open;
  • the second state of the switch module is: the first switch unit and the second switch unit are turned off;
  • the third state of the switch module is: if the anti-fuse device is not broken down, the first switch unit is turned on, and the second switch unit is turned off; if the anti-fuse device is broken down, Then the first switch unit is closed, and the second switch unit is opened.
  • the switch module further includes a third switch unit having a first end, a second end and a control end, and the first end of the third switch unit is coupled to the anti-fuse device
  • the second end of the third switch unit is coupled to the ground signal, and the control end of the third switch unit is coupled to the control module;
  • the first state of the switch module is: the first switch unit and the second switch unit are open, and the third switch unit is closed;
  • the second state of the switch module is: the first switch unit and the second switch unit are closed, and the third switch unit is open;
  • the third state of the switch module is: if the anti-fuse device is not broken down, the control module controls the first switch unit to turn on, the second switch unit to turn off, and the third switch unit Closed; if the anti-fuse device is broken down, the control module controls the first switching unit to close, the second switching unit to open, and the third switching unit to close.
  • the anti-fuse memory cell circuit of the present invention is a pure combinational circuit. Compared with a sequential circuit, after a delay of a certain time, that is, after the read and write operation is completed, all paths are closed, and the entire circuit has no logic action, and the static power consumption is higher. Low, power consumption is approximately 0;
  • the anti-fuse memory cell circuit of the present invention essentially forms two positive feedback loops through the design of switches and logic operation modules, so that the readout circuit can read "0" or "1" more reliably;
  • the anti-fuse memory cell circuit of the present invention can omit the complicated timing control part, and even the output OUTA/OUTB of the readout circuit can be directly used as the code output of the anti-fuse without being latched.
  • the circuit layout of the anti-fuse memory cell of the present invention is flexible.
  • FIG. 1 is a circuit diagram of a specific embodiment of the anti-fuse memory cell circuit of the present invention
  • FIG. 2 is a circuit diagram of a first specific embodiment of an anti-fuse memory array circuit
  • FIG. 3 is a circuit diagram of a second specific embodiment of an anti-fuse memory array circuit
  • FIG. 4 is a circuit diagram of a third specific embodiment of the anti-fuse memory array circuit.
  • the anti-fuse storage unit circuit includes an anti-fuse device; a switch module, which is coupled to the anti-fuse device; a selection module, which is coupled to the switch module; and a control module, which is respectively coupled to the anti-fuse device.
  • the anti-fuse storage unit circuit of the present invention can control the opening and closing of the switch module according to the output of the anti-fuse device (ie, the storage state of the anti-fuse storage unit), thereby achieving the purpose of saving power consumption.
  • FIG. 1 is a circuit diagram of a specific embodiment of the anti-fuse memory cell circuit of the present invention. Please refer to FIG. 1, the anti-fuse memory cell circuit of the present invention includes an anti-fuse device C00, a switch module, a selection module, and a control module 12.
  • the anti-fuse device C00 has a first end and a second end. During programming, if the anti-fuse device C00 is broken down, the on-resistance is approximately 0 ohm; if the anti-fuse device C00 is not broken down, the on-resistance is approximately infinite ohm. In other words, the anti-fuse device C00 is non-conductive when it is not activated, but becomes a conductor after activation (breakdown), forming an electrical connection, and can selectively allow two devices or chips that are originally electrically isolated Make electrical connections and provide different resistance values for logic operations.
  • the switch module is coupled to the anti-fuse device C00.
  • the switch module includes a first switch unit MP2 and a second switch unit MN1. Both the first switch unit MP2 and the second switch unit MN1 have a first terminal, a second terminal and a control terminal.
  • the first switch unit MP2 is a P-type transistor
  • the second switch unit MN1 is an N-type transistor.
  • the control ends of the first switch unit MP2 and the second switch unit MN1 are both coupled to the control module 12. Specifically, the control terminal of the first switch unit MP2 is coupled to the first control signal CTRL_A of the control module 12, and the control terminal of the second switch unit MN1 is coupled to the second control signal CTRL_A of the control module 12. Control signal CTRL_B.
  • the second ends of the first switch unit MP2 and the second switch unit MN1 are both coupled to a selection module. Specifically, the second end of the first switch unit MP2 is coupled to the word line selection unit MP1 of the selection module, and the second end of the second switch unit MN1 is coupled to the bit line of the selection module Select cell MN2.
  • the first end of the first switch unit MP2 is coupled to the first end of the anti-fuse device C00, and the first end of the second switch unit MN1 is coupled to the second end of the anti-fuse device C00. end.
  • the readout circuit of the anti-fuse memory cell After the readout circuit of the anti-fuse memory cell reads the programming result, if the anti-fuse device C00 is broken down, the pull-up of the anti-fuse memory cell is turned off, and if the anti-fuse device C00 is not hit Wear, the pull-up of the anti-fuse memory cell is maintained. After the readout circuit of the anti-fuse memory cell reads the programming result, if the anti-fuse device C00 is broken down, the pull-down of the anti-fuse memory cell is maintained. If the anti-fuse device C00 is not broken down, Then turn off the pull-down of the anti-fuse memory cell.
  • the switch module further includes a third switch unit MN0, and the third switch unit MN0 has a first terminal, a second terminal, and a control terminal.
  • the first end of the third switch unit MN0 is coupled to the first end of the anti-fuse device C00, the second end of the third switch unit MN0 is coupled to the ground signal, and the third switch unit MN0
  • the control terminal of is coupled to the third control signal CTRL_A of the control module 12.
  • the third switch unit MN0 is an N-type transistor.
  • the third switch unit MN0 is used to pull the first-level output node OUTA of the anti-fuse memory unit to the ground when the one-time programmable memory is not working, and is also used to limit the first-level output node OUTA when the one-time programmable memory is working. Initial working state.
  • the selection module includes a bit line selection unit MN2 and a word line selection unit MP1. Both the bit line selection unit MN2 and the word line selection unit MP1 have a first end, a second end and a control end.
  • the bit line selection unit MN2 may be an N-type transistor
  • the word line selection unit MP1 may be a P-type transistor.
  • the control end of the bit line selection unit MN2 is coupled to the bit line BL00, the first end of the bit line selection unit MN2 is coupled to the second end of the second switch unit MN1, and the bit line selection unit MN2 The second end of is coupled to the ground signal.
  • the control end of the word line selection unit MP1 is coupled to the word line WL00, the first end of the word line selection unit MP1 is coupled to the second end of the first switch unit MP2, and the word line selection unit MP1 The second end of is coupled to the power signal.
  • bit line selection unit MN2 can all control the on-off of the anti-fuse memory cell, and play a role in protecting the anti-fuse device C00.
  • the anti-fuse memory cell circuit further includes a current supply module MP0, which has a first end and a second end, the first end of the current supply module MP0 is coupled to the power signal, and the second end is coupled to all The second end of the word line selection unit MP1. That is, the second end of the word line selection unit MP1 is coupled to a power signal through the current supply module MP0.
  • the current supply module MP0 is used as a mirror current source.
  • the current supply module MP0 can control the magnitude of the current flowing through the anti-fuse device C00. In normal operation, the current supply module MP0 can control the anti-fuse device C00.
  • the pull-up capability of the fuse memory cell Wherein, the current supply module MP0 can be a P-type transistor.
  • the control module 12 includes a control unit 121, an amplifying unit 122 and a delay unit 123.
  • the control unit 121 is used for receiving signals and outputting control signals. Specifically, the control unit 121 has an input terminal and an output terminal. The input terminal is coupled to the first terminal of the anti-fuse device C00 through the amplifying unit 122, a write enable signal En_W, and a read enable The signal En_R and the read enable delay signal En_R_DLY, the output terminal is coupled to the switch module, and output a first control signal CTRL_A, a second control signal CTRL_B, and a third control signal CTRL_C.
  • the first control signal CTRL_A is coupled to the control terminal of the first switch unit MP2
  • the second control signal CTRL_B is coupled to the control terminal of the second switch unit MN1
  • the third control signal CTRL_C is coupled to The control terminal of the third switch unit MN0.
  • the amplifying unit 122 has an input terminal and an output terminal.
  • the input terminal is coupled to the first-level output node OUTA of the anti-fuse device C00 for connecting the first-level output node OUTA of the anti-fuse device C00
  • the state is amplified as the state of the secondary output OUTB, which can avoid logic errors in the subsequent digital circuits and improve the reliability of the readout circuit.
  • the output terminal is coupled to the input terminal of the control unit 121 to input the secondary output OUTB of the anti-fuse device C00 to the input terminal of the control unit 121.
  • the amplifying unit 122 is composed of two inverters.
  • the delay unit 123 is used to generate the read enable delay signal En_R_DLY. Specifically, in addition to being coupled to the control unit 121, the read enable signal En_R is also coupled to the delay unit 123. The delay unit 123 delays the read enable signal En_R and then outputs the Read enable delay signal En_R_DLY.
  • the delay unit 123 may be formed by connecting an even number of inverters in series, or the delay unit 123 may be an RC delay circuit.
  • the delay time Td is a minimum of 4 inverter delays, and the amplification unit 122 can complete the amplification of OUTA during Td.
  • the present invention also provides a specific implementation of the method for reading and writing the above-mentioned anti-fuse memory cell circuit. Please refer to Table 1:
  • the programming method is that the control module controls the switch module to be in the first state to perform a write operation on the anti-fuse device. Examples are as follows:
  • the standby method is that the control module controls the switch module to be in the second state, so as to reduce the power consumption of the anti-fuse device. Examples are as follows:
  • the static power consumption of the anti-fuse memory cell is approximately 0, and the default output of OUTB is "0".
  • control module controls the switch module to be in the third state to perform a read operation on the anti-fuse device. Examples are as follows:
  • the first P-type transistor MP0, the first selection transistor MP1 and the first switch tube MP2 will pull OUTA up to "1"; if the anti-fuse is The device C00 is broken down, the on-resistance of the anti-fuse device C00 is approximately 0 ohm, and the second switch tube MN1 and the second selection transistor MN2 will maintain OUTA at “0”. 3.
  • the anti-fuse memory cell circuit of the present invention is a pure combinational circuit. Compared with a sequential circuit, all paths are closed after a Td delay, and the entire circuit has no logic action, the static power consumption is lower, and the power consumption is approximately 0;
  • the inventive anti-fuse memory cell circuit essentially forms two positive feedback loops through the design of the switch and the logic operation module, so that the readout circuit can read "0" or "1" more reliably; at the same time, the present invention is anti-fuse
  • the wire storage unit circuit can save the complicated timing control part, and even the output OUTA/OUTB of the readout circuit can be directly used as the code output of the anti-fuse without being latched.
  • the internal structure of the logic operation unit LOGIC circuit is as follows:
  • CTRL_A (!EN_W)&&((!EN_R)&&(!EN_R_DLY)
  • CTRL_B EN_W&&(!EN_R)&&(!EN_R_DLY)
  • CTRL_C (!EN_W)&&(!EN_R)
  • FIG. 2 is a circuit diagram of a first specific embodiment of an anti-fuse memory array circuit.
  • the anti-fuse memory array circuit includes at least one control module and a plurality of anti-fuse memory cell circuits.
  • the anti-fuse storage unit circuit includes: an anti-fuse device, a switch module, and a selection module.
  • the anti-fuse device, switch module, and selection module are the same as the anti-fuse device, switch module, and switch module of the anti-fuse storage unit circuit.
  • the selection module structure is the same.
  • the control module is respectively coupled to the anti-fuse device and the switch module of the anti-fuse memory unit circuit, and the control module is configured to switch the anti-fuse device according to the breakdown state of the anti-fuse device.
  • the on-off mode of the switch module is respectively coupled to the anti-fuse device and the switch module of the anti-fuse memory unit circuit, and the control module is configured to switch the anti-fuse device according to the breakdown state of the anti-fuse device.
  • the on-off mode of the switch module is respectively coupled to the anti-fuse device and the switch module of the anti-fuse memory unit circuit, and the control module is configured to switch the anti-fuse device according to the breakdown state of the anti-fuse device.
  • control module is a master control module, which is respectively coupled to the anti-fuse device and the switch module of each of the anti-fuse memory unit circuits.
  • the overall control module includes a control unit 121, the input of the control unit is coupled to the write enable signal EN_W, read enable signal EN_R and read enable delay signal EN_R_DLY and each of the anti-fuse device C00 The first end.
  • the anti-fuse memory cell circuit shares the write enable signal EN_W, the read enable signal EN_R, and the read enable delay signal EN_R_DLY to reduce the number of input lines, thereby reducing the area.
  • control unit outputs a control signal
  • control signal is coupled to the third switch unit MN0 of the anti-fuse memory unit, that is, the anti-fuse memory unit circuit shares the control unit's
  • the third control signal CTRL_C is used to reduce the number of control lines, thereby reducing the area.
  • the internal pure combinational logic can continue to be optimized to reduce the number of logic gates, thereby reducing the area.
  • FIG. 3 is a circuit diagram of a second specific embodiment of the anti-fuse memory array circuit.
  • the difference between the second embodiment and the first embodiment is that the anti-fuse memory array circuit further includes at least one current supply module MP0, and at least part of the anti-fuse memory cell circuits share Current supply module MP0.
  • the anti-fuse memory array circuit further includes at least one current supply module MP0, and at least part of the anti-fuse memory cell circuits share Current supply module MP0.
  • the current supply module MP0 acts as a current mirror to provide current and limit current, and the anti-fuse memory unit circuits share the current supply module MP0 to reduce the number of transistors and thereby reduce the area.
  • the anti-fuse memory array circuit further includes at least one word line selection unit MP1, and at least a part of the anti-fuse memory cell circuits share the word line selection unit MP1, for example, all of the anti-fuse memory cell circuits share the word line selection unit MP1.
  • the anti-fuse memory cell circuit shares the word line selection cell MP1.
  • the word line selection unit MP1 is a selection transistor controlled by a word line, and the word line selection unit MP1 shared by the anti-fuse memory cell circuit can reduce the number of transistors, thereby reducing the area.
  • FIG. 4 is a circuit diagram of a third specific embodiment of the anti-fuse memory array circuit. 4, the difference between the third embodiment and the second embodiment is that the control module includes an amplifying unit 122 composed of two inverters, wherein the amplifying unit 122 can be combined with the control unit 121 The circuits are combined to reduce the number of logic gates, thereby reducing the area. In other words, the function of the amplifying unit 122 is realized by the control unit 121.

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Abstract

一种反熔丝存储单元电路、阵列电路及其读写方法，包括：反熔丝器件；开关模块，耦接于所述反熔丝器件；选择模块，耦接于所述开关模块；控制模块（12），分别耦接于所述反熔丝器件和所述开关模块；其中，所述控制模块（12）用于根据所述反熔丝器件的击穿状态，切换所述开关模块的通断模式。反熔丝存储单元电路的优点在于：1、是纯组合电路，相比时序电路，在延迟若干时间之后，所有通路都被关闭，且整个电路没有逻辑动作，静态功耗更低，功耗近似为0；2、通过开关和逻辑运算模块的设计，实质上构成了两个正反馈回路，使得读出电路可以更可靠的读出"0"或"1"；3、省去复杂的时序控制部分，甚至读出电路的输出OUTA/OUTB可以不用锁存，直接作为反熔丝的编码输出。4、电路版图布局布线灵活。

Description

反熔丝存储单元电路、阵列电路及其读写方法
相关申请引用说明
本申请要求于2019年9月29日递交的中国专利申请号201910931356.X，申请名为“反熔丝存储单元电路、阵列电路及其读写方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本发明涉及集成电路领域，尤其涉及一种反熔丝存储单元电路、阵列电路及其读写方法。
背景技术
一次可编程(OTP，One Time Programmable)存储器可将数据存储在具有未编程或已编程两种状态的多个OTP单元中。OTP单元可包括熔丝或反熔丝，一旦熔丝或反熔丝被编程，所存储的数据是永久的。由于这个特性，OTP存储器被用于各种应用中以存储数据。在DRAM中，OTP用来控制冗余(redundancy)存储单元的打开或关断，例如当有一个字线对应的存储单元有缺陷时，对应的OTP单元将被编程(OTP单元的输出状态由“0”到“1”)，DRAM的控制电路将关闭对这个存储单元的读写，并将打开冗余区域的一个存储单元的读写，此时，冗余区域对应的存储单元完全取代了有缺陷的存储单元，DRAM的缺陷被修复。
目前的一次可编程存储器存在如下问题：1、一次可编程存储器静态功耗大的问题；2、一次可编程存储器读出电路可靠性差的问题；3、一次可编程存储器控制电路复杂的问题；4、一次可编程存储器版图布局布线不灵活的问题。
因此，如何克服上述问题，成为目前亟需解决的技术问题。
发明内容
本发明所要解决的技术问题是，提供一种反熔丝存储单元电路、阵列电路及其读写方法，其静态功耗更低，读出电路的可靠性高，且结构简单，布线灵活。
为了解决上述问题，本发明提供了一种反熔丝存储单元电路，其包括：
反熔丝器件；
开关模块，耦接于所述反熔丝器件；
选择模块，耦接于所述开关模块；
控制模块，分别耦接于所述反熔丝器件和所述开关模块；
其中，所述控制模块用于根据所述反熔丝器件的击穿状态，切换所述开关模块的通断模式。
进一步，所述反熔丝器件具有第一端和第二端，所述开关模块包括第一开关单元和第二开关单元，所述第一开关单元及所述第二开关单元均具有第一端、第二端和控制端，且所述控制端均耦接于所述控制模块，所述第二端均耦接于选择模块，所述第一开关单元的第一端耦接于所述反熔丝器件的第一端，所述第二开关单元的第一端耦接于所述反熔丝器件的第二端。
进一步，所述开关模块还包括第三开关单元，所述第三开关单元具有第一端、第二端及控制端，所述第三开关单元的第一端耦接于所述反熔丝器件的第一端，所述第三开关单元的第二端耦接于接地信号，所述第三开关单元的控制端耦接于所述控制模块。
进一步，所述选择模块包括位线选择单元和字线选择单元，所述位线选择单元和所述字线选择单元均具有第一端、第二端和控制端，所述位线选择单元的控制端耦接于位线，所述位线选择单元的第一端耦接于所述第二开关单元的第二端，所述位线选择单元的第二端耦接于接地信号，所述字线选择单元的控 制端耦接于字线，所述字线选择单元的第一端耦接于所述第一开关单元的第二端，所述字线选择单元的第二端耦接于电源信号。
进一步，所述反熔丝存储单元电路还包括电流提供模块，具有第一端和第二端，所述电流提供模块的第一端耦接于电源信号，第二端耦接于所述字线选择单元的第二端。
进一步，所述控制模块包括控制单元，所述控制单元具有输入端及输出端，所述输入端耦接于所述反熔丝器件的第一端、写使能信号、读使能信号、读使能延迟信号，所述输出端耦接于所述开关模块。
进一步，所述控制模块还包括放大单元，所述放大单元具有输入端及输出端，所述输入端耦接于所述反熔丝器件的第一端，所述输出端耦接于所述控制单元的输入端，所述放大单元用于将所述反熔丝器件第一端的信号放大。
进一步，所述控制模块还包括延时单元，所述延时单元具有输入端及输出端，所述读使能信号还耦接于所述延时单元的输入端，所述延时单元的输出端耦接于所述控制单元，所述延时单元用于对读使能信号进行延迟，形成所述读使能延迟信号。
本发明还提供一种反熔丝存储阵列电路，其包括：
至少一控制模块；
至少一反熔丝存储单元电路，所述反熔丝存储单元电路包括：
反熔丝器件；
开关模块，耦接于所述反熔丝器件；
选择模块，耦接于所述开关模块；
所述控制模块分别耦接于所述反熔丝存储单元电路的所述反熔丝器件和所述开关模块，所述控制模块用于根据所述反熔丝器件的击穿状态，切换所述 开关模块的通断模式。
进一步，所述控制模块为总控制模块，其分别耦接于每一个所述反熔丝存储单元电路的所述反熔丝器件和所述开关模块。
进一步，所述总控制模块包括控制单元，所述控制单元具有输入端及输出端，所述输入端分别耦接于每一个所述反熔丝存储单元电路的所述反熔丝器件的第一端、写使能信号、读使能信号、读使能延迟信号，所述输出端分别耦接于每一个所述反熔丝存储单元电路的所述开关模块。
进一步，所述反熔丝存储阵列电路包括多个所述控制模块，一个所述控制模块至少耦接于一个所述反熔丝存储单元电路的所述反熔丝器件和所述开关模块。
进一步，所述反熔丝存储阵列电路还包括至少一电流提供模块，至少部分所述反熔丝存储单元电路共用同一个所述电流提供模块。
进一步，所述反熔丝存储阵列电路还包括至少一字线选择单元，至少部分所述反熔丝存储单元电路共用同一个所述字线选择单元。
本发明还提供一种如上所述的反熔丝存储单元电路的读写方法，其包括：
在编程时，所述控制模块控制所述开关模块处于第一状态，以对所述反熔丝器件进行写操作；
在待机时：所述控制模块控制所述开关模块处于第二状态，以降低所述反熔丝器件的功耗；
在正常工作时：所述控制模块控制所述开关模块处于第三状态，以对所述反熔丝器件进行读操作。
进一步，在编程时，所述选择模块打开，在待机时，所述选择模块关闭，在正常工作时，选择模块打开。
进一步，所述反熔丝器件具有第一端和第二端，所述开关模块包括第一开关单元和第二开关单元，所述第一开关单元及所述第二开关单元均具有第一端、第二端和控制端，且所述控制端均耦接于所述控制模块，所述第二端均耦接于选择模块，所述第一开关单元的第一端耦接于所述反熔丝器件的第一端，所述第二开关单元的第一端耦接于所述反熔丝器件的第二端；
所述开关模块的第一状态为：所述第一开关单元及第二开关单元打开；
所述开关模块的第二状态为：所述第一开关单元及第二开关单元关闭；
所述开关模块的第三状态为：若所述反熔丝器件未被击穿，则所述第一开关单元打开，所述第二开关单元关闭；若所述反熔丝器件被击穿，则所述第一开关单元关闭，所述第二开关单元打开。
进一步，所述开关模块还包括第三开关单元，所述第三开关单元具有第一端、第二端及控制端，所述第三开关单元的第一端耦接于所述反熔丝器件的第一端，所述第三开关单元的第二端耦接于接地信号，所述第三开关单元的控制端耦接于所述控制模块；
所述开关模块的第一状态为：所述第一开关单元及第二开关单元打开，所述第三开关单元关闭；
所述开关模块的第二状态为：所述第一开关单元及第二开关单元关闭，所述第三开关单元打开；
所述开关模块的第三状态为：若所述反熔丝器件未被击穿，则所述控制模块控制所述第一开关单元打开，所述第二开关单元关闭，所述第三开关单元关闭；若所述反熔丝器件被击穿，则所述控制模块控制所述第一开关单元关闭，所述第二开关单元打开，所述第三开关单元关闭。
本发明的优点在于：
1、本发明反熔丝存储单元电路是纯组合电路，相比时序电路，在延迟若干时间之后，即完成读写操作后，所有通路都被关闭，且整个电路没有逻辑动作，静态功耗更低，功耗近似为0；
2、本发明反熔丝存储单元电路通过开关和逻辑运算模块的设计，实质上构成了两个正反馈回路，使得读出电路可以更可靠地读出“0”或“1”；
3、本发明反熔丝存储单元电路可以省去复杂的时序控制部分，甚至读出电路的输出OUTA/OUTB可以不用锁存，直接作为反熔丝的编码输出。
4、本发明反熔丝存储单元电路版图布局布线灵活。
附图说明
图1是本发明反熔丝存储单元电路的一具体实施方式的电路图；
图2是反熔丝存储阵列电路的第一具体实施方式的电路图；
图3是反熔丝存储阵列电路的第二具体实施方式的电路图；
图4是反熔丝存储阵列电路的第三具体实施方式的电路图。
具体实施方式
下面结合附图对本发明提供的反熔丝存储单元电路、阵列电路及其读写方法的具体实施方式做详细说明。
所述反熔丝存储单元电路包括反熔丝器件；开关模块，其耦接于所述反熔丝器件；选择模块，其耦接于所述开关模块；控制模块，分别耦接于所述反熔丝器件和所述开关模块；其中，所述控制模块用于根据所述反熔丝器件的击穿状态，切换所述开关模块的通断模式。本发明反熔丝存储单元电路能够根据所述反熔丝器件的输出(即，反熔丝存储单元的存储状态)来控制所述开关模块的开启及关闭，从而实现节省功耗的目的。图1是本发明反熔丝存储单元电路的一具体实施方式的电路图。请参阅图1，本发明反熔丝存储单元电路包括反 熔丝器件C00、开关模块、选择模块及控制模块12。
所述反熔丝器件C00具有第一端及第二端。在编程时，若所述反熔丝器件C00被击穿，导通电阻近似为0欧姆；若所述反熔丝器件C00未被击穿，导通电阻近似为无穷大欧姆。也就是说，所述反熔丝器件C00在未激活时是不导电的，而在激活(击穿)后变为导体，形成电连接，可以选择性地允许原本电学隔离的两个器件或芯片进行电学连接，且能提供用于进行逻辑操作的不同电阻值。
所述开关模块耦接于所述反熔丝器件C00。所述开关模块包括第一开关单元MP2和第二开关单元MN1，所述第一开关单元MP2及所述第二开关单元MN1均具有第一端、第二端和控制端。其中，在本具体实施方式中，第一开关单元MP2为P型晶体管，所述第二开关单元MN1为N型晶体管。
所述第一开关单元MP2及所述第二开关单元MN1的所述控制端均耦接于所述控制模块12。具体地说，所述第一开关单元MP2的控制端耦接于所述控制模块12的第一控制信号CTRL_A，所述第二开关单元MN1的控制端耦接于所述控制模块12的第二控制信号CTRL_B。
所述第一开关单元MP2及所述第二开关单元MN1的所述第二端均耦接于选择模块。具体地说，所述第一开关单元MP2的第二端耦接于所述选择模块的字线选择单元MP1，所述第二开关单元MN1的第二端耦接于所述选择模块的位线选择单元MN2。
所述第一开关单元MP2的第一端耦接于所述反熔丝器件C00的第一端，所述第二开关单元MN1的第一端耦接于所述反熔丝器件C00的第二端。
当反熔丝存储器单元读出电路读出编程结果后，如果所述反熔丝器件C00被击穿，则关断反熔丝存储器单元的上拉，如果所述反熔丝器件C00未被击穿， 则维持反熔丝存储器单元的上拉。当反熔丝存储器单元读出电路读出编程结果后，如果所述反熔丝器件C00被击穿，维持反熔丝储存器单元的下拉，如果所述反熔丝器件C00未被击穿，则关断反熔丝存储器单元的下拉。
进一步，所述开关模块还包括第三开关单元MN0，所述第三开关单元MN0具有第一端、第二端及控制端。所述第三开关单元MN0的第一端耦接于所述反熔丝器件C00的第一端，所述第三开关单元MN0的第二端耦接于接地信号，所述第三开关单元MN0的控制端耦接于所述控制模块12的第三控制信号CTRL_A。在本具体实施方式中，第三开关单元MN0为N型晶体管。第三开关单元MN0用于在一次可编程存储器不工作时，将反熔丝存储器单元的一级输出节点OUTA拉到地，也用于在一次可编程存储器工作时，限定一级输出节点OUTA的初始工作状态。
所述选择模块包括位线选择单元MN2和字线选择单元MP1，所述位线选择单元MN2和所述字线选择单元MP1均具有第一端、第二端和控制端。其中，所述位线选择单元MN2可为N型晶体管，所述字线选择单元MP1可为P型晶体管。
所述位线选择单元MN2的控制端耦接于位线BL00，所述位线选择单元MN2的第一端耦接于所述第二开关单元MN1的第二端，所述位线选择单元MN2的第二端耦接于接地信号。所述字线选择单元MP1的控制端耦接于字线WL00，所述字线选择单元MP1的第一端耦接于所述第一开关单元MP2的第二端，所述字线选择单元MP1的第二端耦接于电源信号。
在编程时，所述位线选择单元MN2均能够控制所述反熔丝存储器单元的通断，起到保护所述反熔丝器件C00的作用。
进一步，所述反熔丝存储单元电路还包括电流提供模块MP0，其具有第一 端和第二端，所述电流提供模块MP0的第一端耦接于电源信号，第二端耦接于所述字线选择单元MP1的第二端。即所述字线选择单元MP1的第二端通过所述电流提供模块MP0耦接于电源信号。所述电流提供模块MP0作为镜像电流源，在编程时，所述电流提供模块MP0可以控制流过所述反熔丝器件C00的电流大小，在正常工作时，所述电流提供模块MP0可以控制反熔丝存储器单元的上拉能力。其中，所述电流提供模块MP0可为P型晶体管。
所述控制模块12包括控制单元121、放大单元122及延时单元123。
所述控制单元121用于接收信号并输出控制信号。具体地说，所述控制单元121具有输入端及输出端，所述输入端通过所述放大单元122耦接于所述反熔丝器件C00的第一端、写使能信号En_W、读使能信号En_R及读使能延迟信号En_R_DLY，所述输出端耦接于所述开关模块，输出第一控制信号CTRL_A、第二控制信号CTRL_B及第三控制信号CTRL_C。所述第一控制信号CTRL_A耦接于所述第一开关单元MP2的控制端，所述第二控制信号CTRL_B耦接于第二开关单元MN1的控制端，所述第三控制信号CTRL_C耦接于第三开关单元MN0的控制端。
所述放大单元122具有输入端及输出端，所述输入端与所述反熔丝器件C00的一级输出节点OUTA耦接，用于将所述反熔丝器件C00的一级输出节点OUTA的状态放大为二级输出OUTB的状态，可以避免后面数字电路出现逻辑错误，提高读出电路可靠性。所述输出端耦接于所述控制单元121的输入端，以将所述反熔丝器件C00的二级输出OUTB输入至所述控制单元121的输入端。在本具体实施方式中，所述放大单元122由两个反相器组成。
所述延时单元123用于产生所述读使能延迟信号En_R_DLY。具体地说，所述读使能信号En_R除耦接于控制单元121外，还耦接于所述延时单元123， 所述延时单元123将所述读使能信号En_R延迟后输出所述读使能延迟信号En_R_DLY。所述延时单元123可由偶数个反相器串联形成，或者所述延时单元123为RC延迟电路。延迟时间Td最小为4个反相器延迟，在Td期间放大单元122可以完成对OUTA的放大。
本发明还提供了上述反熔丝存储单元电路的读写方法的一具体实施方式。请参阅表1：
EN_W EN_R EN_R_DLY OUTA OUTB CTRL_A CTRL_B CTRL_C
1 0 0 X X 0 1 0
0 0 0 X X 1 0 1
0 1 0 X X 0 1 0
0 1 1 0 0 1 1 0
0 1 1 1 1 0 0 0
表1
编程时的方法是，所述控制模块控制所述开关模块处于第一状态，以对所述反熔丝器件进行写操作。举例说明如下：
当写使能信号EN_W＝1，读使能信号EN_R＝0，则第一控制信号CTRL_A＝0(第一开关管MP2被打开)、第二控制信号CTRL_B＝1(第二开关管MN1被打开)、第三控制信号CTRL_C＝0(第三开关管MN0被关断)、VDD为高电压；如果字线WL00为“0”且位线BL00为“1”，则反熔丝器件C00被击穿，导通电阻近似为0欧姆；其他情况则反熔丝器件C00未被击穿，导通电阻近似为无穷大欧姆。
待机时的方法为，所述控制模块控制所述开关模块处于第二状态，以降低所述反熔丝器件的功耗。举例说明如下：
写使能信号EN_W＝0，读使能信号EN_R＝0时，则第一控制信号CTRL_A＝1(第一开关管MP2被关闭)、第二控制信号CTRL_B＝0(第二开关管MN1被 关闭)、第三控制信号CTRL_C＝1(第三开关管MN0被打开)、VDD为正常电压，此时反熔丝存储器单元静态功耗近似为0，OUTB默认输出为“0”。
正常工作时的方法为，所述控制模块控制所述开关模块处于第三状态，以对所述反熔丝器件进行读操作。举例说明如下：
1、当字线WL00＝0，位线BL00＝1，VDD为正常电压，写使能信号EN_W＝0，读使能信号EN_R＝0，读使能延迟信号EN_R_DLY＝0，则第一控制信号CTRL_A＝1(第一开关管MP2关闭)，第二控制信号CTRL_B＝0(第二开关管MN1关闭)，第三控制信号CTRL_C＝1(第三开关管MN0打开)。2、当字线WL00＝0，位线BL00＝1，VDD为正常电压，写使能信号EN_W＝0，读使能信号EN_R＝1，读使能延迟信号EN_R_DLY＝0，则第一控制信号CTRL_A＝0(第一开关管MP2打开)，第二控制信号CTRL_B＝1(第二开关管MN1打开)，第三控制信号CTRL_C＝0(第三开关管MN0关闭)；如果反熔丝器件C00未被击穿，反熔丝器件C00导通电阻近似为无穷大欧姆，第一P型晶体管MP0、第一选择晶体管MP1和第一开关管MP2会将OUTA上拉至“1”；如果反熔丝器件C00被击穿，反熔丝器件C00导通电阻近似为0欧姆，第二开关管MN1和第二选择晶体管MN2会将OUTA维持在“0”。3、当字线WL00＝0，位线BL00＝1，VDD为正常电压，写使能信号EN_W＝0，读使能信号EN_R＝1，读使能延迟信号EN_R_DLY＝1，如果OUTB＝OUTA＝1，则第一控制信号CTRL_A＝0(第一开关管MP2打开)，第二控制信号CTRL_B＝0(第二开关管MN1关闭)，第三控制信号CTRL_C＝0(第三开关管MN0关闭)；如果OUTB＝OUTA＝0，则第一控制信号CTRL_A＝1(第一开关管MP2关闭)，第二控制信号CTRL_B＝1(第二开关管MN1打开)，第三控制信号CTRL_C＝0(第三开关管MN0关闭)。
本发明反熔丝存储单元电路是纯组合电路，相比时序电路，在Td延迟之后，所有通路都被关闭，且整个电路没有逻辑动作，静态功耗更低，功耗近似为0；且本发明反熔丝存储单元电路通过开关和逻辑运算模块的设计，实质上构成了两个正反馈回路，使得读出电路可以更可靠的读出“0”或“1”；同时，本发明反熔丝存储单元电路可以省去复杂的时序控制部分，甚至读出电路的输出OUTA/OUTB可以不用锁存，直接作为反熔丝的编码输出。
进一步，为了实现本发明反熔丝存储单元电路的控制，逻辑运算单元LOGIC电路内部结构如下：
CTRL_A＝(！EN_W)&&((！EN_R)&&(！EN_R_DLY)||EN_R&&EN_R_DLY&&(！OUTB))
CTRL_B＝EN_W&&(！EN_R)&&(！EN_R_DLY)||(！EN_W)&&EN_R&&((！EN_R_DLY)||EN_R_DLY&&(！OUTB))
CTRL_C＝(！EN_W)&&(！EN_R)
本发明还提供一种反熔丝存储阵列电路的第一具体实施方式。图2是反熔丝存储阵列电路的第一具体实施方式的电路图。请参阅图2，所述反熔丝存储阵列电路包括至少一控制模块及多个反熔丝存储单元电路。所述反熔丝存储单元电路包括：反熔丝器件、开关模块及选择模块，所述反熔丝器件、开关模块及选择模块与上述反熔丝存储单元电路的反熔丝器件、开关模块及选择模块结构相同。所述控制模块分别耦接于所述反熔丝存储单元电路的所述反熔丝器件和所述开关模块，所述控制模块用于根据所述反熔丝器件的击穿状态，切换所述开关模块的通断模式。
在本具体实施方式中，所述控制模块为总控制模块，其分别耦接于每一个所述反熔丝存储单元电路的所述反熔丝器件和所述开关模块。所述总控制模块 包括一控制单元121，所述控制单元的输入端耦接于写使能信号EN_W、读使能信号EN_R及读使能延迟信号EN_R_DLY及每一所述反熔丝器件C00的第一端。也就是说，所述反熔丝存储单元电路共用写使能信号EN_W、读使能信号EN_R及读使能延迟信号EN_R_DLY，以减少输入线个数，从而减小面积。进一步，所述控制单元的输出端输出一控制信号，所述控制信号耦接于所述反熔丝存储单元的第三开关单元MN0，即所述反熔丝存储单元电路共用所述控制单元的第三控制信号CTRL_C，以减少控制线个数，从而减小面积。对于逻辑运算电路，内部纯组合逻辑可以继续优化以减小逻辑门个数，从而减小面积。
本发明还提供一种反熔丝存储阵列电路的第二具体实施方式。图3是反熔丝存储阵列电路的第二具体实施方式的电路图。请参阅图3，所述第二具体实施方式与第一具体实施方式的区别在于，所述反熔丝存储阵列电路还包括至少一电流提供模块MP0，至少部分所述反熔丝存储单元电路共用电流提供模块MP0。例如，全部的所述反熔丝存储单元电路共用一个电流提供模块MP0。所述电流提供模块MP0作为电流镜起到提供电流和限制电流的作用，则所述反熔丝存储单元电路共用电流提供模块MP0，以减小晶体管数目，从而减小面积。进一步，在本具体实施方式中，所述反熔丝存储阵列电路还包括至少一字线选择单元MP1，至少部分所述反熔丝存储单元电路共用字线选择单元MP1，例如，全部的所述反熔丝存储单元电路共用字线选择单元MP1。所述字线选择单元MP1为字线控制的选择晶体管，则所述反熔丝存储单元电路共用字线选择单元MP1可减少晶体管数目，从而减小面积。
发明还提供一种反熔丝存储阵列电路的第三具体实施方式。图4是反熔丝存储阵列电路的第三具体实施方式的电路图。请参阅图4，所述第三具体实施方式与第二具体实施方式的区别在于，所述控制模块包括两个反相器组成的放 大单元122，其中，所述放大单元122可与控制单元121的电路合并，以减小逻辑门个数，从而减小面积。也就是说，通过所述控制单元121实现放大单元122的功能。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (18)

  1. 一种反熔丝存储单元电路，其特征在于，包括：
    反熔丝器件；
    开关模块，耦接于所述反熔丝器件；
    选择模块，耦接于所述开关模块；
    控制模块，分别耦接于所述反熔丝器件和所述开关模块；
    其中，所述控制模块用于根据所述反熔丝器件的击穿状态，切换所述开关模块的通断模式。
  2. 如权利要求1所述的反熔丝存储单元电路，其特征在于，所述反熔丝器件具有第一端和第二端，
    所述开关模块包括第一开关单元和第二开关单元，所述第一开关单元及所述第二开关单元均具有第一端、第二端和控制端，且所述控制端均耦接于所述控制模块，所述第二端均耦接于选择模块，所述第一开关单元的第一端耦接于所述反熔丝器件的第一端，所述第二开关单元的第一端耦接于所述反熔丝器件的第二端。
  3. 如权利要求2所述的反熔丝存储单元电路，其特征在于，所述开关模块还包括第三开关单元，所述第三开关单元具有第一端、第二端及控制端，所述第三开关单元的第一端耦接于所述反熔丝器件的第一端，所述第三开关单元的第二端耦接于接地信号，所述第三开关单元的控制端耦接于所述控制模块。
  4. 如权利要求2所述的反熔丝存储单元电路，其特征在于，所述选择模块包括位线选择单元和字线选择单元，所述位线选择单元和所述字线选择单元均具有第一端、第二端和控制端，所述位线选择单元的控制端耦接于位线，所述位线选择单元的第一端耦接于所述第二开关单元的第二端，所述位线 选择单元的第二端耦接于接地信号，所述字线选择单元的控制端耦接于字线，所述字线选择单元的第一端耦接于所述第一开关单元的第二端，所述字线选择单元的第二端耦接于电源信号。
  5. 如权利要求4所述的反熔丝存储单元电路，其特征在于，所述反熔丝存储单元电路还包括电流提供模块，具有第一端和第二端，所述电流提供模块的第一端耦接于电源信号，第二端耦接于所述字线选择单元的第二端。
  6. 如权利要求1所述的反熔丝存储单元电路，其特征在于，所述控制模块包括控制单元，所述控制单元具有输入端及输出端，所述输入端耦接于所述反熔丝器件的第一端、写使能信号、读使能信号、读使能延迟信号，所述输出端耦接于所述开关模块。
  7. 如权利要求6所述的反熔丝存储单元电路，其特征在于，所述控制模块还包括放大单元，所述放大单元具有输入端及输出端，所述输入端耦接于所述反熔丝器件的第一端，所述输出端耦接于所述控制单元的输入端，所述放大单元用于将所述反熔丝器件第一端的信号放大。
  8. 如权利要求6所述的反熔丝存储单元电路，其特征在于，所述控制模块还包括延时单元，所述延时单元具有输入端及输出端，所述读使能信号还耦接于所述延时单元的输入端，所述延时单元的输出端耦接于所述控制单元，所述延时单元用于对读使能信号进行延迟，形成所述读使能延迟信号。
  9. 一种反熔丝存储阵列电路，其特征在于，包括：
    至少一控制模块；
    多个反熔丝存储单元电路，所述反熔丝存储单元电路包括：
    反熔丝器件；
    开关模块，耦接于所述反熔丝器件；
    选择模块，耦接于所述开关模块；
    所述控制模块分别耦接于所述反熔丝存储单元电路的所述反熔丝器件和所述开关模块，所述控制模块用于根据所述反熔丝器件的击穿状态，切换所述开关模块的通断模式。
  10. 如权利要求9所述的反熔丝存储阵列电路，其特征在于，所述控制模块为总控制模块，其分别耦接于每一个所述反熔丝存储单元电路的所述反熔丝器件和所述开关模块。
  11. 如权利要求10所述的反熔丝存储阵列电路，其特征在于，所述总控制模块包括控制单元，所述控制单元具有输入端及输出端，所述输入端分别耦接于每一个所述反熔丝存储单元电路的所述反熔丝器件的第一端、写使能信号、读使能信号、读使能延迟信号，所述输出端分别耦接于每一个所述反熔丝存储单元电路的所述开关模块。
  12. 如权利要求9所述的反熔丝存储阵列电路，其特征在于，所述反熔丝存储阵列电路包括多个所述控制模块，一个所述控制模块至少耦接于一个所述反熔丝存储单元电路的所述反熔丝器件和所述开关模块。
  13. 如权利要求9所述的反熔丝存储阵列电路，其特征在于，所述反熔丝存储阵列电路还包括至少一电流提供模块，至少部分所述反熔丝存储单元电路共用同一个所述电流提供模块。
  14. 如权利要求9所述的反熔丝存储阵列电路，其特征在于，所述反熔丝存储阵列电路还包括至少一字线选择单元，至少部分所述反熔丝存储单元电路共用同一个所述字线选择单元。
  15. 一种如权利要求1所述的反熔丝存储单元电路的读写方法，其特征在于，包括：
    在编程时，所述控制模块控制所述开关模块处于第一状态，以对所述反熔丝器件进行写操作；
    在待机时：所述控制模块控制所述开关模块处于第二状态，以降低所述反熔丝器件的功耗；
    在正常工作时：所述控制模块控制所述开关模块处于第三状态，以对所述反熔丝器件进行读操作。
  16. 如权利要求15所述的读写方法，其特征在于，在编程时，所述选择模块打开，在待机时，所述选择模块关闭，在正常工作时，选择模块打开。
  17. 如权利要求15所述的读写方法，其特征在于，所述反熔丝器件具有第一端和第二端，所述开关模块包括第一开关单元和第二开关单元，所述第一开关单元及所述第二开关单元均具有第一端、第二端和控制端，且所述控制端均耦接于所述控制模块，所述第二端均耦接于选择模块，所述第一开关单元的第一端耦接于所述反熔丝器件的第一端，所述第二开关单元的第一端耦接于所述反熔丝器件的第二端；
    所述开关模块的第一状态为：所述第一开关单元及第二开关单元打开；
    所述开关模块的第二状态为：所述第一开关单元及第二开关单元关闭；
    所述开关模块的第三状态为：若所述反熔丝器件未被击穿，则所述第一开关单元打开，所述第二开关单元关闭；若所述反熔丝器件被击穿，则所述第一开关单元关闭，所述第二开关单元打开。
  18. 如权利要求17所述的读写方法，其特征在于，所述开关模块还包括第三开关单元，所述第三开关单元具有第一端、第二端及控制端，所述第三开关单元的第一端耦接于所述反熔丝器件的第一端，所述第三开关单元的第二端耦接于接地信号，所述第三开关单元的控制端耦接于所述控制模块；
    所述开关模块的第一状态为：所述第一开关单元及第二开关单元打开，所述第三开关单元关闭；
    所述开关模块的第二状态为：所述第一开关单元及第二开关单元关闭，所述第三开关单元打开；
    所述开关模块的第三状态为：若所述反熔丝器件未被击穿，则所述控制模块控制所述第一开关单元打开，所述第二开关单元关闭，所述第三开关单元关闭；若所述反熔丝器件被击穿，则所述控制模块控制所述第一开关单元关闭，所述第二开关单元打开，所述第三开关单元关闭。
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US20220122680A1 (en) 2022-04-21
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