WO2021103606A1 - 可编程存储单元、可编程存储阵列及其读写方法 - Google Patents

可编程存储单元、可编程存储阵列及其读写方法 Download PDF

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Publication number
WO2021103606A1
WO2021103606A1 PCT/CN2020/103870 CN2020103870W WO2021103606A1 WO 2021103606 A1 WO2021103606 A1 WO 2021103606A1 CN 2020103870 W CN2020103870 W CN 2020103870W WO 2021103606 A1 WO2021103606 A1 WO 2021103606A1
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WIPO (PCT)
Prior art keywords
terminal
fuse
signal
power
power terminal
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PCT/CN2020/103870
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English (en)
French (fr)
Inventor
李新
应战
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长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/432,791 priority Critical patent/US11735279B2/en
Priority to EP20893598.1A priority patent/EP3933840B1/en
Publication of WO2021103606A1 publication Critical patent/WO2021103606A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/812—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a reduced amount of fuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/838—Masking faults in memories by using spares or by reconfiguring using programmable devices with substitution of defective spares

Definitions

  • the present disclosure relates to the field of storage technology, and in particular to a programmable storage unit, a programmable storage array and a reading and writing method thereof.
  • a one-time programmable memory cell can be used in a dynamic random access memory (DRAM) to control the turning on or off of the redundant memory cell.
  • DRAM dynamic random access memory
  • the corresponding one-time programmable memory cell will be programmed (for example, from logic "0" to logic "1"), and the DRAM control circuit will be turned off Read and write to the memory cell corresponding to this word line, and open the read and write of the memory cell in the redundant area.
  • the memory cell corresponding to the redundant area completely replaces the memory cell in the defective memory area. The defect of DRAM was repaired.
  • the one-time programmable memory cell in the prior art has a complicated structure, a large area, slow data reading speed, and poor reliability.
  • a programmable memory unit which includes: a first anti-fuse, a second anti-fuse, and a third switch unit.
  • the first anti-fuse is connected between the first power terminal and the output terminal;
  • the second anti-fuse is connected between the second power terminal and the output terminal;
  • the third switch unit is connected to the output terminal and the third power terminal And a position signal terminal for connecting the third power terminal and the output terminal in response to a signal from the position signal terminal.
  • the programmable storage unit further includes a first switch unit and a second switch unit.
  • the first switch unit is connected to the first power terminal, the first terminal of the first anti-fuse, and the first control terminal, and is used to connect the first power terminal and the first control terminal in response to a signal from the first control terminal.
  • the first end of an anti-fuse; the second switch unit is connected to the second power source, the first end of the second anti-fuse, and the first control end, and is used to respond to the signal of the first control end to communicate with The second power terminal and the first terminal of the second anti-fuse.
  • the programmable storage unit further includes a D-type flip-flop, the data input terminal of the D-type flip-flop is connected to the output terminal, and the CP terminal is connected to the clock signal terminal.
  • the third switch unit includes a third transistor, the control terminal of the third transistor is connected to the position signal terminal, the first terminal is connected to the output terminal, and the second terminal is connected to the The third power terminal.
  • the first switch unit includes a first transistor, a control terminal of the first transistor is connected to the first control terminal, the first terminal is connected to the first power terminal, and the second terminal is The first terminal of the first anti-fuse is connected;
  • the second switch unit includes a second transistor, the control terminal of the second transistor is connected to the first control terminal, the first terminal is connected to the second power terminal, and the first terminal is connected to the second power terminal. The two ends are connected to the first end of the second anti-fuse.
  • a programmable memory array includes a plurality of anti-fuse groups and a plurality of third switch units, and each of the anti-fuse groups is correspondingly connected to a different output terminal
  • the anti-fuse group includes a first anti-fuse and a second anti-fuse, wherein the first anti-fuse is connected between the corresponding output terminal and the first power terminal, and the second anti-fuse
  • the fuse is connected between the corresponding output terminal and the second power terminal;
  • the third switch unit and the output terminal are arranged in one-to-one correspondence, and each of the third switch units is correspondingly connected to a different The output terminal and different position signal terminals, wherein the third switch unit is also connected to a third power terminal for responding to the signal of the position signal terminal corresponding to it to communicate with the third power terminal and its corresponding output terminal .
  • the programmable memory array further includes: a first switch unit and a second switch unit.
  • the first switch unit is connected to the first power terminal, the first control terminal, the first node, and is used to transmit the signal of the first power terminal to the first node in response to the signal of the first control terminal, wherein The first node is connected to the first ends of a plurality of the first anti-fuse; the second switch unit is connected to the second power terminal and the first control terminal, and the second node is used to respond to the signal of the first control terminal to switch
  • the signal of the second power terminal is transmitted to the second node, wherein the second node is connected to the first terminals of a plurality of second antifuses.
  • the programmable memory array further includes: a plurality of D-type flip-flops, the D-type flip-flops and the output terminals are arranged in a one-to-one correspondence, and each of the D-type flip-flops The data input terminal of the device is correspondingly connected to different output terminals, and the CP terminal is connected to the clock signal terminal.
  • the first switch unit includes a first transistor, a control terminal of the first transistor is connected to the first control terminal, the first terminal is connected to the first power terminal, and the second terminal is Connect the first node.
  • the second switch unit includes a second transistor, a control terminal of the second transistor is connected to the first control terminal, the first terminal is connected to the second power terminal, and the second terminal is Connect the second node.
  • the third switch unit includes a third transistor, the control terminal of the third transistor is connected to its corresponding position signal terminal, the first terminal is connected to its corresponding output terminal, and the second terminal is connected to The third power terminal.
  • the third power terminal is a ground terminal.
  • a method for reading and writing a programmable memory array including:
  • a first high-level signal is input to the first power terminal
  • a low-level signal is input to the second power terminal and the third power terminal
  • an effective level is input to the preset position signal terminal to turn on the third switch Unit, thereby puncturing the corresponding first anti-fuse
  • the first high-level signal is input to the second power terminal
  • the low-level signal is input to the first power terminal and the third power terminal
  • the active level is input to the preset position signal terminal to turn on the third switch Unit, thereby puncturing the corresponding second anti-fuse;
  • a second high-level signal is input to the first power terminal, a low-level signal is input to the second power terminal and the third power terminal, and an invalid level is input to the position signal terminal to turn off the third switch unit.
  • the reading phase further includes:
  • Input an effective level to the CP terminal of each D-type flip-flop to write the signal at the output terminal to the first output terminal of the D-type flip-flop, and write and write to the second output terminal of the D-type flip-flop A signal with the opposite logic level at the first output.
  • the first high-level signal voltage is 6V
  • the second high-level signal voltage is 1V
  • the low-level voltage is 0V
  • Figure 1 is a schematic diagram of the circuit structure of a programmable memory array in the related art
  • FIG. 2 is a schematic diagram of a circuit structure of an exemplary embodiment of a programmable memory unit of the present disclosure
  • FIG. 3 is a schematic diagram of the circuit structure of another exemplary embodiment of the programmable memory unit of the present disclosure.
  • FIG. 4 is a schematic diagram of the circuit structure of an exemplary embodiment of the programmable memory array of the present disclosure
  • FIG. 5 is a schematic diagram of the circuit structure of another exemplary embodiment of the programmable memory array of the present disclosure.
  • FIG. 1 it is a schematic diagram of the circuit structure of a programmable memory array in the related art.
  • the programmable memory array includes a plurality of programmable memory cells 1.
  • Figure 1 takes a 2 ⁇ 2 array as an example for illustration.
  • the programmable memory unit 1 includes an anti-fuse AF01 and a switching transistor T01.
  • the first terminal of the anti-fuse AF01 is connected to the column control signal terminal C0
  • the second terminal is connected to the first terminal of the switching transistor T01
  • the second terminal of the switching transistor T01 is connected to the output terminal S1
  • the control terminal is connected to the row control signal terminal R1.
  • the output terminal S1 also needs to be connected to the input terminal of a sensitive amplifier.
  • the programmable memory array has a complex structure and a large area.
  • the signal of the column control signal terminal C0 is obtained through signal decoding on the bit line, and the signal of the row control signal terminal R1 is obtained through the word line The upper signal is decoded.
  • the programmable memory array reads data, it is necessary to input valid level signals to the word line and the bit line, so that the signals at the column control signal terminal C0 and the row control signal terminal R1 are at the valid level.
  • the related art judges the logic state of the data being written by comparing the voltages at the two input terminals of the sensitive amplifier.
  • the voltage difference between the two input terminals of the sense amplifier SA is relatively small when reading data, and the programmable memory array is prone to misreading when reading data. Therefore, the stability of the programmable memory array is relatively small. difference.
  • this exemplary embodiment first provides a programmable memory cell.
  • FIG. 2 it is a circuit diagram of an exemplary embodiment of the programmable memory cell of the present disclosure.
  • the programmable memory cell includes: The wire AF1, the second anti-fuse AF2, and the third switch unit T3.
  • the first anti-fuse AF1 is connected between the first power terminal V1 and the output terminal OUT;
  • the second anti-fuse AF2 is connected between the second power terminal V2 and the output terminal OUT;
  • the third switch unit T3 is connected to the The output terminal OUT, the third power terminal V3, and the position signal terminal PD are used to connect the third power terminal V3 and the output terminal OUT in response to a signal from the position signal terminal PD.
  • a first high-level signal is input to the first power terminal V1
  • a low-level signal is input to the second power terminal V2 and the third power terminal V3.
  • Level signal, the position signal terminal PD inputs an effective level to turn on the third switch unit T3, and the first anti-fuse AF1 is broken down under the action of the voltage between the first power terminal V1 and the third power terminal V3.
  • the programmable memory unit When the programmable memory unit needs to write data "0", the first high-level signal is input to the second power terminal V2, the low-level signal is input to the first power terminal V1 and the third power terminal V3, and the position signal terminal PD The effective level is input to turn on the third switch unit T3, and the second anti-fuse AF2 is broken down under the action of the voltage between the second power terminal V2 and the third power terminal V3.
  • the programmable memory unit needs to read data "0”
  • input a second high level signal to the first power supply terminal V1 input a low level signal to the second power supply terminal V2 and the third power supply terminal V3, and input a low level signal to the position signal terminal
  • the PD inputs an invalid level to turn off the third switch unit T3.
  • the first high-level signal is used to break down the anti-fuse, therefore, the first high-level signal may be greater than the second high-level signal.
  • the first high-level signal voltage may be 6V
  • the second high-level signal voltage may be 1V
  • the low-level voltage may be 0V.
  • the position signal terminal PD can be obtained by decoding the signals on the bit line and the word line. When the bit line and the word line are at the active level at the same time, the level of the position signal terminal PD is the active level. Flat, this setting combines the two position signal terminals in the related technology into one position signal terminal through the "AND gate" in the decoder. Correspondingly, the number of switch units is reduced, thereby further simplifying the programmable memory unit. Structure.
  • the position signal terminal PD outputs an invalid level signal, thereby avoiding the technical problem of slow reading speed caused by the parasitic RC of the word line and the bit line.
  • the resistance of the anti-fuse in the breakdown state and the non-breakdown state differs by at least two orders of magnitude.
  • the voltage difference at the output terminal OUT is relatively large.
  • the programmable memory cell has high stability.
  • FIG. 3 it is a circuit diagram of another exemplary embodiment of the programmable memory cell of the present disclosure.
  • the programmable storage unit also includes a first switch unit T1 and a second switch unit T2.
  • the first switch unit T1 is connected to the first power terminal V1, the first terminal of the first anti-fuse AF1, and the first control terminal CN1, and is used to communicate with the first control terminal CN1 in response to a signal from the first control terminal CN1.
  • the power terminal V1 and the first terminal of the first anti-fuse AF1; the second switch unit T2 is connected to the second power terminal V2, the first terminal of the second anti-fuse AF2, and the first control terminal CN1, It is used to connect the second power terminal V2 and the first terminal of the second anti-fuse AF2 in response to the signal of the first control terminal CN1.
  • the first control terminal CN1 inputs an effective level to turn on the first switch unit T1 and the second switch unit T2.
  • the current flowing through the first anti-fuse AF1 and the second anti-fuse AF2 can be controlled by the voltage of the first control terminal CN1.
  • the programmable memory unit may further include a D-type flip-flop TG.
  • the data input terminal D of the D-type flip-flop TG is connected to the output terminal OUT, and the CP terminal is connected to the clock.
  • Signal terminal Clk When the clock signal terminal Clk is at an effective level, the D-type flip-flop latches the signal of the output terminal OUT at the Q terminal of the D-type flip-flop and latches the reverse logic signal of the output terminal at the Qb terminal of the D-type flip-flop.
  • the third switch unit T3 may include a third transistor, the control terminal of the third transistor is connected to the position signal terminal PD, and the first terminal is connected to the output terminal. OUT, the second terminal is connected to the third power terminal V3.
  • the first switch unit T1 may include a first transistor, the control terminal of the first transistor is connected to the first control terminal CN1, and the first terminal is connected to the first power supply.
  • Terminal V1 the second terminal is connected to the first terminal of the first anti-fuse AF1;
  • the second switch unit T2 may include a second transistor, the control terminal of the second transistor is connected to the first control terminal CN1, the first The terminal is connected to the second power terminal V2, and the second terminal is connected to the first terminal of the second anti-fuse AF2.
  • the first transistor, the second transistor, and the third transistor may be either N-type transistors or P-type transistors.
  • the first transistor and the second transistor are P-type transistors
  • the third transistor is an N-type transistor.
  • This exemplary embodiment also provides a programmable memory array, as shown in FIG. 4, which is a schematic diagram of the circuit structure of an exemplary embodiment of the programmable memory array of the present disclosure.
  • the programmable memory array includes: a plurality of anti-fuse groups 1...n, a plurality of third switch units T31...T3n, each of the anti-fuse groups 1...n is correspondingly connected to a different output terminal OUT1...
  • the anti-fuse group includes a first anti-fuse AF1 and a second anti-fuse AF2, wherein the first anti-fuse AF1 is connected to the corresponding output terminal and the first power terminal V1 In between, the second anti-fuse AF2 is connected between the corresponding output terminal and the second power terminal V2; the third switch unit T31...T3n and the output terminal OUT1...OUTn
  • the third switch unit is correspondingly connected to different output terminals and different position signal terminals PD1...PDn, wherein the third switch unit is also connected to a third power terminal V3, In response to the signal of the position signal terminal corresponding to it, the third power terminal V3 is connected to the output terminal corresponding to it.
  • the programmable memory array includes a plurality of the above-mentioned programmable memory cells.
  • This exemplary embodiment takes the anti-fuse group 1 as an example for description.
  • the programmable memory array needs to write data "1" to the anti-fuse group 1
  • the first high-level signal is input to the first power terminal V1
  • a low-level signal is input to the second power terminal V2 and the third power terminal V3
  • the position signal terminal PD1 inputs an active level to turn on the third switch unit T31
  • the first anti-fuse AF1 is connected between the first power terminal V1 and the third power terminal.
  • the voltage between the power supply terminals V3 is broken down.
  • the first high-level signal is input to the second power supply terminal V2, and the low-level signal is input to the first power supply terminal V1 and the third power supply terminal V3 Signal
  • the position signal terminal PD1 inputs an effective level to turn on the third switch unit T31
  • the second anti-fuse AF2 is broken down under the action of the voltage between the second power terminal V2 and the third power terminal V3.
  • the programmable memory array When the programmable memory array needs to read data "0" from the anti-fuse group 1, input a second high-level signal to the first power supply terminal V1, and input a low-level signal to the second power supply terminal V2 and the third power supply terminal V3 Signal, input an invalid level to the position signal terminal PD1 to turn off the third switch unit T31.
  • the two ends of the second anti-fuse AF2 are turned on, the two ends of the first anti-fuse AF1 are disconnected, so that The output terminal OUT1 outputs a high level signal "0".
  • the first high-level signal is used to puncture the anti-fuse. Therefore, the first high-level signal is greater than the second high-level signal.
  • the first high-level signal voltage may be 6V
  • the second high-level signal voltage may be 1V
  • the low-level voltage may be 0V.
  • the position signal terminals PD1...PDn can be obtained by decoding the signals on the bit line and the word line.
  • the position signal terminals PD1...PDn The level is the effective level. This setting combines the two position signal terminals in the related technology into one position signal terminal through the "AND gate" in the decoder. Correspondingly, the number of switch units is reduced, thereby further The structure of the programmable memory array is simplified.
  • the position signal terminals PD1...PDn output signals of invalid level, thereby avoiding the slow reading speed caused by the RC voltage drop of the word line and the bit line itself.
  • the resistance of the anti-fuse in the breakdown state and the non-breakdown state differs by two orders of magnitude.
  • the voltage difference of the output terminal OUT1 is relatively large, so it can be
  • the programming memory array has high stability.
  • no sensitive amplifier and no word line bit line are needed for positioning during reading, the stored information in the programmable memory array can be read in parallel, which significantly improves the reading speed of the programmable memory array.
  • FIG. 5 it is a schematic diagram of the circuit structure of another exemplary embodiment of the programmable memory array of the present disclosure.
  • the programmable memory array may further include: a first switch unit T1 and a second switch unit T2.
  • the first switch unit T1 is connected to the first power supply terminal V1, the first control terminal CN1, and the first node N1 is used to transmit the signal of the first power supply terminal V1 to the first control terminal CN1 in response to the signal of the first control terminal CN1.
  • the first control terminal CN1 inputs an effective level to turn on the first switch unit T1 and the second switch unit T2.
  • the programmable memory array may further include a plurality of D-type flip-flops TG1...TGn, the D-type flip-flops TG1...TGn and the output terminal OUT1... OUTn is set in one-to-one correspondence, and the data input terminal of each D-type flip-flop is connected to different output terminals, and the CP terminal is connected to the clock signal terminal Clk.
  • the clock signal terminal Clk is at an effective level
  • the D-type flip-flop latches the signal at the output terminal at the Q terminal of the D-type flip-flop and latches the reverse logic signal at the output terminal at the Qb terminal of the D-type flip-flop.
  • the first switch unit may include a first transistor, the control terminal of the first transistor is connected to the first control terminal, and the first terminal is connected to the first power terminal, The second end is connected to the first node.
  • the second switch unit may include a second transistor, the control terminal of the second transistor is connected to the first control terminal, and the first terminal is connected to the second power terminal, The second end is connected to the second node.
  • the third switch unit may include a third transistor, the control terminal of the third transistor is connected to its corresponding position signal terminal, and the first terminal is connected to its corresponding output terminal. , The second terminal is connected to the third power terminal.
  • the first transistor, the second transistor, and the third transistor may be either N-type transistors or P-type transistors.
  • the first transistor and the second transistor are P-type transistors
  • the third transistor is an N-type transistor.
  • the third power terminal V3 may be a ground terminal.
  • This exemplary embodiment also provides a method for reading and writing a programmable storage array, the method including:
  • a first high-level signal is input to the first power terminal
  • a low-level signal is input to the second power terminal and the third power terminal
  • an effective level is input to the preset position signal terminal to turn on the third switch Unit, thereby puncturing the corresponding first anti-fuse
  • the first high-level signal is input to the second power terminal
  • the low-level signal is input to the first power terminal and the third power terminal
  • the active level is input to the preset position signal terminal to turn on the third switch Unit, thereby puncturing the corresponding second anti-fuse;
  • a second high-level signal is input to the first power terminal, a low-level signal is input to the second power terminal and the third power terminal, and an invalid level is input to the position signal terminal to turn off the third switch unit.
  • the programmable memory array includes four anti-fuse groups 1, 2, 3, and 4 as an example for description.
  • the second anti-fuse in the anti-fuse group 1, 2, 3, and 4 needs to be broken down.
  • the second anti-fuse in the anti-fuse group 1, 2, and 3 and the first anti-fuse in the anti-fuse group 4 need to be broken down.
  • the second anti-fuse in the anti-fuse group 1, 2, and 4 and the first anti-fuse in the anti-fuse group 3 need to be broken down.
  • data 1111 needs to be written to the programmable memory array, the first anti-fuse in the anti-fuse group 1, 2, 3, and 4 needs to be broken down.
  • the reading phase may further include:
  • Input an effective level to the CP terminal of each D-type flip-flop to write the signal at the output terminal to the first output terminal of the D-type flip-flop, and write and write to the second output terminal of the D-type flip-flop A signal with the opposite logic level at the first output.
  • the first high-level signal voltage may be 6V
  • the second high-level signal voltage may be 1V
  • the low-level voltage may be 0V

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Abstract

一种可编程存储单元、可编程存储阵列及其读写方法，可编程存储单元包括：第一反熔丝，连接于第一电源端和输出端之间；第二反熔丝，连接于第二电源端和所述输出端之间；第三开关单元，连接所述输出端、第三电源端以及位置信号端，用于响应所述位置信号端的信号连通所述第三电源端和所述输出端。该可编程存储单元结构简单且具有较高的读取速度。

Description

可编程存储单元、可编程存储阵列及其读写方法
交叉引用
本公开要求于2019年11月28日提交的申请号为201911193706.3、名称为“可编程存储单元、可编程存储阵列及其读写方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及存储技术领域，尤其涉及一种可编程存储单元、可编程存储阵列及其读写方法。
背景技术
由于一次可编程(OTP，One Time Programmable)存储器具有存储状态不受断电影响的特性，能够被应用于各种技术领域中。例如，一次可编程存储单元可以应用于动态随机存取存储器(DRAM)中，以控制冗余存储单元的打开或关断。例如，当有一个字线对应的存储单元区域的存储单元有缺陷时，对应的一次可编程存储单元将被编程(如由逻辑“0”变为逻辑“1”)，DRAM的控制电路将关闭对这个字线对应的存储单元的读写，并将打开冗余区域的存储单元的读写，此时，冗余区域对应的存储单元完全取代了有缺陷的存储区域的存储单元，DRAM的缺陷被修复。
然而，现有技术中的一次可编程存储单元结构复杂、占用面积大，且读取数据速度缓慢、可靠性差。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
根据本公开的一个方面，提供一种可编程存储单元，该可编程存储单元包括：第一反熔丝、第二反熔丝、第三开关单元。第一反熔丝连接于第一电源端和输出端之间；第二反熔丝连接于第二电源端和所述输出端之间；第三开关单元连接所述输出端、第三电源端以及位置信号端，用于响应所述位置信号端的信号连通所述第三电源端和所述输出端。
本公开的一种示例性实施例中，该可编程存储单元还包括第一开关单元、第二开关单元。第一开关单元连接所述第一电源端、所述第一反熔丝的第一端、第一控制端，用于响应所述第一控制端的信号连通所述第一电源端和所述第一反熔丝的第一端；第二开关单元连接所述第二电源端、所述第二反熔丝的第一端、第一控制端，用于响应所述第一控制端 的信号连通所述第二电源端和所述第二反熔丝的第一端。
本公开的一种示例性实施例中，该可编程存储单元还包括D型触发器，所述D型触发器的数据输入端连接所述输出端，CP端连接时钟信号端。
本公开的一种示例性实施例中，所述第三开关单元包括第三晶体管，第三晶体管的控制端连接所述位置信号端，第一端连接所述输出端，第二端连接所述第三电源端。
本公开的一种示例性实施例中，所述第一开关单元包括第一晶体管，第一晶体管的控制端连接所述第一控制端，第一端连接所述第一电源端，第二端连接所述第一反熔丝的第一端；所述第二开关单元包括第二晶体管，第二晶体管的控制端连接所述第一控制端，第一端连接所述第二电源端，第二端连接所述第二反熔丝的第一端。
根据本公开的一个方面，提供一种可编程存储阵列，该可编程存储阵列包括多个反熔丝组、多个第三开关单元，每个所述反熔丝组对应连接不同的输出端，所述反熔丝组包括第一反熔丝和第二反熔丝，其中，所述第一反熔丝连接于与其对应的所述输出端和第一电源端之间，所述第二反熔丝连接于与其对应的所述输出端和第二电源端之间；所述第三开关单元与所述输出端一一对应设置，且每个所述第三开关单元对应连接不同的所述输出端和不同的位置信号端，其中，所述第三开关单元还连接第三电源端，用于响应与其对应的所述位置信号端的信号以连通所述第三电源端、与其对应的输出端。
本公开的一种示例性实施例中，该可编程存储阵列还包括：第一开关单元、第二开关单元。第一开关单元连接所述第一电源端、第一控制端，第一节点，用于响应所述第一控制端的信号将所述第一电源端的信号传输到所述第一节点，其中，所述第一节点连接多个所述第一反熔丝的第一端；第二开关单元连接第二电源端、第一控制端，第二节点，用于响应所述第一控制端的信号将所述第二电源端的信号传输到所述第二节点，其中，所述第二节点连接多个所述第二反熔丝的第一端。
本公开的一种示例性实施例中，该可编程存储阵列还包括：多个D型触发器，所述D型触发器与所述输出端一一对应设置，且每个所述D型触发器的数据输入端对应连接不同的所述输出端，CP端连接时钟信号端。
本公开的一种示例性实施例中，所述第一开关单元包括第一晶体管，第一晶体管的控制端连接所述第一控制端，第一端连接所述第一电源端，第二端连接所述第一节点。
本公开的一种示例性实施例中，所述第二开关单元包括第二晶体管，第二晶体管的控制端连接所述第一控制端，第一端连接所述第二电源端，第二端连接所述第二节点。
本公开的一种示例性实施例中，所述第三开关单元包括第三晶体管，第三晶体管的控制端连接与其对应的位置信号端，第一端连接与其对应的输出端，第二端连接所述第三电源端。
本公开的一种示例性实施例中，所述第三电源端为接地端。
根据本公开的一个方面，提供一种可编程存储阵列读写方法，该方法包括：
在写入阶段：
第一阶段，向第一电源端输入第一高电平信号，向第二电源端、第三电源端输入低电平信号，向预设的位置信号端输入有效电平以导通第三开关单元，从而击穿相应的第一反熔丝；
第二阶段，向第二电源端输入第一高电平信号，向第一电源端、第三电源端输入低电平信号，向预设的位置信号端输入有效电平以导通第三开关单元，从而击穿相应的第二反熔丝；
在读取阶段：
向第一电源端输入第二高电平信号，向第二电源端、第三电源端输入低电平信号，向位置信号端输入无效电平以关断第三开关单元。
本公开的一种示例性实施例中，在读取阶段还包括：
向每个D型触发器的CP端输入有效电平，以将输出端的信号写入所述D型触发器的第一输出端，以及向所述D型触发器的第二输出端写入与第一输出端逻辑电平相反的信号。
本公开的一种示例性实施例中，所述第一高电平信号电压为6V，所述第二高电平信号电压为1V，所述低电平电压为0V。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中一种可编程存储阵列的电路结构示意图；
图2为本公开可编程存储单元一种示例性实施例的电路结构示意图；
图3为本公开可编程存储单元另一种示例性实施例的电路结构示意图；
图4为本公开可编程存储阵列一种示例性实施例的电路结构示意图；
图5为本公开可编程存储阵列另一种示例性实施例的电路结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组 件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成区分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成区分/等之外还可存在另外的要素/组成区分/等。
如图1所示，为相关技术中一种可编程存储阵列的电路结构示意图。该可编程存储阵列包括多个可编程存储单元1。图1以2×2阵列为例进行说明。其中，可编程存储单元1包括有反熔丝AF01、开关晶体管T01。其中，反熔丝AF01的第一端连接列控制信号端C0，第二端连接开关晶体管T01的第一端，开关晶体管T01的第二端连接输出端S1，控制端连接行控制信号端R1。输出端S1还需要连接一灵敏放大器的输入端。
然而，一方面，相关技术中，该可编程存储阵列结构复杂、占用面积较大。另一方面，相关技术中，该可编程存储阵列在应用于动态随机存取存储器中，列控制信号端C0的信号是通过位线上信号解码得到，行控制信号端R1的信号是通过字线上信号解码得到。在该可编程存储阵列读取数据时需要通过向字线和位线输入有效电平信号，以使得列控制信号端C0和行控制信号端R1的信号为有效电平。然而，由于字线和位线的长度较长，寄生电容和寄生电阻较大，因此速度较慢，从而导致该可编程存储阵列读取数据的速度较慢。再一方面，相关技术通过比较灵敏放大器两输入端电压的大小，判断在写入数据的逻辑状态。然而，灵敏放大器SA在读取数据时两输入端之间的电压差本身就比较小，该可编程存储阵列在读取数据时容易发生误读现象，因此，该可编程存储阵列的稳定性较差。
基于此，本示例性实施例首先提供一种可编程存储单元，如图2所示，为本公开可编程存储单元一种示例性实施例的电路图，该可编程存储单元包括：第一反熔丝AF1、第二反熔丝AF2、第三开关单元T3。第一反熔丝AF1连接于第一电源端V1和输出端OUT之间；第二反熔丝AF2连接于第二电源端V2和所述输出端OUT之间；第三开关单元T3连接所述输出端OUT、第三电源端V3以及位置信号端PD，用于响应所述位置信号端PD的信号连通所述第三电源端V3和所述输出端OUT。
本示例性实施例中，当可编程存储单元需要写入数据“1”时，向第一电源端V1输入第一高电平信号，向第二电源端V2、第三电源端V3输入低电平信号，位置信号端PD输入有效电平以导通第三开关单元T3，第一反熔丝AF1在第一电源端V1和第三电源端V3之间电压作用下被击穿。当可编程存储单元需要读取数据“1”时，向第一电源端V1输入第二高电平信号，向第二电源端V2、第三电源端V3输入低电平信号，向位置信号端PD输入无效电平以关断第三开关单元T3，此时，由于第一反熔丝AF1的两端导通，第二反熔丝的两端断开，从而使得输出端OUT输出高电平信号“1”。当可编程存储单元需要写 入数据“0”时，向第二电源端V2输入第一高电平信号，向第一电源端V1、第三电源端V3输入低电平信号，位置信号端PD输入有效电平以导通第三开关单元T3，第二反熔丝AF2在第二电源端V2和第三电源端V3之间电压作用下被击穿。当可编程存储单元需要读取数据“0”时，向第一电源端V1输入第二高电平信号，向第二电源端V2、第三电源端V3输入低电平信号，向位置信号端PD输入无效电平以关断第三开关单元T3，此时，由于第二反熔丝AF2的两端导通，第一反熔丝AF1的两端断开，从而使得输出端OUT输出低电平信号“0”。其中，第一高电平信号用于击穿反熔丝，因此，第一高电平信号可以大于第二高电平信号。例如，所述第一高电平信号电压可以为6V，所述第二高电平信号电压可以为1V，所述低电平电压可以为0V。
本示例性实施例中，一方面，该可编程存储单元中不需要设置灵敏放大器，从而简化了可编程存储单元的结构，缩小了可编程存储单元的占用面积。另一方面，本示例性实施例中，位置信号端PD可以通过位线和字线上的信号解码得到，当位线和字线同时为有效电平时，位置信号端PD的电平为有效电平，该设置通过解码器中的“与门”将相关技术中的两个位置信号端合为一个位置信号端，相应的，减小了开关单元的设置数量，从而进一步简化了可编程存储单元的结构。再一方面，由于该可编程存储单元在读取数据阶段，位置信号端PD输出的是无效电平信号，从而避免了字线、位线寄生RC造成的读取速度缓慢的技术问题。再一方面，反熔丝在被击穿和没被击穿状态下的电阻相差至少两个数量级，在读数据“1”和数据“0”时，上述输出端OUT的电压差异比较大，因而该可编程存储单元具有较高的稳定性。
本示例性实施例中，如图3所示，为本公开可编程存储单元另一种示例性实施例的电路图。该可编程存储单元还包括第一开关单元T1、第二开关单元T2。第一开关单元T1连接所述第一电源端V1、所述第一反熔丝AF1的第一端、第一控制端CN1，用于响应所述第一控制端CN1的信号连通所述第一电源端V1和所述第一反熔丝AF1的第一端；第二开关单元T2连接所述第二电源端V2、所述第二反熔丝AF2的第一端、第一控制端CN1，用于响应所述第一控制端CN1的信号连通所述第二电源端V2和所述第二反熔丝AF2的第一端。在该可编程存储单元需要读取或写入数据时，第一控制端CN1输入有效电平以导通第一开关单元T1和第二开关单元T2。在写入数据和读出数据时，可以通过第一控制端CN1的电压大小控制流过第一反熔丝AF1和第二反熔丝AF2的电流大小。
本示例性实施例中，如图3所示，该可编程存储单元还可以包括D型触发器TG，所述D型触发器TG的数据输入端D连接所述输出端OUT，CP端连接时钟信号端Clk。在时钟信号端Clk为有效电平时，D型触发器将输出端OUT的信号锁存在D型触发器的Q端以及将输出端的反向逻辑信号锁存在D型触发器的Qb端。
本示例性实施例中，如图2、3所示，所述第三开关单元T3可以包括第三晶体管，第三晶体管的控制端连接所述位置信号端PD，第一端连接所述输出端OUT，第二端连接所述第三电源端V3。
本示例性实施例中，如图3所示，所述第一开关单元T1可以包括第一晶体管，第一晶体管的控制端连接所述第一控制端CN1，第一端连接所述第一电源端V1，第二端连接所述第一反熔丝AF1的第一端；所述第二开关单元T2可以包括第二晶体管，第二晶体管的控制端连接所述第一控制端CN1，第一端连接所述第二电源端V2，第二端连接所述第二反熔丝AF2的第一端。
其中，第一晶体管、第二晶体管、第三晶体管既可以为N型晶体管也可以为P型晶体管。本示例性实施例中，第一晶体管、第二晶体管为P型晶体管，第三晶体管为N型晶体管。
本示例性实施例还提供一种可编程存储阵列，如图4所示，为本公开可编程存储阵列一种示例性实施例的电路结构示意图。该可编程存储阵列包括：多个反熔丝组1……n、多个第三开关单元T31……T3n，每个所述反熔丝组1……n对应连接不同的输出端OUT1……OUTn，所述反熔丝组包括第一反熔丝AF1和第二反熔丝AF2，其中，所述第一反熔丝AF1连接于与其对应的所述输出端和所述第一电源端V1之间，所述第二反熔丝AF2连接于与其对应的所述输出端和所述第二电源端V2之间；所述第三开关单元T31……T3n与所述输出端OUT1……OUTn一一对应设置，且每个所述第三开关单元对应连接不同的所述输出端和不同的位置信号端PD1……PDn，其中，所述第三开关单元还连接第三电源端V3，用于响应与其对应的所述位置信号端的信号以连通所述第三电源端V3和与其对应的输出端。实质上，该可编程存储阵列包括多个上述的可编程存储单元。
本示例性实施例以反熔丝组1为例进行说明，当可编程存储阵列需要向反熔丝组1写入数据“1”时，向第一电源端V1输入第一高电平信号，向第二电源端V2、第三电源端V3输入低电平信号，位置信号端PD1输入有效电平以导通第三开关单元T31，第一反熔丝AF1在第一电源端V1和第三电源端V3之间电压作用下被击穿。当可编程存储阵列需要从反熔丝组读取数据“1”时，向第一电源端V1输入第二高电平信号，向第二电源端V2、第三电源端V3输入低电平信号，向位置信号端PD1输入无效电平以关断第三开关单元T31，此时，由于第一反熔丝AF1的两端导通，第二反熔丝的两端断开，从而使得输出端OUT1输出高电平信号“1”。当可编程存储阵列需要向反熔丝组1写入数据“0”时，向第二电源端V2输入第一高电平信号，向第一电源端V1、第三电源端V3输入低电平信号，位置信号端PD1输入有效电平以导通第三开关单元T31，第二反熔丝AF2在第二电源端V2和第三电源端V3之间电压作用下被击穿。当可编程存储阵列需要从反熔丝组1读取数据“0”时，向第一电源端V1输入第二高电平信号，向第二电源端V2、第三电源端V3输入低电平信号，向位置信号端PD1输入无效电平以关断第三开关单元T31，此时，由于第二反熔丝AF2的两端导通，第一反熔丝AF1的两端断开，从而使得输出端OUT1输出高电平信号“0”。其中，第一高电平信号用于击穿反熔丝，因此，第一高电平信号大于第二高电平信号。例如，所述第一高电平信号电压可以为6V，所述第二高电平信号电压可以为1V，所述低电平电压可以为0V。
本示例性实施例中，一方面，该可编程存储阵列中不需要设置灵敏放大器，从而简化了可编程存储阵列的结构，缩小了可编程存储阵列的占用面积。另一方面，本示例性实施例中，位置信号端PD1……PDn可以通过位线和字线上的信号解码得到，当位线和字线同时为有效电平时，位置信号端PD1……PDn的电平为有效电平，该设置通过解码器中的“与门”将相关技术中的两个位置信号端合为一个位置信号端，相应的，减小了开关单元的设置数量，从而进一步简化了可编程存储阵列的结构。再一方面，由于该可编程存储阵列在读取数据阶段，位置信号端PD1……PDn输出的是无效电平信号，从而避免了字线、位线自身RC压降造成的读取速度缓慢的技术问题。再一方面，反熔丝在被击穿和没被击穿状态下的电阻相差两个数量级，在读数据“1”和数据“0”时，上述输出端OUT1的电压差异比较大，因而该可编程存储阵列具有较高的稳定性。再一方面，由于读取时不需要灵敏放大器且不需要字线位线进行定位，可编程存储阵列中存储信息可以并行读出，显著提高了可编程存储阵列的读取速度。
本示例性实施例中，如图5所示，为本公开可编程存储阵列另一种示例性实施例的电路结构示意图。该可编程存储阵列还可以包括：第一开关单元T1、第二开关单元T2。第一开关单元T1连接第一电源端V1、第一控制端CN1，第一节点N1，用于响应所述第一控制端CN1的信号将所述第一电源端V1的信号传输到所述第一节点N1，其中，所述第一节点N1连接多个所述第一反熔丝AF1的第一端；第二开关单元T2连接第二电源端V2、第一控制端CN1，第二节点N2，用于响应所述第一控制端CN1的信号将所述第二电源端V2的信号传输到所述第二节点N2，其中，所述第二节点N2连接多个所述第二反熔丝AF2的第一端。在该可编程存储阵列需要读取或写入数据时，第一控制端CN1输入有效电平以导通第一开关单元T1和第二开关单元T2。
本示例性实施例中，如图5所示，该可编程存储阵列还可以包括多个D型触发器TG1……TGn，所述D型触发器TG1……TGn与所述输出端OUT1……OUTn一一对应设置，且每个所述D型触发器的数据输入端对应连接不同的所述输出端，CP端连接时钟信号端Clk。在时钟信号端Clk为有效电平时，D型触发器将输出端的信号锁存在D型触发器的Q端以及将输出端的反向逻辑信号锁存在D型触发器的Qb端。
本示例性实施例中，如图5所示，所述第一开关单元可以包括第一晶体管，第一晶体管的控制端连接所述第一控制端，第一端连接所述第一电源端，第二端连接所述第一节点。
本示例性实施例中，如图5所示，所述第二开关单元可以包括第二晶体管，第二晶体管的控制端连接所述第一控制端，第一端连接所述第二电源端，第二端连接所述第二节点。
本示例性实施例中，如图4、5所示，所述第三开关单元可以包括第三晶体管，第三晶体管的控制端连接与其对应的位置信号端，第一端连接与其对应的输出端，第二端连接所述第三电源端。
其中，第一晶体管、第二晶体管、第三晶体管既可以为N型晶体管也可以为P型晶体管。本示例性实施例中，第一晶体管、第二晶体管为P型晶体管，第三晶体管为N型 晶体管。
本示例性实施例中，所述第三电源端V3可以为接地端。
本示例性实施例还提供一种可编程存储阵列读写方法，该方法包括：
在写入阶段：
第一阶段，向第一电源端输入第一高电平信号，向第二电源端、第三电源端输入低电平信号，向预设的位置信号端输入有效电平以导通第三开关单元，从而击穿相应的第一反熔丝；
第二阶段，向第二电源端输入第一高电平信号，向第一电源端、第三电源端输入低电平信号，向预设的位置信号端输入有效电平以导通第三开关单元，从而击穿相应的第二反熔丝；
在读取阶段：
向第一电源端输入第二高电平信号，向第二电源端、第三电源端输入低电平信号，向位置信号端输入无效电平以关断第三开关单元。
本示例性实施例以该可编程存储阵列包括四个反熔丝组1、2、3、4为例进行说明。当需要向该可编程存储阵列写入数据0000时，需要击穿反熔丝组1、2、3、4中的第二反熔丝。当需要向该可编程存储阵列写入数据0001时，需要击穿反熔丝组1、2、3中的第二反熔丝，反熔丝组4中的第一反熔丝。当需要向该可编程存储阵列写入数据0010时，需要击穿反熔丝组1、2、4中的第二反熔丝，反熔丝组3中的第一反熔丝。当需要向该可编程存储阵列写入数据1111时，需要击穿反熔丝组1、2、3、4中的第一反熔丝。
本示例性实施例中，在读取阶段还可以包括：
向每个D型触发器的CP端输入有效电平，以将输出端的信号写入所述D型触发器的第一输出端，以及向所述D型触发器的第二输出端写入与第一输出端逻辑电平相反的信号。
本示例性实施例中，所述第一高电平信号电压可以为6V，所述第二高电平信号电压可以为1V，所述低电平电压可以为0V。
本领域技术人员在考虑说明书及实践这里公开的公开后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性远离并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (15)

  1. 一种可编程存储单元，其中，包括：
    第一反熔丝，连接于第一电源端和输出端之间；
    第二反熔丝，连接于第二电源端和所述输出端之间；
    第三开关单元，连接所述输出端、第三电源端以及位置信号端，用于响应所述位置信号端的信号连通所述第三电源端和所述输出端。
  2. 根据权利要求1所述的可编程存储单元，其中，还包括：
    第一开关单元，连接所述第一电源端、所述第一反熔丝的第一端、第一控制端，用于响应所述第一控制端的信号连通所述第一电源端和所述第一反熔丝的第一端；
    第二开关单元，连接所述第二电源端、所述第二反熔丝的第一端、第一控制端，用于响应所述第一控制端的信号连通所述第二电源端和所述第二反熔丝的第一端。
  3. 根据权利要求1所述的可编程存储单元，其中，还包括：
    D型触发器，所述D型触发器的数据输入端连接所述输出端，CP端连接时钟信号端。
  4. 根据权利要求1所述的可编程存储单元，其中，所述第三开关单元包括：
    第三晶体管，控制端连接所述位置信号端，第一端连接所述输出端，第二端连接所述第三电源端。
  5. 根据权利要求2所述的可编程存储单元，其中，
    所述第一开关单元包括：
    第一晶体管，控制端连接所述第一控制端，第一端连接所述第一电源端，第二端连接所述第一反熔丝的第一端；
    所述第二开关单元包括：
    第二晶体管，控制端连接所述第一控制端，第一端连接所述第二电源端，第二端连接所述第二反熔丝的第一端。
  6. 一种可编程存储阵列，其中，包括：
    多个多个反熔丝组，每个所述多个反熔丝组对应连接不同的输出端，所述多个反熔丝组包括第一反熔丝和第二反熔丝，其中，所述第一反熔丝连接于与其对应的所述输出端和第一电源端之间，所述第二反熔丝连接于与其对应的所述输出端和第二电源端之间；
    多个第三开关单元，所述第三开关单元与所述输出端一一对应设置，且每个所述第三开关单元对应连接不同的所述输出端和不同的位置信号端，其中，所述第三开关单元还连接第三电源端，用于响应与其对应的所述位置信号端的信号以连通所 述第三电源端、与其对应的输出端。
  7. 根据权利要求6所述的可编程存储阵列，其中，还包括：
    第一开关单元，连接所述第一电源端、第一控制端，第一节点，用于响应所述第一控制端的信号将所述第一电源端的信号传输到所述第一节点，其中，所述第一节点连接多个所述第一反熔丝的第一端；
    第二开关单元，连接第二电源端、第一控制端，第二节点，用于响应所述第一控制端的信号将所述第二电源端的信号传输到所述第二节点，其中，所述第二节点连接多个所述第二反熔丝的第一端。
  8. 根据权利要求6所述的可编程存储阵列，其中，还包括：
    多个D型触发器，所述D型触发器与所述输出端一一对应设置，且每个所述D型触发器的数据输入端对应连接不同的所述输出端，CP端连接时钟信号端。
  9. 根据权利要求7所述的可编程存储阵列，其中，所述第一开关单元包括：
    第一晶体管，控制端连接所述第一控制端，第一端连接所述第一电源端，第二端连接所述第一节点。
  10. 根据权利要求7所述的可编程存储阵列，其中，所述第二开关单元包括：
    第二晶体管，控制端连接所述第一控制端，第一端连接所述第二电源端，第二端连接所述第二节点。
  11. 根据权利要求6所述的可编程存储阵列，其中，所述第三开关单元包括：
    第三晶体管，控制端连接与其对应的位置信号端，第一端连接与其对应的输出端，第二端连接所述第三电源端。
  12. 根据权利要求6所述的可编程存储阵列，其中，所述第三电源端为接地端。
  13. 一种可编程存储阵列读写方法，其中，包括：
    在写入阶段：
    第一阶段，向第一电源端输入第一高电平信号，向第二电源端、第三电源端输入低电平信号，向预设的位置信号端输入有效电平以导通第三开关单元，从而击穿相应的第一反熔丝；
    第二阶段，向第二电源端输入第一高电平信号，向第一电源端、第三电源端输入低电平信号，向预设的位置信号端输入有效电平以导通第三开关单元，从而击穿相应的第二反熔丝；
    在读取阶段：
    向第一电源端输入第二高电平信号，向第二电源端、第三电源端输入低电平信号，向位置信号端输入无效电平以关断第三开关单元。
  14. 根据权利要求13所述的可编程存储阵列读写方法，其中，在读取阶段还包括：
    向每个D型触发器的CP端输入有效电平，以将输出端的信号写入所述D型触发器的第一输出端，以及向所述D型触发器的第二输出端写入与第一输出端逻辑电平相反的信号。
  15. 根据权利要求13所述的可编程存储阵列读写方法，其中，
    所述第一高电平信号电压为6V，所述第二高电平信号电压为1V，所述低电平电压为0V。
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