WO2021056957A1 - 电源模块和存储器 - Google Patents

电源模块和存储器 Download PDF

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Publication number
WO2021056957A1
WO2021056957A1 PCT/CN2020/076310 CN2020076310W WO2021056957A1 WO 2021056957 A1 WO2021056957 A1 WO 2021056957A1 CN 2020076310 W CN2020076310 W CN 2020076310W WO 2021056957 A1 WO2021056957 A1 WO 2021056957A1
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Prior art keywords
output terminal
terminal
unit
inverter
output
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PCT/CN2020/076310
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English (en)
French (fr)
Inventor
季汝敏
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长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP20869411.7A priority Critical patent/EP3896832B1/en
Priority to US17/268,239 priority patent/US11393521B2/en
Publication of WO2021056957A1 publication Critical patent/WO2021056957A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
    • H02M1/0035—Control circuits allowing low power mode operation, e.g. in standby mode using burst mode control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0041—Control circuits in which a clock signal is selectively enabled or disabled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/033—Monostable circuits

Definitions

  • the invention relates to the field of integrated circuits, in particular to a power supply module and a memory.
  • DRAM chips require various power modules, such as charge pumps, linear regulators, etc., for different functional modules (such as word line drive voltage VPP, back gate bias voltage VBB, bit line precharge voltage VCC/2, etc.) powered by.
  • various operation modes are frequently switched. Under different operation modes, the current drawn by each functional module is different, which causes the output voltage of the power module to change. For example, in the low-power mode, when a heavy load suddenly occurs, the output voltage of the power module will be quickly pulled down, and the voltage module will start boosting with a certain delay. During this delay, there is no energy supply. The output voltage of the voltage module continues to decrease, resulting in a large undershot of the output voltage, which affects the subsequent operations of other modules.
  • the technical problem to be solved by the present invention is to provide a power module and a memory to improve the transient response capability of the power module, thereby improving the stability of the memory.
  • the present invention provides a power supply module, including: a boost unit having a power output terminal for outputting a power supply voltage; an enable unit connected to the power output terminal for generating an enable signal When the voltage at the output terminal of the power supply drops to a set value, the enable signal generates a rising edge;
  • the control unit includes: an oscillator, a pulse generator, and an OR operation unit; the oscillator and the enable The output terminal of the enable unit is connected, the oscillator is triggered by the rising edge of the enable signal, and is used to generate a delay pulse control signal of a certain period;
  • the pulse generator is connected with the output terminal of the enable unit , Used to synchronously generate an instant pulse control signal while receiving the rising edge of the enable signal;
  • the "OR" operation unit is connected to the oscillator and the output terminal of the pulse generator for matching The delayed pulse control signal and the instant pulse control signal are ORed to generate a boost control signal;
  • the output terminal of the control unit is connected to the boost unit for controlling the boost The signal
  • the boosting unit is a charge pump circuit.
  • the enabling unit includes: a comparator and a voltage divider circuit, one end of the voltage divider circuit is connected to the power output terminal, the other end is grounded, and the output terminal of the voltage divider circuit is connected to the comparator
  • the positive input terminal of the comparator is connected to the reference voltage terminal, and the voltage value of the reference voltage terminal is the set value.
  • the voltage dividing circuit includes: a first voltage dividing resistor and a second voltage dividing resistor, a first end of the first voltage dividing resistor is connected to the power output terminal, and the first voltage dividing resistor is The second end is connected to the first end of the second voltage dividing resistor, the second end of the second voltage dividing resistor is grounded, and the connecting end of the first voltage dividing resistor and the second voltage dividing resistor is used as the The output terminal of the voltage divider circuit.
  • the "OR" operation unit includes a NOR gate and a NOR gate connected in sequence, and the two input terminals of the NOR gate are respectively connected to the output terminal of the pulse generator and the oscillator.
  • the output terminal, the output terminal of the NOR gate is connected to the input terminal of the NOT gate, and the output terminal of the NOT gate is connected to the input terminal of the boost unit.
  • the pulse generator includes a delay inverting circuit and an AND operation unit; the input terminal of the delay inverting circuit is connected to the output terminal of the enabling unit for enabling the The signal is inverted and output with a delay; the AND operation unit is connected to the output terminal of the delay inverting circuit and the output terminal of the enabling unit, and is used to output the signal from the delay inverting circuit Perform an AND operation with the enable signal.
  • the delay inverting circuit includes: a first inverter, a resistor, and a capacitor, the input terminal of the first inverter is connected to the output terminal of the enabling unit, and the first inverter The output end of the resistor is connected to the first end of the resistor, the second end of the resistor is connected to the first end of the capacitor, the second end of the capacitor is grounded, and the first end of the capacitor serves as the The output terminal of the delay inverter circuit.
  • the delay inverting circuit includes: a first inverter, a second inverter, a third inverter, a first capacitor, and a second capacitor; the input terminal of the first inverter is connected To the output terminal of the enabling unit, the first inverter output terminal is connected to the first terminal of the first capacitor and connected to the input terminal of the second inverter; the second inverter The output terminal is connected to the first terminal of the second capacitor and connected to the input terminal of the third inverter; the second terminals of the first capacitor and the second capacitor are both grounded, and the third inverter The output terminal of the converter is used as the output terminal of the delay inverting circuit.
  • the "AND" operation unit includes a NAND gate and a NAND gate connected to the NAND gate.
  • the first rising edge of the instant pulse control signal and the rising edge of the enable signal are generated at the same time.
  • the technical solution of the present invention also provides a memory, including a power supply module, the power supply module includes: the power supply module includes: a boosting unit having a power output terminal for outputting a power supply voltage; an enabling unit connected to the The power output terminal is used to generate an enable signal.
  • the control unit includes: an oscillator, a pulse generator, and an OR operation Unit; the oscillator is connected to the output terminal of the enabling unit, the oscillator is triggered by the rising edge of the enabling signal, and is used to generate a certain period of delayed pulse control signal; the pulse generator, Connected to the output terminal of the enabling unit, and used to synchronously generate an instant pulse control signal while receiving the rising edge of the enabling signal; the OR operation unit is connected to the oscillator and the The output terminal of the pulse generator is used to OR the delay pulse control signal and the instant pulse control signal to generate a boost control signal; the output terminal of the control unit is connected to the boost The unit is used for outputting the boosting control signal to the boosting unit, and controlling the boosting unit to increase the output power supply voltage.
  • the boosting unit is a charge pump circuit.
  • the enabling unit includes: a comparator and a voltage divider circuit, one end of the voltage divider circuit is connected to the power output terminal, the other end is grounded, and the output terminal of the voltage divider circuit is connected to the comparator
  • the positive input terminal of the comparator is connected to the reference voltage terminal, and the voltage value of the reference voltage terminal is the set value.
  • the voltage dividing circuit includes: a first voltage dividing resistor and a second voltage dividing resistor, a first end of the first voltage dividing resistor is connected to the power output terminal, and the first voltage dividing resistor is The second end is connected to the first end of the second voltage dividing resistor, the second end of the second voltage dividing resistor is grounded, and the connecting end of the first voltage dividing resistor and the second voltage dividing resistor is used as the The output terminal of the voltage divider circuit.
  • the "OR" operation unit includes a NOR gate and a NOR gate connected in sequence, and the two input terminals of the NOR gate are respectively connected to the output terminal of the pulse generator and the oscillator.
  • the output terminal, the output terminal of the NOR gate is connected to the input terminal of the NOT gate, and the output terminal of the NOT gate is connected to the input terminal of the boost unit.
  • the pulse generator includes a delay inverting circuit and an AND operation unit; the input terminal of the delay inverting circuit is connected to the output terminal of the enabling unit for enabling the The signal is inverted and output with a delay; the AND operation unit is connected to the output terminal of the delay inverting circuit and the output terminal of the enabling unit, and is used to output the signal from the delay inverting circuit Perform an AND operation with the enable signal.
  • the delay inverting circuit includes: a first inverter, a resistor, and a capacitor, the input terminal of the first inverter is connected to the output terminal of the enabling unit, and the first inverter The output end of the resistor is connected to the first end of the resistor, the second end of the resistor is connected to the first end of the capacitor, the second end of the capacitor is grounded, and the first end of the capacitor serves as the The output terminal of the delay inverter circuit.
  • the delay inverting circuit includes: a first inverter, a second inverter, a third inverter, a first capacitor, and a second capacitor; the input terminal of the first inverter is connected To the output terminal of the enabling unit, the first inverter output terminal is connected to the first terminal of the first capacitor and connected to the input terminal of the second inverter; the second inverter The output terminal is connected to the first terminal of the second capacitor and connected to the input terminal of the third inverter; the second terminals of the first capacitor and the second capacitor are both grounded, and the third inverter The output terminal of the converter is used as the output terminal of the delay inverting circuit.
  • the "AND" operation unit includes a NAND gate and a NAND gate connected to the NAND gate.
  • the first rising edge of the instant pulse control signal and the rising edge of the enable signal are generated at the same time.
  • the power supply module of the present invention can supplement energy to the boost unit in time after detecting the voltage drop at the output terminal of the power supply, and adjust the output voltage back to a normal potential, so that the output terminal of the power supply can obtain energy supplement without waiting. Reduce the drop in output voltage to prevent errors in subsequent circuits.
  • Figure 1a is a schematic structural diagram of a power module in the prior art of the present invention.
  • FIG. 1b is a schematic diagram of the sequence of each signal of the power module in the prior art of the present invention.
  • FIG. 2 is a schematic structural diagram of a power supply module according to a specific embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a specific circuit structure of a boost unit of a power supply module according to a specific embodiment of the present invention
  • FIG. 4 is a schematic diagram of the timing of each signal in the power supply module in a specific embodiment of the present invention.
  • 5a is a schematic diagram of a circuit structure of a pulse generator of a power module according to a specific embodiment of the present invention.
  • 5b is a schematic diagram of a circuit structure of a pulse generator of a power module according to a specific embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a time sequence of a specific embodiment of the present invention and a change in output voltage of a power supply module in the prior art.
  • FIG. 1a is a schematic structural diagram of a power module in the prior art.
  • the power supply module includes: a charge pump circuit 102, the power output terminal Vout is used to output a power supply voltage to the load, the power output terminal Vout is connected to a resistor R1 and a resistor R2 connected in series to the ground, and the resistor R1 and the resistor R2 serve as a voltage divider Circuit, the connection terminal of the two is connected to the negative input terminal of the comparator CMP1, the positive input terminal of the comparator CMP1 is connected to the reference voltage Vref, and the output terminal of the comparator CMP1 is connected to the oscillator 101, through the oscillation The output terminal of the device 101 is connected to the charge pump circuit 102.
  • the oscillator 101 is turned off to save power.
  • the oscillator 101 is enabled from receiving the enable signal OSC_EN to outputting the pulse signal CLK, there will be a delay T_delay (please refer to Figure 1b).
  • T_delay please refer to Figure 1b.
  • reducing the pulse delay of the boost control signal CLK for controlling the boost of the charge pump circuit 102 can reduce the drop in the output voltage Vout, and supplement energy to the charge pump circuit 102 in time to stabilize the output power supply voltage.
  • the inventor proposes a new power module that can respond quickly when the load suddenly becomes heavier and reduce the drop in output voltage.
  • FIG. 2 is a schematic structural diagram of a power module according to a specific embodiment of the present invention.
  • the power supply module includes: a boosting unit 201, an enabling unit 202, and a control unit 203.
  • the boosting unit 201 has a power output terminal Vout for outputting a power supply voltage Vout;
  • the boosting unit 201 includes a load capacitor, one end of the load capacitor serves as a power output terminal Vout, and the load capacitor is charged to output a power supply voltage. When the output drops, the output voltage can be pulled up by supplementing energy to the load capacitor.
  • the boosting unit 201 may be a charge pump circuit.
  • FIG. 3 is a schematic diagram of a specific circuit structure of the boost unit 201 according to a specific embodiment of the present invention.
  • the boost unit 201 includes an inverter INV, a capacitor C′, a transistor M1 and a transistor M2, and a load capacitor C LOAD .
  • Drain of the transistor M1 is connected to the power supply Vcc, a source connected to the drain of the transistor M2, the transistor M2 is connected to the source terminal of a first load capacitor C LOAD is the load capacitance C LOAD second terminal is grounded.
  • the gates of the transistor M1 and the transistor M2 are both connected to the drain.
  • the input terminal of the inverter INV is used to input the boost control signal CLK, the output terminal is connected to the first terminal A of the capacitor C', and the other terminal B of the capacitor C'is connected to the transistors M1 and M2. Connect the end.
  • the capacitor C' is charged by the boost control signal CLK, thereby supplementing energy to the load capacitor C LOAD and increasing the power supply voltage output by the first end of the load capacitor C LOAD.
  • the boost unit 201 may also adopt a charge pump circuit of other structure, or adopt another structure of a boost unit that can be controlled by a pulse signal.
  • Those skilled in the art can reasonably select a suitable circuit structure as the boosting unit 201 according to the requirements of the output voltage of the power supply module.
  • the enabling unit 202 is connected to the power output terminal Vout and is used to generate an enable signal. When the voltage at the power output terminal Vout drops to a set value, the enable signal generates a rising edge. The enabling unit 202 is used to detect the voltage of the power output terminal Vout.
  • the enabling unit 202 includes a voltage divider circuit 2021 and a comparator CMP2.
  • One end of the voltage divider circuit 2021 is connected to the power output terminal Vout, and the other end is grounded to GND1.
  • the output terminal of the voltage divider circuit 2021 is connected to the negative input terminal of the comparator CMP2, and the positive input terminal of the comparator CMP2
  • the terminal is connected to the reference voltage terminal, and the reference voltage value Vref2 is a set value.
  • the voltage at the output terminal of the voltage divider circuit 2021 varies with the voltage at the output terminal Vout of the power supply. Preferably, it is proportional to the voltage at the output terminal Vout of the power supply, and can accurately reflect the output voltage of the output terminal Vout of the power supply. And changes.
  • the voltage dividing circuit 2021 includes a first voltage dividing resistor R11 and a second voltage dividing resistor R12, a first end of the first voltage dividing resistor R11 is connected to the power output terminal Vout, and the The second end of the first voltage divider R11 is connected to the first end of the second voltage divider R12, the second end of the second voltage divider R12 is grounded to GND1, the first voltage divider R11 and the The connecting end of the second voltage dividing resistor R12 serves as the output end of the voltage dividing circuit 2021.
  • the size of the first voltage dividing resistor R11 and the second voltage dividing resistor R12 can be reasonably selected according to the requirements of the ratio of the voltage division.
  • the voltage divider circuit 2021 may also have other circuit structures. In other specific embodiments, the voltage divider circuit 2021 of the enabling unit 202 may also be another circuit structure capable of monitoring the voltage at the output terminal Vout of the power supply at any time.
  • the oscillator 2031 When the output voltage of the power supply output terminal Vout is relatively high, the voltage value of the voltage divider circuit 2021 output to the negative input terminal of the comparator CMP2 is greater than the reference voltage Vref2 of the positive input terminal, and the enable signal OSC_EN2 output by the comparator CMP2 is low power Level, the oscillator 2031 is turned off. When the power supply voltage Vout decreases, the voltage value output by the voltage divider circuit 2021 to the negative input terminal of the comparator CMP2 is less than the reference voltage Vref2 at the positive input terminal, and the enable signal OSC_EN2 output by the comparator CMP2 generates a rising edge and becomes a high-level signal. The oscillator 2031 is triggered to work.
  • the enabling unit 202 outputs a corresponding enabling signal OSC_EN2 according to the voltage change of the power output terminal Vout.
  • the control unit 203 includes: an oscillator 2031, a pulse generator 2032, and an OR operation unit 2033.
  • the input terminal of the oscillator 2031 is connected to the output terminal of the enabling unit 202.
  • the enable signal OSC_EN2 is at a high level, the oscillator 2031 is triggered by the enable signal OSC_EN2 to generate a certain amount of Periodic delayed pulse control signal CLK2.
  • the pulse generator 2032 is connected to the output terminal of the enabling unit 202, and is used to synchronously generate an instant pulse control signal one-shot while receiving the rising edge of the enabling signal OSC_EN2.
  • the pulse generator 2032 is triggered by the rising edge of the enable signal OSC_EN2 to generate the instant pulse control signal one-shot that is a single pulse signal, that is, there is only one pulse.
  • the “OR” operation unit 2033 is connected to the output terminals of the oscillator 2031 and the pulse generator 2032, and is used to perform “OR” on the delayed pulse control signal CLK2 and the instant pulse control signal one-shot. "Operation to generate the boost control signal CLK2'.
  • the "OR" operation unit 2033 includes a NOR gate NOR1 and a NOT gate NOT1 connected in sequence, and two input terminals of the NOR gate NOR1 are respectively connected to the output of the pulse generator 2032 Terminal and the output terminal of the oscillator 2031, the output terminal of the NOR gate NOR1 is connected to the input terminal of the NOT gate NOT1, and the output terminal of the NOT gate NOT1 is connected to the input terminal of the boost unit 201 .
  • the output terminal of the control unit 203 is connected to the boost unit 202 for outputting the boost control signal CLK2' to the boost unit 202, and controls the boost unit 202 to increase the output power supply voltage .
  • FIG. 4 is a timing diagram of each signal in the power module in a specific embodiment of the present invention.
  • the first pulse of the delay pulse control signal CLK2 is delayed at the moment when the enable signal OSC_EN2 becomes high level (that is, the rising edge moment), and the delay time is T.
  • the pulse generator 2032 receives the high-level enable signal OSC_EN2, it will generate an instant pulse control signal one-shot, and the instant pulse control signal one-shot is basically aligned with the rising edge of the enable signal OSC_EN2 , Produced at the same time or almost at the same time.
  • the "OR” operation unit 2033 performs an “OR” operation on the delay pulse control signal CLK2 and the instant pulse control signal one-shot to generate a boost control signal CLK2'.
  • the boost control signal CLK2' is an instant pulse of the instant pulse control signal one-shot, followed by the delayed pulse control signal CLK2.
  • the power module of the present invention when detecting the voltage drop of the power output terminal Vout, the enable signal OSC_EN2 becomes high level, immediately generates the pulse of the boost control signal CLK2', and timely supplements the energy of the boost unit 201 to improve
  • the voltage at the output terminal Vout of the power supply adjusts the output voltage back to the normal potential. Since the instant pulse control signal one-shot signal is generated immediately when the oscillator 2031 is enabled, and the boost unit 201 supplements energy to the power output terminal Vout, the output terminal Vout does not need to wait for T to obtain energy supplementation, thus It can reduce the output voltage drop and prevent errors in subsequent circuits.
  • the pulse generator 2032 includes a delay inversion circuit and an AND operation unit; the input terminal of the delay inversion circuit is connected to the output terminal of the enabling unit 202 for inverting the enabling signal Phase parallel delayed output; the AND operation unit is connected to the output terminal of the delay inverting circuit and the output terminal of the enabling unit 202, and is used to sum the signal output by the delay inverting circuit
  • the enable signal performs an "AND" operation.
  • FIG. 5a is a schematic structural diagram of a pulse generator according to a specific embodiment of the present invention.
  • the pulse generator 2032 includes the delay inversion circuit 601 and the AND operation unit 602.
  • the delay inverting circuit 601 includes: a first inverter INV1, a second inverter INV2, a third inverter INV3, a first capacitor C1 and a second capacitor C2;
  • the input terminal is connected to the output terminal of the enabling unit 202, and the output terminal of the first inverter INV1 is connected to the first terminal of the first capacitor C1 and to the input terminal of the second inverter INV2;
  • the output terminal of the second inverter INV2 is connected to the first terminal of the second capacitor C2, and is connected to the input terminal of the third inverter INV3;
  • the second terminals are all grounded, and the output terminal of the third inverter INV3 is used as the output terminal of the delay inverter circuit 601.
  • the AND operation unit 602 includes a NAND gate NAND1, and a NAND gate NOT2 connected to the NAND gate NAND1.
  • the two input terminals of the NAND gate NAND1 are respectively connected to the output terminal of the enabling unit 202 and the output terminal of the delay inverting circuit 601.
  • the output terminal of the NAND gate NAND1 is connected to the input terminal of the NOT gate NOT2, and the output terminal of the NOT gate NOT2 serves as the output terminal of the pulse generator 2032.
  • the delay inverting circuit 601 includes a first capacitor C1 and a second capacitor C2, when the enable signal OSC_EN2 output by the enabling unit 202 changes to a high level, the capacitors C1 and C2 need to be charged,
  • the enable signal OSC_EN2 can be inverted and output, that is, after a delay, can the low level be output to the "and" operation unit 602; therefore, the "and" operation unit 602 responds to the enable signal
  • OSC_EN2 and the delay inversion circuit 601 perform an AND operation, they will output a high level for a certain period of time, and after the delay inversion circuit 601 outputs a low level, the AND operation unit 602 outputs low level.
  • the pulse generator 2032 will generate a high level at the moment when OSC_EN2 changes to a high level and within a certain period of time, and then generate a low level, thereby generating an instant control pulse one-shot.
  • the pulse width of the one-shot instant control pulse can be adjusted by adjusting the size of the first capacitor C1 and the second capacitor C2, so as to prevent the pulse width from being too small to cause the energy supplement of the boost unit 201 to be too small, or the pulse Excessively large energy supplementation of the boost unit 201 results in an overshoot of the output voltage.
  • the pulse width of the one-shot can be adjusted to be close to or consistent with the pulse width generated by the oscillator 203.
  • FIG. 5b is a schematic structural diagram of a pulse generator according to another specific embodiment of the present invention.
  • the delay inverting circuit 603 includes an inverter INV4, a resistor R', and a capacitor C3.
  • the input terminal of the inverter INV4 is connected to the output terminal of the enabling unit 202, and the output of the inverter INV4 Terminal is connected to the first terminal of the resistor R', the second terminal of the resistor R'is connected to the first terminal of the capacitor C3, the second terminal of the capacitor C3 is grounded, and the first terminal of the capacitor C3 The terminal is used as the output terminal of the delay inverting circuit 603.
  • the delay inversion circuit 603 includes a capacitor C3, when the enable signal OSC_EN2 output by the enable unit 202 changes to a high level, the capacitor C3 needs to be charged before the enable signal OSC_EN2 can be inverted. After-phase output, that is, after a delay, can the low level be output to the "and" operation unit 602; therefore, the "and" operation unit 602 controls the enable signal OSC_EN2 and the delay inverting circuit When the 603 performs an AND operation, it outputs a high level for a certain period of time, and after the delay inversion circuit 603 outputs a low level, the AND operation unit 602 outputs a low level.
  • the pulse generator 2032 will generate a high level at the moment when the enable signal OSC_EN2 generates a rising edge and change to a high level and within a certain period of time, and then generate a low level, thereby generating an instant control pulse one-shot.
  • the charging time of the capacitor C3 can be adjusted by adjusting the size of the capacitor C3 and the resistor R', thereby adjusting the pulse width of the one-shot instant pulse.
  • the pulse generator 2032 or the delay inverting circuit 603 may also have other circuit structures, and no examples are given here. Those skilled in the art can reasonably choose the circuit structure to realize the function of the pulse generator 2032.
  • FIG. 6 is a timing diagram of the output voltage change of the power module in a specific embodiment of the present invention and the prior art.
  • the load current ILOAD increases, which causes the output terminal voltage Vout to decrease.
  • the delayed pulse signal CLK2' output by the oscillator is used to supplement energy to the boost unit 201 (please refer to the figure) to increase the voltage at the output terminal Vout of the power supply. Since the delay pulse signal CLK2' is generated after a delay time after the voltage of the power output terminal Vout drops, it will gradually rise after the power supply voltage drops by ⁇ V1.
  • the pulse of the boost control signal CLK2' randomly generates a pulse signal after Vout drops, so as to reduce the degree of voltage drop at the power output terminal Vout.
  • the voltage at the power output terminal Vout will gradually drop by ⁇ V2. Rising, where ⁇ V2 ⁇ V1.
  • the oscillator 203 will also generate a pulse signal with a larger clock interval to maintain the stability of the output voltage Vout.
  • the power supply module of the above specific embodiment can instantaneously respond to the drop of the output voltage of the power supply output terminal, instantly adjust the output voltage back to a normal level, and improve the response speed of the power supply module.
  • the specific embodiment of the present invention also provides a memory using the above-mentioned power supply module, such as a DRAM memory.
  • the power supply module can be used to provide word line drive voltage, bit line precharge voltage and so on.
  • the output voltage can be adjusted in time when the load of each module changes, and the load current changes to maintain a stable power supply voltage. Output, thereby improving the reliability and stability of the memory.

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Abstract

一种电源模块和一种存储器，所述电源模块包括：升压单元，用于输出电源电压；使能单元，连接至所述电源输出端，用于产生并输出一使能信号；控制单元，包括：振荡器、脉冲发生器以及"或"运算单元；所述振荡器用于产生一定周期的延时脉冲控制信号；所述脉冲发生器，与所述使能单元的输出端连接，用于在接收到所述使能信号的同时，同步产生即时脉冲控制信号；所述"或"运算单元用于对所述延时脉冲控制信号以及所述即时脉冲控制信号进行"或"运算，以产生升压控制信号；所述控制单元的输出端连接至所述升压单元，用于将所述升压控制信号输出至所述升压单元。上述的电源模块具有较高的瞬态响应能力，维持输出电压的稳定性。

Description

电源模块和存储器
相关申请引用说明
本申请要求于2019年9月27日递交的中国申请号2019109228406，申请名为“电源模块和存储器”的优先权，其全部内容以引用的形式附录于此。
技术领域
本发明涉及集成电路领域，尤其涉及一种电源模块和存储器。
背景技术
DRAM芯片中需要各种电源模块，例如电荷泵、线性稳压器等，为不同的功能模块(例如字线驱动电压VPP，背栅偏压电压VBB，位线预充电电压VCC/2等等)供电。在DRAM芯片工作过程中，各种操作模式之间会频繁切换，不同的操作模式下，各功能模块所汲取的电流会有差异，导致电源模块的输出电压发生变化。例如，在低功耗模式下，当重的负载突然发生时，电源模块的输出电压会被快速拉低，而电压模块启动升压具有一定延迟，在这段延迟的时间内，没有能量补给，电压模块的输出电压继续降低，导致输出电压产生较大下冲(under shot)，影响后续其他模块的工作。
因此，如何增强电源模块的瞬态响应，成为目前亟需解决的技术问题。
发明内容
本发明所要解决的技术问题是，提供一种电源模块及存储器，提高电源模块的瞬态响应能力，从而提高存储器的稳定性。
为了解决上述问题，本发明提供了一种电源模块，包括：升压单元，具有一电源输出端，用于输出电源电压；使能单元，连接至所述电源输出端，用于产生使能信号，当所述电源输出端电压下降至设定值时，所述使能信号产生上升沿；控制单元，包括：振荡器、脉冲发生器以及“或”运算单元；所述振荡器与所述使能单元的输出端连接，所述振荡器受所述使能信号的上升沿触发，用于产生一定周期的延时脉冲控制信号；所述脉冲发生器，与所述使能单元的输出端连接，用于在接收到所述使能信号的上升沿的同时，同步产生即时脉冲 控制信号；所述“或”运算单元连接至所述振荡器及所述脉冲发生器的输出端，用于对所述延时脉冲控制信号以及所述即时脉冲控制信号进行“或”运算，以产生升压控制信号；所述控制单元的输出端连接至所述升压单元，用于将所述升压控制信号输出至所述升压单元，控制所述升压单元升高输出的电源电压。
可选的，所述升压单元为电荷泵浦电路。
可选的，所述使能单元包括：比较器和分压电路，所述分压电路一端连接至所述电源输出端，另一端接地，所述分压电路的输出端连接至所述比较器的负输入端，所述比较器的正输入端连接至参考电压端，所述参考电压端的电压值为所述设定值。
可选的，所述分压电路包括：第一分压电阻和第二分压电阻，所述第一分压电阻的第一端连接至所述电源输出端，所述第一分压电阻的第二端连接至所述第二分压电阻的第一端，所述第二分压电阻的第二端接地，所述第一分压电阻和所述第二分压电阻的连接端作为所述分压电路的输出端。
可选的，所述“或”运算单元包括顺次连接的或非门和非门，所述或非门的两个输入端分别连接至所述脉冲发生器的输出端和所述振荡器的输出端，所述或非门的输出端连接至所述非门的输入端，所述非门的输出端连接至所述升压单元的输入端。
可选的，所述脉冲发生器包括延时反相电路以及“与”运算单元；所述延时反相电路的输入端连接至所述使能单元的输出端，用于将所述使能信号反相并延时输出；所述“与”运算单元与所述延时反相电路的输出端以及所述使能单元的输出端连接，用于对所述延时反相电路输出的信号和所述使能信号进行“与”运算。
可选的，所述延时反相电路包括：第一反相器、电阻和电容，所述第一反相器的输入端连接至所述使能单元的输出端，所述第一反相器的输出端连接至所述电阻的第一端，所述电阻的第二端连接至所述电容的第一端，所述电容的第二端接地，所述电容的第一端作为所述延时反相电路的输出端。
可选的，所述延时反相电路包括：第一反相器、第二反相器、第三反相器、第一电容和第二电容；所述第一反相器的输入端连接至所述使能单元的输出端，所述第一反相器输出端连接至第一电容的第一端，并连接至所述第二反相 器的输入端；所述第二反相器输出端连接至第二电容的第一端，并连接至所述第三反相器的输入端；所述第一电容和所述第二电容的第二端均接地，所述第三反相器的输出端作为所述延时反相电路的输出端。
可选的，所述“与”运算单元包括与非门，以及连接所述与非门的非门。
可选的，所述即时脉冲控制信号的第一个上升沿与所述使能信号的上升沿同时刻产生。
本发明的技术方案还提供一种存储器，包括电源模块，所述电源模块包括：所述电源模块包括：升压单元，具有电源输出端，用于输出电源电压；使能单元，连接至所述电源输出端，用于产生使能信号，当所述电源输出端电压下降至设定值时，所述使能信号产生上升沿；控制单元，包括：振荡器、脉冲发生器以及“或”运算单元；所述振荡器与所述使能单元的输出端连接，所述振荡器受所述使能信号的上升沿触发，用于产生一定周期的延时脉冲控制信号；所述脉冲发生器，与所述使能单元的输出端连接，用于在接收到所述使能信号的上升沿的同时，同步产生即时脉冲控制信号；所述“或”运算单元连接至所述振荡器及所述脉冲发生器的输出端，用于对所述延时脉冲控制信号以及所述即时脉冲控制信号进行“或”运算，以产生升压控制信号；所述控制单元的输出端连接至所述升压单元，用于将所述升压控制信号输出至所述升压单元，控制所述升压单元升高输出的电源电压。
可选的，所述升压单元为电荷泵浦电路。
可选的，所述使能单元包括：比较器和分压电路，所述分压电路一端连接至所述电源输出端，另一端接地，所述分压电路的输出端连接至所述比较器的负输入端，所述比较器的正输入端连接至参考电压端，所述参考电压端的电压值为所述设定值。
可选的，所述分压电路包括：第一分压电阻和第二分压电阻，所述第一分压电阻的第一端连接至所述电源输出端，所述第一分压电阻的第二端连接至所述第二分压电阻的第一端，所述第二分压电阻的第二端接地，所述第一分压电阻和所述第二分压电阻的连接端作为所述分压电路的输出端。
可选的，所述“或”运算单元包括顺次连接的或非门和非门，所述或非门的两个输入端分别连接至所述脉冲发生器的输出端和所述振荡器的输出端，所 述或非门的输出端连接至所述非门的输入端，所述非门的输出端连接至所述升压单元的输入端。
可选的，所述脉冲发生器包括延时反相电路以及“与”运算单元；所述延时反相电路的输入端连接至所述使能单元的输出端，用于将所述使能信号反相并延时输出；所述“与”运算单元与所述延时反相电路的输出端以及所述使能单元的输出端连接，用于对所述延时反相电路输出的信号和所述使能信号进行“与”运算。
可选的，所述延时反相电路包括：第一反相器、电阻和电容，所述第一反相器的输入端连接至所述使能单元的输出端，所述第一反相器的输出端连接至所述电阻的第一端，所述电阻的第二端连接至所述电容的第一端，所述电容的第二端接地，所述电容的第一端作为所述延时反相电路的输出端。
可选的，所述延时反相电路包括：第一反相器、第二反相器、第三反相器、第一电容和第二电容；所述第一反相器的输入端连接至所述使能单元的输出端，所述第一反相器输出端连接至第一电容的第一端，并连接至所述第二反相器的输入端；所述第二反相器输出端连接至第二电容的第一端，并连接至所述第三反相器的输入端；所述第一电容和所述第二电容的第二端均接地，所述第三反相器的输出端作为所述延时反相电路的输出端。
可选的，所述“与”运算单元包括与非门，以及连接所述与非门的非门。
可选的，所述即时脉冲控制信号的第一个上升沿与所述使能信号的上升沿同时刻产生。
本发明的电源模块，在检测到电源输出端的电压下降后，能够及时对所述升压单元补充能量，将输出电压调整回正常电位，使得电源输出端不需要等待就可以获得能量补充，因而可以减小输出电压的跌落，防止后续电路发生错误。
附图说明
图1a为本发明现有技术的电源模块的结构示意图；
图1b为本发明现有技术的电源模块的各个信号的时序示意图；
图2为本发明一具体实施方式的电源模块的结构示意图；
图3为本发明一具体实施方式的电源模块的升压单元的具体电路结构示意 图；
图4为本发明一具体实施方式中所述电源模块中各个信号的时序示意图；
图5a为本发明一具体实施方式的电源模块的脉冲发生器的电路结构示意图；
图5b为本发明一具体实施方式的电源模块的脉冲发生器的电路结构示意图；
图6为本发明一具体实施方式与现有技术中电源模块的输出电压变化的时序示意图。
附图标记含义：
101振荡器；102电荷泵浦电路；201升压单元；202使能单元；2021分压电路；203控制单元；2031振荡器；2032脉冲发生器；2033“或”运算单元；601延时反相电路；602“与”运算单元；Vout电源输出端；R1电阻；R2电阻；R’电阻；CMP1比较器；CMP2比较器；Vref参考电压；OSC_EN使能信号；OSC_EN2使能信号；CLK升压控制信号；CLK2’升压控制信号；T_delay延迟；T延迟时间；INV反相器；INV4反相器；C’电容；C3电容；M1晶体管；M2晶体管；CLOAD负载电容；Vcc电源；R11第一分压电阻；R12第二分压电阻；Vref2参考电压；CLK2延时脉冲控制信号；one-shot即时脉冲控制信号；NOR1或非门；NOT1非门；NOT2非门；INV1第一反相器；INV2第二反相器；INV3第三反相器；C1第一电容；C2第二电容；NAND1与非门；NOT2非门；ILOAD负载电流。
具体实施方式
如背景技术中所述，现有技术的电源模块的相应较慢，容易导致输出电压不稳定的问题。
请参考图1a，为一现有技术的电源模块的结构示意图。
所述电源模块包括：电荷泵浦电路102，电源输出端Vout用于向负载输出电源电压，电源输出端Vout连接至依次串联接地的电阻R1和电阻R2，所述电阻R1和电阻R2作为分压电路，两者的连接端连接至比较器CMP1的负输 入端，所述比较器CMP1的正输入端连接至参考电压Vref，所述比较器CMP1的输出端连接至振荡器101，通过所述振荡器101的输出端连接至所述电荷泵浦电路102。
在低功耗模式下，比较器CMP1负输入端输入的电压大于参考电压Vref，比较器CMP1输出使能信号OSC_EN为低，此时振荡器101被关断以节约功耗。在此模式下，如果电源输出端Vout的负载突然变重，输出的电源电压Vout会被迅速拉低，比较器CMP1输出使能信号OSC_EN为高电平，振荡器101被使能。振荡器101从接收到使能信号OSC_EN而被使能，到输出脉冲信号CLK，会有一个延迟T_delay(请参考图1b)，在这段时间内，没有能量补给到电荷泵浦电路102内的输出电容，输出电压Vout会继续跌落，导致输出电压Vout产生较大的下跌幅度，这会对后续模块的工作稳定性产生影响。
由此可见，减少控制电荷泵浦电路102升压的升压控制信号CLK的脉冲延时，可以减少输出电压Vout的下跌幅度，及时向电荷泵浦电路102补充能量，使得输出的电源电压稳定。
基于此，发明人提出一种新的电源模块，当负载突然变重的时候，能够快速响应，减小输出电压的跌落。
请参考图2，为本发明的一个具体实施方式的电源模块的结构示意图。
该具体实施方式中，所述电源模块包括：升压单元201、使能单元202、控制单元203。
所述升压单元201，具有电源输出端Vout，用于输出电源电压Vout；
所述升压单元201包括负载电容，所述负载电容一端作为电源输出端Vout，通过对所述负载电容充电，从而输出电源电压。当输出下降时，可以通过对所述负载电容补充能量，将输出电压被拉高。在本发明的一个具体实施方式中，所述升压单元201可以为电荷泵浦电路。
请参考图3，为本发明一具体实施方式的升压单元201的具体电路结构示意图。
该具体实施方式中，所述升压单元201包括反相器INV、电容C’、晶体管M1和晶体管M2以及负载电容C LOAD。晶体管M1的漏极连接至电源Vcc，源极连接至晶体管M2的漏极，晶体管M2的源极连接至负载电容C LOAD的第 一端，所述负载电容C LOAD的第二端接地。所述晶体管M1和晶体管M2的栅极均与漏极连接。所述反相器INV的输入端用于输入升压控制信号CLK，输出端连接至电容C’的第一端A，所述电容C’的另一端B连接至所述晶体管M1和晶体管M2的连接端。通过所述升压控制信号CLK对电容C’充电，从而向负载电容C LOAD补充能量，提高负载电容C LOAD的第一端输出的电源电压。
在其他具体实施方式中，所述升压单元201还可以采用其他结构的电荷泵浦电路，或者采用其他能够通过脉冲信号控制的升压单元结构。本领域的技术人员可以根据电源模块的输出电压的需求，合理选择合适的电路结构作为所述升压单元201。
所述使能单元202，连接至所述电源输出端Vout，用于产生使能信号，当所述电源输出端Vout电压下降至设定值时，所述使能信号产生上升沿。所述使能单元202用于检测所述电源输出端Vout的电压。
该具体实施方式中，所述使能单元202包括分压电路2021和比较器CMP2。所述分压电路2021一端连接至所述电源输出端Vout，另一端接地GND1，所述分压电路2021的输出端连接至所述比较器CMP2的负输入端，所述比较器CMP2的正输入端连接至参考电压端，所述参考电压值Vref2为设定值。
所述分压电路2021的输出端电压随所述电源输出端Vout的电压变化，较佳的，与所述电源输出端Vout的电压成正比，能够准确反映所述电源输出端Vout的输出电压大小及变化。该具体实施方式中，所述分压电路2021包括第一分压电阻R11和第二分压电阻R12，所述第一分压电阻R11的第一端连接至所述电源输出端Vout，所述第一分压电阻R11的第二端连接至所述第二分压电阻R12的第一端，所述第二分压电阻R12的第二端接地GND1，所述第一分压电阻R11和所述第二分压电阻R12的连接端作为所述分压电路2021的输出端。可以根据分压的比例要求，合理选择所述第一分压电阻R11和所述第二分压电阻R12的大小。在其他具体实施方式中，所述分压电路2021还可以为其他电路结构。在其他具体实施方式中，所述使能单元202的分压电路2021还可以为其他能够随时监控电源输出端Vout电压的电路结构。
当所述电源输出端Vout输出电压较高时，所述分压电路2021输出至比较器CMP2的负输入端的电压值大于正输入端的参考电压Vref2，比较器CMP2 输出的使能信号OSC_EN2为低电平，振荡器2031关闭。当电源电压Vout降低，所述分压电路2021输出至比较器CMP2的负输入端的电压值小于正输入端的参考电压Vref2，比较器CMP2输出的使能信号OSC_EN2产生上升沿，成为高电平信号，触发所述振荡器2031工作。
所述使能单元202根据所述电源输出端Vout的电压变化，输出对应的使能信号OSC_EN2。
所述控制单元203，包括：振荡器2031、脉冲发生器2032以及“或”运算单元2033。
所述振荡器2031的输入端连接至所述使能单元202的输出端，当所述使能信号OSC_EN2为高电平时，所述振荡器2031受所述使能信号OSC_EN2触发，用于产生一定周期的延时脉冲控制信号CLK2。
所述脉冲发生器2032，与所述使能单元202的输出端连接，用于在接收到所述使能信号OSC_EN2的上升沿的同时，同步产生即时脉冲控制信号one-shot。该具体实施方式中，所述脉冲发生器2032在所述使能信号OSC_EN2的上升沿触发下，产生的即时脉冲控制信号one-shot为单脉冲信号，即仅有一个脉冲。
所述“或”运算单元2033连接至所述振荡器2031及所述脉冲发生器2032的输出端，用于对所述延时脉冲控制信号CLK2以及所述即时脉冲控制信号one-shot进行“或”运算，以产生升压控制信号CLK2’。
该具体实施方式中，所述“或”运算单元2033包括顺次连接的或非门NOR1和非门NOT1，所述或非门NOR1的两个输入端分别连接至所述脉冲发生器2032的输出端和所述振荡器2031的输出端，所述或非门NOR1的输出端连接至所述非门NOT1的输入端，所述非门NOT1的输出端连接至所述升压单元201的输入端。
所述控制单元203的输出端连接至所述升压单元202，用于将所述升压控制信号CLK2’输出至所述升压单元202，控制所述升压单元202升高输出的电源电压。
请参考图4，为本发明一具体实施方式中所述电源模块中各个信号的时序示意图。
该具体实施方式中，当电源输出端Vout负载变重，输出电压降低，使得使能信号OSC_EN2变为高电平，使得振荡器2031使能，输出延时脉冲控制信号CLK2，由于所述振荡器2031的电路特性，所述延时脉冲控制信号CLK2的第一个脉冲延后于所述使能信号OSC_EN2变为高电平的时刻(即上升沿时刻)，延迟时间为T。
而脉冲发生器2032一旦接受到高电平的使能信号OSC_EN2，就会产生一个即时脉冲控制信号one-shot，所述即时脉冲控制信号one-shot与所述使能信号OSC_EN2的上升边沿基本对齐，同时刻或几乎同时刻产生。
通过所述“或”运算单元2033对所述延时脉冲控制信号CLK2以及所述即时脉冲控制信号one-shot进行“或”运算，产生升压控制信号CLK2’，在所述延迟时间T内，所述升压控制信号CLK2’为所述即时脉冲控制信号one-shot的即时脉冲，后续为所述延时脉冲控制信号CLK2。
本发明的电源模块，在检测到电源输出端Vout的电压下降，使能信号OSC_EN2变为高电平时，即时产生升压控制信号CLK2’的脉冲，及时对所述升压单元201补充能量，提高电源输出端Vout的电压，将输出电压调整回正常电位。由于即时脉冲控制信号one-shot信号是在振荡器2031使能的时刻立刻产生进而通过升压单元201对电源输出端Vout补充能量，输出端Vout不需要在等待T之后就可以获得能量补充，因而可以减小输出电压的跌落，防止后续电路发生错误。
所述脉冲发生器2032包括延时反相电路以及“与”运算单元；所述延时反相电路的输入端连接至所述使能单元202的输出端，用于将所述使能信号反相并延时输出；所述“与”运算单元与所述延时反相电路的输出端以及所述使能单元202的输出端连接，用于对所述延时反相电路输出的信号和所述使能信号进行“与”运算。
请参考图5a，为本发明一具体实施方式的脉冲发生器的结构示意图。
所述脉冲发生器2032包括所述延时反相电路601和所述“与”运算单元602。
所述延时反相电路601包括：第一反相器INV1、第二反相器INV2、第三反相器INV3、第一电容C1和第二电容C2；所述第一反相器INV1的输入端 连接至所述使能单元202的输出端，所述第一反相器INV1输出端连接至第一电容C1的第一端，并连接至所述第二反相器INV2的输入端；所述第二反相器INV2输出端连接至第二电容C2的第一端，并连接至所述第三反相器INV3的输入端；所述第一电容C1和所述第二电容C2的第二端均接地，所述第三反相器INV3的输出端作为所述延时反相电路601的输出端。
所述“与”运算单元602包括与非门NAND1，以及连接所述与非门NAND1的非门NOT2。所述与非门NAND1的两个输入端分别连接至所述使能单元202的输出端以及所述延时反相电路601的输出端。所述与非门NAND1的输出端连接至所述非门NOT2的输入端，所述非门NOT2的输出端作为所述脉冲发生器2032的输出端。
由于所述延时反相电路601内包括第一电容C1和第二电容C2，当所述使能单元202输出的使能信号OSC_EN2变为高电平时，需要对电容C1和C2充电完成后，才能将所述使能信号OSC_EN2反相后输出，即经过一段延迟之后，才能输出低电平至所述“与”运算单元602；因此，所述“与”运算单元602对所述使能信号OSC_EN2以及所述延时反相电路601进行“与”运算时，会在一端时间内输出高电平，而在所述延时反相电路601输出低电平之后，所述“与”运算单元602输出低电平。因此，脉冲发生器2032会在OSC_EN2变为高电平的瞬间及一端时间内产生高电平，随后产生低电平，从而产生一个即时控制脉冲one-shot。所述即时控制脉冲one-shot的脉冲宽度可以通过调整所述第一电容C1和第二电容C2的大小进行调整，以避免脉宽过小导致对升压单元201的能量补充过小，或者脉冲过大导致对升压单元201的能量补充过大，造成输出电压过冲。较佳的，可以将所述one-shot的脉宽调整至与所述振荡器203产生的脉冲宽度接近或一致。
请参考图5b，为本发明另一具体实施方式的脉冲发生器的结构示意图。
该具体实施方式中，提供了另一种的延迟反相电路603的电路结构。所述延迟反相电路603包括：反相器INV4、电阻R’和电容C3，所述反相器INV4的输入端连接至所述使能单元202的输出端，所述反相器INV4的输出端连接至所述电阻R’的第一端，所述电阻R’的第二端连接至所述电容C3的第一端，所述电容C3的第二端接地，所述电容C3的第一端作为所述延时反相电路603 的输出端。
由于所述延时反相电路603内包括电容C3，当所述使能单元202输出的使能信号OSC_EN2变为高电平时，需要对电容C3充电完成后，才能将所述使能信号OSC_EN2反相后输出，即经过一段延迟之后，才能输出低电平至所述“与”运算单元602；因此，所述“与”运算单元602对所述使能信号OSC_EN2以及所述延时反相电路603进行“与”运算时，会在一端时间内输出高电平，而在所述延时反相电路603输出低电平之后，所述“与”运算单元602输出低电平。因此，脉冲发生器2032会在使能信号OSC_EN2产生上升沿变为高电平的瞬间及一端时间内产生高电平，随后产生低电平，从而产生一个即时控制脉冲one-shot。
该具体实施方式中，可以通过调整所述电容C3以及电阻R’的大小，调整对电容C3的充电时间，从而调整个所述即时脉冲one-shot的脉宽。
在本发明的其他具体实施方式中，所述脉冲发生器2032或者所述延时反相电路603还可以具有其他电路结构，在此不一一举例。本领域技术人员，可以合理选择电路结构，以实现所述脉冲发生器2032的功能。
请参考图6，为本发明一具体实施方式与现有技术中电源模块的输出电压变化的时序示意图。
现有技术中，在重负载状态下，负载电流ILOAD上升，导致输出端电压Vout下降。通常仅通过振荡器输出的延时脉冲信号CLK2’对升压单元201(请参考图)补充能量，以提高电源输出端Vout的电压。由于延时脉冲信号CLK2’在电源输出端Vout的电压下降后经过一段延迟时间才会产生，因此，在电源电压跌落ΔV1后才会逐渐上升。
而本申请的具体实施方式中，升压控制信号CLK2’的脉冲在Vout下降后随机产生脉冲信号，从而可以减少电源输出端Vout的电压的跌落程度，电源输出端Vout的电压跌落ΔV2后会逐渐上升，其中ΔV2＜ΔV1。
其中，在所述电源模块的轻负载低功耗模式下，所述振荡器203也会产生一个时钟间隔较大的脉冲信号，以维持所述输出电压Vout的稳定性。
上述具体实施方式的电源模块能够瞬时相应电源输出端的输出电压的下降，即时将输出电压调整回正常水平，提高电源模块的响应速度。
本发明的具体实施方式，还提供一种采用上述电源模块的存储器，例如DRAM存储器。所述电源模块可以用于提供字线驱动电压，位线预充电压等。以向所述存储器提供稳定的电源电压，且在存储器芯片工作过程中，在各种操作模式之间频繁切换，各模块负载变化，负载电流发生变化时能够及时调整输出电压，维持稳定的电源电压输出，从而提高存储器的可靠性和稳定性。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (20)

  1. 一种电源模块，其特征在于，包括：
    升压单元，具有电源输出端，用于输出电源电压；
    使能单元，连接至所述电源输出端，用于产生使能信号，当所述电源输出端电压下降至设定值时，所述使能信号产生上升沿；
    控制单元，包括：振荡器、脉冲发生器以及“或”运算单元；
    所述振荡器与所述使能单元的输出端连接，所述振荡器受所述使能信号的上升沿触发，用于产生一定周期的延时脉冲控制信号；
    所述脉冲发生器，与所述使能单元的输出端连接，用于在接收到所述使能信号的上升沿的同时，同步产生即时脉冲控制信号；
    所述“或”运算单元连接至所述振荡器及所述脉冲发生器的输出端，用于对所述延时脉冲控制信号以及所述即时脉冲控制信号进行“或”运算，以产生升压控制信号；
    所述控制单元的输出端连接至所述升压单元，用于将所述升压控制信号输出至所述升压单元，控制所述升压单元升高输出的电源电压。
  2. 根据权利要求1所述的电源模块，其特征在于，所述升压单元为电荷泵浦电路。
  3. 根据权利要求1所述的电源模块，其特征在于，所述使能单元包括：比较器和分压电路，所述分压电路一端连接至所述电源输出端，另一端接地，所述分压电路的输出端连接至所述比较器的负输入端，所述比较器的正输入端连接至参考电压端，所述参考电压端的电压值为所述设定值。
  4. 根据权利要求3所述的电源模块，其特征在于，所述分压电路包括：第一分压电阻和第二分压电阻，所述第一分压电阻的第一端连接至所述电源输出端，所述第一分压电阻的第二端连接至所述第二分压电阻的第一端，所述第二分压电阻的第二端接地，所述第一分压电阻和所述第二分压电阻的连接端作为所述分压电路的输出端。
  5. 根据权利要求1所述的电源模块，其特征在于，所述“或”运算单元包括顺次连接的或非门和非门，所述或非门的两个输入端分别连接至所述脉冲发生器的输出端和所述振荡器的输出端，所述或非门的输出端连接至所述 非门的输入端，所述非门的输出端连接至所述升压单元的输入端。
  6. 根据权利要求1所述的电源模块，其特征在于，所述脉冲发生器包括延时反相电路以及“与”运算单元；所述延时反相电路的输入端连接至所述使能单元的输出端，用于将所述使能信号反相并延时输出；所述“与”运算单元与所述延时反相电路的输出端以及所述使能单元的输出端连接，用于对所述延时反相电路输出的信号和所述使能信号进行“与”运算。
  7. 根据权利要求6所述的电源模块，其特征在于，所述延时反相电路包括：第一反相器、电阻和电容，所述第一反相器的输入端连接至所述使能单元的输出端，所述第一反相器的输出端连接至所述电阻的第一端，所述电阻的第二端连接至所述电容的第一端，所述电容的第二端接地，所述电容的第一端作为所述延时反相电路的输出端。
  8. 根据权利要求6所述的电源模块，其特征在于，所述延时反相电路包括：第一反相器、第二反相器、第三反相器、第一电容和第二电容；所述第一反相器的输入端连接至所述使能单元的输出端，所述第一反相器输出端连接至第一电容的第一端，并连接至所述第二反相器的输入端；所述第二反相器输出端连接至第二电容的第一端，并连接至所述第三反相器的输入端；所述第一电容和所述第二电容的第二端均接地，所述第三反相器的输出端作为所述延时反相电路的输出端。
  9. 根据权利要求6所述的电源模块，其特征在于，所述“与”运算单元包括与非门，以及连接所述与非门的非门。
  10. 根据权利要求6所述的电源模块，其特征在于，所述即时脉冲控制信号的第一个上升沿与所述使能信号的上升沿同时刻产生。
  11. 一种存储器，其特征在于，包括电源模块，所述电源模块包括：
    升压单元，具有电源输出端，用于输出电源电压；
    使能单元，连接至所述电源输出端，用于产生使能信号，当所述电源输出端电压下降至设定值时，所述使能信号产生上升沿；
    控制单元，包括：振荡器、脉冲发生器以及“或”运算单元；
    所述振荡器与所述使能单元的输出端连接，所述振荡器受所述使能信号的上升沿触发，用于产生一定周期的延时脉冲控制信号；
    所述脉冲发生器，与所述使能单元的输出端连接，用于在接收到所述使能信号的上升沿的同时，同步产生即时脉冲控制信号；
    所述“或”运算单元连接至所述振荡器及所述脉冲发生器的输出端，用于对所述延时脉冲控制信号以及所述即时脉冲控制信号进行“或”运算，以产生升压控制信号；
    所述控制单元的输出端连接至所述升压单元，用于将所述升压控制信号输出至所述升压单元，控制所述升压单元升高输出的电源电压。
  12. 根据权利要求11所述的存储器，其特征在于，所述升压单元为电荷泵浦电路。
  13. 根据权利要求11所述的存储器，其特征在于，所述使能单元包括：比较器和分压电路，所述分压电路一端连接至所述电源输出端，另一端接地，所述分压电路的输出端连接至所述比较器的负输入端，所述比较器的正输入端连接至参考电压端，所述参考电压端的电压值为所述设定值。
  14. 根据权利要求13所述的存储器，其特征在于，所述分压电路包括：第一分压电阻和第二分压电阻，所述第一分压电阻的第一端连接至所述电源输出端，所述第一分压电阻的第二端连接至所述第二分压电阻的第一端，所述第二分压电阻的第二端接地，所述第一分压电阻和所述第二分压电阻的连接端作为所述分压电路的输出端。
  15. 根据权利要求11所述的存储器，其特征在于，所述“或”运算单元包括顺次连接的或非门和非门，所述或非门的两个输入端分别连接至所述脉冲发生器的输出端和所述振荡器的输出端，所述或非门的输出端连接至所述非门的输入端，所述非门的输出端连接至所述升压单元的输入端。
  16. 根据权利要求11所述的存储器，其特征在于，所述脉冲发生器包括延时反相电路以及“与”运算单元；所述延时反相电路的输入端连接至所述使能单元的输出端，用于将所述使能信号反相并延时输出；所述“与”运算单 元与所述延时反相电路的输出端以及所述使能单元的输出端连接，用于对所述延时反相电路输出的信号和所述使能信号进行“与”运算。
  17. 根据权利要求16所述的存储器，其特征在于，所述延时反相电路包括：第一反相器、电阻和电容，所述第一反相器的输入端连接至所述使能单元的输出端，所述第一反相器的输出端连接至所述电阻的第一端，所述电阻的第二端连接至所述电容的第一端，所述电容的第二端接地，所述电容的第一端作为所述延时反相电路的输出端。
  18. 根据权利要求16所述的存储器，其特征在于，所述延时反相电路包括：第一反相器、第二反相器、第三反相器、第一电容和第二电容；所述第一反相器的输入端连接至所述使能单元的输出端，所述第一反相器输出端连接至第一电容的第一端，并连接至所述第二反相器的输入端；所述第二反相器输出端连接至第二电容的第一端，并连接至所述第三反相器的输入端；所述第一电容和所述第二电容的第二端均接地，所述第三反相器的输出端作为所述延时反相电路的输出端。
  19. 根据权利要求16所述的存储器，其特征在于，所述“与”运算单元包括与非门，以及连接所述与非门的非门。
  20. 根据权利要求16所述的存储器，其特征在于，所述即时脉冲控制信号的第一个上升沿与所述使能信号的上升沿同时刻产生。
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