WO2021036284A1 - 一种液晶显示装置 - Google Patents

一种液晶显示装置 Download PDF

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WO2021036284A1
WO2021036284A1 PCT/CN2020/085011 CN2020085011W WO2021036284A1 WO 2021036284 A1 WO2021036284 A1 WO 2021036284A1 CN 2020085011 W CN2020085011 W CN 2020085011W WO 2021036284 A1 WO2021036284 A1 WO 2021036284A1
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signal
data
demultiplexing circuit
source driver
liquid crystal
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PCT/CN2020/085011
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English (en)
French (fr)
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文超平
王梅
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南京中电熊猫液晶显示科技有限公司
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Publication of WO2021036284A1 publication Critical patent/WO2021036284A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only

Definitions

  • This application relates to the technical field of liquid crystal panels, and in particular to a liquid crystal display device.
  • the demultiplexing circuit technology (English: DeMUX, hereinafter referred to as MUX) is widely used in liquid crystal display panels. It can convert the strobe signal S output by the source driver (Source IC) to 1:n (such as 1:2, 1 :3, etc.) in the form of time-sharing transmission to the data line D of n columns of pixels. Take 1:2 as an example.
  • Two sets of Thin Film Transistor (TFT) switches are controlled by two clock signals CK1 and CK2, so that the strobe signal output by a source driver is time-divisionally output to the data of two columns of pixels.
  • Line D so that the signal lines output by the source driver can be reduced by at least half, and the number of source drivers can also be reduced. Therefore, the cost of panel design can be reduced, and the drawing space of the panel design can be reduced.
  • the width of the lower frame so that the panel meets the high specification requirements of a narrower frame.
  • a TFT switch is required when the strobe signal is divided to the data line D, and a clock signal CK for controlling the TFT switch is also introduced. Since the clock signal CK is turned off, it will affect the potential of the data line and thus the potential of the charged pixel through the coupling capacitor Ckd, and different clock signals CK have different effects on the feedback voltage of the pixels due to the inconsistent turn-off time.
  • the panel includes a gate electrode 01, an insulating layer 02, a semiconductor layer 03, a source electrode 04 and a drain electrode 05, and the gate electrode 01 and source electrode at the TFT device structure 04.
  • Both the gate 01 and the drain 05 have an overlapping area, so there will be parasitic capacitances Cgs and Cgd.
  • the MUX part due to the existence of the parasitic capacitance, there will be a large coupling capacitance Ckd between the clock signal CK and the data line D.
  • the coupling capacitance Ckd due to the existence of the coupling capacitance Ckd, the data line potential reaches a predetermined value
  • the clock signal CK jumps
  • the data line potential will also undergo a certain jump due to the potential jump of the clock signal CK and the coupling capacitor.
  • This jump can be regarded as the clock signal CK
  • the feedback voltage (English: Feedthrough) to the potential of the data line brought by the shutdown. Pixels that are charged first, because the gate is still open, the pixel electrode will leak to the data line affected by the clock signal feedback voltage, and indirectly will also be affected by the feedback voltage brought by the clock signal turned off, the degree of impact and the leakage to the data line
  • the length of time is related.
  • the pixels charged in the first n-1 channels are inevitably affected by the feedback voltage of the clock signal CK
  • a certain amount of feedback voltage time is reserved between the falling edge of the last switching signal CKn and the falling edge of the gate scanning signal Gm (such as T2 shown in Figure 3).
  • a strobe signal of the current source driver (English: Source IC) outputs n data signals in a mode of equal duration, that is, if a gate scan time is T, then for MUX 1: In the n circuit, the duration of a single data signal is T/n (as shown in Figure 4).
  • t1-tn is the overlap time of each CK and Data, that is, the charging time of each pixel. Due to the influence of T1 and T2, the high-level duration of a single CK pulse is only (T-T1-T2 )/n-T3, which is less than the duration of a single Data signal, causing the charging time of each pixel to be unequal.
  • the charging time t1, t2...tn of each pixel may be different from each other.
  • the first charging time is the longest and the most There is (T-T1-T2)/n-T3, and the last charging time tn is only T/n-T1-T2-T3. This will cause uneven pixel charging rate or insufficient charging of one or more of the pixels, which will cause poor display such as color shift or rough picture on the display.
  • the purpose of the present application is to provide a liquid crystal display device that improves the problems of insufficient pixel charging or uneven charging rate.
  • the present application provides a liquid crystal display device, which includes a source driver and a display panel.
  • the display panel includes criss-crossed data lines and signal lines, and a demultiplexing circuit connecting the source driver and the data lines.
  • One of the source drivers The strobe signal inputs n data signals to the demultiplexing circuit, and the demultiplexing circuit outputs n data signals to the n data lines in the form of 1:n, and the demultiplexing circuit is provided with The TFT switch and the clock signal that controls the opening and closing of the TFT switch; within one scan time of the gate, the duration of the first n-1 data signals input by the source driver to the demultiplexing circuit is less than the duration of the last data signal.
  • the duration of the first n-1 data signals input by the source driver to the demultiplexing circuit is (T-T1-T2)/n, and the duration of the last data signal Is (T-T1-T2)/n+T1+T2; among them, Gm is the gate scanning signal of the mth row; T is a scanning time of the gate; T1 is the clock signal and the error-proof charging time of Gm; T2 is The time reserved for the feedback voltage of the demultiplexing circuit of the last pixel; n ⁇ 2, m ⁇ 1.
  • the present application also provides a liquid crystal display device, which includes a source driver and a display panel.
  • the display panel includes crisscrossed data lines and signal lines, and a demultiplexing circuit connecting the source driver and the data lines.
  • the demultiplexing circuit is equipped with a TFT switch and a clock signal that controls the opening and closing of the TFT switch; during a scan time of the gate, a strobe signal of the source driver inputs n+1 data to the demultiplexing circuit Signal, the demultiplexing circuit outputs n data signals to n data lines in a 1:n format; the signal duration of the first n data signals is equal and different from the signal duration of the last data signal.
  • the first n data signals are used as the actual input data signals, and the signal duration is (T-T1-T2)/n; the last data signal is used as the backup data signal, and the duration is T1+T2;
  • Gm is the mth Row gate scanning signal; T is a scanning time of the gate; T1 is the time of the clock signal and the error-proof charging of Gm; T2 is the time reserved for the feedback voltage of the demultiplexing circuit of the last pixel; n ⁇ 2, m ⁇ 1.
  • the first n signals are used as the actual input effective data signals D(m,1) to D(m,n).
  • the present application also provides a liquid crystal display device, which includes a source driver and a display panel.
  • the display panel includes crisscrossed data lines and signal lines, and a demultiplexing circuit connecting the source driver and the data lines.
  • the demultiplexing circuit is provided with a TFT switch and a clock signal that controls the opening and closing of the TFT switch; a strobe signal of the source driver inputs n+1 data signals to the demultiplexing circuit, and the demultiplexing circuit Output n data signals to the data line in the form of 1:n; the time of each data signal is the same.
  • the time of each data signal is T/(n+1); where T is a scan time of the gate, n ⁇ 2.
  • the first n data signals are used as the actual input effective data signals, and the last data signal is used as the backup data signal.
  • the interval between CKx-1 and CKx is T/(n+1), the high level duration of each clock signal is the same, and is less than or equal to T/(n+1), where CK1, CK2,... CKn is a clock signal, 2 ⁇ x ⁇ n.
  • the start time of the source driver inputting a valid data signal to the demultiplexing circuit is synchronized with the rising edge of the clock signal of the TFT switch of the demultiplexing circuit.
  • the liquid crystal display device of this application for the source driver (English: Source IC) input demultiplexing circuit data signal and the corresponding CK/Gm timing combination, can significantly improve the liquid crystal display device using the demultiplexing circuit technology The problem of insufficient charging or uneven charging rate of a certain channel or channels.
  • FIG. 1 is a schematic diagram of the structure of an existing back channel type TFT
  • Figure 2 is a schematic diagram of the parasitic capacitance of the existing MUX
  • FIG. 3 is a timing diagram of the combination of the gate scan signal and the clock signal of the MUX that are currently commonly used;
  • FIG. 4 is a time sequence diagram of the gate signal output by the existing source driver
  • Figure 5 is a diagram of the existing overall timing arrangement
  • FIG. 6 is a schematic diagram of data charging in the first embodiment of the demultiplexing circuit of the liquid crystal display device of the present application.
  • FIG. 7 is a timing diagram of the specific use of the demultiplexing circuit of the liquid crystal display device shown in FIG. 6;
  • FIG. 8 is a schematic diagram of data charging in the second embodiment of the demultiplexing circuit of the liquid crystal display device of the present application.
  • FIG. 9 is a timing diagram of the specific use of the demultiplexing circuit of the liquid crystal display device shown in FIG. 8;
  • FIG. 10 is a schematic diagram of data charging of the third embodiment of the demultiplexing circuit of the liquid crystal display device of the present application.
  • FIG. 11 is a timing chart of the specific use of the demultiplexing circuit of the liquid crystal display device shown in FIG. 10.
  • the azimuthal terms such as “upper” and “lower” may include but are not limited to the directions defined relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative Concepts, they are used for relative description and clarification, which can be changed correspondingly according to the changes in the orientation of the parts in the drawings.
  • At least one (item) refers to one or more, and “multiple” refers to at least two, that is, two or more.
  • the liquid crystal display device of the present application includes a source driver (English: Source IC) and a display panel.
  • the display panel includes crisscrossed data lines and signal lines, and multiple channels connecting the source driver (English: Source IC) and the data lines.
  • Demultiplexing circuit hereinafter referred to as MUX
  • MUX Demultiplexing circuit
  • MUX strobe signal of the source driver
  • MUX the demultiplexing circuit
  • MUX Output n data signals to n data lines D in the form of 1:n.
  • MUX is equipped with a TFT switch (not shown) and a clock signal CK that controls the opening and closing of the TFT switch.
  • the opening and closing of the TFT switch is controlled by the clock signal CK. Turn off to output the data signal to the data line.
  • FIG. 6 is a schematic diagram of data charging in the first embodiment of the application.
  • the first n-1 data signal durations input by the source driver to the demultiplexing circuit are less than The duration of the last data signal, that is: within a scan time T of the gate, a strobe signal of the source driver (English: Source IC) inputs n data signals to the MUX, and the first n-1 data signal duration is ( T-T1-T2)/n, the duration of the last data signal is (T-T1-T2)/n+T1+T2, so that it matches the waveform of the clock signal CK, which is the clock signal of MUX.
  • CK1, CK2,...CKn are clock signals; Gm is the gate scan signal of the mth row; T is the gate scan time; T1 is the error-proof charging time of the clock signals CK and Gm; T2 is reserved for the last pixel
  • the time of MUX Feedthrough (Chinese: feedback voltage of demultiplexing circuit); T3 is the error-proof charging time between CKx-1 and CKx, 2 ⁇ x ⁇ n, T3 can prevent the waveform of the clock signal CK from passing through RC Delay causes the previous pixel to mischarge the data signal of the next pixel; Tc is the time interval between the rising edge of CKx-1 and the rising edge of CKx during a row of gate scan time, n ⁇ 2, m ⁇ 2.
  • the time interval Tc between the rising edge of CKx-1 and the rising edge of CKx is (T-T1-T2)/n, the start of the MUX inputting the data signal D(m,x) (where x ⁇ n) to the data line
  • the time is synchronized with the rising edge of the switching signal CKn of the TFT of the MUX.
  • FIG. 7 is a specific example of data charging in the first embodiment.
  • T1, T2, and T3 are determined according to the specific design of the display panel of the liquid crystal display device.
  • the resistance and capacitance of each part of the display panel of the liquid crystal display device are known.
  • the values of T1, T2, and T3 can be specifically determined.
  • FIG. 8 is a schematic diagram of data charging according to the second embodiment of the application.
  • a strobe signal of a source driver inputs n+1 data signals to the MUX.
  • the MUX outputs n data signals to the data line in the form of 1:n, and the signal duration of the first n data signals is equal and different from the signal duration of the last data signal.
  • the first n data signals are used as the actual input data signals D(m,1) to D(m,n), the signal duration is (T-T1-T2)/n; the last data signal is used as a backup data signal (English: D dummy), the duration is T1+T2, so that it matches the waveform of the clock signal CK.
  • the standby data signal (English: D dummy) is the last signal D(m,n) of the row or the first signal D(m+1,1) of the next row, or the intermediate transition signal of the two signals.
  • a strobe signal of the source driver (English: Source IC) outputs n+1 data signals in time-sharing, and the first n data signals are used as the actual input data signal D(m,1).
  • the signal duration is (T-T1-T2)/n; the last data signal is used as a backup data signal (English: D dummy), and the duration is T1+T2, considering the source driver (English : Source IC) output power consumption, the standby data signal (English: D dummy) can be given to the current row D(m,n) signal or the next row D(m+1,1) signal or the intermediate signal between the two signals .
  • the high-level duration of the pulse of each clock signal CK is the same, and ⁇ (T-T1-T2)/n, the time interval Tc between the rising edge of CKx-1 and the rising edge of CKx is (T-T1-T2) /n, the start time when MUX inputs data signal D(m,x) (where x ⁇ n) to the data line is synchronized with the rising edge of the switching signal CKn of the TFT of the MUX, so that the charging time of each pixel is consistent,
  • the charging duration is the high level duration of a single CK pulse.
  • Figure 9 is a specific example of data charging in the second embodiment.
  • the source driver (English: Source IC) is required
  • a strobe signal outputs n+1 data signals
  • the first n signals are the actual input data signals D(m,1) to D(m,n)
  • the duration of the data signal is 2*T/(2n+1) );
  • the latter data signal is used as a backup data signal (English: D dummy), and the duration is T/(2n+1).
  • the backup data signal (English: D Dummy) can give the current line D(m,n) signal or the next line D(m+1,1) signal or the intermediate signal between the two signals, such as D(m,n) is a positive polarity 128 gray-scale signal , D(m+1,1) is a 72-gray-level signal with positive polarity, and the standby data signal (English: D dummy) can be any signal from a positive polarity of 128 gray-level signals to a positive polarity 72-gray-level signal;
  • FIG. 10 is a schematic diagram of data charging in the third embodiment of the application.
  • a strobe signal of a source driver (English: Source IC) equally outputs n+1 channels of data.
  • the time of each data signal is the same and is T/(n+1); the first n signals are the actual input data signals D(m,1) to D(m,n), and the last data signal is reserved
  • the distance between adjacent signals of CK is adjusted to T/(n+1) to match the waveform of the data line.
  • the standby data signal (English: D dummy): for the last signal D (m, n) of the current row or the first signal D (m+1, 1) of the next row, or the intermediate transition signal of the two signals.
  • the time interval t1 between Source CKx-1 and CKx is adjusted to T/(n+1), and the high level duration of each clock signal pulse is the same, and is less than or equal to T/(n+1).
  • the start time when the MUX inputs the data signal D(m,x) to the data line is synchronized with the rising edge of the clock signal CKn of the TFT switch of the MUX, so that the charging time of each pixel can be consistent, and the charging time is the high of a single CK pulse.
  • Level duration is the start time when the MUX inputs the data signal D(m,x) to the data line.
  • FIG 11 is a specific example of data charging in the third embodiment.
  • a gate scan time T is approximately equal to 8.4us. If it is assumed that Gm and CK1 are between The minimum error-proof charging time T1 is 0.3us, and the minimum time T2 of the last pixel affected by the feedthrough of the MUX is 0.3us.
  • the minimum error-proof charging time T3 between CK is 0.2us, and the current data line is equally divided into n In the power supply mode of the channel data, the charging time of the last channel is only T/n-T1-T2-T3, which is 0.6us.
  • a strobe signal of the source driver (English: Source IC) outputs 7 data signals equally, each of which has a duration of 1.2us, and the first 6 signals are the actual input data signals D(m,1) to D(m) ,6), the latter data signal is used as a backup data signal (English: D dummy), considering the power consumption of the source driver (English: Source IC) output, the backup data signal (English: D dummy) can be given to the current row D( m,n) signal or the next line D(m+1,1) signal or the intermediate signal between the two signals, such as D(m,n) is a positive polarity 128 gray-scale signal, D(m+1,1 ) Is a positive 72 gray-scale signal, the standby data signal (English: D dummy) can be any signal from a positive 128 gray-scale to a positive 72 gray-scale signal; the distance between adjacent signals of CK Set to 1.2us, then the high level duration Tck of each CK signal is set to 1us; the
  • This application increases the power supply duration of the last data signal output by the source driver (English: Source IC); or inserts a null signal (that is, the standby data signal (English: D dummy)) at the end of the n data signals; or A source driver (English: Source IC) is used to equally output n+1 signals, the first n signals are used as n data signals, and the last signal is a null signal (that is, the standby data signal (English: D dummy)), which can make The charging time of each pixel is kept the same and the charging time is as large as possible, so as to avoid color shift or roughness or other display defects.
  • a null signal that is, the standby data signal (English: D dummy)
  • This application focuses on the data supply method of the source driver (English: Source IC) and the corresponding CK/Gm timing combination, which can significantly improve the insufficient charging of one or more pixels in the liquid crystal display device using the demultiplexing circuit technology Or the problem of uneven charging rate.

Abstract

一种液晶显示装置，包括源极驱动器和显示面板，显示面板包括纵横交错的数据线（D1,……,Dn）和信号线、以及连接源极驱动器和数据线（D1,……,Dn）的多路分用电路，源极驱动器的一个选通信号（S）向多路分用电路输入n路数据信号（D(m,1),……,D(m,n)），多路分用电路以1：n形式输出n路数据信号（D(m,1),……,D(m,n)）给n路数据线（D1,……,Dn），多路分用电路内设有TFT开关和控制TFT开关打开和关闭的时钟信号（CK1,……,CKn）；在栅极的一个扫描时间（T）内，源极驱动器向多路分用电路输入的前n-1路数据信号（D(m,1),……,D(m,n-1)）时长小于最后一路数据信号（D(m,n)）时长。通过对源极驱动器输入多路分用电路的数据信号和相应的CK/Gm的时序搭配，可明显改善采用多路分用电路技术的液晶显示装置中某一路或几路像素充电不足或充电率不均的问题。

Description

一种液晶显示装置
本申请要求于2019年8月28日提交中国国家知识产权局、申请号为201910799361.X、发明名称为“一种液晶显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及液晶面板的技术领域，特别是涉及一种液晶显示装置。
背景技术
多路分用电路技术(英文：DeMUX，以下简称MUX)正广泛应用于液晶显示面板，它可以将源极驱动器(Source IC)输出的选通信号S以1:n(如1:2、1:3等)的形式分时传送给n列像素的数据线D。以1:2为例，通过两个时钟信号CK1、CK2控制两组薄膜场效应晶体管(Thin Film Transistor，TFT)开关从而将一根源极驱动器输出的选通信号分时输出给两列像素的数据线D，从而使源极驱动器输出的信号线可以至少减少一半，同样也可以使源极驱动器的数量减少，因此能够减少面板设计的成本，并且通过节省了面板设计的绘图空间，可以减小面板的下边框宽度，从而使面板达到更窄边框的高规格要求。
由于采用多路分用电路技术，在选通信号分到数据线D处时需要用TFT开关，并且还要引入控制TFT开关的时钟信号CK。由于时钟信号CK关闭会通过耦合电容Ckd影响数据线的电位进而影响充电像素的电位，不同的时钟信号CK由于关闭时刻不一致对像素的反馈电压的影响也不一致。对于例如背沟道型的TFT来说，如图1所示，面板包括栅极01、绝缘层02、半导体层03、源极04以及漏极05，TFT器件结构处的栅极01和源极04、栅极01和漏极05都会有一个交叠面积，因此会存在寄生电容Cgs和Cgd。在MUX部分，由于该寄生电容的存在，时钟信号CK和数据线D之间会有一个很大的耦合电容Ckd，如图2所示，由于耦合电容Ckd的存在，在数据线电位达到预定值，MUX的一组TFT开关关断，时钟信号CK发生跳变时，数据线电位受时钟信号CK电位跳变和耦合电容的影响也会出现一定跳变，该跳变可看做是时钟信号CK关闭带来的对数据线电位的回馈电压(英文：Feedthrough)。先充电的像素由于栅极仍然打开像素电极会向受时钟信号回馈电压影响的数据线漏电，从而间接也会被时钟信号关断带来的回馈电压影响，受影响的程度和向数据线漏电的时间长短有关。
由于前n-1路充电的像素必定会受到时钟信号CK的回馈电压的影响，为减小或消除最后一路像素与前n-1路像素所受时钟信号CK的回馈电压的影响的差异，通常在最后一路开关信号CKn的下降沿和栅极扫描信号Gm的下降沿之间预留一定的回馈电压时间(如附图3所示T2)，该回馈电压的时间越长，第n路像素受到的回馈电压与前n-1路像素受到的回馈电压差异越小；但通常在该时间大于某一τ值时，n路像素所受的时钟信号CK的回馈电压差异已可以接受。
在一个栅极扫描时间内，当前源极驱动器(英文：Source IC)的一个选通信号输出n路数据信号是时长等分的模式，即若一个栅极扫描时间是T，则对于MUX 1：n电路，单个数据信号的时长均是T/n(如附图4所示)。
结合Data的时序，一种考虑了错充影响和多路分用电路技术的回馈电压差异影响总的时序搭配如附图5所示，其中Gm是第m行栅极扫描信号；D(m,n)是第m行第n路像素的数据信号；T是单个栅极扫描的时间；T1是MUX首路开关信号CK1的上升沿和Gm的下降沿之间的防错充时间，防止由于Gm波形经RC Delay后造成本行首路像素错充下一行首路像素的数据信号，即防止第m行第1路像素错充第m+1行第1路像素的数据信号；T2是预留给最后一路像素的MUX的回馈电压的时间；T3：CKx-1和CKx之间的防错充时间，2≤x≤n，T3可以防止由于时钟信号CK的波形经RC Delay后造成上一路像素错充下一路像素的数据信号；Tc为一行栅极扫描时间内CKx-1的上升沿和CKx的上升沿之间的时间间距，包含单个CK脉冲信号的高电平时间和CK之间的防错充时间T3(T3≥0)两部分。如图5所示，t1-tn是各个CK和Data的交叠时间，即各路像素的充电时间，由于受到T1和T2的影响，单个CK脉冲的高电平时长只有(T-T1-T2)/n-T3，小于单个Data信号的时长，造成各路像素的充电时间不相等，各路像素的充电时间t1、t2……tn均可能互不相同，第一路充电时间最长，最多有(T-T1-T2)/n-T3，而最后一路充电时间tn只有T/n-T1-T2-T3。这会造成像素充电率不均或其中一路或几路像素充电不足的问题，从而在显示上会造成色偏或画面粗糙等显示不良。
发明内容
本申请的目的在于提供一种改善像素充电不足或充电率不均的问题的液晶显示装置。
本申请提供一种液晶显示装置，其包括源极驱动器和显示面板，显示面板包括纵横交错的数据线和信号线、以及连接源极驱动器和数据线的多路分用电路，源极驱动器的一个选通信号向所述多路分用电路输入n路数据信号，所述多路分用电路以1：n形式输出n路数据信号给n路数据线，所述多路分用电路内设有TFT开关和控制TFT开关打开和关闭的时钟信号；在栅极的一个扫描时间内，源极驱动器向所述多路分用电路输入的前n-1路数据信号时长小于最后一路数据信号时长。
可选地，在栅极的一个扫描时间内，源极驱动器向所述多路分用电路输入的前n-1路数据信号时长为(T-T1-T2)/n，最后一路数据信号时长为(T-T1-T2)/n+T1+T2；其中，Gm为第m行栅极扫描信号；T为栅极的一个扫描时间；T1为时钟信号和Gm的防错充时间；T2为预留给最后一路像素的多路分用电路的回馈电压的时间；n≥2，m≥1。
本申请还提供一种液晶显示装置，其包括源极驱动器和显示面板，显示面板包括纵横交错的数据线和信号线、以及连接源极驱动器和数据线的多路分用电路，所述多路分用电路内设有TFT开关和控制TFT开关打开和关闭的时钟信号；在栅极的一个扫描时间内，源极驱动器的一个选通信号向所述多路分用电路输入n+1路数据信号，所述多路分用电路以1：n形式输出n路数据信号给n路数据线；前n路数据信号的信号时长相等且与最后一路数据信号的信号时长不同。
可选地，前n路数据信号作为实际输入的数据信号，信号时长为(T-T1-T2)/n；最后一路数据信号作备用数据信号，时长为T1+T2；其中，Gm为第m行栅极扫描信号；T为栅极的一个扫描时间；T1为时钟信号和Gm的防错充时间；T2为预留给最后一路像素的路分用电路的回馈电压的时间；n≥2，m≥1。
可选地，前n路信号做实际输入的有效数据信号D(m,1)至D(m,n)。
本申请还提供一种液晶显示装置，其包括源极驱动器和显示面板，显示面板包括纵横交错的数据线和信号线、以及连接源极驱动器和数据线的多路分用电路，所述多路分用电路内设有TFT开关和控制TFT开关打开和关闭的时钟信号；源极驱动器的一个选通信号向所述多路分用电路输入n+1路数据信号，所述多路分用电路以1：n形式输出n路数据信号给数据线；各路数据信号的时间均相同。
可选地，所述各路数据信号的时间均为T/(n+1)；其中，T为栅极的一个扫描时间，n≥2。
可选地，前n路数据信号做实际输入的有效数据信号，最后一路数据信号作备用数据信号。
可选地，CKx-1和CKx之间的间隔为T/(n+1),各个时钟信号的高电平时长相同，且小于或等于T/(n+1)，其中CK1、CK2、…CKn为时钟信号，2≤x≤n。
可选地，源极驱动器向多路分用电路输入某路有效数据信号的开始时刻和该路多路分用电路的TFT开关的时钟信号的上升沿同步。
本申请液晶显示装置，针对源极驱动器(英文：Source IC)输入多路分用电路的数据信号和相应的CK/Gm的时序搭配，可明显改善采用多路分用电路技术的液晶显示装置中某一路或几路像素充电不足或充电率不均的问题。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请中记载的一些实施例，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。
图1为现有背沟道型TFT结构示意图；
图2为现有MUX的寄生电容示意图；
图3为现有当前常用的栅极扫描信号和MUX的时钟信号的搭配时序图；
图4为现有源极驱动器输出选通信号的时序模式图；
图5为现有总的时序搭配图；
图6为本申请液晶显示装置的多路分用电路的第一实施例的数据充电的示意图；
图7为图6所示液晶显示装置的多路分用电路具体使用的时序图；
图8为本申请液晶显示装置的多路分用电路的第二实施例的数据充电的示意图；
图9为图8所示液晶显示装置的多路分用电路具体使用的时序图；
图10为本申请液晶显示装置的多路分用电路的第三实施例的数据充电的示意图；
图11为图10所示液晶显示装置的多路分用电路具体使用的时序图。
具体实施方式
下面结合附图和具体实施例，进一步阐明本申请，应理解这些实施例仅用于说明本申请而不用于限制本申请的范围，在阅读了本申请之后，本领域技术人员对本申请的各种等价形式的修改均落于本申请所附权利要求所限定的范围。
为使图面简洁，各图中只示意性地表示出了与本申请相关的部分，它们并不代表其作为产品的实际结构。另外，以使图面简洁便于理解，在有些图中具有相同结构或功能的部件，仅示意性地绘示了其中的一个，或仅标出了其中的一个。在本文中，“一个”不仅表示“仅此一个”，也可以表示“多于一个”的情形。
此外，本申请实施例中，“上”、“下”等方位术语可以包括但不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
应当理解，在本申请中，“至少一个(项)”是指一个或者多个，“多个”是指至少两个，即两个或两个以上。
本申请液晶显示装置，其包括源极驱动器(英文：Source IC)和显示面板，显示面板包括纵横交错的数据线和信号线、以及连接源极驱动器(英文：Source IC)和数据线的多路分用电路(以下简称MUX)，源极驱动器(英文：Source IC)的一个选通信号向多路分用电路(以下简称MUX)输入n路数据信号，多路分用电路(以下简称MUX)以1：n形式输出n路数据信号给n路数据线D，MUX内设有TFT开关(图未示)和控制TFT开关打开和关闭的时钟信号CK，通过时钟信号CK控制TFT开关的打开和关闭，以输出数据信号给数据线。
如图6所示为本申请第一实施例的数据充电的示意图，在栅极的一个扫描时间T内，源极驱动器向所述多路分用电路输入的前n-1路数据信号时长小于最后一路数据信号时长，即：在栅极的一个扫描时间T内，源极驱动器(英文：Source IC)的一个选通信号向MUX输入n路数据信号，前n-1路数据信号时长为(T-T1-T2)/n，最后一路数据信号时长为(T-T1-T2)/n+T1+T2，使得与时钟信号CK的波形图匹配，时钟信号CK为MUX的时钟信号。
其中，CK1、CK2、…CKn为时钟信号；Gm为第m行栅极扫描信号；T为栅极扫描时间；T1为时钟信号CK和Gm的防错充时间；T2为预留给最后一路像素的MUX  Feedthrough(中文：多路分用电路的回馈电压)的时间；T3为CKx-1和CKx之间的防错充时间，2≤x≤n，T3可以防止由于时钟信号CK的波形经RC Delay后造成上一路像素错充下一路像素的数据信号；Tc为一行栅极扫描时间内CKx-1的上升沿和CKx的上升沿之间的时间间距，n≥2，m≥2。
CKx-1的上升沿和CKx的上升沿之间的时间间距Tc为(T-T1-T2)/n，MUX向数据线输入数据信号D(m,x)(其中，x≤n)的开始时刻和该路MUX的TFT的开关信号CKn的上升沿同步。
如图7为第一实施例的数据充电的具体实施例，T1和T2和T3是根据液晶显示装置的显示面板的具体设计而定，知道液晶显示装置的显示面板的各部分的电阻电容等参数，则可具体确定T1、T2和T3的值。
在栅极的一个扫描时间T内，假定T1+T2＝T/(2n+1)，则要求源极驱动器(Source IC)的一个选通信号向MUX输入的前n-1路数据信号的时长均为2*T/(2n+1)，最后一路数据信号的时长为3*T/(2n+1)；时钟信号CK的相邻信号之间的间距设为2*T/(2n+1)，若T3＝0.2*T/(2n+1)，则每个时钟信号CK的高电平时长Tckh＝1.8*T/(2n+1)；使MUX向数据线输入数据信号D(m,n)的转换时刻和该路MUX的TFT开关信号CKn的上升沿同步，则各路像素的充电时长都可调为1.8*T/(2n+1)。
如图8所示为本申请第二实施例的数据充电的示意图，在栅极的一个扫描时间T内，源极驱动器(Source IC)的一个选通信号向MUX输入n+1路数据信号，MUX以1：n形式输出n路数据信号给数据线，前n路数据信号的信号时长相等且与最后一路数据信号的信号时长不同。
前n路数据信号作为实际输入的数据信号D(m,1)至D(m,n)，信号时长为(T-T1-T2)/n；最后一路数据信号作备用数据信号(英文：D dummy)，时长为T1+T2，使得与时钟信号CK的波形图匹配。
备用数据信号(英文：D dummy)为本行末路信号D(m,n)或下一行首路信号D(m+1,1)，或这两信号的中间过渡信号。
在栅极的一个扫描时间T内，源极驱动器(英文：Source IC)的一路选通信号分时输出n+1路数据信号，前n路数据信号做实际输入的数据信号D(m,1)至D(m,n)，信号时长为(T-T1-T2)/n；最后一路数据信号作备用数据信号(英文：D dummy)，时长为T1+T2，考虑到源极驱动器(英文：Source IC)输出的功耗，备用数据信号(英文：D dummy)可给当前行D(m,n)信号或下一行D(m+1,1)信号或该两信号之间的中间信号。各个时钟信号CK 的脉冲的高电平时长相同，且≤(T-T1-T2)/n，CKx-1的上升沿和CKx的上升沿之间的时间间距Tc为(T-T1-T2)/n，MUX向数据线输入数据信号D(m,x)(其中，x≤n)的开始时刻和该路MUX是TFT的开关信号CKn的上升沿同步，使各路像素的充电时间一致,充电时长为单个CK脉冲的高电平时长。
如图9为第二实施例的数据充电的具体实施例，在栅极的一个扫描时间T内，假定T1+T2＝T/(2n+1)，要求源极驱动器(英文：Source IC)的一个选通信号输出n+1路数据信号，前n路信号做实际输入的数据信号D(m,1)至D(m,n)，数据信号的时长均为2*T/(2n+1)；后一路数据信号作备用数据信号(英文：D dummy)，时长为T/(2n+1)，考虑到源极驱动器(英文：Source IC)输出的功耗，备用数据信号(英文：D dummy)可给当前行D(m,n)信号或下一行D(m+1,1)信号或该两信号之间的中间信号，如D(m,n)是正极性的128灰阶信号，D(m+1,1)是正极性的72灰阶信号，则备用数据信号(英文：D dummy)可是正极性的128灰阶到正极性的72灰阶信号之间的任一信号；CK相邻信号之间的间距设为2*T/(2n+1)，若T3＝0.2*T/(2n+1)，则每个CK信号的高电平时长Tckh＝1.8*T/(2n+1)；使MUX向数据线输入数据信号D(m,n)的转换时刻和该路MUX的TFT开关信号CKn的上升沿同步，则各路像素的充电时长都可调为1.8*T/(2n+1)。
如图10所示为本申请第三实施例的数据充电的示意图，在栅极的一个扫描时间T内，源极驱动器(英文：Source IC)的一个选通信号等分输出n+1路数据信号，各路数据信号的时间均相同且为T/(n+1)；前n路信号做实际输入的数据信号D(m,1)至D(m,n)，最后一路数据信号作备用数据信号(英文：D dummy)，CK相邻信号之间的间距为调整为T/(n+1),以和数据线的波形匹配。
其中，备用数据信号(英文：D dummy)：给本行末路信号D(m,n)或下一行首路信号D(m+1,1)，或这两信号的中间过渡信号。
Source CKx-1和CKx的时间间隔t1调整为T/(n+1),各个时钟信号脉冲的高电平时长相同，且小于或等于T/(n+1)。MUX向数据线输入数据信号D(m,x)的开始时刻和该路MUX的TFT开关的时钟信号CKn的上升沿同步，可使各路像素的充电时间一致,充电时长为单个CK脉冲的高电平时长。
如图11为第三实施例的数据充电的具体实施例，对于分辨率为1920*1080的MUX 1:6的显示屏，一个栅极扫描时间是T大致等于8.4us，若假定Gm和CK1之间的防错充时间T1最小是0.3us，最后一路像素受MUX的Feedthrough影响的时长T2最小是0.3us，CK之间的防错充时间T3最小是0.2us，则在当前数据线均分n路数据的给电模式下，最后一 路的充电时长只有T/n-T1-T2-T3即0.6us。
源极驱动器(英文：Source IC)的一个选通信号等分输出7路数据信号，各路时长均为1.2us，前6路信号做实际输入的数据信号D(m,1)至D(m,6)，后一路数据信号作备用数据信号(英文：D dummy)，考虑到源极驱动器(英文：Source IC)输出的功耗，备用数据信号(英文：D dummy)可给当前行D(m,n)信号或下一行D(m+1,1)信号或该两信号之间的中间信号，如D(m,n)是正极性的128灰阶信号，D(m+1,1)是正极性的72灰阶信号，则备用数据信号(英文：D dummy)可是正极性的128灰阶到正极性的72灰阶信号之间的任一信号；CK相邻信号之间的间距设为1.2us，则每个CK信号的高电平时长Tck设为1us；使MUX向数据线输入数据信号D(m,n)的转换时刻和该路MUX的TFT开关信号CKn的上升沿同步，则各路像素的充电时长都可调为1us。
本申请增大源极驱动器(英文：Source IC)输出最后一路数据信号的给电时长；或者在n路数据信号的末尾插入一路空信号(即备用数据信号(英文：D dummy))；或者所采用源极驱动器(英文：Source IC)等分输出n+1路信号，前n路信号用作n路数据信号，最后一路信号做空信号(即备用数据信号(英文：D dummy))，可使各路像素充电时间保持相同且使充电时间尽可能大，从而可避免色偏或粗糙或其他显示不良。
本申请针对源极驱动器(英文：Source IC)的数据给电方法和相应的CK/Gm的时序搭配，可明显改善采用多路分用电路技术的液晶显示装置中某一路或几路像素充电不足或充电率不均的问题。
以上详细描述了本申请的优选实施方式，但是本申请并不限于上述实施方式中的具体细节，在本申请的技术构思范围内，可以对本申请的技术方案进行多种等同变换(如数量、形状、位置等)，这些等同变换均属于本申请的保护范围。

Claims (10)

  1. 一种液晶显示装置，其特征在于，所述液晶显示装置包括源极驱动器和显示面板，所述显示面板包括纵横交错的数据线和信号线、以及连接所述源极驱动器和数据线的多路分用电路，所述源极驱动器的一个选通信号向所述多路分用电路输入n路数据信号，所述多路分用电路以1：n形式输出n路数据信号给n路数据线，所述多路分用电路内设有TFT开关和控制所述TFT开关打开和关闭的时钟信号；
    在栅极的一个扫描时间内，所述源极驱动器向所述多路分用电路输入的前n-1路数据信号时长小于最后一路数据信号时长。
  2. 根据权利要求1所述的液晶显示装置，其特征在于，
    在栅极的一个扫描时间内，所述源极驱动器向所述多路分用电路输入的前n-1路数据信号时长为(T-T1-T2)/n，最后一路数据信号时长为(T-T1-T2)/n+T1+T2；其中，Gm为第m行栅极扫描信号；T为栅极的一个扫描时间；T1为时钟信号和所述Gm的防错充时间；T2为预留给最后一路像素的多路分用电路的回馈电压的时间；n≥2，m≥1。
  3. 一种液晶显示装置，其特征在于，所述液晶显示装置包括源极驱动器和显示面板，所述显示面板包括纵横交错的数据线和信号线、以及连接所述源极驱动器和数据线的多路分用电路，所述多路分用电路内设有TFT开关和控制所述TFT开关打开和关闭的时钟信号；
    在栅极的一个扫描时间内，所述源极驱动器的一个选通信号向所述多路分用电路输入n+1路数据信号，所述多路分用电路以1：n形式输出n路数据信号给n路数据线；前n路数据信号的信号时长相等且与最后一路数据信号的信号时长不同。
  4. 根据权利要求3所述的液晶显示装置，其特征在于，
    前n路数据信号作为实际输入的数据信号，信号时长为(T-T1-T2)/n；最后一路数据信号作备用数据信号，时长为T1+T2；其中，Gm为第m行栅极扫描信号；T为栅极的一个扫描时间；T1为时钟信号和所述Gm的防错充时间；T2为预留给最后一路像素的路分用电路的回馈电压的时间；n≥2，m≥1。
  5. 根据权利要求3所述的液晶显示装置，其特征在于：前n路信号做实际输入的有效数据信号D(m,1)至D(m,n)。
  6. 一种液晶显示装置，其特征在于，所述液晶显示装置包括源极驱动器和显示面板，所述显示面板包括纵横交错的数据线和信号线、以及所述连接源极驱动器和数据线的多路分用电路，所述多路分用电路内设有TFT开关和控制所述TFT开关打开和关闭的时钟信号；
    所述源极驱动器的一个选通信号向所述多路分用电路输入n+1路数据信号，所述多路分用电路以1：n形式输出n路数据信号给数据线；各路数据信号的时间均相同。
  7. 根据权利要求6所述的液晶显示装置，其特征在于，
    所述各路数据信号的时间均为T/(n+1)；其中，T为栅极的一个扫描时间，n≥2。
  8. 根据权利要求7所述的液晶显示装置，其特征在于，
    前n路数据信号做实际输入的有效数据信号，最后一路数据信号作备用数据信号。
  9. 根据权利要求7所述的液晶显示装置，其特征在于，
    CKx-1和CKx之间的间隔为T/(n+1),各个时钟信号的高电平时长相同，且小于或等于T/(n+1)，其中CK1、CK2、…CKn为时钟信号，2≤x≤n。
  10. 根据权利要求9所述的液晶显示装置，其特征在于，
    所述源极驱动器向多路分用电路输入某路有效数据信号的开始时刻和该路多路分用电路的TFT开关的时钟信号的上升沿同步。
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