WO2021036034A1 - 多级驱动数据传输电路及数据传输方法 - Google Patents

多级驱动数据传输电路及数据传输方法 Download PDF

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Publication number
WO2021036034A1
WO2021036034A1 PCT/CN2019/120279 CN2019120279W WO2021036034A1 WO 2021036034 A1 WO2021036034 A1 WO 2021036034A1 CN 2019120279 W CN2019120279 W CN 2019120279W WO 2021036034 A1 WO2021036034 A1 WO 2021036034A1
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Prior art keywords
signal
input terminal
generating unit
terminal
data transmission
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PCT/CN2019/120279
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English (en)
French (fr)
Inventor
冀康灵
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长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/055,082 priority Critical patent/US11323116B2/en
Priority to EP19943007.5A priority patent/EP3934102B1/en
Publication of WO2021036034A1 publication Critical patent/WO2021036034A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0002—Multistate logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H03K19/09429—Multistate logic one of the states being the high impedance or floating state
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0233—Bistable circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/101—Analog or multilevel bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1003—Interface circuits for daisy chain or ring bus memory arrangements

Definitions

  • the present disclosure relates to a three-state drive bus transmission technology, and in particular, to a multi-level drive data transmission circuit and a data transmission method.
  • the tri-state output of the tri-state driver is controlled by the control signal.
  • the control signal When the control signal is valid, the device realizes the normal logic state output, that is, the input data is directly sent to the output terminal; when the control signal is invalid, the output is in a high-impedance state, that is, wait Effective in disconnecting from the connected circuit.
  • control signal of the tri-state driver may undergo relatively large changes, resulting in too short output driving time, incomplete output signals, or confusion in continuous data with different beats.
  • the present disclosure provides a multi-level drive data transmission circuit and data transmission method.
  • a multi-level drive data transmission circuit including: a first drive module and a second drive module; wherein, the first drive module includes: a first signal generating unit and a first tri-state driver;
  • the second drive module includes: a second three-state driver; the first input terminal of the second three-state driver is coupled to the output terminal of the first three-state driver;
  • the first signal generating unit includes: a first input terminal, a second input terminal, and Output terminal; the output terminal of the first signal generating unit is coupled to the second input terminal of the first three-state driver; the first signal generating unit is used to receive the first signal through its first input terminal and through its second input terminal
  • the first feedback signal of the first signal from the second driving module generates a first control signal with an effective signal width wider than the first signal according to the first signal and the first feedback signal, and provides the first control signal to the first three-state driver One control signal.
  • the first signal generating unit includes: a first RS latch, and the first input terminal of the first signal generating unit is a setting terminal of the first RS latch, so The second input terminal of the first signal generating unit is the reset terminal of the first RS latch, and the output terminal of the first signal generating unit is the first output terminal of the first RS latch.
  • the first signal generating unit includes: a first D flip-flop, a first input terminal of the first signal generating unit is a clock input terminal of the first D flip-flop, and The second input terminal of the first signal generating unit is the reset terminal of the first D flip-flop, and the output terminal of the first signal generating unit is the output terminal of the first D flip-flop.
  • the second driving module further includes: a signal shaping unit including: an input terminal and an output terminal; the signal shaping unit is configured to receive the first signal through its input terminal, and to The first signal is shaped to generate and output the first feedback signal through its output terminal.
  • a signal shaping unit including: an input terminal and an output terminal; the signal shaping unit is configured to receive the first signal through its input terminal, and to The first signal is shaped to generate and output the first feedback signal through its output terminal.
  • the signal shaping unit includes: an even number of first inverters connected in series.
  • the first driving module further includes: a pulse signal generating unit including: an input terminal and an output terminal, the output terminal of which is coupled to the first input terminal of the first signal generating unit, Used for receiving the first signal, generating a pulse signal according to the rising edge of the first signal, and providing the pulse signal to the first signal generating unit through the first input terminal of the first signal generating unit .
  • a pulse signal generating unit including: an input terminal and an output terminal, the output terminal of which is coupled to the first input terminal of the first signal generating unit, Used for receiving the first signal, generating a pulse signal according to the rising edge of the first signal, and providing the pulse signal to the first signal generating unit through the first input terminal of the first signal generating unit .
  • the pulse signal generating unit includes: an odd-stage gate circuit, a NAND gate, and a second inverter; wherein the odd-stage gate circuit receives the first signal through its input terminal;
  • the NAND gate receives the first signal through its first input terminal, is coupled to the output terminal of the odd-stage gate circuit through its second input terminal, and receives the output signal of the odd-stage gate circuit through its The output terminal is coupled with the input terminal of the second inverter; the output terminal of the second inverter is coupled with the first input terminal of the first signal generating unit.
  • a third driving module including: a third three-state driver; the first input terminal of the third three-state driver is coupled to the output terminal of the second three-state driver;
  • the second driving module further includes: a second signal generating unit; the second signal generating unit includes: a first input terminal, a second input terminal, and an output terminal; the output terminal of the second signal generating unit and the The second input terminal of the second tri-state driver is coupled; the second signal generating unit is configured to receive the first signal through its first input terminal, and receive the signal from the third drive module through its second input terminal , The second feedback signal of the first signal, based on the first signal and the second feedback signal, generate a second control signal with an effective signal width wider than the first signal, and send it to the second third
  • the state driver provides the second control signal.
  • the second signal generating unit includes: a second RS latch, and the first input terminal of the second signal generating unit is the setting terminal of the second RS latch, so The second input terminal of the second signal generating unit is the reset terminal of the second RS latch, and the output terminal of the second signal generating unit is the first output terminal of the second RS latch.
  • the second signal generating unit includes: a second D flip-flop, a first input terminal of the second signal generating unit is a clock input terminal of the second D flip-flop, and The second input terminal of the second signal generating unit is the reset terminal of the second D flip-flop, and the output terminal of the second signal generating unit is the output terminal of the second D flip-flop.
  • a multi-level drive data transmission method including: receiving a first signal and a feedback signal of the first signal from a next-level drive module respectively; and according to the first signal And the feedback signal to generate a control signal with an effective signal width wider than the first signal, and provide the control signal to the tri-state driver in the drive module of the current level.
  • generating a control signal with an effective signal width wider than the first signal according to the first signal and the feedback signal includes: inputting the first signal and the feedback signal respectively To the set terminal and the reset terminal of the RS latch, the signal of the first output terminal of the RS latch is used as the control signal.
  • generating a control signal with an effective signal width wider than the first signal according to the first signal and the feedback signal includes: inputting the first signal and the feedback signal respectively To the clock input terminal and the reset terminal of the D flip-flop, the signal output from the output terminal of the D flip-flop is used as the control signal, and a fixed voltage signal is input to the data terminal of the D flip-flop.
  • the method before receiving the feedback signal, the method further includes: in the next-level driving module, shaping the first signal to obtain and output the feedback signal.
  • the method before receiving the first signal, the method further includes: generating a pulse signal according to the rising edge of the first signal, and outputting the pulse signal as the first signal .
  • the control signal input to the three-state driver can be processed, and the original control signal can be sent to the next-level drive module and then fed back to the current level.
  • Drive module Due to the existence of the feedback path, according to the feedback control signal and the original control signal, a new control signal with an effective signal width wider than the original control signal can be generated, thereby avoiding the inability to completely transmit the data to the next due to insufficient effective time of the control signal. The problem in the first-level drive module.
  • Fig. 1 is a block diagram showing a multi-level driving data transmission circuit according to an exemplary embodiment.
  • Fig. 2 is a schematic diagram showing the first signal generating unit 101 according to an exemplary embodiment.
  • Fig. 3 is a schematic diagram showing a second signal generating unit 201 according to an exemplary embodiment.
  • Fig. 4 is a block diagram showing a pulse signal generating unit according to an exemplary embodiment.
  • Fig. 5 is a flow chart showing a method for transmitting multi-level driving data according to an exemplary embodiment.
  • Fig. 6 is a schematic diagram showing signal timing according to an example.
  • Fig. 7 is a schematic diagram showing another first signal generating unit 101 according to an exemplary embodiment.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features.
  • the tri-state driver is turned on during the valid period of the control signal to output the input data; during the invalid period of the control signal, it is turned off, the output is in a high-impedance state, and the data on the bus is held by the holding circuit.
  • the turn-on time of the tri-state driver may not be sufficient for the data to be completely transmitted to the next-level driver module, resulting in errors.
  • the embodiments of the present disclosure provide a multi-level drive data transmission circuit and a multi-level drive data transmission method, which can process the control signal input to the three-state driver, and send the original control signal to the next-level drive module and then feedback it back The driver module of this level. Due to the existence of the feedback path, according to the feedback control signal and the original control signal, a new control signal with an effective signal width wider than the original control signal can be generated, thereby avoiding the inability to completely transmit the data to the next due to insufficient effective time of the control signal. The problem in the first-level drive module.
  • Fig. 1 is a block diagram showing a multi-level driving data transmission circuit according to an exemplary embodiment.
  • the multi-level driving data transmission circuit 1 includes: a first driving module 10 and a second driving module 20.
  • the first driving module 10 includes: a first signal generating unit 101 and a first tri-state driver 102.
  • the second driving module 20 includes: a second three-state driver 202.
  • the output terminal 102c (data output terminal) of the first three-state driver 102 is coupled to the first input terminal 202a (data input terminal) of the second three-state driver 202 through the bus Bus, and the data output by the first driver module 10 is transmitted through the bus The Bus is output to the second driving module 20.
  • the first signal generating unit 101 includes: a first input terminal 101a, a second input terminal 101b, and an output terminal 101c.
  • the output terminal 101c of the first signal generating unit 101 is coupled to the second input terminal 102b (control signal input terminal) of the first tri-state driver 102.
  • the first input terminal 101a of the first signal generating unit 101 is used to receive the first signal (such as the control signal in the data transmission circuit 1), and the second input terminal 101b is used to receive the first signal from the second driving module 20.
  • the first feedback signal That is, the leading edge of the original control signal (the first signal) is used to turn on the first tri-state driver 102 to send the data signal. At the same time, use the same signal line to send out the control signals together.
  • the first signal is fed back to the second input terminal 101b of the first signal generating unit 101 in the first driving module 10.
  • the first signal generating unit 101 After receiving the first signal and its feedback signal, the first signal generating unit 101 generates a first control signal with an effective signal width wider than the first signal according to the first signal and its feedback signal, which is used to provide to the first tri-state driver 102 to perform data transmission control on the first tri-state driver 102.
  • Fig. 2 is a schematic diagram showing the first signal generating unit 101 according to an exemplary embodiment. As shown in FIG. 2, in some embodiments, the first signal generating unit 101 may be implemented as an RS latch.
  • the first input terminal 101a of the first signal generating unit 101 is the setting terminal of the RS latch (ie S terminal), and the second input terminal 101b is the reset terminal (ie R terminal) of the RS latch.
  • the output terminal 101c is, for example, the first output terminal (ie, the Q terminal) of the RS latch.
  • the effective signal width of the first signal (such as the duration of 1) is not enough to enable the data signal to be completely transmitted to the next drive module (such as the second drive module 20), but because the RS latch
  • the other input terminal also inputs a feedback signal, as long as the feedback signal is still 0, the RS latch will not be reset, so that the RS latch can continue to maintain a valid signal output, making the first three-state driver 102 continues to remain in the on state, thereby ensuring the complete transmission of the data signal.
  • Fig. 6 is a schematic diagram showing signal timing according to an example.
  • the effective width of the first signal is relatively narrow (t1 to t2 as shown in the figure)
  • the feedback signal is 0 at t2 to t3
  • the first output of the first output The output of the control signal at t2 to t3 is still 1, thereby extending the effective width of the first signal (as shown in the figure, the effective signal width is t1 to t3).
  • Fig. 7 is a schematic diagram showing another first signal generating unit 101 according to an exemplary embodiment. As shown in FIG. 7, in some embodiments, the first signal generating unit 101 may also be implemented as a D flip-flop.
  • the first input terminal 101a of the first signal generating unit 101 is the clock signal terminal of the D flip-flop (ie, the CLK terminal in the figure) for receiving the first signal;
  • the second input terminal 101b is the clock signal terminal of the D flip-flop
  • the reset terminal that is, the RESET terminal in the figure
  • the output terminal 101c such as the output terminal of the D flip-flop (that is, the Q terminal in the figure), outputs the first control signal.
  • the data terminal 101d (ie, the DATA terminal in the figure) of the D flip-flop can input a fixed voltage signal VDD.
  • the effective signal width of the first signal (such as the duration of 1) is not enough to enable the data signal to be completely transmitted to the next drive module (such as the second drive module 20), it is because in D
  • the RESET input terminal of the flip-flop also inputs a feedback signal, still taking Figure 6 as an example, at t2 ⁇ t3, the feedback signal is 0, and the D flip-flop cannot be reset (RESET), that is, the current output state of the D flip-flop
  • the latching is performed, so the output of the first control signal output by the first output terminal at time t2 to t3 is still 1, thereby extending the effective width of the first signal, thereby ensuring the complete transmission of the data signal.
  • the second driving module 20 may further include: a signal shaping unit 203.
  • the signal shaping unit 203 includes an input terminal 203a and an output terminal 203b for receiving a first signal through its input terminal, shaping the first signal, and generating a first feedback signal output through its output terminal 203b. Since the quality of the first signal will become poorer after a long bus transmission, the signal shaping unit 203 can shape it to improve its signal quality, thereby ensuring that the feedback signal is fed back to the first driving module 10 with Better signal quality.
  • the signal shaping unit 203 may be implemented as an even number of inverters connected in series to function as a buffer. After the first signal is transmitted through the bus, it is shaped by the buffer.
  • the positions of the two inverters connected in series in FIG. 1 are only examples.
  • An even number of inverters connected in series can be connected in series, or connected in series through wires.
  • the different positions in the second driving module 20 are used to shape the received first signal.
  • the first driving module 10 when the first driving module 10 is also previously coupled to other driving modules, the first driving module 10 also includes a signal shaping unit to provide feedback of the shaped first signal to the previous driving module. signal.
  • the control signal input end of the tri-state driver can be coupled to one of the above-mentioned signal generating units.
  • the data transmission circuit 1 may further include: a third driving module 30.
  • the third driving module 30 includes: a third three-state driver 302. The first input terminal 302a (data input terminal) of the third three-state driver 302 and the output terminal 202c (data output terminal) of the second three-state driver 202 are coupled through a bus.
  • the second driving module 20 may further include: a second signal generating unit 201.
  • the second signal generating unit 201 includes: a first input terminal 201a, a second input terminal 201b, and an output terminal 201c.
  • the output terminal 201c of the second signal generating unit 201 is coupled to the second input terminal 202b (control signal input terminal) of the second tri-state driver 202, and is used to receive the first signal through its first input terminal 201a, and through its second input terminal 201a.
  • the input terminal 201b receives the second feedback signal of the first signal from the third driving module 30, that is, when the first signal and the data signal are simultaneously transmitted to the third driving module 30, the first signal is fed back to the second driving module 30.
  • the second input terminal 201b of the second signal generating unit 201 in the module 20 After receiving the first signal and its feedback signal, the second signal generating unit 201 generates a second control signal whose effective signal width is wider than the first signal according to the first signal and its feedback signal, and is used to provide the second control signal to the second tri-state driver. 202, to perform data transmission control on the second tri-state driver 202.
  • Fig. 3 is a schematic diagram showing a second signal generating unit 201 according to an exemplary embodiment. As shown in FIG. 3, in some embodiments, the second signal generating unit 201 can also be implemented as an RS latch.
  • the first input terminal 201a of the second signal generating unit 201 is the setting terminal (ie S terminal) of the RS latch
  • the second input terminal 201b is the reset terminal (ie R terminal) of the RS latch
  • the output terminal 201c is, for example, the first output terminal (ie, the Q terminal) of the RS latch.
  • the effective signal width of the first signal (such as the duration of 1) is not enough to enable the data signal to be completely transmitted to the next drive module (such as the second drive module 20), but because the RS latch
  • the other input terminal also inputs a feedback signal, as long as the feedback signal is still 0, the RS latch will not be reset, so that the RS latch can still maintain a valid signal output, making the second three-state driver 202 continues to remain on, so as to ensure the complete transmission of the data signal.
  • the second signal generating unit 201 can also be implemented as the D flip-flop shown in FIG.
  • the third driving module 30 may further include: a signal shaping unit 303.
  • the signal shaping unit 303 includes: an input terminal 303a and an output terminal 303b, for receiving a first signal through its input terminal, shaping the first signal, and generating a second feedback signal output through its output terminal 303b. Since the quality of the first signal will become poor after a long bus transmission, the signal shaping unit 303 can shape it to improve its signal quality, thereby ensuring that the second feedback signal is fed back to the second driving module 20. , With good signal quality.
  • the signal shaping unit 303 can also be implemented as two coupled inverters to function as a buffer. After the first signal is transmitted through the bus, it is shaped by the buffer.
  • the third driving module 30 shown in FIG. 1 may also include the above-mentioned signal generating unit, the output of which is coupled to the second input terminal 302b (control signal input terminal) of the third three-state driver 302.
  • the signal generating unit is not shown in the figure.
  • the data transmission circuit 1 in FIG. 1 takes the serial connection of multiple drive modules as an example, but the present disclosure is not limited to this.
  • two parallel connection branches of the drive modules may also be serially connected through a bus. To the next level of drive module, etc.
  • a pulse signal in order to prevent the RS latch from working abnormally due to the too large width of the input first signal, a pulse signal can be generated according to the rising edge of the first signal as the first signal generation unit (101 or 201).
  • Fig. 4 is a block diagram showing a pulse signal generating unit according to an exemplary embodiment.
  • the first driving module 10 may further include: a pulse signal generating unit 104.
  • the pulse signal generating unit 104 includes an input terminal 104a and an output terminal 104b.
  • the output terminal 104b is coupled to the first input terminal 101a of the first signal generating unit 101 for receiving the first signal according to the rising edge of the first signal.
  • a pulse signal is generated, and the pulse signal is provided to the first signal generating unit 101 through the first input terminal 101a of the first signal generating unit 101.
  • the pulse signal generating unit 104 may include, for example, an odd-numbered gate circuit 1041, a NAND gate 1042, and an inverter 1043.
  • the odd-stage gate circuit 1041 receives the first signal through its input terminal 1041a;
  • the NAND gate 1042 receives the first signal through its first input terminal 1042a, and through its second input terminal 1042b and the output terminal 1041b of the odd-stage gate circuit 1041 Is coupled to receive the output signal of the odd-numbered gate circuit 1041, and is coupled to the input terminal 1043a of the inverter 1043 through its output terminal 1042c; the output terminal 1043b of the inverter 1043 and the first input terminal of the first signal generating unit 101 101a is coupled.
  • the delay of the odd-numbered gate circuit 1041 is the width of the pulse signal.
  • the pulse signal generation unit 104 generates a pulse signal as input, which can prevent the RS latch from working because the width of the input first signal is too large. Unusual problem.
  • the second driving module 20 and the third driving module 30 may also include the above-mentioned pulse signal generating unit. In order to simplify the drawings, it is not shown in FIG. 1 and will not be repeated here.
  • the first signal generating unit 101 may also be implemented as a combination of an inverter and a falling edge detection circuit, for example.
  • the falling edge detection circuit can be implemented, for example, by replacing the NAND gate 1042 shown in FIG. 4 with a NOR gate and removing the inverter 1043.
  • an inverter needs to be added before the falling edge detection circuit, so that the rising edge of the received first signal becomes a falling edge. .
  • Fig. 5 is a flow chart showing a method for transmitting multi-level driving data according to an exemplary embodiment.
  • the multi-level driving data transmission method shown in FIG. 5 can be applied to the above-mentioned multi-level driving data transmission circuit.
  • the multi-level drive data transmission method 2 includes:
  • step S22 the first signal and the feedback signal of the first signal from the next-level driving module are respectively received.
  • the first signal and the feedback signal of the first signal from the second driving module 20 or the third driving module 30 are received through the first signal generating unit 101 or the second signal generating unit 201 in FIG. 1.
  • step S24 a control signal with an effective signal width wider than the first signal is generated according to the first signal and the feedback signal, and the control signal is provided to the tri-state driver in the driver module of the current level.
  • a control signal with an effective signal width wider than the first signal is generated, and the control signal is transmitted to the first signal
  • the state driver 102 or the second tri-state driver 202 provides the control signal.
  • step S24 can be further implemented by the following embodiments: respectively input the first signal and the feedback signal to the set terminal and the reset terminal of the RS latch, and use the signal of the first output terminal of the RS latch as The control signal.
  • step 24 can be implemented by the following embodiments: input the first signal and the feedback signal to the clock input terminal and the reset terminal of the D flip-flop, respectively, and use the signal output from the output terminal of the D flip-flop as the control Signal, a fixed voltage signal VDD is input to the data terminal of the D flip-flop.
  • the multi-level driving data transmission method 1 may further include: in the next-level driving module, shaping the received first signal to obtain and output the feedback signal.
  • the received first signal may be shaped by the signal shaping unit 203 or the signal shaping unit 303 as shown in FIG. 1, so as to provide first feedback to the first signal generating unit 101 or the second signal generating unit 102 Signal or second feedback signal.
  • the multi-level driving data transmission method 1 may further include: generating a pulse signal according to the rising edge of the first signal, and outputting the pulse signal as the first signal.

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Abstract

本公开公开一种多级驱动数据传输电路及数据传输方法。该多级驱动数据传输电路，包括：第一驱动模块与第二驱动模块；其中，第一驱动模块包括：第一信号产生单元及第一三态驱动器；第二驱动模块包括：第二三态驱动器；第二三态驱动器的第一输入端与第一三态驱动器的输出端耦接；第一信号产生单元包括：第一输入端、第二输入端及输出端；第一信号产生单元的输出端与第一三态驱动器的第二输入端耦接；第一信号产生单元用于通过其第一输入端接收第一信号，通过其第二输入端接收来自第二驱动模块的、第一信号的第一反馈信号，根据第一信号及第一反馈信号，产生有效信号宽度宽于第一信号的第一控制信号，并向第一三态驱动器提供第一控制信号。

Description

多级驱动数据传输电路及数据传输方法 技术领域
本公开涉及三态驱动总线传输技术，具体而言，涉及一种多级驱动数据传输电路及数据传输方法。
背景技术
在半导体集成电路中，将三态驱动器连接在总线上，使用三态驱动器来驱动总线传输是很常用的技术。
三态驱动器的三态输出受到控制信号的控制，当控制信号有效时，器件实现正常逻辑状态输出，即将输入的数据直接送到输出端；当控制信号无效时，输出处于高阻状态，即等效于与所连的电路断开。
但由于不同的制程、电压、温度的变化，三态驱动器的控制信号可能会发生比较大的变化，导致输出驱动时间过短，输出信号不完整，或者导致连续的不同节拍的数据发生混乱。
在所述背景技术部分公开的上述信息仅用于加强对本公开的背景的理解，因此它可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
有鉴于此，本公开提供一种多级驱动数据传输电路及数据传输方法。
本公开的其他特性和优点将通过下面的详细描述变得显然，或部分地通过本公开的实践而习得。
根据本公开的一方面，提供一种多级驱动数据传输电路，包括：第一驱动模块与第二驱动模块；其中，第一驱动模块包括：第一信号产生单元及第一三态驱动器；第二驱动模块包括：第二三态驱动器；第二三态驱动器的第一输入端与第一三态驱动器的输出端耦接；第一信号产生单元包括：第一输入端、第二输入端及输出端；第一信号产生单元的输出端与第一三态驱动器的第二输入端耦接；第一信号产生单元用于通过其第一输入端接收第一信号，通过其第二输入端接收来自第二驱动模块的、第一信号的第一反馈信号，根据第一信号及第一反馈信号，产生有效信号宽度宽于第一信号的第一控制信号，并向第一三态驱动器提供第一控制信号。
根据本公开的一实施方式，所述第一信号产生单元包括：第一RS锁存器，所述第一信号产生单元的第一输入端为所述第一RS锁存器的设置端，所述第一信号产生单元的第二输入端为所述第一RS锁存器的重置端，所述第一信号产生单元的输出端为所述第一RS锁存器的第一输出端。
根据本公开的一实施方式，所述第一信号产生单元包括：第一D触发器，所述第一信号产生单元的第一输入端为所述第一D触发器的时钟输入端，所述第一信号产生单元的第二输入端为所述第一D触发器的重置端，所述第一信号产生单元的输出端为所述第一D触发器的输出端。
根据本公开的一实施方式，所述第二驱动模块还包括：信号整形单元，包括：输入端和输出端；所述信号整形单元用于通过其输入端接收所述第一信号，对所述第一信号进行整形，产生并通过其输出端输出所述第一反馈信号。
根据本公开的一实施方式，所述信号整形单元包括：偶数个相互串接的第一反相器。
根据本公开的一实施方式，所述第一驱动模块还包括：脉冲信号产生单元，包括：输入端和输出端，通过其输出端与所述第一信号产生单元的第一输入端耦接，用于接收所述第一信号，根据所述第一信号的上升沿，产生脉冲信号，并通过所述第一信号产生单元的第一输入端向所述第一信号产生单元提供所述脉冲信号。
根据本公开的一实施方式，所述脉冲信号产生单元包括：奇数级门电路、与非门及第二反相器；其中，所述奇数级门电路通过其输入端接收所述第一信号；所述与非门通过其第一输入端接收所述第一信号，通过其第二输入端与所述奇数级门电路的输出端耦接，接收所述奇数级门电路的输出信号，通过其输出端与所述第二反相器的输入端耦接；所述第二反相器的输出端与所述第一信号产生单元的第一输入端耦接。
根据本公开的一实施方式，还包括：第三驱动模块，包括：第三三态驱动器；所述第三三态驱动器的第一输入端与所述第二三态驱动器的输出端耦接；所述第二驱动模块还包括：第二信号产生单元；所述第二信号产生单元包括：第一输入端、第二输入端及输出端；所述第二信号产生单元的输出端与所述第二三态驱动器的第二输入端耦接；所述第二信号产生单元用于通过其第一输入端接收所述第一信号，通过其第二输入端接收来自所述第三驱动模块的、所述第一信号的第二反馈信号，根据所述第一信号及所述第二反馈信号，产生有效信号宽度宽于所述第一信号的第二控制信号，并向所述第二三态驱动器提供所述第二控制信号。
根据本公开的一实施方式，所述第二信号产生单元包括：第二RS锁存器，所述第二信号产生单元的第一输入端为所述第二RS锁存器的设置端，所述第二信号产生单元的第二输入端为所述第二RS锁存器的重置端，所述第二信号产生单元的输出端为所述第二RS锁存器的第一输出端。
根据本公开的一实施方式，所述第二信号产生单元包括：第二D触发器，所述第二信号产生单元的第一输入端为所述第二D触发器的时钟输入端，所述第二信号产生单元的第二输入端为所述第二D触发器的重置端，所述第二信号产生单元的输出端为所述第二D触发器的输出端。
根据本公开的另一方面，提供一种多级驱动数据传输方法，包括：分别接收第一信号及来自下一级驱动模块的、所述第一信号的反馈信号；以及根据所述第一信号及所述反馈信号，产生有效信号宽度宽于所述第一信号的控制信号，并向本级驱动模块中的三态驱动器提供所述控制信号。
根据本公开的一实施方式，根据所述第一信号及所述反馈信号，产生有效信号宽度宽于所述第一信号的控制信号，包括：分别将所述第一信号及所述反馈信号输入到RS锁存器的设置端和重置端，将所述RS锁存器第一输出端的信号作为所述控制信号。
根据本公开的一实施方式，根据所述第一信号及所述反馈信号，产生有效信号宽度宽于所述第一信号的控制信号，包括：分别将所述第一信号及所述反馈信号输入到D触发器的时钟输入端和重置端，将所述D触发器输出端输出的信号作为所述控制信号，将一固定电压信号输入到所述D触发器的数据端。
根据本公开的一实施方式，在接收所述反馈信号之前，所述方法还包括：在所述下一级驱动模块中，对所述第一信号进行整形，以获得并输出所述反馈信号。
根据本公开的一实施方式，在接收所述第一信号之前，所述方法还包括：根据所述第一信号的上升沿，产生脉冲信号，并将所述脉冲信号作为所述第一信号输出。
根据本公开的多级驱动数据传输电路及多级驱动数据传输方法，可以对输入到三态驱动器的控制信号进行处理，将原控制信号送至下一级驱动模块后，再反馈回本级的驱动模块。由于反馈路径的存在，可以根据反馈回来的控制信号与原控制信号，产生有效信号宽度宽于原控制信号的新的控制信号，从而避免因控制信号有效时间不足而导致无法将数据完整传输到下一级驱动模块中的问题。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性的，并不能限制本公开。
附图说明
通过参照附图详细描述其示例实施例，本公开的上述和其它目标、特征及优点将变得更加显而易见。
图1是根据一示例性实施方式示出的一种多级驱动数据传输电路的框图。
图2是根据一示例性实施例示出的第一信号产生单元101的示意图。
图3是根据一示例性实施例示出的第二信号产生单元201的示意图。
图4是根据一示例实施例示出的一种脉冲信号产生单元的框图。
图5是根据一示例性实施方式示出的一种多级驱动数据传输方法的流程图。
图6是根据一示例示出的信号时序示意图。
图7是根据一示例性实施例示出的另一种第一信号产生单元101的示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。
此外，所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知结构、方法、装置、实现或者操作以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。
如前所述，三态驱动器在控制信号有效期间被开启，用于将输入的数据输出；在控制信号无效期间被关闭，输出处于高阻状态，总线上的数据由保持电路保持住。但 如果控制信号的有效宽度由于制程或者工作电压和温度等原因变得太窄，三态驱动器的开启时间可能会不足以使数据完整地传输到下一级驱动模块中，从而发生错误。
本公开实施方式提供一种多级驱动数据传输电路及多级驱动数据传输方法，可以对输入到三态驱动器的控制信号进行处理，将原控制信号送至下一级驱动模块后，再反馈回本级的驱动模块。由于反馈路径的存在，可以根据反馈回来的控制信号与原控制信号，产生有效信号宽度宽于原控制信号的新的控制信号，从而避免因控制信号有效时间不足而导致无法将数据完整传输到下一级驱动模块中的问题。
下面首先说明本公开实施方式提供的多级驱动数据传输电路。
图1是根据一示例性实施方式示出的一种多级驱动数据传输电路的框图。
参考图1，多级驱动数据传输电路1包括：第一驱动模块10及第二驱动模块20。
其中，第一驱动模块10包括：第一信号产生单元101和第一三态驱动器102。第二驱动模块20包括：第二三态驱动器202。
第一三态驱动器102的输出端102c(数据输出端)通过总线Bus与第二三态驱动器202的第一输入端202a(数据输入端)耦接，将第一驱动模块10输出的数据通过总线Bus输出到第二驱动模块20中。
第一信号产生单元101包括：第一输入端101a、第二输入端101b及输出端101c。第一信号产生单元101的输出端101c与第一三态驱动器102的第二输入端102b(控制信号输入端)耦接。第一信号产生单元101的第一输入端101a用于接收第一信号(如数据传输电路1中的控制信号)，第二输入端101b用于接收来自第二驱动模块20的、第一信号的第一反馈信号。也即，用原有控制信号(第一信号)的前沿打开第一三态驱动器102，发送数据信号。同时，使用同样的信号线，将控制信号一起发送出去。当第一信号与数据信号被同时传输到第二驱动模块20后，第一信号再反馈回第一驱动模块10中的第一信号产生单元101的第二输入端101b。第一信号产生单元101在分别接收到第一信号与其反馈信号后，根据第一信号与其反馈信号，产生有效信号宽度宽于第一信号的第一控制信号，用于提供给第一三态驱动器102，以对第一三态驱动器102进行数据传输控制。
图2是根据一示例性实施例示出的第一信号产生单元101的示意图。如图2所示，在一些实施例中，第一信号产生单元101可以被实施为一个RS锁存器。
其中，第一信号产生单元101的第一输入端101a如为RS锁存器的设置端(即S端)，第二输入端101b如为RS锁存器的重置端(即R端)，输出端101c如为RS 锁存器的第一输出端(即Q端)。
由于反馈路径的存在，即使第一信号的有效信号宽度(如为1的时长)不足以使得数据信号完整地传输到下一个驱动模块(如第二驱动模块20)，但因为在RS锁存器的另一输入端还输入了反馈信号，只要反馈信号仍为0，就不会对RS锁存器进行重置，从而仍可使RS锁存器继续保持有效信号输出，使得第一三态驱动器102继续保持开启状态，进而保证数据信号的完整传输。
图6是根据一示例示出的信号时序示意图。如图6所示，当第一信号的有效宽度较较窄(如图中所示的t1～t2)时，由于在t2～t3时刻，反馈信号为0，因此第一输出端输出的第一控制信号在t2～t3时刻的输出仍为1，从而延展了第一信号的有效宽度(如图中所示，有效信号宽度为t1～t3)。
图7是根据一示例性实施例示出的另一种第一信号产生单元101的示意图。如图7所示，在一些实施例中，第一信号产生单元101还可以被实施为一个D触发器。
其中，第一信号产生单元101的第一输入端101a如为D触发器的时钟信号端(即图中的CLK端)，用于接收第一信号；第二输入端101b如为D触发器的重置端(即图中的RESET端)，用于接收反馈信号；输出端101c如为D触发器的输出端(即图中的Q端)，输出第一控制信号。
此外，D触发器的数据端101d(即图中的DATA端)可以输入一固定电压信号VDD。
同样地，由于反馈路径的存在，即使第一信号的有效信号宽度(如为1的时长)不足以使得数据信号完整地传输到下一个驱动模块(如第二驱动模块20)，但因为在D触发器的RESET输入端还输入了反馈信号，仍以图6为例，在t2～t3时刻，反馈信号为0，无法对D触发器进行重置(RESET)，即对D触发器当前输出状态进行了锁存，因此第一输出端输出的第一控制信号在t2～t3时刻的输出仍为1，从而延展了第一信号的有效宽度，进而保证数据信号的完整传输。继续参考图1，在一些实施例中，第二驱动模块20还可以包括：信号整形单元203。信号整形单元203包括：输入端203a和输出端203b，用于通过其输入端接收第一信号，对第一信号进行整形，进而产生通过其输出端203b输出的第一反馈信号。由于经过较长的总线传输后，第一信号的质量会变得较差，通过信号整形单元203对其进行整形，可以提高其信号质量，从而保证反馈信号反馈回第一驱动模块10时，具有较好的信号质量。
在一些实施例中，信号整形单元203可以被实施为偶数个串接的反相器，起到缓 冲器的作用。在第一信号经过总线传输后，经过缓冲器对其进行整形。本领域技术人员应理解的是，图1中两个相互串接的反相器的位置仅为示例，偶数个相互串接的反相器可以串接在一起，也可以通过导线串接在第二驱动模块20中的不同位置，用于对接收到的第一信号进行整形。
需要说明的是，当第一驱动模块10之前也耦接有其他驱动模块时，第一驱动模块10中也包含信号整形单元，以向前一级驱动模块提供经过整形后的第一信号的反馈信号。
如果是多级的传输路径，每一级驱动模块中，都可以为三态驱动器的控制信号输入端耦接一个上述的信号产生单元。参考图1，在一些实施例中，数据传输电路1还可以包括：第三驱动模块30。第三驱动模块30包括：第三三态驱动器302。第三三态驱动器302的第一输入端302a(数据输入端)与第二三态驱动器202的输出端202c(数据输出端)通过总线耦接。
第二驱动模块20还可以包括：第二信号产生单元201。第二信号产生单元201包括：第一输入端201a、第二输入端201b及输出端201c。第二信号产生单元201的输出端201c与第二三态驱动器202的第二输入端202b(控制信号输入端)耦接，用于通过其第一输入端201a接收第一信号，通过其第二输入端201b接收来自第三驱动模块30的、第一信号的第二反馈信号，也即当第一信号与数据信号被同时传输到第三驱动模块30后，第一信号再反馈回第二驱动模块20中的第二信号产生单元201的第二输入端201b。第二信号产生单元201在分别接收到第一信号与其反馈信号后，根据第一信号与其反馈信号，产生有效信号宽度宽于第一信号的第二控制信号，用于提供给第二三态驱动器202，以对第二三态驱动器202进行数据传输控制。
图3是根据一示例性实施例示出的第二信号产生单元201的示意图。如图3所示，在一些实施例中，第二信号产生单元201同样可以被实施为一个RS锁存器。
其中，第二信号产生单元201的第一输入端201a如为RS锁存器的设置端(即S端)，第二输入端201b如为RS锁存器的重置端(即R端)，输出端201c如为RS锁存器的第一输出端(即Q端)。
由于反馈路径的存在，即使第一信号的有效信号宽度(如为1的时长)不足以使得数据信号完整地传输到下一个驱动模块(如第二驱动模块20)，但因为在RS锁存器的另一输入端还输入了反馈信号，只要反馈信号仍为0，就不会对RS锁存器进行重置，从而仍可使RS锁存器继续保持有效信号输出，使得第二三态驱动器202继续 保持开启状态，从而保证数据信号的完整传输。
同样地，如图6所示，当第二信号的有效宽度较较窄(如图中所示的t1～t2)时，由于在t2～t3时刻，反馈信号仍为0，因此第一输出端输出的新的第二控制信号在t2～t3时刻的输出仍为1，从而延展了第二信号的有效宽度(如图中所示，有效信号宽度为t1～t3)。
此外，第二信号产生单元201也可以被实施为图7所示的D触发器，其连接关系及工作原理在此不再赘述。
同样地，第三驱动模块30还可以包括：信号整形单元303。信号整形单元303包括：输入端303a和输出端303b，用于通过其输入端接收第一信号，对第一信号进行整形，进而产生通过其输出端303b输出的第二反馈信号。由于经过较长的总线传输后，第一信号的质量会变得较差，通过信号整形单元303对其进行整形，可以提高其信号质量，从而保证第二反馈信号反馈回第二驱动模块20时，具有较好的信号质量。
在一些实施例中，信号整形单元303同样可以被实施为两个耦接的反相器，起到缓冲器的作用。在第一信号经过总线传输后，经过缓冲器对其进行整形。
此外，如图1中所示的第三驱动模块30中也可以包括如上述的信号产生单元，其输出与第三三态驱动器302的第二输入端302b(控制信号输入端)耦接。为了简化附图，图中未示出该信号产生单元。
需要说明的是，图1中的数据传输电路1以多个驱动模块串行连接为例，但本公开不以此为限，例如还可以为两个驱动模块并行连接支路通过总线串行连接至下一级驱动模块中等。
在一些实施例中，为了防止输入的第一信号宽度太大而导致RS锁存器工作异常，可以根据第一信号的上升沿，产生一个脉冲信号，作为信号产生单元(101或201)中第一输入端(101a或201a)的输入。
图4是根据一示例实施例示出的一种脉冲信号产生单元的框图。联合参考图1和图4，第一驱动模块10还可以包括：脉冲信号产生单元104。脉冲信号产生单元104包括：输入端104a和输出端104b，通过其输出端104b与第一信号产生单元101的第一输入端101a耦接，用于接收第一信号，根据第一信号的上升沿，产生一个脉冲信号，并通过第一信号产生单元101的第一输入端101a向第一信号产生单元101提供该脉冲信号。
如图4所示，脉冲信号产生单元104例如可以包括：奇数级门电路1041、与非门 1042及反相器1043。其中，奇数级门电路1041通过其输入端1041a接收第一信号；与非门1042通过其第一输入端1042a接收第一信号，通过其第二输入端1042b与奇数级门电路1041的输出端1041b耦接，接收奇数级门电路1041的输出信号，通过其输出端1042c与反相器1043的输入端1043a耦接；反相器1043的输出端1043b与第一信号产生单元101的第一输入端101a耦接。
其中，奇数级门电路1041的延时就是脉冲信号的宽度，通过该脉冲信号产生单元104来产生脉冲信号作为输入，可以防止出现因为输入的第一信号的宽度太大而导致RS锁存器工作异常的问题。
类似地，第二驱动模块20与第三驱动模块30中也可以包括上述的脉冲信号产生单元，为了简化附图，图1中未示出，且在此不再赘述。
此外，第一信号产生单元101例如还可以被实施为反相器与下降沿检测电路的组合。下降沿检测电路例如可以将图4中所示的与非门1042替换为一或非门，并去掉反相器1043来实现。同时，为了实现对第一信号上升沿的检测，并根据上升沿产生脉冲信号，还需要在下降沿检测电路之前增加一反相器，从而使接收到的第一信号的上升沿变为下降沿。
应清楚地理解，本公开描述了如何形成和使用特定示例，但本公开的原理不限于这些示例的任何细节。相反，基于本公开公开的内容的教导，这些原理能够应用于许多其它实施方式。
下述为本公开方法实施例，可以应用于本公开装置实施例中。对于本公开方法实施例中未披露的细节，请参照本公开装置实施例。
图5是根据一示例性实施方式示出的一种多级驱动数据传输方法的流程图。图5所示的多级驱动数据传输方法可以应用于上述多级驱动数据传输电路中。
参考图5，多级驱动数据传输方法2包括：
在步骤S22中，分别接收第一信号及来自下一级驱动模块的、该第一信号的反馈信号。
例如，通过图1中的第一信号产生单元101或第二信号产生单元201接收第一信号及来自第二驱动模块20或第三驱动模块30的、该第一信号的反馈信号。
在步骤S24中，根据第一信号及反馈信号，产生有效信号宽度宽于第一信号的控制信号，并向本级驱动模块中的三态驱动器提供该控制信号。
例如，通过如图1中所示的第一信号产生单元101或第二信号产生单元201，根据第一信号及反馈信号，产生有效信号宽度宽于第一信号的控制信号，并向第一三态驱动器102或第二三态驱动器202提供该控制信号。
由于反馈路径的存在，可以根据反馈回来的控制信号与原控制信号，产生有效信号宽度宽于原控制信号的新的控制信号，从而避免因控制信号有效时间不足而导致无法将数据完整传输到下一级驱动模块中的问题。
在一些实施例中，步骤S24可以进一步通过下述实施例实现：分别将第一信号及反馈信号输入到RS锁存器的设置端和重置端，将RS锁存器第一输出端的信号作为该控制信号。
在一些实施例中，步骤24可以通过下述实施例实现：分别将第一信号及反馈信号输入到D触发器的时钟输入端和重置端，将D触发器输出端输出的信号作为该控制信号，将一固定电压信号VDD输入到D触发器的数据端。
在一些实施例中，多级驱动数据传输方法1在步骤S22之前，还可以进一步包括：在下一级驱动模块中，对接收到的第一信号进行整形，以获得并输出该反馈信号。例如，可以通过如图1中所示的信号整形单元203或信号整形单元303来对接收到的第一信号进行整形，从而向第一信号产生单元101或第二信号产生单元102提供第一反馈信号或第二反馈信号。
在一些实施例中，多级驱动数据传输方法1在步骤S22之前，还可以进一步包括：根据所述第一信号的上升沿，产生脉冲信号，并将该脉冲信号作为第一信号输出。
此外，需要注意的是，上述附图仅是根据本公开示例性实施方式的方法所包括的处理的示意性说明，而不是限制目的。易于理解，上述附图所示的处理并不表明或限制这些处理的时间顺序。另外，也易于理解，这些处理可以是例如在多个模块中同步或异步执行的。
以上具体地示出和描述了本公开的示例性实施方式。应可理解的是，本公开不限于这里描述的详细结构、设置方式或实现方法；相反，本公开意图涵盖包含在所附权利要求的精神和范围内的各种修改和等效设置。

Claims (13)

  1. 一种多级驱动数据传输电路，其特征在于，包括：
    第一驱动模块，包括：第一信号产生单元及第一三态驱动器；以及
    第二驱动模块，包括：第二三态驱动器；
    其中，所述第二三态驱动器的第一输入端与所述第一三态驱动器的输出端耦接；
    所述第一信号产生单元包括：第一输入端、第二输入端及输出端；所述第一信号产生单元的输出端与所述第一三态驱动器的第二输入端耦接；所述第一信号产生单元用于通过其第一输入端接收第一信号，通过其第二输入端接收来自所述第二驱动模块的、所述第一信号的第一反馈信号，根据所述第一信号及所述第一反馈信号，产生有效信号宽度宽于所述第一信号的第一控制信号，并向所述第一三态驱动器提供所述第一控制信号。
  2. 根据权利要求1所述的多级驱动数据传输电路，其特征在于，所述第一信号产生单元包括：第一RS锁存器，所述第一信号产生单元的第一输入端为所述第一RS锁存器的设置端，所述第一信号产生单元的第二输入端为所述第一RS锁存器的重置端，所述第一信号产生单元的输出端为所述第一RS锁存器的第一输出端。
  3. 根据权利要求1所述的多级驱动数据传输电路，其特征在于，所述第一信号产生单元包括：第一D触发器，所述第一信号产生单元的第一输入端为所述第一D触发器的时钟输入端，所述第一信号产生单元的第二输入端为所述第一D触发器的重置端，所述第一信号产生单元的输出端为所述第一D触发器的输出端。
  4. 根据权利要求1-3任一项所述的多级驱动数据传输电路，其特征在于，所述第二驱动模块还包括：信号整形单元，包括：输入端和输出端；所述信号整形单元用于通过其输入端接收所述第一信号，对所述第一信号进行整形，产生并通过其输出端输出所述第一反馈信号。
  5. 根据权利要求4所述的多级驱动数据传输电路，其特征在于，所述信号整形单元包括：偶数个相互串接的第一反相器。
  6. 根据权利要求1-3任一项所述的多级驱动数据传输电路，其特征在于，所述第一驱动模块还包括：脉冲信号产生单元，包括：输入端和输出端，通过其输出端与所述第一信号产生单元的第一输入端耦接，用于接收所述第一信号，根据所述第一信号的上升沿，产生脉冲信号，并通过所述第一信号产生单元的第一输入端向所述第一信 号产生单元提供所述脉冲信号。
  7. 根据权利要求6所述的多级驱动数据传输电路，其特征在于，所述脉冲信号产生单元包括：奇数级门电路、与非门及第二反相器；其中，所述奇数级门电路通过其输入端接收所述第一信号；所述与非门通过其第一输入端接收所述第一信号，通过其第二输入端与所述奇数级门电路的输出端耦接，接收所述奇数级门电路的输出信号，通过其输出端与所述第二反相器的输入端耦接；所述第二反相器的输出端与所述第一信号产生单元的第一输入端耦接。
  8. 根据权利要求1-3任一项所述的多级驱动数据传输电路，其特征在于，还包括：第三驱动模块，包括：第三三态驱动器；所述第三三态驱动器的第一输入端与所述第二三态驱动器的输出端耦接；所述第二驱动模块还包括：第二信号产生单元；所述第二信号产生单元包括：第一输入端、第二输入端及输出端；所述第二信号产生单元的输出端与所述第二三态驱动器的第二输入端耦接；所述第二信号产生单元用于通过其第一输入端接收所述第一信号，通过其第二输入端接收来自所述第三驱动模块的、所述第一信号的第二反馈信号，根据所述第一信号及所述第二反馈信号，产生有效信号宽度宽于所述第一信号的第二控制信号，并向所述第二三态驱动器提供所述第二控制信号。
  9. 一种多级驱动数据传输方法，其特征在于，包括：
    分别接收第一信号及来自下一级驱动模块的、所述第一信号的反馈信号；以及
    根据所述第一信号及所述反馈信号，产生有效信号宽度宽于所述第一信号的控制信号，并向本级驱动模块中的三态驱动器提供所述控制信号。
  10. 根据权利要求9所述的多级驱动数据传输方法，其特征在于，根据所述第一信号及所述反馈信号，产生有效信号宽度宽于所述第一信号的控制信号，包括：分别将所述第一信号及所述反馈信号输入到RS锁存器的设置端和重置端，将所述RS锁存器第一输出端的信号作为所述控制信号。
  11. 根据权利要求9所述的多级驱动数据传输方法，其特征在于，根据所述第一信号及所述反馈信号，产生有效信号宽度宽于所述第一信号的控制信号，包括：分别将所述第一信号及所述反馈信号输入到D触发器的时钟输入端和重置端，将所述D触发器输出端输出的信号作为所述控制信号，将一固定电压信号输入到所述D触发器的数据端。
  12. 根据权利要求9所述的多级驱动数据传输方法，其特征在于，在接收所述反 馈信号之前，所述方法还包括：在所述下一级驱动模块中，对所述第一信号进行整形，以获得并输出所述反馈信号。
  13. 根据权利要求9所述的多级驱动数据传输方法，其特征在于，在接收所述第一信号之前，所述方法还包括：根据所述第一信号的上升沿，产生脉冲信号，并将所述脉冲信号作为所述第一信号输出。
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