WO2021027131A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2021027131A1
WO2021027131A1 PCT/CN2019/117147 CN2019117147W WO2021027131A1 WO 2021027131 A1 WO2021027131 A1 WO 2021027131A1 CN 2019117147 W CN2019117147 W CN 2019117147W WO 2021027131 A1 WO2021027131 A1 WO 2021027131A1
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WO
WIPO (PCT)
Prior art keywords
display panel
insulating layer
line
data lines
lines
Prior art date
Application number
PCT/CN2019/117147
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English (en)
French (fr)
Inventor
蔡振飞
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/620,893 priority Critical patent/US20210050407A1/en
Publication of WO2021027131A1 publication Critical patent/WO2021027131A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance

Definitions

  • This application relates to the field of electronic display, and in particular to a display panel.
  • FIG. 1 shows the power line layout adopted in the AMOLED display panel in the prior art.
  • the power line 30 is input through a chipon film (COF) surrounding the source and drain metal layers.
  • COF chipon film
  • the power line 30 is easily short-circuited with the gate line, causing the panel to burn.
  • the power line 30 is limited by the space of the thin film transistors, and the line width cannot be made too large, resulting in relatively high resistance of the power line 30, which increases the power loss of the display panel.
  • the present application provides a display panel to solve the technical problem that the power line is easily short-circuited with the gate line and the panel is damaged.
  • the present application provides a display panel, the display panel including:
  • a plurality of gate lines, the plurality of gate lines are located on the first insulating layer and are electrically connected to the gates of the plurality of thin film transistors through a plurality of first through holes;
  • a second insulating layer covering the gate line
  • a plurality of data lines, the plurality of data lines are located on the second insulating layer and are electrically connected to the source and drain of the plurality of thin film transistors through a plurality of second through holes;
  • a third insulating layer covering the data line
  • a light-emitting layer includes a plurality of pixels, and the cathode of the plurality of pixels is a conductive film;
  • the power line surrounds the conductive film and is electrically connected to the data line through a plurality of third through holes.
  • each pixel includes:
  • An anode, the anode is located on the third insulating layer;
  • a pixel definition layer is located on the third insulating layer and has an opening exposing the anode
  • a luminescent material located in the opening and is electrically connected to the anode;
  • the cathode, the cathode is the conductive film covering the pixel defining layer and the luminescent material.
  • the plurality of gate lines are a plurality of conductive metals arranged in parallel, and the extending direction of the plurality of gate lines is a first direction.
  • the plurality of gate lines are arranged at intervals, and the distance between any two adjacent gate lines is equal.
  • the plurality of data lines are a plurality of conductive metals arranged in parallel, an extension direction of the plurality of data lines is a second direction, and the second direction is perpendicular to the first direction.
  • the multiple data lines are arranged at intervals, and the distance between any two adjacent data lines is equal.
  • each of the data lines includes a first end and a second end, the first ends of the multiple data lines are connected to the input data signal, and the second ends of the multiple data lines pass through The first connecting wire extending in the first direction realizes electrical connection.
  • the first connection line is located directly below the power line, and two third through holes are respectively located at both ends of the first connection line for realizing the connection between the first connection line and the Electrical connection of the power cord.
  • the plurality of data lines further includes at least two second connecting lines, the second connecting lines are located on both sides of the first ends of the plurality of data lines, and the second connecting lines One end of the second connection line is connected to the input signal, and the other end of the second connection line is located directly under the power line, and is electrically connected to the power line through a third through hole.
  • the width of the power line is greater than or equal to twice the width of the data line.
  • the display panel in this application has the power line and the cathode arranged on the same layer, and uses the metal film surrounding the cathode as the power line through the through hole Realize the electrical connection of the power line and the data line.
  • the display panel in this application After layering, there are at least three insulating layers between the power line and the gate line, which greatly reduces the probability of a short circuit between the power line and the gate line.
  • the power line is not restricted by the layout of the data line, and its line width can be several times that of the data line, thereby effectively reducing the impedance of the power line and avoiding voltage drop The uneven brightness caused by the phenomenon.
  • FIG. 1 is a schematic diagram of the structure of metal traces in a display panel in the prior art
  • FIG. 2 is a schematic diagram of the structure of a display panel in the prior art
  • FIG. 3 is a schematic diagram of the structure of metal traces in a display panel in a specific embodiment of the application.
  • FIG. 4 is a schematic structural diagram of a display panel in a specific embodiment of the application.
  • FIG. 1 is a schematic diagram of the structure of the metal wiring in the display panel in the prior art
  • FIG. 2 is a schematic diagram of the structure of the display panel in the prior art.
  • the power supply line 30 is input through a film-coated chip surrounding the source and drain metal layers.
  • the power line 30 and the data line 10 are connected together around the edge of the display area, that is, the power line 30 will cross all the data lines 10 in the panel.
  • the laminated structure of the display panel in the prior art usually includes a substrate 201, a buffer layer 202, a thin film transistor layer 203, an interlayer dielectric layer 204, a planarization layer 205, and a pixel definition layer 206.
  • the gate line is located between the thin film transistor layer 203 and the interlayer dielectric layer 204
  • the data line 10 is located between the interlayer dielectric layer 204 and the planarization layer 205. Since there is only an interlayer dielectric layer 204 between the data line 10 and the gate line 20, when a defective circuit or electrostatic breakdown occurs in the display panel, the power line 30 is easily short-circuited with the gate line 10, causing the panel to burn. At the same time, in the display panel adopting this layout, the power line 30 is limited by the layout of the data line 10, and the line width cannot be made too large, resulting in a relatively high resistance of the power line 30, which increases the power loss of the display panel. .
  • the present application provides a display panel to solve the technical problem that the power line is easily short-circuited with the gate line and the panel is damaged.
  • FIG. 3 is a schematic diagram of the structure of the metal wiring in the display panel in a specific embodiment of the application
  • FIG. 4 is a schematic diagram of the structure of the display panel in a specific embodiment of the application.
  • the display panel includes: a substrate, a first insulating layer, a plurality of gate lines 20, a second insulating layer, a plurality of data lines 10, a third insulating layer, a light emitting layer, and a power line 50.
  • the substrate includes a substrate 201, a buffer layer 202 on the substrate, and a thin film transistor layer 203a on the buffer layer 202.
  • the thin film transistor layer 203a includes an active region and a gate stack located above the active region.
  • the active region includes a channel region and a source and drain region; the gate stack is located above the channel region and includes a gate dielectric layer and a gate metal layer located above the gate dielectric layer.
  • the first insulating layer 203b covers the thin film transistors on the substrate, that is, the first insulating layer 203b covers the active region and the gate stack.
  • the plurality of gate lines 20 are located on the first insulating layer 203b. One end of the plurality of gate lines 20 is connected to the input gate signal, and the other end is electrically connected to the gate stack of the plurality of thin film transistors through a plurality of first through holes.
  • the plurality of gate lines 20 are used to provide gate control signals to the gates of the plurality of thin film transistors in the substrate.
  • the plurality of gate lines 20 are a plurality of conductive metals arranged in parallel, and the extending direction of the plurality of gate lines 20 is the first direction.
  • the first direction is parallel to one side of the display panel.
  • the plurality of gate lines 20 are arranged at intervals, and the distance between any two adjacent gate lines is equal.
  • the second insulating layer 204 covers the gate line 20.
  • the second insulating layer 204 is an interlayer dielectric layer.
  • the plurality of data lines 10 are located on the second insulating layer 204. One end of the plurality of data lines 10 is connected to the input signal, and the other end is electrically connected to the source region and the drain region of the plurality of thin film transistors through a plurality of second through holes.
  • the third insulating layer covers the data line.
  • the third insulating layer is a planarization layer 205.
  • the light-emitting layer includes a plurality of pixels, and each pixel includes an anode, a pixel defining layer 206, a light-emitting material, and a cathode 40. Since the structural diagram shown in FIG. 4 is a cross-sectional view of the wiring area where the power line 50 is located, the anode, the luminescent material, and the cathode are not shown in FIG. 4.
  • the anode is located on the third insulating layer 205.
  • the pixel definition layer 206 is located on the third insulating layer 205 and has an opening exposing the anode.
  • the luminescent material is located in the opening and is electrically connected to the anode.
  • the cathode 40 is a conductive film covering the pixel defining layer and the luminescent material.
  • the power line 50 surrounds the conductive film and is electrically connected to the data line 10 through a plurality of third through holes 66.
  • the data line is used to provide a driving voltage to the source region or the drain region of a plurality of thin film transistors in the substrate.
  • the plurality of data lines 10 are a plurality of conductive metals arranged in parallel, the extension direction of the plurality of data lines 10 is a second direction, and the second direction is perpendicular to the first direction.
  • the multiple data lines 10 are arranged at intervals, and the distance between any two adjacent data lines 10 is equal.
  • each of the data lines includes a first end and a second end, the first ends of the multiple data lines are connected to the input data signal, and the second ends of the multiple data lines pass along the first direction
  • the extended first connecting wire 64 realizes electrical connection.
  • the first connection line 64 is located directly under the power line 50, and two third through holes 66 are respectively located at both ends of the first connection line 64, and are used to realize the first connection line 64 and the power line 50.
  • the electrical connection provides the power supply voltage for the multiple data lines.
  • the plurality of data lines 10 further includes at least two second connecting lines 62, the second connecting lines 62 are located on both sides of the first ends of the plurality of data lines 10, and the second One end of the connection line 62 is connected to the input signal, and the other end of the second connection line 62 is located directly under the power line 50 and is electrically connected to the power line 50 through the third through hole 66.
  • the number of the third through holes 66 can be set as required.
  • the number of the third through holes 66 is equal to the number of the data lines 10.
  • the power line 50 and the data line 10 are arranged in layers, the power line 50 is not restricted by the layout of the data line 10, and its line width can be several times that of the data line, thereby effectively reducing the power supply.
  • the impedance of the line avoids uneven brightness caused by voltage drop.
  • the width of the power line 50 is greater than or equal to twice the width of the data line 10.
  • the display panel in this application has the power line and the cathode arranged on the same layer, and uses the metal film surrounding the cathode as the power line through the through hole Realize the electrical connection of the power line and the data line.
  • the display panel in this application After layering, there are at least three insulating layers between the power line and the gate line, which greatly reduces the probability of a short circuit between the power line and the gate line.
  • the power line is not restricted by the layout of the data line, and its line width can be several times that of the data line, thereby effectively reducing the impedance of the power line and avoiding voltage drop The uneven brightness caused by the phenomenon.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

本申请提供一种显示面板，其包括：基板、第一绝缘层、多条栅极线、第二绝缘层、多条数据线、第三绝缘层、发光层和电源线。所述基板上具有多个薄膜晶体管。所述第一绝缘层覆盖所述基板上的薄膜晶体管。所述多条栅极线位于所述第一绝缘层上，所述第二绝缘层覆盖所述栅极线。所述多条数据线位于所述第二绝缘层上。所述第三绝缘层覆盖所述数据线。所述发光层包括多个像素点。所述电源线环绕所述发光层。

Description

显示面板 技术领域
本申请涉及电子显示领域，尤其涉及一种显示面板。
 背景技术
主动矩阵有机发光二极管（Active-matrix organic light-emitting diode  , AMOLED）显示面板的对比度高，视角广且响应速度快，有望取缔液晶成为下一代显示器主流选择。图1示出了现有技术中的AMOLED显示面板中采取的电源线布局。电源线30通过源漏金属层周围的覆膜芯片（chiponfilm, COF）输入。为了减小压降，电源线30和数据线10围绕显示区域边缘连接在一起，即电源线30会与面板内所有的数据线10发生交叉。
 技术问题
参见图2，数据线10和栅极线20之间只有一层间介质层204。当显示面板中出现线路不良或静电击穿时，电源线30很容易与栅极线短路，导致面板烧毁。同时，在采用这种布局的显示面板中，电源线30会受到薄膜晶体管的空间限制，线宽不能做的很大，导致电源线30的电阻相对较高，增大了显示面板的功率损耗。
 技术解决方案
本申请提供了一种显示面板，以解决电源线容易与栅极线短路导致面板损毁的技术问题。
为解决上述问题，本申请提供了一种显示面板，所述显示面板包括：
基板，所述基板上具有多个薄膜晶体管；
第一绝缘层，所述第一绝缘层覆盖所述基板上的薄膜晶体管；
多条栅极线，所述多条栅极线位于所述第一绝缘层上，并通过多个第一通孔与所述多个薄膜晶体管的栅极电连接；
第二绝缘层，所述第二绝缘层覆盖所述栅极线；
多条数据线，所述多条数据线位于所述第二绝缘层上，并通过多个第二通孔与所述多个薄膜晶体管的源极和漏极电连接；
第三绝缘层，所述第三绝缘层覆盖所述数据线；
发光层，所述发光层包括多个像素点，所述多个像素点的阴极为一导电薄膜；
电源线，所述电源线环绕所述导电薄膜，并通过多个第三通孔与所述数据线电连接。
根据本申请的其中一个方面，每一个所述像素点包括：
阳极，所述阳极位于所述第三绝缘层上；
像素定义层，所述像素定义层位于所述第三绝缘层上，并具有暴露出所述阳极的开口；
发光材料，所述发光材料位于所述开口中，与所述阳极电连接；
阴极，所述阴极为覆盖所述像素定义层和发光材料的所述导电薄膜。
根据本申请的其中一个方面，所述多条栅极线为多条平行设置的导电金属，所述多条栅极线的延伸方向为第一方向。
根据本申请的其中一个方面，所述多条栅极线间隔设置，任意两条相邻的栅极线之间的距离相等。
根据本申请的其中一个方面，所述多条数据线为多条平行设置的导电金属，所述多条数据线的延伸方向为第二方向，所述第二方向与所述第一方向垂直。
根据本申请的其中一个方面，所述多条数据线间隔设置，任意两条相邻的数据线之间的距离相等。
根据本申请的其中一个方面，每一条所述数据线包括第一端和第二端，所述多条数据线的第一端连接输入数据信号，所述多条数据线的第二端通过沿第一方向延伸的第一连接线实现电连接。
根据本申请的其中一个方面，所述第一连接线位于所述电源线正下方，两个第三通孔分别位于所述第一连接线的两端，用于实现所述第一连接线和电源线的电连接。
根据本申请的其中一个方面，所述多条数据线还包括至少两条第二连接线，所述第二连接线位于所述多条数据线的第一端两侧，所述第二连接线的一端连接输入信号，所述第二连接线的另一端位于所述电源线的正下方，通过第三通孔与所述电源线电连接。
根据本申请的其中一个方面，所述电源线的宽度大于或等于所述数据线的宽度的两倍。
 有益效果
相比于现有技术中将电源线与数据线设置在同一层的显示面板，本申请中的显示面板将电源线与阴极设置在同一层，采用环绕阴极的金属薄膜作为电源线，通过通孔实现电源线和数据线的电连接。分层设置后，电源线与栅极线之间间隔了至少三层绝缘层，极大的减小了电源线与栅极线之间发生短路的概率。同时，由于电源线与数据线分层设置，电源线可以不受数据线的布局限制，其线宽可以数倍于数据线的线宽，从而有效的降低了电源线的阻抗，避免了压降现象带来的亮度不均。
 附图说明
图1为现有技术中的显示面板中的金属走线的结构示意图；
图2为现有技术中的显示面板的结构示意图；
图3为本申请的一个具体实施例中的显示面板中的金属走线的结构示意图；
图4为本申请的一个具体实施例中的显示面板的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
首先对现有技术进行简要说明。参见图1和图2，图1为现有技术中的显示面板中的金属走线的结构示意图，图2为现有技术中的显示面板的结构示意图。
现有技术中，电源线30通过源漏金属层周围的覆膜芯片输入。为了减小压降，电源线30和数据线10围绕显示区域边缘连接在一起，即电源线30会与面板内所有的数据线10发生交叉。
参见图2，现有技术中的显示面板的叠层结构通常包括衬底201、缓冲层202、薄膜晶体管层203、层间介质层204、平坦化层205、像素定义层206。其中，栅极线位于薄膜晶体管层203和层间介质层204之间，数据线10位于层间介质层204和平坦化层205之间。由于数据线10和栅极线20之间只有一层间介质层204，当显示面板中出现线路不良或静电击穿时，电源线30很容易与栅极线10短路，导致面板烧毁。同时，在采用这种布局的显示面板中，电源线30会受到数据线10的布局限制，线宽不能做的很大，导致电源线30的电阻相对较高，增大了显示面板的功率损耗。
因此，本申请提供了一种显示面板，以解决电源线容易与栅极线短路导致面板损毁的技术问题。
下面将结合附图对本申请的其中一个实施例进行详细说明。参见图3和图4，图3为本申请的一个具体实施例中的显示面板中的金属走线的结构示意图，图4为本申请的一个具体实施例中的显示面板的结构示意图。
本实施例中，所述显示面板包括：基板、第一绝缘层、多条栅极线20、第二绝缘层、多条数据线10、第三绝缘层、发光层、电源线50。
所述基板上具有多个薄膜晶体管。具体的，所述基板包括衬底201、位于衬底上的缓冲层202以及位于所述缓冲层202上的薄膜晶体管层203a。所述薄膜晶体管层203a包括有源区和位于所述有源区上方的栅极叠层。所述有源区包括沟道区和源漏区；所述栅极叠层位于所述沟道区上方，包括栅极介质层和位于所述栅极介质层上方的栅极金属层。
所述第一绝缘层203b覆盖所述基板上的薄膜晶体管，即所述第一绝缘层203b覆盖所述有源区和栅极叠层。
所述多条栅极线20位于所述第一绝缘层203b上。所述多条栅极线20的一端连接输入的栅极信号，另一端通过多个第一通孔与所述多个薄膜晶体管的栅极叠层电连接。
所述多条栅极线20用于向基板中的多个薄膜晶体管的栅极提供栅极控制信号。在本实施例中，所述多条栅极线20为多条平行设置的导电金属，所述多条栅极线20的延伸方向为第一方向。所述第一方向与所述显示面板的一条侧边平行。所述多条栅极线20间隔设置，任意两条相邻的栅极线之间的距离相等。
所述第二绝缘层204覆盖所述栅极线20。本实施例中，所述第二绝缘层204为层间介质层。
所述多条数据线10位于所述第二绝缘层204上。所述多条数据线10的一端连接输入信号，另一端通过多个第二通孔与所述多个薄膜晶体管的源区和漏区电连接。
所述第三绝缘层覆盖所述数据线。在本实施例中，所述第三绝缘层为平坦化层205。
所述发光层包括多个像素点，每一个所述像素点包括阳极、像素定义层206、发光材料和阴极40。由于图4示出的结构图为电源线50所在的走线区的剖面图，因此所述阳极、发光材料和阴极没有在图4中示出。所述阳极位于所述第三绝缘层205上。所述像素定义层206位于所述第三绝缘层205上，并具有暴露出所述阳极的开口。所述发光材料位于所述开口中，与所述阳极电连接。参见图3，所述阴极40为覆盖所述像素定义层和发光材料的导电薄膜。
所述电源线50环绕所述导电薄膜，并通过多个第三通孔66与所述数据线10电连接。
所述数据线用于向所述基板中的多个薄膜晶体管的源区或漏区提供驱动电压。在本实施例中，所述多条数据线10为多条平行设置的导电金属，所述多条数据线10的延伸方向为第二方向，所述第二方向与所述第一方向垂直。所述多条数据线10间隔设置，任意两条相邻的数据线10之间的距离相等。
本实施例中，每一条所述数据线包括第一端和第二端，所述多条数据线的第一端连接输入数据信号，所述多条数据线的第二端通过沿第一方向延伸的第一连接线64实现电连接。所述第一连接线64位于所述电源线50正下方，两个第三通孔66分别位于所述第一连接线64的两端，用于实现所述第一连接线64和电源线50的电连接，为所述多条数据线提供电源电压。
为了进一步避免压降，所述多条数据线10还包括至少两条第二连接线62，所述第二连接线62位于所述多条数据线10的第一端两侧，所述第二连接线62的一端连接输入信号，所述第二连接线62的另一端位于所述电源线50的正下方，通过第三通孔66与所述电源线50电连接。所述第三通孔66设置的数目越多，电源线50上小号的压降相应的越小。在实际应用中，可以根据需要设置所述第三通孔66的数目。优选的，所述第三通孔66的数目等于所述数据线10的数目。
在本实施例中，由于电源线50与数据线10分层设置，电源线50可以不受数据线10的布局限制，其线宽可以数倍于数据线的线宽，从而有效的降低了电源线的阻抗，避免了压降现象带来的亮度不均。优选的，所述电源线50的宽度大于或等于所述数据线10的宽度的两倍。
相比于现有技术中将电源线与数据线设置在同一层的显示面板，本申请中的显示面板将电源线与阴极设置在同一层，采用环绕阴极的金属薄膜作为电源线，通过通孔实现电源线和数据线的电连接。分层设置后，电源线与栅极线之间间隔了至少三层绝缘层，极大的减小了电源线与栅极线之间发生短路的概率。同时，由于电源线与数据线分层设置，电源线可以不受数据线的布局限制，其线宽可以数倍于数据线的线宽，从而有效的降低了电源线的阻抗，避免了压降现象带来的亮度不均。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (10)

  1. 一种显示面板，其中，所述显示面板包括：
    基板，所述基板上具有多个薄膜晶体管；
    第一绝缘层，所述第一绝缘层覆盖所述基板上的薄膜晶体管；
    多条栅极线，所述多条栅极线位于所述第一绝缘层上，并通过多个第一通孔与所述多个薄膜晶体管的栅极电连接；
    第二绝缘层，所述第二绝缘层覆盖所述栅极线；
    多条数据线，所述多条数据线位于所述第二绝缘层上，并通过多个第二通孔与所述多个薄膜晶体管的源极和漏极电连接；
    第三绝缘层，所述第三绝缘层覆盖所述数据线；
    发光层，所述发光层包括多个像素点，所述多个像素点的阴极为一导电薄膜；
    电源线，所述电源线环绕所述导电薄膜，并通过多个第三通孔与所述数据线电连接。
  2. 根据权利要求1所述的显示面板，其中，每一个所述像素点包括：
    阳极，所述阳极位于所述第三绝缘层上；
    像素定义层，所述像素定义层位于所述第三绝缘层上，并具有暴露出所述阳极的开口；
    发光材料，所述发光材料位于所述开口中，与所述阳极电连接；
    阴极，所述阴极为覆盖所述像素定义层和发光材料的所述导电薄膜。
  3. 根据权利要求1所述的显示面板，其中，所述多条栅极线为多条平行设置的导电金属，所述多条栅极线的延伸方向为第一方向。
  4. 根据权利要求3所述的显示面板，其中，所述多条栅极线间隔设置，任意两条相邻的栅极线之间的距离相等。
  5. 根据权利要求3所述的显示面板，其中，所述多条数据线为多条平行设置的导电金属，所述多条数据线的延伸方向为第二方向，所述第二方向与所述第一方向垂直。
  6. 根据权利要求5所述的显示面板，其中，所述多条数据线间隔设置，任意两条相邻的数据线之间的距离相等。
  7. 根据权利要求5所述的显示面板，其中，每一条所述数据线包括第一端和第二端，所述多条数据线的第一端连接输入数据信号，所述多条数据线的第二端通过沿第一方向延伸的第一连接线实现电连接。
  8. 根据权利要求7所述的显示面板，其中，所述第一连接线位于所述电源线正下方，两个第三通孔分别位于所述第一连接线的两端，用于实现所述第一连接线和电源线的电连接。
  9. 根据权利要求7所述的显示面板，其中，所述多条数据线还包括至少两条第二连接线，所述第二连接线位于所述多条数据线的第一端两侧，所述第二连接线的一端连接输入信号，所述第二连接线的另一端位于所述电源线的正下方，通过第三通孔与所述电源线电连接。
  10. 根据权利要求1所述的显示面板，其中，所述电源线的宽度大于或等于所述数据线的宽度的两倍。
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