WO2021019333A1 - 撮像装置、その動作方法および電子機器 - Google Patents
撮像装置、その動作方法および電子機器 Download PDFInfo
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Definitions
- One aspect of the present invention relates to an imaging device.
- One aspect of the present invention is not limited to the above technical fields.
- the technical field of one aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method.
- one aspect of the invention relates to a process, machine, manufacture, or composition (composition of matter). Therefore, more specifically, the technical fields of one aspect of the present invention disclosed in the present specification include semiconductor devices, display devices, liquid crystal display devices, light emitting devices, lighting devices, power storage devices, storage devices, imaging devices, and the like.
- the operation method or the manufacturing method thereof can be given as an example.
- the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics.
- Transistors and semiconductor circuits are one aspect of semiconductor devices.
- the storage device, the display device, the image pickup device, and the electronic device may have a semiconductor device.
- Patent Document 1 discloses an image pickup apparatus having an oxide semiconductor and using a transistor having an extremely low off-current in a pixel circuit.
- Patent Document 2 discloses a technique for adding a calculation function to an image pickup apparatus.
- an image pickup device equipped with a solid-state image sensor such as a CMOS image sensor
- high-quality images can be easily taken due to technological development.
- the imaging device it is required that the imaging device be equipped with more intelligent functions.
- image data compression and image recognition are processed after digital data conversion of image data (analog data) is performed and extracted to the outside. If the processing can be performed in the imaging device, the cooperation with an external device becomes faster and the convenience of the user is improved. In addition, the load and power consumption of peripheral devices can be reduced. Further, if complicated data processing can be performed in the state of analog data, the time required for data conversion can be shortened.
- surveillance cameras and the like are always in operation and consume a large amount of power.
- the power consumption can be significantly reduced if the operation can be simplified when the event does not occur and the operation shifts to the normal imaging operation when the event occurs. Further, when no event has occurred, it is preferable that power gating can reduce power consumption.
- one aspect of the present invention is to provide an image pickup apparatus capable of performing image processing.
- Another object of the present invention is to provide an imaging device capable of detecting a change in a subject.
- one of the purposes is to provide an image pickup device with low power consumption.
- one of the purposes is to provide a small imaging device.
- one of the purposes is to provide a highly reliable imaging device.
- one of the purposes is to provide a new imaging device or the like.
- one of the purposes is to provide an operation method of the above-mentioned imaging device.
- one of the purposes is to provide a new semiconductor device or the like.
- One aspect of the present invention relates to an imaging device having a motion detection function and an image processing function and operating with low power consumption. Or, it relates to the operation method.
- One aspect of the present invention is an image pickup apparatus having a pixel, a first circuit, and a second circuit, and the first circuit has a function of supplying a first potential to the pixel.
- the pixel has a function of acquiring the first data and the second data, and the pixel has a function of generating a third data which is a difference between the first data and the second data.
- the second circuit has the third data output by the pixels and the fourth data. It is an image pickup apparatus having a function of generating the fifth data corresponding to the difference between.
- another aspect of the present invention is an image pickup apparatus having a pixel block, a first circuit, and a second circuit, and the pixel block has a plurality of pixels arranged in a matrix.
- the first circuit has a function of supplying the first potential to the pixel
- the pixel has a function of acquiring the first data and the second data
- the pixel has the function of acquiring the first data and the first data. It has a function of generating a third data which is a difference from the second data
- the pixel has a function of adding a potential based on the first potential to the third data to generate a fourth data.
- the fifth data corresponding to the difference between the sum of the third data output by the plurality of pixels of the pixel block and the sum of the fourth data output by the plurality of pixels of the pixel block. It is an image pickup apparatus having a function of generating.
- the pixels include a photoelectric conversion device, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, and the like.
- a photoelectric conversion device With a second capacitor, one electrode of the photoelectric conversion device is electrically connected to one of the source or drain of the first transistor, and the other of the source or drain of the first transistor is the second.
- one of the source or drain of the fourth transistor is electrically connected to one of the source or drain of the fifth transistor and the second
- the other electrode of the capacitor is electrically connected to one of the source or drain of the sixth transistor, the other of the source or drain of the fifth transistor is electrically connected to the second circuit, and the sixth The other of the source or drain of the capacitor can be electrically connected to the first circuit.
- a correlated double sampling circuit can be used for the second circuit.
- the transistor contained in the pixel has a metal oxide in the channel forming region, and the metal oxides are In, Zn, and M (M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, It is preferable to have one or more of Nd or Hf).
- another aspect of the present invention includes a first step of starting an imaging operation at a first frame rate, a second step of capturing and storing a reference image, and a third step of capturing a comparative image.
- the sixth step of comparing the feature amounts of the above is performed in the above order, and when it is determined that the first feature amount is detected from the second feature amount, the image pickup operation is performed by switching to the second frame rate.
- This is an operation method of the image pickup apparatus that returns to the third step when it is determined that the first feature amount is not detected from the second feature amount.
- the second frame rate is preferably larger than the first frame rate.
- the first frame rate is preferably 0.1 fps or more and 10 fps or less, and the second frame rate is preferably 15 fps or more and 240 fps or less.
- Power gating may be performed during the period during which the imaging operation is performed at the first frame rate.
- an image pickup apparatus capable of performing image processing.
- an imaging device capable of detecting a change in a subject.
- a low power consumption imaging device can be provided.
- a small imaging device can be provided.
- a highly reliable imaging device can be provided.
- a new imaging device or the like can be provided.
- a method of operating the image pickup apparatus can be provided.
- a new semiconductor device or the like can be provided.
- FIG. 1 is a block diagram illustrating an imaging device.
- FIG. 2 is a diagram illustrating the pixel block 200 and the circuit 201.
- 3A and 3B are diagrams for explaining the pixel 100.
- 4A and 4B are diagrams for explaining the pixel 100.
- FIG. 5 is a timing chart illustrating a normal imaging operation.
- FIG. 6 is a timing chart illustrating a motion detection operation (no difference) and a product-sum calculation operation.
- FIG. 7 is a timing chart for explaining the motion detection operation (with a difference).
- FIG. 8 is a diagram illustrating the circuit 304.
- FIG. 9 is a timing chart illustrating the operation of the circuit 304.
- FIG. 10 is a timing chart illustrating the operation of the circuit 304.
- FIG. 11A and 11B are diagrams for explaining the circuit 301 and the circuit 302.
- FIG. 12 is a diagram illustrating a memory cell.
- 13A and 13B are diagrams showing a configuration example of a neural network.
- FIG. 14 is a flowchart illustrating the operation of the image pickup apparatus.
- 15A and 15B are diagrams for explaining the operation of the image pickup apparatus.
- 16A to 16D are diagrams for explaining the configuration of pixels of the image pickup apparatus.
- 17A to 17C are diagrams for explaining the configuration of the photoelectric conversion device.
- FIG. 18 is a cross-sectional view illustrating the pixels.
- 19A to 19C are diagrams for explaining Si transistors.
- FIG. 20 is a cross-sectional view illustrating the pixels.
- FIG. 21 is a cross-sectional view illustrating the pixels.
- FIG. 22A to 22D are diagrams illustrating an OS transistor.
- FIG. 23 is a cross-sectional view illustrating the pixels.
- 24A1 to 24A3 and 24B1 to 24B3 are perspective views of a package and a module containing an imaging device.
- FIG. 25A is a block diagram illustrating a memory circuit.
- 25B to 25E are circuit diagrams illustrating memory cells.
- 26A and 26B are block diagrams showing a configuration example of a semiconductor device.
- 27A to 27D are diagrams for explaining an operation example of power management of the semiconductor device.
- FIG. 28 is a flowchart showing an operation example of power management of the semiconductor device.
- 29A and 29B are block diagrams showing a configuration example of a semiconductor device.
- FIG. 30 is a block diagram showing a configuration example of a processor core.
- FIG. 31 is a circuit diagram showing a configuration example of the storage circuit.
- FIG. 32 is a timing chart illustrating an operation example of the storage circuit.
- FIG. 33 is a circuit diagram showing a configuration example of a memory cell of the cache.
- FIG. 34 is a timing chart illustrating an operation example of the memory cell.
- 35A to 35F are diagrams for explaining an electronic device.
- the element may be composed of a plurality of elements as long as there is no functional inconvenience.
- a plurality of transistors operating as switches may be connected in series or in parallel.
- the capacitor may be divided and arranged at a plurality of positions.
- one conductor may have a plurality of functions such as wiring, electrodes, and terminals, and in the present specification, a plurality of names may be used for the same element. Further, even if the elements are shown to be directly connected on the circuit diagram, the elements may actually be connected via one or a plurality of conductors. , In the present specification, such a configuration is also included in the category of direct connection.
- the imaging device holds analog data (image data) acquired in the imaging operation in pixels, and can extract data obtained by multiplying the analog data by an arbitrary weighting coefficient.
- processing such as image recognition can be performed. Since a huge amount of image data can be held in pixels in the state of analog data, processing can be performed efficiently.
- the image pickup apparatus of one aspect of the present invention has a motion detection function.
- the imaging device can detect the difference between the reference frame image and the frame image to be compared, and can switch from the motion detection mode to the normal imaging mode when a significant difference is detected.
- power consumption can be suppressed by operating at a low frame rate.
- high-quality image data can be acquired by operating at a high frame rate.
- the image pickup apparatus of one aspect of the present invention can switch from the motion detection mode to the normal image pickup mode when a specific image is recognized by combining the image recognition function and the motion detection function described above. Therefore, for example, humans, animals, plants, etc. can be separated, and it is also possible to deal with abnormalities such as defective products, occurrence of changes over time, and natural disasters.
- FIG. 1 is a block diagram illustrating an imaging device according to an aspect of the present invention.
- the imaging device includes a pixel array 300, a circuit 201, a circuit 301, a circuit 302, a circuit 303, a circuit 304, and a circuit 305.
- the circuit 201 and the circuits 301 to 305 are not limited to a single circuit configuration, and may be composed of a plurality of circuits. Alternatively, any one of the above circuits may be integrated. Further, a circuit other than the above may be connected.
- the pixel array 300 has an imaging function and a calculation function.
- the circuits 201 and 301 have an arithmetic function.
- the circuit 302 has an arithmetic function or a data conversion function.
- the circuits 303 and 304 have a selection function.
- the circuit 305 has a function of supplying a potential for multiply-accumulate calculation to the pixels.
- a shift register, a decoder, or the like can be used for the circuit having the selection function.
- the circuits 301 and 302 may be provided externally.
- the pixel array 300 has a plurality of pixel blocks 200. As shown in FIG. 2, the pixel block 200 has a plurality of pixels 100 arranged in a matrix, and each pixel 100 is electrically connected to the circuit 201.
- the circuit 201 can also be provided in the pixel block 200.
- the number of pixels of the pixel block 200 is set to 2 ⁇ 2 as an example, but the number is not limited to this. For example, it can be 3 ⁇ 3, 4 ⁇ 4, or the like. Alternatively, the number of pixels in the horizontal direction and the number of pixels in the vertical direction may be different. Further, some pixels may be shared by adjacent pixel blocks.
- the pixel block 200 operates as a product-sum calculation circuit. Further, the circuit 201 electrically connected to the pixel block 200 has a function of extracting the product of the image data and the weighting coefficient from the pixel 100.
- the pixel 100 has a photoelectric conversion device 101, a transistor 102, a transistor 103, a capacitor 104, a transistor 105, a capacitor 106, a transistor 107, a transistor 108, and a transistor 109. Can be done.
- One electrode of the photoelectric conversion device 101 is electrically connected to one of the source and drain of the transistor 102.
- the other of the source or drain of the transistor 102 is electrically connected to one of the source or drain of the transistor 103 and one of the electrodes of the capacitor 104.
- the other electrode of the capacitor 104 is electrically connected to one of the source or drain of the transistor 105, one electrode of the capacitor 106, and the gate of the transistor 107.
- One of the source or drain of transistor 107 is electrically connected to one of the source or drain of transistor 108.
- the other electrode of the capacitor 106 is electrically connected to one of the source or drain of the transistor 109.
- the other electrode of the photoelectric conversion device 101 is electrically connected to the wiring 113.
- the other of the source or drain of the transistor 103 is electrically connected to the wiring 114.
- the other of the source or drain of the transistor 105 is electrically connected to the wiring 115.
- the other of the source or drain of the transistor 107 is electrically connected to a GND wiring or the like.
- the other of the source or drain of the transistor 108 is electrically connected to the wiring 112.
- the other of the source or drain of the transistor 109 is electrically connected to the wiring 111.
- the gate of the transistor 102 is electrically connected to the wiring 121.
- the gate of the transistor 103 is electrically connected to the wiring 122.
- the gate of the transistor 105 is electrically connected to the wiring 123.
- the gate of the transistor 108 is electrically connected to the wiring 125.
- the gate of the transistor 109 is electrically connected to the wiring 124.
- a node N1 is an electrical connection point (wiring) between the other of the source or drain of the transistor 102, the other of the source or drain of the transistor 103, and one electrode of the capacitor 104. Further, the other electrode of the capacitor 104, one of the source or drain of the transistor 105, one electrode of the capacitor 106, and the gate electrical connection point (wiring) of the transistor 107 are designated as a node N2.
- Wiring 113, 114, 115 can have a function as a power line.
- the wirings 114 and 115 can function as high-potential power lines, and the wiring 113 can function as low-potential power lines.
- Wiring 121, 122, 123, 124, 125 can function as a signal line for controlling the continuity of each transistor.
- the wiring 111 can function as a wiring that supplies a potential corresponding to a weighting coefficient to the pixel 100.
- the wiring 112 can function as a wiring that electrically connects the pixel 100 and the circuit 201.
- An amplifier circuit or a gain adjustment circuit may be electrically connected to the wiring 112.
- a photodiode can be used as the photoelectric conversion device 101. Regardless of the type of photodiode, a Si photodiode having silicon in the photoelectric conversion layer, an organic photodiode having an organic photoconductor in the photoelectric conversion layer, or the like can be used. If it is desired to increase the light detection sensitivity at low illuminance, it is preferable to use an avalanche photodiode.
- the transistor 102 can have a function of controlling the potential of the node N1.
- the transistor 103 can have a function of initializing the potential of the node N1.
- the transistor 105 can have a function of initializing the potential of the node N2.
- the transistor 107 can have a function of controlling the current flowing through the circuit 201 according to the potential of the node N2.
- the transistor 108 can have a function of selecting pixels.
- the transistor 109 can have a function of supplying a potential corresponding to a weighting coefficient to the node N2.
- the transistor 107 and the transistor 108 electrically connect one of the source or drain of the transistor 107 and one of the source or drain of the transistor 108, and wire the other of the source or drain of the transistor 107. It may be connected to 112 and the other of the source or drain of the transistor 108 may be electrically connected to the GND wiring or the like.
- the transistor 107 may be provided with a second gate, and either the source or the drain of the transistor 109 may be electrically connected to the second gate. Further, a capacitor 151 connecting the second gate and one electrode may be provided. The capacitor 151 functions as a holding capacitance. The capacitor 151 may not be provided.
- the connection direction of the photoelectric conversion device 101 may be reversed.
- the wirings 114 and 115 may function as low-potential power lines
- the wiring 113 may function as high-potential power lines.
- one of the source or drain of the transistor 107 and one of the source or drain of the transistor 108 are electrically connected, and the other of the source or drain of the transistor 107 is connected to the wiring 112.
- the other side of the source or drain of the transistor 108 may be electrically connected to the GND wiring or the like.
- a high voltage may be applied, and it is preferable to use a high voltage transistor for the transistor connected to the photoelectric conversion device 101.
- a high voltage transistor for example, a transistor using a metal oxide in the channel forming region (hereinafter, OS transistor) or the like can be used. Specifically, it is preferable to apply an OS transistor to the transistor 102.
- the OS transistor also has a characteristic that the off-current is extremely low.
- OS transistors for the transistors 102, 103, 105, and 109 the period during which electric charges can be retained at the nodes N1 and N2 can be made extremely long. Therefore, it is possible to apply the global shutter method in which charge accumulation operation is performed simultaneously in all pixels without complicating the circuit configuration and operation method. Further, while holding the image data in the node N2, it is possible to perform a plurality of operations using the image data.
- the transistor 107 may be desired to have excellent amplification characteristics. Further, since the transistor 108 may be repeatedly turned on and off, it may be preferable to use a transistor having high mobility capable of high-speed operation. Therefore, transistors using silicon in the channel forming region (hereinafter referred to as Si transistors) may be applied to the transistors 107 and 108.
- Si transistors transistors using silicon in the channel forming region
- an OS transistor and a Si transistor may be arbitrarily combined and applied. Moreover, all the transistors may be OS transistors. Alternatively, all the transistors may be Si transistors. Examples of the Si transistor include a transistor having amorphous silicon, a transistor having crystalline silicon (microcrystalline silicon, low temperature polysilicon, single crystal silicon), and the like.
- the potential of the node N2 in the pixel 100 is a potential in which the fluctuation amount (image data) of the potential of the node N1 is capacitively coupled to the reset potential supplied from the wiring 115 and a potential corresponding to the weighting coefficient supplied from the wiring 111. It is determined by the capacitive coupling of. That is, the gate of the transistor 107 has a potential obtained by adding an arbitrary weighting coefficient to the image data, and a current including a term of the product of the image data and the arbitrary weighting coefficient flows through the transistor 107.
- each pixel 100 is electrically connected to each other by wiring 112.
- the circuit 201 can perform calculations using the sum of the currents flowing through the transistors 107 of each pixel 100.
- the circuit 201 has a capacitor 202, a transistor 203, a transistor 204, a transistor 205, a transistor 206, and a resistor 207.
- One electrode of the capacitor 202 is electrically connected to one of the source or drain of the transistor 203.
- One of the source and drain of transistor 203 is electrically connected to the gate of transistor 204.
- One of the source or drain of transistor 204 is electrically connected to one of the source or drain of transistor 205.
- One of the source or drain of transistor 205 is electrically connected to one of the source or drain of transistor 206.
- One electrode of the resistor 207 is electrically connected to the other electrode of the capacitor 202.
- the other electrode of the capacitor 202 is electrically connected to the wiring 112.
- the other of the source or drain of transistor 203 is electrically connected to wiring 218.
- the other of the source or drain of transistor 204 is electrically connected to wire 219.
- the other of the source or drain of the transistor 205 is electrically connected to a reference power line such as GND wiring.
- the other of the source or drain of the transistor 206 is electrically connected to the wiring 212.
- the other electrode of resistor 207 is electrically connected to wiring 217.
- Wiring 217, 218, 219 can have a function as a power line.
- the wiring 218 can have a function as a wiring for supplying a reset potential for reading.
- Wiring 217 and 219 can function as high potential power lines.
- the wirings 213, 215, and 216 can function as signal lines for controlling the continuity of each transistor.
- the wiring 212 is an output line and can be electrically connected to, for example, the circuit 301 shown in FIG.
- the transistor 203 can have a function of resetting the potential of the wiring 211 to the potential of the wiring 218.
- the transistors 204 and 205 can have a function as a source follower circuit.
- the transistor 206 can have a function of controlling reading.
- the circuit 201 has a function as a correlated double sampling circuit (CDS circuit), and can be replaced with a circuit having another configuration having the function.
- CDS circuit correlated double sampling circuit
- an offset component other than the product of the image data (X) and the weighting coefficient (W) is removed, and the target WX is extracted.
- the WX can be calculated by using the data with and without imaging for the same pixel and the data when weights are added to each of them.
- the total current (I p ) flowing through the pixel 100 when imaging is k ⁇ (X-V th ) 2
- the total current (I p ) flowing through the pixel 100 when weighted is k ⁇ (W + X-V th).
- the total current (I ref ) flowing through the pixel 100 without imaging is k ⁇ (0-V th ) 2
- the total current (I ref ) flowing through the pixel 100 when weighted is k ⁇ (W-).
- V th ) 2 is a constant and Vth is the threshold voltage of the transistor 107.
- the difference (data A) between the data with imaging and the data obtained by weighting the data is calculated.
- k ⁇ ((X-V th ) 2- (W + X-V th ) 2 ) k ⁇ (-W 2 -2W ⁇ X + 2W ⁇ V th ).
- data A and data B can be read out.
- the difference calculation between the data A and the data B can be performed by, for example, the circuit 301.
- the pixel 100 shown in FIGS. 3A, 3B and 4A, 4B has a normal imaging function and a motion detection function. Further, the pixel 100 has a part of the product-sum calculation function.
- ⁇ Normal imaging mode> First, a normal imaging mode will be described using the timing chart shown in FIG. Since the product-sum calculation is not performed in the normal imaging mode, the potential of the wiring 111 is always "L”, the potential of the wiring 124 is always "H”, and the potential of the other electrode of the capacitor 106 is fixed. preferable. Further, here, the operation of the pixel 100 having the configuration of FIG. 3A or FIG. 3B will be described.
- the transistors 102 and 103 are electrically connected, and the potential of the node N1 is the reset potential ( (Potential of wiring 114) "V RES1 ". Further, the transistor 105 conducts, and the potential of the node N2 becomes the reset potential (potential of the wiring 115) “V RES2 ”. In addition, “V RES1 " and “V RES2 " may have the same potential.
- the transistor 203 is conducted in the circuit 201, and the potential of the wiring 211 becomes the potential "Vr" of the wiring 218. That is, the output potential of the pixel 100 in the reset state is initialized to the potential “Vr”.
- the potential of the wiring 121 is "H”
- the potential of the wiring 122 is “L”
- the potential of the wiring 123 is “L”
- the potential of the wiring 125 is “L”
- the potential of the wiring 216 is “L” at time T2.
- the transistors 103, 105, and 108 become non-conducting, and the potential of the node N1 changes to "V RES1 - VA " due to the operation of the photoelectric conversion device 101.
- the potential of the node N2 also changes to "V RES2- V B " due to the capacitive coupling of the capacitor 104. If the capacitance of the capacitor 104 is sufficiently larger than the capacitance of the node N2, VA and V B have almost the same value. Further, the transistor 203 becomes non-conducting, and the potential of the wiring 221 is held at "Vr".
- the transistor 108 conducts and the wiring 112 to the transistor 107 A current corresponding to the potential of the node N2 flows through.
- the potential of the other electrode of the capacitor 202 changes according to the current flowing through the wiring 112, and the change Y is added to the potential “Vr” of the wiring 211 by capacitive coupling.
- Vr + Y the potential of the wiring 211 becomes "Vr + Y".
- Vr 0, Y is the difference between the image data and the data (noise) at the time of reset. That is, it is possible to acquire image data from which noise components have been removed.
- the image data can be output to the wiring 212 by the source follower operation of the transistors 204.
- FIG. 6 shows a case where there is no change between the reference image and the comparison image.
- the period from time T1 to T7 is a period for determining the potential of the node N2. Since the weight (W) is later added to the node N2 by the capacitive coupling of the capacitor 106, the potential of the other electrode of the capacitor 106 is set to the potential corresponding to the weight coefficient 0 at least during this period. Therefore, during the period, the potential of the wiring 111 is set to the potential corresponding to the weighting coefficient 0 (for example, 0V), and the potential of the wiring 124 is set to “H”.
- the potential of the node N1 becomes the same potential as the reference image held before the time T5. Further, the potential of the node N2 is a reset potential, indicating that there is no difference between the reference image and the comparison image.
- the potential of the node N1 is "V RES1 -V C", and the potential of the node N2 "V RES2 + V B ⁇ V D ”.
- V C is a value different from the "V A”
- V D is a value different from the "V B”. That is, the potential of the node N2 is a potential different from the reset potential, indicating that there is a difference between the reference image and the comparison image.
- the transistor 203 is conducted in the circuit 201, and the potential of the wiring 211 becomes the potential "Vr" of the wiring 218. That is, the output potential of the pixel 100 in the reset state is initialized to "Vr".
- the operation up to the period T7 corresponds to the acquisition of data with imaging, and the data is represented as the potential “Vr” of the wiring 211.
- the potential of the wiring 124 is “L”
- the potential of the wiring 125 is “H”
- the potential of the wiring 213 is “H”
- the potential of the wiring 215 is "H” at time T10
- the potential of the other electrode of the capacitor 106 and The potential of the node N2 is maintained, the transistor 108 conducts, and a current corresponding to the potential “X + W” of the node N2 flows from the wiring 112 to the transistor 107.
- the potential of the other electrode of the capacitor 202 changes according to the current flowing through the wiring 112, and the change Z is added to the potential Vr of the wiring 211 by capacitive coupling. Therefore, the potential of the wiring 211 becomes "Vr + Z".
- Vr 0, Z is the difference itself, and the data A has been calculated.
- the circuit 201 outputs a signal potential according to the data A by the source follower operation. Can be done.
- the difference (data B) between the data without imaging and the data obtained by weighting the data can be calculated. Since there is no imaging, the operation does not have an accumulation period. For example, when the wiring 121 is “H”, the node N1 can be maintained at the reset potential by setting the wiring 122 to “H” as well. Further, the operation of the times T5 to T8 may be omitted, and the node N1 and the node N2 may be reset potentials before the time T8.
- the data A and the data B output from the circuit 201 by the above operation are input to the circuit 301.
- an operation for taking the difference between the data A and the data B is performed, and an unnecessary offset component other than the product of the image data (potential X) and the weighting coefficient (potential W) can be removed.
- the circuit 301 may be configured to have an arithmetic circuit such as the circuit 201, or may be configured to take a difference by using a memory circuit (also referred to as a storage circuit) and software processing.
- the weighting coefficient can be output from the circuit 305 shown in FIG. 1 to the wiring 111, and it is preferable to rewrite the weighting coefficient at least once within the frame period.
- a decoder can be used as the circuit 305. Further, the circuit 305 may have a D / A converter and SRAM.
- a signal can be output from the circuit 303 to the wiring 112 that selects the pixel 100 for inputting the weighting coefficient.
- a decoder or shift register can be used in the circuit 303.
- a signal can be output from the circuit 304 to the wiring 125 or the like connected to the gate of the transistor 108 of the pixel 100.
- a decoder or shift register can be used in the circuit 304.
- the processing of the captured image data has been described, but in the image pickup apparatus of one aspect of the present invention, the image data can be taken out without processing.
- the circuit 304 for selecting the pixel 100 is provided with a function of switching the number of rows to be selected.
- FIG. 8 is an example of a circuit that can be used in the circuit 304.
- the circuit is a shift register circuit, and a plurality of logic circuits (SR) are electrically connected.
- Signal lines such as wiring RES, wiring VSS_RDRS, wiring RPWC_SE [0: 3], wiring RCLK [0: 3], and wiring RSP are connected to each logic circuit (SR), and appropriate signals are connected to each signal line.
- the selected signal potential can be sequentially output from the logic circuit (SR).
- the circuit 170 is electrically connected to the logic circuit (SR).
- a plurality of transistors are provided in the circuit 170, signal lines such as wiring SE_SW [0: 2] and wiring SX [0: 2] are connected, and an appropriate signal potential is input to each signal line to connect the transistors. Continuity is controlled. By controlling the circuit 170, the number of rows of selected pixels can be switched.
- One of the source or drain of one transistor is electrically connected to the output terminal of one logic circuit (SR), and the wiring SE is connected to the other of the source or drain of the transistor.
- the wiring SE is electrically connected to the wiring 122 that selects the pixel 100.
- the signal potential supplied from the wiring SE_SW [0] can be input to the gate of the transistor connected to the wiring SE [0].
- the signal potential supplied from the wiring SE_SW [1] can be input to the gate of the transistor connected to the wiring SE [1].
- the signal potential supplied from the wiring SE_SW [2] can be input to the gate of the transistor connected to the wiring SE [2].
- a signal potential supplied from any of the wiring SE_SW [0: 2] can be input to the gate of the transistor connected after the wiring SE [3] in the same order.
- the adjacent wiring SEs are electrically connected via one transistor, and the wiring SE [0] is electrically connected to the power supply line (VSS) via one transistor.
- the signal potential supplied from the wiring SX [0] can be input to the gate of the transistor that electrically connects the power line (VSS) and the wiring SE [0].
- the signal potential supplied from the wiring SX [1] can be input to the gate of the transistor that electrically connects the wiring SE [0] and the wiring SE [1].
- the signal potential supplied from the wiring SX [2] can be input to the gate of the transistor that electrically connects the wiring SE [1] and the wiring SE [2]. Any of the signal potentials supplied from the wiring SX [0: 2] can be input to the gate of the transistor that electrically connects the wiring SEs thereafter in the same order.
- FIG. 9 is a timing chart illustrating an operation of simultaneously selecting a plurality of rows (3 rows) by the circuit shown in FIG. (0) to (161) correspond to the timing at which the logic circuit (SR) outputs the signal potential to the wiring SE.
- the potential of the wiring SX [0] is “L”
- the potential of the wiring SX [1] is “H”
- the potential of the wiring SX [2] is "H”
- the potential of the wiring SE_SW [0] is.
- three rows can be selected at the same time, and for example, a product-sum calculation of pixels in three rows and three columns can be performed.
- the potential of the wiring SX [0] is “H”
- the potential of the wiring SX [1] is “L”
- the potential of the wiring SX [2] is "H”
- the potential of the wiring SE_SW [0] is.
- the continuity of each transistor is controlled, and wiring SE [0] becomes “L”
- wiring SE. “H” is output to [1]
- “H” is output to wiring SE [2]
- “H” is output to wiring SE [3].
- “L” is output to the other wiring SEs.
- FIG. 10 is a timing chart illustrating an operation of selecting one row by the circuit shown in FIG.
- FIG. 11A is a diagram illustrating a circuit 301 and a circuit 302 connected to the circuit 201.
- the product-sum calculation result data output from the circuit 201 is sequentially input to the circuit 301.
- the circuit 301 may have various calculation functions in addition to the above-mentioned function of calculating the difference between the data A and the data B.
- the circuit 301 can have the same configuration as the circuit 201.
- the function of the circuit 301 may be replaced by software processing.
- the circuit 301 may have a circuit for calculating the activation function.
- a comparator circuit can be used for the circuit.
- the comparator circuit outputs the result of comparing the input data with the set threshold value as binary data. That is, the pixel block 200 and the circuit 301 can act as a part of the neural network.
- the circuit 301 may have an A / D converter.
- the circuit 301 can convert the analog data into digital data.
- the data output by the pixel block 200 corresponds to the image data of a plurality of bits, but if it can be binarized by the circuit 301, it can be said that the image data is compressed.
- the data output from the circuit 301 is sequentially input to the circuit 302.
- the circuit 302 can be configured to include, for example, a latch circuit and a shift register. With this configuration, parallel serial conversion can be performed, and the data input in parallel can be output to the wiring 311 as serial data.
- the connection destination of the wiring 311 is not limited. For example, it can be connected to a neural network, a storage device, a communication device, or the like.
- the circuit 302 may have a neural network.
- the neural network has memory cells arranged in a matrix, and each memory cell holds a weighting coefficient.
- the data output from the circuit 301 is input to each of the memory cells 320, and the product-sum operation can be performed.
- the number of memory cells shown in FIG. 11B is an example and is not limited.
- the neural network shown in FIG. 11B has memory cells 320 and reference memory cells 325 installed in a matrix, a circuit 330, a circuit 350, a circuit 360, and a circuit 370.
- FIG. 12 shows an example of the memory cell 320 and the reference memory cell 325.
- Reference memory cells 325 are provided in an arbitrary row.
- the memory cell 320 and the reference memory cell 325 have a similar configuration and include a transistor 161 and a transistor 162 and a capacitor 163.
- One of the source or drain of transistor 161 is electrically connected to the gate of transistor 162.
- the gate of transistor 162 is electrically connected to one electrode of capacitor 163.
- a node NM is a point where one of the source and drain of the transistor 161, the gate of the transistor 162, and one electrode of the capacitor 163 are connected.
- the gate of the transistor 161 is electrically connected to the wiring WL.
- the other electrode of the capacitor 163 is electrically connected to the wiring RW.
- One of the source and drain of the transistor 162 is electrically connected to a reference potential wiring such as a GND wiring.
- the other of the source or drain of the transistor 161 is electrically connected to the wiring WD.
- the other of the source or drain of the transistor 162 is electrically connected to the wiring BL.
- the other of the source or drain of the transistor 161 is electrically connected to the wiring WDref.
- the other of the source or drain of the transistor 162 is electrically connected to the wiring BLref.
- the wiring WL is electrically connected to the circuit 330.
- a decoder, a shift register, or the like can be used for the circuit 330.
- the wiring RW is electrically connected to the circuit 301.
- Binary data output from the circuit 301 is written to each memory cell.
- a sequential circuit such as a shift register may be provided between the circuit 301 and each memory cell.
- the wiring WD and the wiring WDref are electrically connected to the circuit 350.
- a decoder, a shift register, or the like can be used for the circuit 350.
- the circuit 350 may have a D / A converter and SRAM.
- the circuit 350 can output the weighting factor written to the node NM.
- the wiring BL and the wiring BLref are electrically connected to the circuit 360.
- the circuit 360 can have the same configuration as the circuit 201.
- the circuit 360 can obtain a signal obtained by removing the offset component from the product-sum calculation result.
- the circuit 360 is electrically connected to the circuit 370.
- the circuit 370 can also be rephrased as an activation function circuit.
- the activation function circuit has a function of performing an operation for converting a signal input from the circuit 360 according to a predefined activation function.
- As the activation function for example, a sigmoid function, a tanh function, a softmax function, a ReLU function, a threshold function, and the like can be used.
- the signal converted by the activation function circuit is output to the outside as output data.
- the neural network NN can be composed of an input layer IL, an output layer OL, and an intermediate layer (hidden layer) HL.
- the input layer IL, the output layer OL, and the intermediate layer HL each have one or more neurons (units).
- the intermediate layer HL may be one layer or two or more layers.
- a neural network having two or more intermediate layers HL can also be called a DNN (deep neural network).
- learning using a deep neural network can also be called deep learning.
- Input data is input to each neuron in the input layer IL.
- the output signals of the neurons in the anterior layer or the posterior layer are input to each neuron in the intermediate layer HL.
- the output signal of the presheaf neuron is input to each neuron in the output layer OL.
- each neuron may be connected to all neurons in the anterior-posterior layer (fully connected), or may be connected to some neurons.
- FIG. 13B shows an example of calculation by neurons.
- two neurons in the presheaf layer that output a signal to the neuron N are shown.
- the output x 1 of the presheaf neuron and the output x 2 of the presheaf neuron are input to the neuron N.
- the sum of the multiplication result of the output x 1 and the weight w 1 (x 1 w 1 ) and the multiplication result of the output x 2 and the weight w 2 (x 2 w 2 ) is x 1 w 1 + x 2 w 2.
- the operation by the neuron includes the operation of adding the product of the output of the neuron in the previous layer and the weight, that is, the product-sum operation (x 1 w 1 + x 2 w 2 above ).
- This product-sum operation may be performed by software using a program or by hardware.
- the product-sum calculation is performed using an analog circuit as hardware.
- an analog circuit is used for the product-sum calculation circuit, the processing speed can be improved and the power consumption can be reduced by reducing the circuit scale of the product-sum calculation circuit or reducing the number of times the memory is accessed.
- the product-sum calculation circuit preferably has an OS transistor. Since the OS transistor has an extremely small off-current, it is suitable as a transistor constituting an analog memory of a product-sum calculation circuit.
- the product-sum calculation circuit may be configured by using both the Si transistor and the OS transistor.
- the imaging operation is selected (S1).
- the process proceeds to the setting of the normal imaging mode (S11).
- the normal imaging mode is a high-speed moving image imaging mode, and for example, the frame rate is set to 15 fps to 240 fps, preferably 30 fps to 120 fps, and typically 60 fps. Subsequently, continuous operation or timer operation is performed under the set conditions (S12). The imaging operation ends after the timer operates or at the discretion of the user.
- the motion detection mode is a low-speed moving image imaging mode, and for example, the frame rate is set to 0.1 fps or more and 10 fps or less, typically 1 fps. Power consumption can be reduced by setting a low frame rate. If the imaging target changes and the period until it returns to the original state is short, a relatively high frame rate may be set.
- a reference image is taken (S3).
- the operation of capturing the reference image corresponds to the operation of times T1 to T4 in the timing chart of FIG.
- the feature amount B extraction operation 1 is performed (S5).
- This operation corresponds to the acquisition of data A by the operation at times T8 to T11 in the timing chart of FIG. 6 and the acquisition of data B in the operation without imaging.
- the weight added to the image data here corresponds to the convolutional filter of the convolutional neural network (CNN).
- the feature amount B extraction operation 2 is performed (S6).
- the operation can be performed, for example, in the circuit 301 or an external circuit, and performs the differential calculation between the data A and the data B. Further, a pooling process may be performed. By acquiring the difference between the data A and the data B, it is possible to remove an offset component other than the product of the image data (X) and the weighting coefficient (W). That is, the feature amount B is a feature amount extracted from the captured image data.
- the feature quantities A and B comparison operation is performed (S7, S8).
- the operation can be performed by, for example, an external circuit.
- the feature amount A as a reference is set at any timing before this (S0).
- As the feature amount A for example, a feature amount such as a shape or a pattern of the target object can be used. Therefore, it is preferable to select the convolution filter according to the feature amount A.
- the process proceeds to S11 and imaging is performed in the normal imaging mode. If the feature amount A is not detected, the process returns to S3 or S4 through counter operations (S9, S10) and the like.
- the threshold value for whether or not the feature amount A is detected can be arbitrarily set.
- the reference image is held in the pixel, so there is no problem in returning to S4 in the short term, but if the illuminance change of natural light or the change with time appears in the subject, the feature amount May affect the comparison behavior of. Therefore, it is preferable to use a counter or the like to return to S3 when the set value reaches 1 minute, 10 minutes, 1 hour, 6 hours, or the like in terms of time, and take a reference image again. Alternatively, it may be controlled by time using a timer or the like.
- the feature amount A may be plural. In this case, it is possible to set conditions such as whether or not all of the feature amount A is detected and whether or not a part of the feature amount A is detected. Alternatively, even if the feature amount A is not detected, the operation of proceeding to S11 may be performed when there is a change between the reference image and the comparison image.
- 15A and 15B show diagrams for explaining the specific operation of the motion detection mode.
- FIG. 15A is a diagram illustrating an operation when the feature amount A is detected, and illustrates a change in the frame image on the time axis.
- the subject is a landscape
- the feature amount A is data including the features of a bird.
- a low frame rate is set, and a reference image is captured in the first frame (corresponding to S3).
- the landscape image is shown by a broken line, but in reality, the reference image is held in the pixels and the image data is not output from the imaging device.
- the determination operation (corresponding to S8) of the feature amount A detection from the imaging of the comparative image and the intra-pixel difference calculation (corresponding to S4) is performed for each frame.
- the output image data is the difference data between the reference image and the comparison image, and the image data without change corresponds to all white or all black. If there is no change in the landscape, the same frame as the n-x frame is repeated.
- the mode is switched to the normal imaging mode having a high frame rate (S11). The above is the operation when the feature amount A is detected.
- FIG. 15B is a diagram illustrating an operation when the feature amount A is not detected. If imaging is started under the same conditions as in FIG. 15A and the feature amount A (bird) is not captured even if a change appears in the landscape, the motion detection mode is continued and the normal imaging mode is not switched.
- FIG. 15B shows a case where the airship is imaged in the nth frame, but since it is determined that the airship does not match the feature amount A, the motion detection mode is continued even after the n + 1th frame.
- the presence or absence of detection can be determined by limiting the object. Therefore, when the imaging device is used as a security camera or the like, for example, dogs, cats, plants, etc. are not targeted for mode switching, and only humans can be targeted for mode switching.
- FIG. 16A is a diagram showing an example of the pixel structure of the image pickup apparatus, and can be a laminated structure of layers 561 and 563.
- Layer 561 has a photoelectric conversion device 101.
- the photoelectric conversion device 101 can have a layer 565a and a layer 565b as shown in FIG. 17A. In some cases, the layer may be referred to as an area.
- the photoelectric conversion device 101 shown in FIG. 17A is a pn junction type photodiode.
- a p-type semiconductor can be used for the layer 565a and an n-type semiconductor can be used for the layer 565b.
- an n-type semiconductor may be used for the layer 565a and a p-type semiconductor may be used for the layer 565b.
- the pn junction type photodiode can be typically formed by using single crystal silicon.
- the photoelectric conversion device 101 included in the layer 561 may be a laminate of the layer 566a, the layer 566b, the layer 566c, and the layer 566d.
- the photoelectric conversion device 101 shown in FIG. 17B is an example of an avalanche photodiode, in which layers 566a and 566d correspond to electrodes, and layers 566b and 566c correspond to photoelectric conversion units.
- the layer 566a is preferably a low resistance metal layer or the like.
- a low resistance metal layer or the like aluminum, titanium, tungsten, tantalum, silver or a laminate thereof can be used.
- the layer 566d it is preferable to use a conductive layer having high translucency with respect to visible light.
- a conductive layer having high translucency with respect to visible light For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, graphene and the like can be used. It should be noted that the layer 566d may be omitted.
- the layers 566b and 566c of the photoelectric conversion unit can be configured as a pn junction type photodiode using, for example, a selenium-based material as a photoelectric conversion layer. It is preferable that a selenium-based material, which is a p-type semiconductor, is used as the layer 566b, and gallium oxide, which is an n-type semiconductor, is used as the layer 566c.
- a photoelectric conversion device using a selenium-based material has a characteristic of high external quantum efficiency with respect to visible light.
- the amplification of electrons with respect to the amount of incident light can be increased by utilizing the avalanche multiplication.
- the selenium-based material has a high light absorption coefficient, it has a production advantage such that the photoelectric conversion layer can be formed of a thin film.
- a thin film of a selenium-based material can be formed by a vacuum deposition method, a sputtering method, or the like.
- selenium-based material examples include crystalline selenium such as single crystal selenium and polycrystalline selenium, amorphous selenium, copper, indium, and selenium compounds (CIS), or copper, indium, gallium, and selenium compounds (CIGS). Can be used.
- crystalline selenium such as single crystal selenium and polycrystalline selenium, amorphous selenium, copper, indium, and selenium compounds (CIS), or copper, indium, gallium, and selenium compounds (CIGS).
- the n-type semiconductor is preferably formed of a material having a wide bandgap and translucency with respect to visible light.
- a material having a wide bandgap and translucency with respect to visible light For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or an oxide in which they are mixed can be used.
- these materials also have a function as a hole injection blocking layer, and can reduce the dark current.
- the photoelectric conversion device 101 included in the layer 561 may be a stack of the layer 567a, the layer 567b, the layer 567c, the layer 567d, and the layer 567e.
- the photoelectric conversion device 101 shown in FIG. 17C is an example of an organic photoconductor, layer 567a is a lower electrode, layer 567e is a translucent upper electrode, and layers 567b, 567c, and 567d correspond to a photoelectric conversion unit. ..
- One of the layers 567b and 567d of the photoelectric conversion unit can be a hole transport layer and the other can be an electron transport layer. Further, the layer 567c can be a photoelectric conversion layer.
- the hole transport layer for example, molybdenum oxide or the like can be used.
- the electron transport layer for example, fullerenes such as C 60 and C 70 , or derivatives thereof and the like can be used.
- a mixed layer (bulk heterojunction structure) of an n-type organic semiconductor and a p-type organic semiconductor can be used.
- a silicon substrate can be used as the layer 563 shown in FIG. 16A.
- the silicon substrate has a Si transistor and the like.
- the Si transistor can be used to form a circuit for driving the pixel circuit, an image signal readout circuit, an image processing circuit, a neural network, a communication circuit, and the like.
- a storage circuit such as a DRAM (Dynamic Random Access Memory), a CPU (Central Processing Unit), an MCU (Micro Controller Unit), or the like may be formed.
- the above circuit excluding the pixel circuit is referred to as a functional circuit.
- a part or all of them may be provided on the layer 563. it can.
- the layer 563 may be a stack of a plurality of layers as shown in FIG. 16B. In FIG. 16B, three layers 563a, 563b, and 563c are illustrated, but two layers may be used. Alternatively, the layer 563 may be a stack of four or more layers. These layers can be laminated by using, for example, a bonding step. With this configuration, the pixel circuit and the functional circuit can be dispersed in a plurality of layers, and the pixel circuit and the functional circuit can be provided in an overlapping manner, so that a compact and highly functional imaging device can be manufactured.
- the pixel may have a laminated structure of layers 561, 562, and 563.
- Layer 562 can have an OS transistor.
- One or more of the above-mentioned functional circuits may be formed of OS transistors.
- one or more functional circuits may be formed by using the Si transistor of layer 563 and the OS transistor of layer 562.
- a normally-off CPU (also referred to as "Noff-CPU") can be realized by using an OS transistor and a Si transistor.
- the Nonf-CPU is an integrated circuit including a normally-off type transistor that is in a non-conducting state (also referred to as an off state) even when the gate voltage is 0V.
- the Noff-CPU can stop the power supply to the unnecessary circuit in the Noff-CPU and put the circuit in the standby state. No power is consumed in the circuit where the power supply is stopped and the circuit is in the standby state. Therefore, the Nonf-CPU can minimize the amount of power used. Further, the Nonf-CPU can retain information necessary for operation such as setting conditions for a long period of time even if the power supply is stopped. To return from the standby state, it is only necessary to restart the power supply to the circuit, and it is not necessary to rewrite the setting conditions and the like. That is, it is possible to return from the standby state at high speed. In this way, the Nonf-CPU can reduce the power consumption without significantly reducing the operating speed.
- the layer 562 may be a stack of a plurality of layers as shown in FIG. 16D.
- FIG. 16D two layers of layers 562a and 563b are illustrated, but three or more layers may be laminated. These layers can be formed, for example, to stack on layer 563.
- the layer formed on the layer 563 and the layer formed on the layer 561 may be bonded together.
- a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used.
- a typical example is an oxide semiconductor containing indium, and for example, CAAC-OS or CAC-OS described later can be used.
- CAAC-OS is suitable for transistors and the like in which the atoms constituting the crystal are stable and reliability is important. Further, since CAC-OS exhibits high mobility characteristics, it is suitable for a transistor or the like that performs high-speed driving.
- the OS transistor Since the OS transistor has a large energy gap in the semiconductor layer, it exhibits an extremely low off-current characteristic of several yA / ⁇ m (current value per 1 ⁇ m of channel width). Further, the OS transistor has features different from those of the Si transistor such as impact ionization, avalanche breakdown, and short channel effect, and can form a circuit having high withstand voltage and high reliability. In addition, variations in electrical characteristics due to crystallinity non-uniformity, which is a problem with Si transistors, are unlikely to occur with OS transistors.
- the semiconductor layer of the OS transistor includes, for example, indium, zinc and M (one or more selected from metals such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium or hafnium). It can be a film represented by an In—M—Zn-based oxide containing.
- the In—M—Zn-based oxide can be typically formed by a sputtering method. Alternatively, it may be formed by using an ALD (Atomic layer deposition) method.
- the atomic number ratio of the metal element of the sputtering target used for forming the In—M—Zn-based oxide by the sputtering method preferably satisfies In ⁇ M and Zn ⁇ M.
- the atomic number ratio of the semiconductor layer to be formed includes a variation of plus or minus 40% of the atomic number ratio of the metal element contained in the sputtering target.
- the semiconductor layer an oxide semiconductor having a low carrier density is used.
- the semiconductor layer has a carrier density of 1 ⁇ 10 17 / cm 3 or less, preferably 1 ⁇ 10 15 / cm 3 or less, more preferably 1 ⁇ 10 13 / cm 3 or less, and more preferably 1 ⁇ 10 11 / cm. 3 or less, more preferably less than 1 ⁇ 10 10 / cm 3, it is possible to use an oxide semiconductor of 1 ⁇ 10 -9 / cm 3 or more carrier density.
- Such oxide semiconductors are referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. It can be said that the oxide semiconductor is an oxide semiconductor having a low defect level density and stable characteristics.
- the present invention is not limited to these, and a transistor having an appropriate composition may be used according to the required semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the transistor. Further, in order to obtain the required semiconductor characteristics of the transistor, it is preferable that the carrier density, impurity concentration, defect density, atomic number ratio of metal element and oxygen, interatomic distance, density, etc. of the semiconductor layer are appropriate. ..
- the concentration of silicon or carbon in the semiconductor layer is set to 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
- the concentration of alkali metal or alkaline metalloid (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
- the nitrogen concentration in the semiconductor layer is preferably 5 ⁇ 10 18 atoms / cm 3 or less.
- the oxide semiconductor constituting the semiconductor layer when hydrogen is contained in the oxide semiconductor constituting the semiconductor layer, it reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency in the oxide semiconductor. If the channel formation region in the oxide semiconductor contains oxygen deficiency, the transistor may have a normally-on characteristic. Furthermore, a defect containing hydrogen in an oxygen deficiency may function as a donor and generate electrons as carriers. In addition, a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have a normally-on characteristic.
- Defects containing hydrogen in oxygen deficiencies can function as donors for oxide semiconductors. However, it is difficult to quantitatively evaluate the defect. Therefore, in oxide semiconductors, the carrier concentration may be evaluated instead of the donor concentration. Therefore, in the present specification and the like, as a parameter of the oxide semiconductor, a carrier concentration assuming a state in which an electric field is not applied may be used instead of the donor concentration. That is, the "carrier concentration" described in the present specification and the like may be paraphrased as the "donor concentration".
- the hydrogen concentration obtained by secondary ion mass spectrometry is less than 1 ⁇ 10 20 atoms / cm 3 , preferably 1 ⁇ 10 19 atoms / cm. It is less than 3 , more preferably less than 5 ⁇ 10 18 atoms / cm 3 , and even more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
- the semiconductor layer may have a non-single crystal structure, for example.
- the non-single crystal structure includes, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having crystals oriented on the c-axis, a polycrystalline structure, a microcrystal structure, or an amorphous structure.
- CAAC-OS C-Axis Aligned Crystalline Oxide Semiconductor
- the amorphous structure has the highest defect level density
- CAAC-OS has the lowest defect level density.
- An oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and no crystal component.
- the amorphous oxide film has, for example, a completely amorphous structure and has no crystal portion.
- the semiconductor layer is a mixed film having two or more of an amorphous structure region, a microcrystal structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region.
- the mixed film may have, for example, a single-layer structure or a laminated structure including any two or more of the above-mentioned regions.
- CAC Cloud-Binded Composite
- the CAC-OS is, for example, a composition of a material in which the elements constituting the oxide semiconductor are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or a size close thereto.
- the oxide semiconductor one or more metal elements are unevenly distributed, and the region having the metal elements is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or a size in the vicinity thereof.
- the state of being mixed with is also called a mosaic shape or a patch shape.
- the oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. Also, in addition to them, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc. One or more selected from the above may be included.
- CAC-OS in In-Ga-Zn oxide is indium oxide (hereinafter, InO).
- InO indium oxide
- X1 is a real number greater than 0
- In X2 Zn Y2 O Z2 X2, Y2, and Z2 are real numbers greater than 0
- GaO X3 (X3 is a real number larger than 0)
- gallium zinc oxide hereinafter, Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers larger than 0)
- the material is separated into a mosaic-like structure, and the mosaic-like InO X1 or In X2 Zn Y2 O Z2 is uniformly distributed in the film (hereinafter, also referred to as cloud-like). is there.
- CAC-OS is a composite oxide semiconductor having a structure in which a region containing GaO X3 as a main component and a region containing In X2 Zn Y2 O Z2 or InO X1 as a main component are mixed.
- the atomic number ratio of In to the element M in the first region is larger than the atomic number ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that of region 2.
- IGZO is a common name and may refer to one compound consisting of In, Ga, Zn, and O. As a typical example, it is represented by InGaO 3 (ZnO) m1 (m1 is a natural number) or In (1 + x0) Ga (1-x0) O 3 (ZnO) m0 (-1 ⁇ x0 ⁇ 1, m0 is an arbitrary number). Crystalline compounds can be mentioned.
- the crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure.
- the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have a c-axis orientation and are connected without being oriented on the ab plane.
- CAC-OS relates to the material composition of oxide semiconductors.
- CAC-OS is a region that is partially observed as nanoparticles containing Ga as a main component and nanoparticles containing In as a main component in a material composition containing In, Ga, Zn, and O. The regions observed in the shape are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.
- CAC-OS does not include a laminated structure of two or more types of films having different compositions.
- CAC-OS has a region observed in the form of nanoparticles mainly composed of the metal element and a nano portion containing In as a main component.
- the regions observed in the form of particles refer to a configuration in which the regions are randomly dispersed in a mosaic pattern.
- the CAC-OS can be formed by a sputtering method, for example, under the condition that the substrate is not intentionally heated.
- a sputtering method one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as the film forming gas.
- an inert gas typically argon
- an oxygen gas typically a nitrogen gas
- a nitrogen gas may be used as the film forming gas.
- the flow rate ratio of the oxygen gas is preferably 0% or more and less than 30%, preferably 0% or more and 10% or less. ..
- CAC-OS is characterized by the fact that no clear peak is observed when measured using the ⁇ / 2 ⁇ scan by the Out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. Have. That is, from the X-ray diffraction measurement, it can be seen that the orientation of the measurement region in the ab plane direction and the c-axis direction is not observed.
- XRD X-ray diffraction
- CAC-OS has a ring-shaped region with high brightness (ring region) and the ring in an electron diffraction pattern obtained by irradiating an electron beam having a probe diameter of 1 nm (also referred to as a nanobeam electron beam). Multiple bright spots are observed in the area. Therefore, from the electron diffraction pattern, it can be seen that the crystal structure of CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.
- GaO X3 is the main component by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX). It can be confirmed that the region and the region containing In X2 Zn Y2 O Z2 or InO X1 as the main component have a structure in which they are unevenly distributed and mixed.
- EDX energy dispersive X-ray spectroscopy
- CAC-OS has a structure different from that of the IGZO compound in which metal elements are uniformly distributed, and has properties different from those of the IGZO compound. That is, the CAC-OS is phase-separated into a region containing GaO X3 or the like as a main component and a region containing In X2 Zn Y2 O Z2 or InO X1 as a main component, and a region containing each element as a main component. Has a mosaic-like structure.
- the region in which In X2 Zn Y2 O Z2 or InO X1 is the main component is a region having higher conductivity than the region in which GaO X3 or the like is the main component. That is, the conductivity as an oxide semiconductor is exhibited by the carrier flowing through the region where In X2 Zn Y2 O Z2 or InO X1 is the main component. Therefore, a high field effect mobility ( ⁇ ) can be realized by distributing the region containing In X2 Zn Y2 O Z2 or InO X1 as the main component in the oxide semiconductor in a cloud shape.
- the region in which GaO X3 or the like is the main component is a region having higher insulating property than the region in which In X2 Zn Y2 O Z2 or InO X1 is the main component. That is, the region containing GaO X3 or the like as the main component is distributed in the oxide semiconductor, so that the leakage current can be suppressed and a good switching operation can be realized.
- CAC-OS when CAC-OS is used for a semiconductor element, the insulation property caused by GaO X3 and the like and the conductivity caused by In X2 Zn Y2 O Z2 or InO X1 act in a complementary manner, resulting in high efficiency.
- On-current (I on ) and high field-effect mobility ( ⁇ ) can be achieved.
- CAC-OS is suitable as a constituent material for various semiconductor devices.
- ⁇ Laminate structure 1> Next, the laminated structure of the image pickup apparatus will be described with reference to a cross-sectional view.
- the elements such as the insulating layer and the conductive layer shown below are examples, and other elements may be included. Alternatively, some of the elements shown below may be omitted.
- the laminated structure shown below can be formed by using a bonding step, a polishing step, or the like, if necessary.
- FIG. 18 is an example of a cross-sectional view of a laminated body having layers 560, 561 and 563 and having a bonding surface between the layers 563a and 563b constituting the layer 563.
- Layer 563b has a functional circuit provided on the silicon substrate 611.
- the capacitor 202, the transistor 203, and the transistor 204 included in the circuit 201 are shown as a part of the functional circuit.
- One electrode of the capacitor 202, one of the source or drain of the transistor 203, and the gate of the transistor 204 are electrically connected.
- the layer 563b is provided with a silicon substrate 611 and insulating layers 612, 613, 614, 615, 616, 617, and 618.
- the insulating layer 612 has a function as a protective film.
- the insulating layers 613, 613, 616, and 617 have functions as an interlayer insulating film and a flattening film.
- the insulating layer 615 has a function as a dielectric layer of the capacitor 202.
- the insulating layer 618 and the conductive layer 619 have a function as a bonding layer.
- the conductive layer 619 is electrically connected to one electrode of the capacitor 202.
- a silicon nitride film, a silicon oxide film, an aluminum oxide film, or the like can be used as the protective film.
- an inorganic insulating film such as a silicon oxide film or an organic insulating film such as an acrylic resin or a polyimide resin can be used.
- a silicon nitride film, a silicon oxide film, an aluminum oxide film, or the like can be used as the dielectric layer of the capacitor. The bonding layer will be described later.
- Conductors that can be used as wiring, electrodes, and plugs for electrical connections between devices include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, and hafnium. , Vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or alloys containing the above-mentioned metal elements as components, or alloys containing the above-mentioned metal elements. Etc. may be appropriately selected and used.
- the conductor is not limited to a single layer, and may be a plurality of layers made of different materials.
- Layer 563a has elements of pixel 100.
- the transistor 102 and the transistor 108 are shown as a part of the elements of the pixel 100. In the cross-sectional view shown in FIG. 18, the electrical connection between the two is not shown.
- the layer 563a is provided with a silicon substrate 632 and insulating layers 631, 633, 634, 635, 637, 638. In addition, conductive layers 636 and 639 are provided.
- the insulating layer 631 and the conductive layer 639 have a function as a bonding layer.
- the insulating layers 634, 635, and 637 have a function as an interlayer insulating film and a flattening film.
- the insulating layer 633 has a function as a protective film.
- the insulating layer 638 has a function of insulating the silicon substrate 632 and the conductive layer 639.
- the insulating layer 638 can be formed of the same material as other insulating layers. Further, the insulating layer 638 may be made of the same material as the insulating layer 631.
- the conductive layer 639 is electrically connected to the other of the source or drain of the transistor 108 and to the conductive layer 619. Further, the conductive layer 636 is electrically connected to the wiring 113 (see FIG. 3A).
- the Si transistor shown in FIG. 18 is a fin type having a channel forming region on a silicon substrate (silicon substrates 611, 632). A cross section in the channel width direction (cross section of A1-A2 shown in layer 563a of FIG. 18) is shown in FIG. 19A.
- the Si transistor may be a planar type as shown in FIG. 19B.
- the transistor may have a semiconductor layer 545 of a silicon thin film.
- the semiconductor layer 545 can be, for example, single crystal silicon (SOI (Silicon on Insulator)) formed on the insulating layer 546 on the silicon substrate 611.
- SOI Silicon on Insulator
- Layer 561 has a photoelectric conversion device 101.
- the photoelectric conversion device 101 can be formed on the layer 563a.
- FIG. 18 shows a configuration in which the organic photoconductivity shown in FIG. 17C is used for the photoelectric conversion layer as the photoelectric conversion device 101.
- the layer 567a is used as a cathode and the layer 567e is used as an anode.
- the layer 561 is provided with insulating layers 651, 652, 653, 654, and a conductive layer 655.
- the insulating layers 651, 653, and 654 have a function as an interlayer insulating film and a flattening film. Further, the insulating layer 654 is provided so as to cover the end portion of the photoelectric conversion device 101, and has a function of preventing a short circuit between the layer 567e and the layer 567a.
- the insulating layer 652 has a function as an element separation layer. It is preferable to use an organic insulating film or the like as the element separation layer.
- the layer 567a corresponding to the cathode of the photoelectric conversion device 101 is electrically connected to one of the source and drain of the transistor 102 included in the layer 563a.
- the layer 567e corresponding to the anode of the photoelectric conversion device 101 is electrically connected to the conductive layer 636 of the layer 563a via the conductive layer 655.
- Layer 560 is formed on layer 561.
- Layer 560 includes a light-shielding layer 671, an optical conversion layer 672, and a microlens array 673.
- the light-shielding layer 671 can suppress the inflow of light to adjacent pixels.
- a metal layer such as aluminum or tungsten can be used for the light-shielding layer 671. Further, the metal layer and a dielectric film having a function as an antireflection film may be laminated.
- a color filter can be used for the optical conversion layer 672.
- a color image can be obtained by assigning colors such as (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to the color filter for each pixel.
- a wavelength cut filter is used for the optical conversion layer 672, it is possible to obtain an image pickup device that can obtain images in various wavelength regions.
- the optical conversion layer 672 uses a filter that blocks light having a wavelength equal to or lower than that of visible light. Further, if the optical conversion layer 672 uses a filter that blocks light having a wavelength of near infrared rays or less, a far infrared ray imaging device can be obtained. Further, if the optical conversion layer 672 uses a filter that blocks light having a wavelength equal to or higher than that of visible light, it can be used as an ultraviolet imaging device.
- the image pickup device can obtain an image that visualizes the intensity of radiation used in an X-ray image pickup device or the like.
- radiation such as X-rays transmitted through a subject
- a scintillator it is converted into light (fluorescence) such as visible light or ultraviolet light by a photoluminescence phenomenon.
- the image data is acquired by detecting the light with the photoelectric conversion device 101.
- an imaging device having the above configuration may be used as a radiation detector or the like.
- the scintillator contains a substance that absorbs the energy and emits visible light or ultraviolet light when irradiated with radiation such as X-rays and gamma rays.
- Gd 2 O 2 S Tb
- Gd 2 O 2 S Pr
- Gd 2 O 2 S Eu
- BaFCl Eu
- NaI, CsI, CaF 2 , BaF 2 , CeF 3 LiF, LiI, ZnO, etc.
- Those dispersed in resin or ceramics can be used.
- a microlens array 673 is provided on the optical conversion layer 672. Light passing through the individual lenses of the microlens array 673 passes through the optical conversion layer 672 directly below and irradiates the photoelectric conversion device 101. By providing the microlens array 673, the focused light can be incident on the photoelectric conversion device 101, so that photoelectric conversion can be performed efficiently.
- the microlens array 673 is preferably formed of a resin or glass having high translucency with respect to visible light.
- the layer 563b is provided with an insulating layer 618 and a conductive layer 619.
- the conductive layer 619 has a region embedded in the insulating layer 618. Further, the surfaces of the insulating layer 618 and the conductive layer 619 are flattened so that their heights match.
- the layer 563a is provided with an insulating layer 631 and a conductive layer 639.
- the conductive layer 639 has a region embedded in the insulating layer 631. Further, the surfaces of the insulating layer 631 and the conductive layer 639 are flattened so that their heights match.
- the conductive layer 619 and the conductive layer 639 are metal elements having the same main components. Further, it is preferable that the insulating layer 618 and the insulating layer 631 are composed of the same components.
- Cu, Al, Sn, Zn, W, Ag, Pt, Au, or the like can be used for the conductive layers 619 and 639.
- Cu, Al, W, or Au is preferably used because of the ease of joining.
- silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, titanium nitride and the like can be used for the insulating layers 618 and 631.
- the conductive layer 619 and the conductive layer 639 may have a multi-layer structure of a plurality of layers, in which case, the surface layer (bonding surface) may be the same metal material. Further, the insulating layer 618 and the insulating layer 631 may also have a multilayer structure of a plurality of layers, and in that case, the insulating materials having the same surface layer (bonding surface) may be used.
- a surface activation bonding method can be used in which the oxide film on the surface and the adsorption layer of impurities are removed by sputtering or the like, and the cleaned and activated surfaces are brought into contact with each other for bonding. ..
- a diffusion bonding method or the like in which surfaces are bonded to each other by using both temperature and pressure can be used. Since bonds occur at the atomic level in both cases, excellent bonding can be obtained not only electrically but also mechanically.
- the surfaces treated with hydrophilicity such as oxygen plasma are brought into contact with each other for temporary bonding, and then main bonding is performed by dehydration by heat treatment.
- a joining method or the like can be used. Since the hydrophilic bonding method also causes bonding at the atomic level, it is possible to obtain mechanically excellent bonding.
- a method can be used in which the surface is cleaned after polishing, the surface of the metal layer is subjected to an antioxidant treatment, and then a hydrophilic treatment is performed to join the metal layer.
- the surface of the metal layer may be made of a refractory metal such as Au and subjected to hydrophilic treatment.
- a joining method other than the above-mentioned method may be used.
- the circuit 201 included in the layer 563b and the element of the pixel 100 included in the layer 563a can be electrically connected.
- FIG. 20 is a modification of the laminated structure shown in FIG. 18, in which the configuration of the photoelectric conversion device 101 included in the layer 561 and the partial configuration of the layer 563a are different, and the bonded surface is also formed between the layer 561 and the layer 563a. It is a configuration having.
- Layer 561 includes a photoelectric conversion device 101, insulating layers 661, 662, 664, 665 and conductive layers 135, 136.
- the photoelectric conversion device 101 is a pn junction type photodiode formed on a silicon substrate, and has a layer 565b corresponding to a p-type region and a layer 565a corresponding to an n-type region.
- the photoelectric conversion device 101 is an embedded photodiode, and a thin p-shaped region (a part of the layer 565b) provided on the surface side (current extraction side) of the layer 565a can suppress dark current and reduce noise. it can.
- the insulating layer 661 and the conductive layers 135 and 136 have a function as a bonding layer.
- the insulating layer 662 has a function as an interlayer insulating film and a flattening film.
- the insulating layer 664 has a function as an element separation layer.
- the insulating layer 665 has a function of suppressing the outflow of carriers.
- the silicon substrate is provided with an opening for separating pixels, and the insulating layer 665 is provided on the upper surface of the silicon substrate and the opening.
- the insulating layer 665 By providing the insulating layer 665, it is possible to prevent the carriers generated in the photoelectric conversion device 101 from flowing out to the adjacent pixels.
- the insulating layer 665 also has a function of suppressing the intrusion of stray light. Therefore, the insulating layer 665 can suppress color mixing.
- An antireflection film may be provided between the upper surface of the silicon substrate and the insulating layer 665.
- the element separation layer can be formed by using the LOCOS (LOCOS Occidation of Silicon) method. Alternatively, it may be formed by using an STI (Shallow Trench Isolation) method or the like.
- LOCOS LOC Occidation of Silicon
- STI Shallow Trench Isolation
- the insulating layer 665 for example, an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as polyimide or acrylic can be used.
- the insulating layer 665 may have a multi-layer structure.
- the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101 is electrically connected to the conductive layer 135.
- the layer 565b (p-type region, corresponding to the anode) is electrically connected to the conductive layer 136.
- the conductive layers 135 and 136 have a region embedded in the insulating layer 661. Further, the surfaces of the insulating layer 661 and the conductive layers 135 and 136 are flattened so that their heights match.
- an insulating layer 638 is formed on the insulating layer 637. Further, a conductive layer 133 electrically connected to one of the source or drain of the transistor 102 and a conductive layer 134 electrically connected to the conductive layer 636 are formed.
- the insulating layer 638 and the conductive layers 133 and 134 have a function as a bonding layer.
- the conductive layers 133 and 134 have a region embedded in the insulating layer 638. Further, the surfaces of the insulating layer 638 and the conductive layers 133 and 134 are flattened so that their heights match.
- the conductive layers 133, 134, 135, and 136 are the same bonded layers as the conductive layers 619 and 639 described above.
- the insulating layers 638 and 661 are the same bonded layers as the insulating layers 618 and 631 described above.
- the conductive layer 133 and the conductive layer 135 one of the source or drain of the transistor 102 can be electrically connected to the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device. Further, by laminating the conductive layer 134 and the conductive layer 136, the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device and the wiring 113 (see FIG. 3) can be electrically connected. Further, by laminating the insulating layer 638 and the insulating layer 661, the layer 561 and the layer 563a can be electrically and mechanically bonded.
- FIG. 21 is an example of a cross-sectional view of a laminated body having layers 560, 561, 562, and 563 and having no bonding surface.
- a Si transistor is provided on the layer 563.
- An OS transistor is provided on the layer 562.
- the components of the memory circuit are provided on the layer 562 and the layer 563, and the drive circuit of the memory circuit is provided on the layer 563. Since the configurations of the layers 561 and 560 are the same as those shown in FIG. 18, the description thereof will be omitted here.
- Layer 563 has a functional circuit provided on the silicon substrate 611.
- transistors 251 included in the drive circuit of the memory circuit and transistors 252 and 253 included in the memory circuit are shown as a part of the functional circuit.
- Layer 562b is formed on layer 563.
- Layer 562b has an OS transistor.
- the transistor 254 is shown as part of the memory circuit.
- the layer 562b is provided with insulating layers 621, 622, 623, 624, 625, 626, 628 and 629. Further, a conductive layer 627 is provided. The conductive layer 627 can be electrically connected to the wiring 113 (see FIG. 3).
- the insulating layer 621 has a function as a blocking layer. It has a function as an interlayer insulating film and a flattening film of the insulating layers 622, 623, 625, 626, 628, and 629.
- the insulating layer 624 has a function as a protective film.
- the blocking layer it is preferable to use a film having a function of preventing the diffusion of hydrogen.
- hydrogen is required to terminate dangling bonds, but hydrogen in the vicinity of the OS transistor becomes one of the factors that generate carriers in the oxide semiconductor layer, which reduces reliability. .. Therefore, it is preferable to provide a hydrogen blocking film between the layer on which the Si device is formed and the layer on which the OS transistor is formed.
- the blocking film for example, aluminum oxide, aluminum nitride, gallium oxide, gallium nitride, yttrium oxide, yttrium oxide, hafnium oxide, hafnium oxide, yttria-stabilized zirconia (YSZ) and the like can be used.
- aluminum oxide, aluminum nitride, gallium oxide, gallium nitride, yttrium oxide, yttrium oxide, hafnium oxide, hafnium oxide, yttria-stabilized zirconia (YSZ) and the like can be used.
- the memory circuit included in the layer 563 and the layer 562b has the transistor 254, the transistor 253, and the transistor 252 in the memory cell.
- One of the source or drain of transistor 254 is electrically connected to the gate of transistor 253.
- the gate of the transistor 254 is electrically connected to the transistor 251 included in the drive circuit of the memory circuit.
- the gate of the transistor 253 is used as a data holding unit, and data is written by the transistor 254.
- the memory cell is read out by conducting the transistor 252.
- an OS transistor having a small off-current for the transistor 254 connected to the data holding unit the data holding time can be lengthened.
- NO SRAM and the like in the embodiment described later can be referred to.
- FIG. 22A shows the details of the OS transistor.
- the OS transistor shown in FIG. 22A is a self-aligned type in which an insulating layer is provided on a laminate of an oxide semiconductor layer and a conductive layer, and an opening reaching the oxide semiconductor layer is provided to form a source electrode 705 and a drain electrode 706. It is the composition of.
- the OS transistor may have a channel forming region, a source region 703, and a drain region 704 formed in the oxide semiconductor layer, as well as a gate electrode 701 and a gate insulating film 702. At least the gate insulating film 702 and the gate electrode 701 are provided in the opening. An oxide semiconductor layer 707 may be further provided in the groove.
- the OS transistor may have a self-aligned configuration in which the source region 703 and the drain region 704 are formed in the semiconductor layer using the gate electrode 701 as a mask.
- FIG. 22C it may be a non-self-aligned top gate type transistor having a region where the source electrode 705 or the drain electrode 706 and the gate electrode 701 overlap.
- the OS transistor shows a structure having a back gate 535, it may have a structure without a back gate.
- the back gate 535 may be electrically connected to the front gate of the transistor provided opposite to each other as shown in the cross-sectional view in the channel width direction of the transistor shown in FIG. 22D.
- FIG. 22D shows a cross section of the transistor B1-B2 of FIG. 22A as an example, but the same applies to transistors having other structures.
- the back gate 535 may be configured to be able to supply a fixed potential different from that of the front gate.
- Layer 562a is formed on the layer 562b.
- Layer 562a has an element of pixel 100 having an OS transistor.
- the transistor 102 and the transistor 103 are shown as a part of the elements of the pixel 100.
- the layer 562a is provided with insulating layers 641, 642, 643, 644, 645, 647. Further, a conductive layer 646 is provided.
- the insulating layers 641, 642, 644, 645, and 647 have functions as an interlayer insulating film and a flattening film.
- the insulating layer 643 has a function as a protective film.
- One of the source and drain of the transistor 102 is electrically connected to the cathode of the photoelectric conversion device 101 included in the layer 561.
- the conductive layer 646 is electrically connected to the anode of the photoelectric conversion device 101 included in the layer 561 and the conductive layer 627 included in the layer 562b.
- the pixel circuit included in the layer 562a can be electrically connected to the circuit 201 included in the layer 563. Further, the circuit 201 can be electrically connected to other functional circuits.
- FIG. 23 is a modification of the laminated structure shown in FIG. 22, in which the configuration of the photoelectric conversion device 101 included in the layer 561 and the partial configuration of the layer 562a are different, and a bonded surface is formed between the layer 561 and the layer 562a. It is a structure to have.
- the photoelectric conversion device 101 included in the layer 561 is a pn junction type photodiode formed on a silicon substrate, and has the same configuration as that shown in FIG.
- an insulating layer 648 is formed on the insulating layer 647. Further, a conductive layer 138 that is electrically connected to one of the source and drain of the transistor 102 and a conductive layer 139 that is electrically connected to the conductive layer 646 are formed.
- the insulating layer 648 and the conductive layers 138 and 139 have a function as a bonding layer.
- the conductive layers 138 and 139 have a region embedded in the insulating layer 648. Further, the surfaces of the insulating layer 648 and the conductive layers 133 and 134 are flattened so that their heights match.
- the conductive layers 138 and 139 are the same bonded layers as the conductive layers 619 and 639 described above.
- the insulating layer 648 is the same bonded layer as the above-mentioned insulating layers 618 and 631.
- the conductive layer 138 and the conductive layer 135 one of the source or drain of the transistor 102 can be electrically connected to the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device. Further, by laminating the conductive layer 139 and the conductive layer 136, the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device and the wiring 113 (see FIG. 3) can be electrically connected. Further, by laminating the insulating layer 648 and the insulating layer 661, the layer 561 and the layer 562a can be electrically and mechanically bonded.
- FIG. 24A1 is an external perspective view of the upper surface side of the package containing the image sensor chip.
- the package has a package substrate 410 for fixing the image sensor chip 450 (see FIG. 24A3), a cover glass 420, an adhesive 430 for adhering both, and the like.
- FIG. 24A2 is an external perspective view of the lower surface side of the package.
- the lower surface of the package has a BGA (Ball grid array) in which solder balls are bumps 440.
- BGA Ball grid array
- LGA Land grid array
- PGA Peripheral Component Interconnect
- FIG. 26A3 is a perspective view of the package shown by omitting a part of the cover glass 420 and the adhesive 430.
- An electrode pad 460 is formed on the package substrate 410, and the electrode pad 460 and the bump 440 are electrically connected via a through hole.
- the electrode pad 460 is electrically connected to the image sensor chip 450 by a wire 470.
- FIG. 24B1 is an external perspective view of the upper surface side of the camera module in which the image sensor chip is housed in a lens-integrated package.
- the camera module has an image sensor chip 451 (a package substrate 411 for fixing FIG. 24B3, a lens cover 421, a lens 435, and the like. Further, a drive circuit of an image pickup device and an image sensor chip 451 are located between the package substrate 411 and the image sensor chip 451.
- An IC chip 490 having a function such as a signal conversion circuit (FIG. 24B3 is also provided, and has a configuration as a SiP (Sensem in package)).
- FIG. 24B2 is an external perspective view of the lower surface side of the camera module.
- the lower surface and the side surface of the package substrate 411 have a QFN (Quad flat no-lead package) configuration in which a land 441 for mounting is provided.
- the configuration is an example, and a QFP (Quad flat package) or the above-mentioned BGA may be provided.
- FIG. 24B3 is a perspective view of the module shown by omitting a part of the lens cover 421 and the lens 435.
- the land 441 is electrically connected to the electrode pad 461, and the electrode pad 461 is electrically connected to the image sensor chip 451 or the IC chip 490 by a wire 471.
- the image sensor chip By housing the image sensor chip in a package having the above-mentioned form, it can be easily mounted on a printed circuit board or the like, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.
- the memory circuit can store the data captured by the pixel circuit or the product-sum calculation result. Therefore, an imaging device having a memory circuit can perform high-speed imaging and calculation.
- FIG. 25A is a diagram showing a connection relationship of elements (memory cell 321a, low driver 312, column driver 313) included in the memory circuit 321. It is preferable to use an OS transistor as the transistor constituting the memory cell 321a.
- the memory circuit 321 has m (m is an integer of 1 or more) in a column, n (n is an integer of 1 or more) in a row, and a total of m ⁇ n memory cells 321a, and the memory cells 321a have a matrix shape. Is located in. In FIG. 25A, the address of the memory cell 321a is also shown. For example, [1,1] indicates a memory cell 321a located at the address of the first row and the first column, and [i, j] (i is an integer of 1 or more and m or less, j is an integer of 1 or more and n or less). Indicates a memory cell 321a located at the address of the i-row and the j-th column.
- the number of wires connecting the memory circuit 321 and the low driver 312 is determined by the configuration of the memory cells 321a, the number of the memory cells 321a included in the row, and the like. Further, the number of wirings connecting the memory circuit 321 and the column driver 313 is determined by the configuration of the memory cells 321a, the number of the memory cells 321a included in one line, and the like.
- 25B to 25E are diagrams illustrating memory cells 321aA to memory cells 321aD that can be applied to memory cells 321a.
- the bit wires can be connected to the column driver 313.
- the word wires can be connected to the low driver 312.
- a decoder or a shift register can be used for the low driver 312 and the column driver 313, for example.
- a plurality of low drivers 312 and column drivers 313 may be provided.
- FIG. 25B shows a circuit configuration example of the DRAM type memory cell 321aA.
- a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory).
- the memory cell 321aA has a transistor M11 and a capacitor Cs.
- the first terminal of the transistor M11 is connected to the first terminal of the capacitor Cs, the second terminal of the transistor M11 is connected to the wiring BIL, the gate of the transistor M11 is connected to the wiring WL, and the back gate of the transistor M11 is. , Is connected to the wiring BGL.
- the second terminal of the capacitor Cs is connected to the wiring GNDL.
- Wiring GNDL is wiring that gives a low level potential (reference potential).
- the wiring BIL functions as a bit line.
- the wiring WL functions as a word line.
- the wiring BGL functions as wiring for applying an electric potential to the back gate of the transistor M11.
- the threshold voltage of the transistor M11 can be increased or decreased by applying an arbitrary potential to the wiring BGL.
- Data writing and reading is performed by applying a high level potential to the wiring WL, making the transistor M11 conductive, and electrically connecting the wiring BIL and the first terminal of the capacitor Cs.
- an OS transistor for the transistor M11.
- the semiconductor layer of the OS transistor it is preferable to use an oxide semiconductor having any one of indium, element M (element M is one or more of aluminum, gallium, yttrium, or tin) and zinc.
- oxide semiconductor having indium, gallium, and zinc it is preferable to use an oxide semiconductor having indium, gallium, and zinc.
- An OS transistor to which an oxide semiconductor containing indium, gallium, and zinc is applied has a characteristic that the off-current is extremely small.
- the leakage current of the transistor M11 can be made very low. That is, since the written data can be held by the transistor M11 for a long time, the frequency of refreshing the memory cells can be reduced. Moreover, the refresh operation of the memory cell can be eliminated.
- FIG. 25C shows a circuit configuration example of a gain cell type (also referred to as “2Tr1C type”) memory cell 321aB having two transistors and one capacitor.
- the memory cell 321aB has a transistor M11, a transistor M3, and a capacitor Cs.
- the first terminal of the transistor M11 is connected to the first terminal of the capacitor Cs
- the second terminal of the transistor M11 is connected to the wiring WBL
- the gate of the transistor M11 is connected to the wiring WL
- the back gate of the transistor M11 is , Is connected to the wiring BGL.
- the second terminal of the capacitor Cs is connected to the wiring RL.
- the first terminal of the transistor M3 is connected to the wiring RBL
- the second terminal of the transistor M3 is connected to the wiring SL
- the gate of the transistor M3 is connected to the first terminal of the capacitor Cs.
- the wiring WBL functions as a write bit line.
- the wiring RBL functions as a read bit line.
- the wiring WL functions as a word line.
- the wiring RL functions as wiring for applying a predetermined potential to the second terminal of the capacitor Cs. When writing data, it is preferable to apply a reference potential to the wiring RL during data retention.
- the wiring BGL functions as wiring for applying an electric potential to the back gate of the transistor M11.
- the threshold voltage of the transistor M11 can be increased or decreased by applying an arbitrary potential to the wiring BGL.
- Data writing is performed by applying a high level potential to the wiring WL, making the transistor M11 conductive, and electrically connecting the wiring WBL and the first terminal of the capacitor Cs. Specifically, when the transistor M11 is in a conductive state, a potential corresponding to the information recorded in the wiring WBL is applied, and the potential is written to the first terminal of the capacitor Cs and the gate of the transistor M3. After that, a low level potential is applied to the wiring WL to bring the transistor M11 into a non-conducting state, thereby holding the potential of the first terminal of the capacitor Cs and the potential of the gate of the transistor M3.
- Data reading is performed by applying a predetermined potential to the wiring RL and the wiring SL. Since the current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3, they are connected to the first terminal of the transistor M3.
- the potential held in the first terminal (or the gate of the transistor M3) of the capacitor Cs can be read out. That is, the information written in the memory cell can be read from the potential held in the first terminal of the capacitor Cs (or the gate of the transistor M3). Alternatively, it is possible to know whether or not there is information written in this memory cell.
- the wiring WBL and the wiring RBL may be combined into one wiring BIL.
- the memory cell 321aC shown in FIG. 25D has a configuration in which the wiring WBL and the wiring RBL of the memory cell 321aB are used as one wiring BIL, and the second terminal of the transistor M11 and the first terminal of the transistor M3 are connected to the wiring BIL. It has become. That is, the memory cell 321aC has a configuration in which the write bit line and the read bit line operate as one wiring BIL.
- an OS transistor for the transistor M11
- a storage device that uses an OS transistor for the transistor M11 and uses a 2Tr1C type memory cell such as a memory cell 321aB and a memory cell 321aC is called a NOSRAM (Non-volatile Oxide Sensor Random Access Memory).
- FIG. 25E shows a circuit configuration example of a gain cell type (also referred to as “3Tr1C type”) memory cell 321aD of a 3-transistor 1-capacitor.
- the memory cell 321aD includes a transistor M11, a transistor M5, a transistor M6, and a capacitor Cs.
- the first terminal of the transistor M11 is connected to the first terminal of the capacitor Cs, the second terminal of the transistor M11 is connected to the wiring BIL, the gate of the transistor M11 is connected to the wiring WL, and the back gate of the transistor M11 is. , Electrically connected to the wiring BGL.
- the second terminal of the capacitor Cs is electrically connected to the first terminal of the transistor M5 and the wiring GNDL.
- the second terminal of the transistor M5 is connected to the first terminal of the transistor M6, and the gate of the transistor M5 is connected to the first terminal of the capacitor Cs.
- the second terminal of the transistor M6 is connected to the wiring BIL, and the gate of the transistor M6 is connected to the wiring RL.
- the wiring BIL functions as a bit line
- the wiring WL functions as a write word line
- the wiring RL functions as a read word line.
- the wiring BGL functions as wiring for applying an electric potential to the back gate of the transistor M11.
- the threshold voltage of the transistor M11 can be increased or decreased by applying an arbitrary potential to the wiring BGL.
- Data writing is performed by applying a high level potential to the wiring WL, making the transistor M11 conductive, and connecting the wiring BIL and the first terminal of the capacitor Cs. Specifically, when the transistor M11 is in a conductive state, a potential corresponding to the information recorded in the wiring BIL is applied, and the potential is written to the first terminal of the capacitor Cs and the gate of the transistor M5. After that, a low level potential is applied to the wiring WL to bring the transistor M11 into a non-conducting state, thereby holding the potential of the first terminal of the capacitor Cs and the potential of the gate of the transistor M5.
- Data reading is performed by precharging the wiring BIL with a predetermined potential, then electrically suspending the wiring BIL, and applying a high level potential to the wiring RL. Since the wiring RL has a high level potential, the transistor M6 is in a conductive state, and the wiring BIL and the second terminal of the transistor M5 are in an electrically connected state. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5, but the transistor M5 depends on the potential held in the first terminal of the capacitor Cs (or the gate of the transistor M5). The potential of the second terminal and the potential of the wiring BIL change.
- the potential held in the first terminal (or the gate of the transistor M5) of the capacitor Cs can be read out. That is, the information written in the memory cell can be read from the potential held in the first terminal of the capacitor Cs (or the gate of the transistor M5). Alternatively, it is possible to know whether or not there is information written in this memory cell.
- the memory cell 321aD it is preferable to use an OS transistor for the transistor M11.
- the 3Tr1C type memory cell 321aD to which the OS transistor is applied as the transistor M11 is one aspect of the NOSRAM described above.
- the circuit configuration of the memory cell can be changed as appropriate.
- a Si transistor can also be used as the transistor constituting the memory cell.
- the semiconductor device described in this embodiment includes a processor and has a function of controlling the operation of the image pickup device.
- the semiconductor device described in this embodiment is an example of a basic configuration in a processor and its peripheral circuits, and the circuit including the configuration can be called a CPU, an MCU, or the like.
- the semiconductor device is a normally-off type, and can perform image pickup timing control and the like for a pixel circuit and a drive circuit.
- a power gating capable circuit or power supply circuit in a semiconductor device can perform power gating and enter hibernation. Further, if necessary, only a specific circuit and a power supply circuit can be shifted to the power-on mode, and an image pickup permission signal can be output to the pixel circuit and the drive circuit. If there are other necessary processes in the semiconductor device, they can be executed.
- power gating can be performed in the motion detection mode, so that power consumption can be reduced.
- FIG. 26A A semiconductor device and its power management will be described with reference to FIGS. 26A and 26B.
- the semiconductor device shown in FIG. 26A includes a power supply circuit 10 and a processing unit (PU: Processing Unit) 20.
- the PU 20 is a circuit having a function of executing an instruction.
- the PU 20 has a plurality of functional circuits integrated on one chip.
- the PU 20 includes a processor core 30, a power management device (PMU) 60, a clock control circuit 65, a power switch (PSW) 70, and terminals 80 to 83.
- FIG. 26A shows an example in which the power supply circuit 10 is provided on a chip different from the PU 20.
- the terminal 80 is a terminal to which the power supply potential VDD is input from the power supply circuit 10.
- the terminal 81 is a terminal to which the reference clock signal CLKM is input from the outside.
- the terminal 82 is a terminal to which a signal INT is input from the outside.
- the signal INT is an interrupt signal that requires interrupt processing.
- the signal INT is input to PU20 and PMU60.
- the terminal 83 is a terminal to which the control signal generated by the PMU 60 is output, and is electrically connected to the power supply circuit 10.
- the processor core 30 is a circuit having a function capable of processing instructions, and can be called an arithmetic processing circuit. It has a storage circuit 31, a combinational circuit 32, and the like, and various functional circuits are configured by these. For example, the storage circuit 31 is included in the register. Note that D represents an input signal and Q represents an output signal.
- the storage circuit 31 has a circuit MemC1 and a circuit BKC1.
- the circuit MemC1 has a function of holding the data generated by the processor core 30, and can be configured by, for example, a flip-flop circuit, a latch circuit, or the like.
- the circuit BKC1 is a circuit that can function as a backup circuit of the circuit MemC1 and can hold data for a long period of time even if the power supply is cut off or the clock signal is cut off. Having such a storage circuit 31 makes it possible to perform power gating of the processor core 30.
- the state of the processor core 30 at the time of power cutoff can be maintained by saving the data of the circuit MemC1 in the circuit BKC1 in the storage circuit 31 before shutting off the power supply.
- the data held in the circuit BKC1 is written to the circuit MemC1, so that the processor core 30 can be returned to the state when the power is cut off. Therefore, the PU 20 can immediately perform the normal processing operation after the power supply is restarted.
- the circuit BKC1 has at least a holding circuit having one transistor (MW1) and one capacitive element (CB1).
- the holding circuit shown in FIG. 26B has a circuit configuration similar to that of a standard DRAM (dynamic random access memory) 1T1C (1 transistor, 1 capacitance element) type memory cell, and writes and reads operations are also performed in the same manner. Can be done.
- DRAM dynamic random access memory
- 1T1C (1 transistor, 1 capacitance element
- the drain current (off current) of the transistor MW1 in the off state By making the drain current (off current) of the transistor MW1 in the off state extremely small, the fluctuation of the potential of the node FN1 can be suppressed, so that the data holding time of the circuit BKC1 can be lengthened.
- the data holding time of the circuit BKC1 is determined by the leakage current of the transistor MW1, the capacitance of the capacitive element CB1, and the like.
- the circuit BKC1 can substantially function as a non-volatile storage circuit while the PU 20 is operating.
- the circuit BKC1 Since the circuit BKC1 writes data by voltage, the write power can be suppressed as compared with MRAM (magnetoresistive RAM) which writes by current. Further, since the data is held by the load capacity of the node FN1, there is no limit on the number of times the data can be rewritten as in the flash memory.
- MRAM magnetoresistive RAM
- the energy required for writing data corresponds to the energy associated with charging / discharging the electric charge to the capacitive element CB1.
- the energy required for writing data corresponds to the energy consumed when a current flows through the storage element. Since the current continues to flow in the MRAM during the data writing period, the energy required for writing the data becomes high.
- the circuit BKC1 can reduce the energy consumed in writing data. Therefore, as compared with the storage circuit in which the backup circuit is composed of MRAM, the storage circuit 31 has more opportunities to perform voltage scaling and power gating that can reduce the energy consumed, so that the power consumption of the PU 20 can be reduced. It can be reduced.
- the PMU 60 has a function of controlling a power gating operation, a clock gating operation, a voltage scaling operation, and the like. More specifically, the PMU 60 can control a function capable of controlling the power supply circuit 10, a function capable of controlling the storage circuit 31, a function capable of controlling the clock control circuit 65, and a function capable of controlling the PSW 70. It has a function that can be used. Therefore, the PMU 60 has a function of generating a control signal for controlling these circuits (10, 31, 65, 70).
- the PMU 60 has a circuit 61.
- the circuit 61 has a function of measuring time.
- the PMU 60 has a function of being able to perform power management based on the time-related data obtained in the circuit 61.
- the PSW 70 has a function of being able to control the supply of the power supply potential M VDD to the PU 20 according to the control signal of the PMU 60.
- the power supply potential supplied to the PU 20 via the PSW 70 is referred to as a power supply potential VDD.
- the processor core 30 may have a plurality of power supply domains. In this case, the PSW 70 may be able to independently control the power supply to the plurality of power supply domains. Further, the processor core 30 may have a power supply domain that does not require power gating. In this case, the power supply potential may be supplied to this power supply domain without going through the PSW 70.
- the clock control circuit 65 has a function of inputting a reference clock signal CLKM, generating a gated clock signal, and outputting the gated clock signal.
- the clock control circuit 65 has a function of blocking the clock signal to the processor core 30 according to the control signal of the PMU 60.
- the power supply circuit 10 has a function of changing the magnitude of the VDD potential according to the control signal of the PMU 60.
- the signal SLP output from the processor core 30 to the PMU 60 is a signal that triggers the transition of the processor core 30 to the hibernation state.
- the PMU 60 When the signal SLP is input, the PMU 60 generates a control signal for shifting to the hibernation state and outputs the control signal to the functional circuit to be controlled.
- the power supply circuit 10 lowers M VDD lower than in normal operation based on the control signal of PMU 60.
- the PMU 60 controls the PSW 70 to cut off the power supply to the processor core 30.
- the PMU 60 performs a voltage scaling operation for lowering the power supply potential VDD of the processor core 30.
- FIGS. 27A to 27D are diagrams schematically showing changes in the potential of the power supply line.
- the power supply line is a wiring to which the power supply potential VDD is supplied via the PSW 70.
- the horizontal axis of the figure is the elapsed time from the normal state to the hibernation state, and t0, t1, etc. represent the time.
- FIG. 27A is an example in which only power gating is executed in the hibernation state
- FIG. 27B is an example in which only voltage scaling is executed in the hibernation state.
- 27C and 27D are examples of performing voltage scaling and power gating.
- the magnitude of the power supply potential MVDD supplied from the power supply circuit 10 is assumed to be VH1.
- the power mode of the PU 20 is divided into three modes: a power on mode, a power off mode, and a low power mode.
- the power-on mode is a mode in which the power potential VDD that can be normally processed is supplied to the PU 20.
- the power off mode is a mode in which the supply of VDD is stopped by the PSW 70.
- the low power supply mode is a mode for supplying a power supply potential VDD lower than that of the power on mode.
- FIG. 27A An example of FIG. 27A will be described.
- the process of transitioning to hibernation in the processor core 30 is started.
- the storage circuit 31 is backed up.
- the PMU 60 controls the PSW 70 and cuts off the power supply to the processor core 30 at time t1.
- the power line 35 spontaneously discharges, and its potential drops to 0V.
- the leakage current of the processor core 30 in the hibernation state can be significantly reduced, so that the power consumption in the hibernation state (hereinafter, may be referred to as standby power) can be reduced.
- the PMU 60 controls the PSW 70 and restarts the supply of VDD.
- the supply of VDD is restarted.
- the potential of the power line 35 rises and becomes VH1 at time t6.
- the PMU 60 controls the power supply circuit 10 at time t1, and the potential of M VDD is lowered to VH2.
- the potential of the power line 35 eventually becomes VH2.
- the power supply potential M VDD returns from VH2 to VH1 at time t4, the potential of the power supply line 35 rises and becomes VH1 at time t5.
- the time (overhead time) required to return from the hibernation state to the normal state is the time required for the potential of the power supply line 35 to rise from 0V to VH1, and the energy required for the return.
- the overhead is the energy required to charge the load capacity of the power line 35 from 0V to VH1. If the power-off mode period (t1-t4) is sufficiently long, power gating is effective in reducing the standby power of the PU 20. On the other hand, if the period (t1-t4) is short, the power required to return to the normal state is larger than the power that can be reduced by shutting off the power supply, and the effect of power gating cannot be obtained.
- the voltage scaling operation is performed in the hibernation state, and the mode shifts from the power-on mode to the low power-on mode.
- the PMU 60 controls the power supply circuit 10 and lowers the potential of M VDD to VH2, so that the potential of the power supply line 35 eventually becomes VH2.
- the PMU 60 controls the PSW 70 to set the power off mode.
- the potential VH2 is a power supply potential having a size capable of holding data in the circuit MemC1 of the storage circuit 31, and the potential VH3 is a potential at which the data in the circuit MemC1 is lost.
- the circuit BKC1 is a circuit capable of holding data even during a period when the power supply is stopped.
- the PMU 60 has a function of returning the PU 20 to the normal state based on an interrupt request or the like.
- the PMU 60 controls the power supply circuit 10 to boost the magnitude of M VDD to VH1, and also controls the PSW 70 to restart the supply of VDD of the PU 20.
- the power-on mode is set. Since the potential of the power supply line 35 stabilizes at time t6, the PU 20 can operate normally after time t6.
- FIG. 27D shows an example in which there is an interrupt request for returning to the normal operation before the time t3.
- the power-on mode is set.
- the PMU 60 controls the power supply circuit 10 to change the magnitude of MVDD to the potential VH1 in the power-on mode.
- the potential of the power line 35 rises to VH1.
- the time required to return the potential of the power supply line 35 to VH1 in the hibernation state is changed from the low power supply mode to the power on mode by returning from the power off mode to the power on mode. Longer than returning. Therefore, the PMU 60 has a function of adjusting the timing of the operation of returning the processor core 30 from the hibernation state to the normal state according to the power supply mode. As a result, the processor core 30 can be returned from the hibernation state to the normal state in the shortest time.
- the transition from the low power supply mode to the power off mode can be performed by measuring the time with the circuit 61 provided in the PMU 60.
- the PMU 60 starts measuring the time in the circuit 61.
- a predetermined time elapses after the low power supply mode is set, the PMU 60 shifts to the power off mode.
- the control signal of the PMU 60 turns off the PSW 70 and cuts off the supply of VDD. In this way, it is possible to shift from the low power supply mode to the power off mode by the interrupt request based on the measurement data of the circuit 61.
- FIG. 28 an example of power management operation of the PMU 60 will be described with reference to the flowchart shown in FIG. 28.
- the PU 20 is operating normally.
- the power supply mode is the power on mode, and the PMU 60 is in the idle state (S10).
- the PMU 60 is in an idle state until a signal SLP is input, and executes a save sequence triggered by the input of the signal SLP (S11).
- the PMU 60 outputs a control signal to the clock control circuit 65 and stops the output of the clock signal (S12).
- a control signal for saving data is output to the storage circuit 31 (S13).
- the data held in the circuit MemC1 is saved in the circuit BKC1 according to the control signal of the PMU 60.
- the PMU 60 controls the power supply circuit 10 to reduce M VDD.
- the power supply mode shifts to the low power supply mode (S14).
- the PMU 60 controls the built-in circuit 61 and measures the time Ta in the low power supply mode (S15).
- the timing for operating the circuit 61 is arbitrary as long as the save sequence is being executed. For example, when the signal SLP is input or when the control signal is output to the clock control circuit 65, data save is started. When, when the data saving is completed, when the control signal is output to the power supply circuit 10, and the like can be mentioned.
- the PMU 60 After executing the evacuation sequence, the PMU 60 goes into an idle state (S16), monitors the input of the signal INT, and monitors the measurement time Ta of the clock control circuit 65.
- the process shifts to the return sequence (S17). It is determined whether or not the time Ta exceeds the set time T vs (S18).
- the PMU 60 controls to shift the power supply mode to the power off mode (S19), and if it does not exceed the time Ta, the idle state is maintained (S16).
- the time T vs. may be set so that the standby power of the processor core 30 can be reduced by setting the power off mode rather than the low power mode.
- the PMU 60 outputs a control signal that causes the PSW 70 to cut off the power supply to the processor core 30.
- the PMU 60 is idle again (S20) and monitors the signal INT input (S21).
- the PMU 60 executes a return sequence.
- the PMU 60 first shifts from the power-off mode to the power-on mode (S22).
- the PMU 60 controls the power supply circuit 10 to output a power supply potential for normal operation.
- the PMU 60 controls the PSW 70 to restart the supply of VDD to the processor core 30.
- a control signal is output to the storage circuit 31 to restore the data in the storage circuit 31 (S23).
- the storage circuit 31 writes back the data held in the circuit BKC1 to the circuit MemC1 according to the control signal of the PMU 60.
- the PMU 60 outputs a control signal for outputting the clock signal to the clock control circuit 65 (S24).
- the clock control circuit 65 resumes the output of the clock signal according to the control signal of the PMU 60.
- the power-on mode is restored from the low power supply mode, and the potential of the power supply line 35 is stabilized faster than when the return sequence is executed from the determination process of S21. Can be done. Therefore, in the PMU 60, the timing of executing S23 is earlier when shifting from S17 to the return sequence than when shifting from S21 to the return sequence. As a result, the time for returning the processor core 30 from the hibernation state to the normal state can be shortened.
- the leakage current is first reduced by lowering the power potential supplied to the processor core 30 by the voltage scaling operation. While reducing, the processing time and energy overhead of returning from hibernation to normal is reduced. When the hibernation state continues for a certain period of time, a power gating operation is performed to suppress the leakage current of the processor core 30 as much as possible. This makes it possible to reduce the power consumption of the PU 20 in the hibernation state without reducing the processing capacity of the PU 20.
- FIG. 29A shows a modified example of the semiconductor device of FIG. 26A.
- the processing device (PU) 21 shown in FIG. 29A has a configuration in which a cache 40 and a power switch (PSW) 71 are added to the PU 20.
- the cache 40 is capable of power gating and voltage scaling, and the power mode of the cache 40 changes in conjunction with the power mode of the PU 21.
- the PSW 71 is a circuit that controls the supply of the power supply potential M VDD to the cache 40, and is controlled by the PMU 60.
- the power supply potential input to the cache 40 via the PSW 71 is set to VDD_MEM.
- a control signal from the PMU 60 and a gated clock signal from the clock control circuit 65 are input to the cache 40 as in the processor core 30.
- the cache 40 is a storage device having a function of temporarily storing frequently used data.
- the cache 40 has a memory array 41, a peripheral circuit 42, and a control circuit 43.
- the memory array 41 has a plurality of memory cells 45.
- the control circuit 43 controls the operation of the cache 40 according to the request of the processor core 30. For example, the write operation and read operation of the memory array 41 are controlled.
- the peripheral circuit 42 has a function of generating a signal for driving the memory array 41 according to a control signal from the control circuit 43.
- the memory array 41 has a memory cell 45 that holds data.
- the memory cell 45 has a circuit MemC2 and a circuit BKC2.
- the circuit MemC2 is a memory cell to be accessed in normal operation.
- a memory cell of SRAM Static Random Access Memory
- the circuit BKC2 is a circuit that can function as a backup circuit of the circuit MemC2 and can hold data for a long period of time even if the power supply is cut off or the clock signal is cut off. By providing such a memory cell 45, it becomes possible to perform power gating of the cache 40.
- the data of the circuit MemC2 is saved in the BKC2 in the memory cell 45.
- the data held in the circuit BKC2 is written back to the circuit MemC2, so that the PU 21 can be returned to the state before the power is cut off at high speed.
- the circuit BKC2 of the memory cell 45 also has at least a holding circuit having one transistor (MW2) and one capacitive element (CB2) like the circuit BKC1 of FIG. 26B. That is, the circuit BKC2 also has a holding circuit having a configuration similar to that of a standard DRAM 1T1C type memory cell. As with the transistor MW1, an OS transistor having an extremely low off-current may be applied to the transistor MW2. With such a configuration, the circuit BKC2 can also suppress the fluctuation of the potential of the node FN2 which is in an electrically floating state, so that the circuit BKC2 can hold the data for a long period of time.
- MW2 transistor
- CB2 capacitive element
- the data retention time of the circuit BKC2 is determined by the leakage current of the transistor MW2, the capacitance of the capacitive element CB2, and the like.
- the circuit BKC2 can be used as a non-volatile storage circuit that does not require a refresh operation.
- the PMU 60 manages the power supply as in the PU 20. (See FIG. 28).
- the data saving operation of the storage circuit 31 and the cache 40 is performed.
- PSW70 and PSW71 are controlled to stop the power supply to the processor core 30 and the cache 40.
- PSW70 and PSW71 are controlled, and power supply to the processor core 30 and the cache 40 is restarted.
- the data recovery operation of the storage circuit 31 and the cache 40 is performed.
- the processor core 180 shown in FIG. 30 is an example of a circuit that can be used as the processor core 30.
- the processor core 180 includes a control device 181, a program counter 182, a pipeline register 183, a pipeline register 184, a register file 185, an arithmetic logic unit (ALU) 186, and a data bus 187.
- Data exchange between the processor core 180 and peripheral circuits such as the PMU and cache is performed via the data bus 187.
- the control device 181 comprehensively controls the operations of the program counter 182, the pipeline register 183, the pipeline register 184, the register file 185, the ALU186, and the data bus 187, so that the instructions included in the program such as the input application are included.
- the ALU186 has a function of performing various arithmetic operations such as four arithmetic operations and logical operations.
- the program counter 182 is a register having a function of storing the address of the instruction to be executed next.
- the pipeline register 183 is a register having a function of temporarily storing instruction data.
- the register file 185 has a plurality of registers including general-purpose registers, and can store data read from the main memory, data obtained as a result of arithmetic processing of ALU186, and the like.
- the pipeline register 184 is a register having a function of temporarily storing data used for the arithmetic processing of ALU186, data obtained by the arithmetic processing of ALU186, and the like.
- the storage circuit 31 of FIG. 26B is used for a register included in the processor core 180.
- FIG. 31 is a circuit diagram showing an example of the configuration of the storage circuit.
- the storage circuit 190 shown in FIG. 31 functions as a flip-flop circuit.
- a standard flip-flop circuit can be applied to the circuit MemC1, and for example, a master-slave type flip-flop circuit can be applied.
- An example of such a configuration is shown in FIG.
- the flip-flop circuit 110 includes transmission gates (TG1, TG2, TG3, TG4, TG5), inverter circuits (INV1, INV2, INV3, INV4), and NAND circuits (NAND1, NAND2).
- the signal SETT and the signal OSR are control signals output from the PMU 60.
- the signal OSR and its inverted signal are input to the TG5.
- the clock signal CLK and its inversion signal are input to the TG1 to TG4.
- One clocked inverter circuit may be provided instead of TG1 and INV1.
- One clocked NAND circuit may be provided instead of the TG2 and the NAND2.
- a clocked inverter circuit may be provided instead of the TG3 and the INV3.
- the TG5 functions as a switch for controlling the conduction state between the output node of the NAND1 and the node NR1.
- Node NB1 is electrically connected to the input node of circuit BKC10, and node NR1 is electrically connected to the output node of circuit BKC10.
- the circuit BKC10 shown in FIG. 31 functions as a backup circuit of the flip-flop circuit 110.
- the circuit BKC10 has a circuit RTC10 and a circuit PCC10.
- the signals (OSG, OSC, OSR) input to the circuit BKC10 are control signals output from the PMU60.
- the power supply potential VSS is a low power supply potential, and may be, for example, a ground potential (GND) or 0V.
- the power supply potential VSS and the power supply potential VDD are also input to the flip-flop circuit 110 as in the circuit BKC1. In the storage circuit 190, the supply of VDD is controlled by the PMU 60.
- the circuit RTC10 includes a transistor MW1, a transistor MA1, a transistor MR1, a node FN1, and a node NK1.
- the circuit RTC10 has a function of holding data, and here, it is composed of a storage circuit having a 3T type gain cell structure.
- the transistor MW1 is a write transistor and an OS transistor.
- the transistor MR1 is a read transistor, and the transistor MA1 is an amplification transistor and a read transistor. Data is held at node FN1.
- Node NK1 is a data input node.
- Node NR1 is a data output node of circuit RTC10.
- FIG. 31 shows a configuration example in which the circuit BKC10 reads the data of the slave side latch circuit of the flip-flop circuit 110 in the retract operation and writes the data held in the return operation back to the latch circuit on the master side.
- the data to be saved may be the data of the latch circuit on the master side. Further, the data may be returned to the latch circuit on the slave side.
- the TG5 may be provided in the latch circuit on the slave side.
- the transistor MR1 and the transistor MA1 of the circuit RTC10 may be n-type or p-type, and the potential of the signal OSR and the level of the power supply potential supplied to the transistor MA1 may be changed depending on the conductive type of the transistor MR1 and the transistor MA1. .. Further, the logic circuit of the flip-flop circuit 110 may be appropriately set. For example, when the transistor MR1 and the transistor MA1 are p-type transistors, the master side latch circuit may replace NAND1 and INV3, and the slave side latch circuit may replace INV2 and NAND2. Further, VDD may be input to the transistor MA1 instead of VSS.
- the circuit BKC10 Since the circuit BKC10 writes data by voltage, the write power can be suppressed as compared with MRAM which writes by current. Further, since the data is held by the load capacity of the node FN1, there is no limit on the number of times the data can be rewritten as in the flash memory.
- the energy required for writing data corresponds to the energy associated with charging / discharging the electric charge to the capacitive element CB1.
- the energy required for writing data corresponds to the energy consumed when a current flows through the storage element. Therefore, the circuit BKC10 can reduce the energy consumed by saving the data as compared with the case of using an MRAM or the like in which the current continues to flow during the data writing period. Therefore, by providing the circuit BKC10 in the backup circuit, the BET (break-even point arrival time, Break Even Time) can be shortened as compared with the case where the MRAM is provided. As a result, the opportunity for power gating that can reduce the energy consumed is increased, and the power consumption of the semiconductor device can be reduced.
- the circuit PCC10 has a transistor MC1 and a transistor MC2.
- the circuit PCC10 has a function of precharging the node FN1.
- the circuit PCC10 may not be provided. As will be described later, by providing the circuit PCC10, the data save time of the circuit BKC10 can be shortened.
- FIG. 32 is a timing chart showing an example of the operation of the storage circuit 190, and shows the waveforms of the control signals (SLP, SETET, CLK, OSG, OSC, OSR), and the potentials of the power supply potential VDD, the node FN1 and the node NR1. Show change.
- the power supply potential VDD and the signal CLK are supplied to the storage circuit 190.
- the flip-flop circuit 110 functions as a sequential circuit. Since the signal SETT is maintained at a high level, NAND1 and NAND2 function as inverter circuits. In the circuit BKC10, since the transistor MC1 is in the off state and the transistor MC2 and the transistor MW1 are in the on state, the potential of the node FN1 is precharged to a high level.
- the clock signal CLK is stopped.
- the rewriting of the data of the node NB1 is stopped.
- the potential level of node NB1 is low level (“0”) if the potential of node NR1 is high level (“1”), and high if the potential level of node NR1 is low level (“0”).
- the data of the node NB1 is saved in the node FN1 during the period when the signal OSC is at a high level. Specifically, since the transistor MC1 and the transistor MW1 are in the ON state, the node FN1 and the node NB1 are electrically connected.
- node FN1 By lowering the signal OSG and turning off the transistor MW1, the node FN1 is electrically suspended and the circuit BKC10 is in a data holding state.
- the potential of node FN1 is high if node NR1 is low level (“0”) and low level if node NR1 is high level (“1”).
- the voltage scaling operation of the PU 20 can be performed immediately after the signal OSG is lowered to a low level. Further, since the node FN1 is precharged to a high level during normal operation by the transistor MC2, the charge of the node FN1 does not move in the data saving operation for setting the node FN1 to a high level. Therefore, the circuit BKC10 can complete the evacuation operation in a short time.
- the signal CLK may be inactive, and in the example of FIG. 32, the potential of the signal CLK is set to a low level, but it may be set to a high level.
- the PMU 60 performs a voltage scaling operation in conjunction with the falling edge of the signal OSC. As a result, the storage circuit 190 shifts to the low power supply mode.
- the PMU 60 In response to the interrupt request, the PMU 60 returns the storage circuit 190 to the power-on mode.
- the signal CLK is set to a high level.
- the data recovery operation is performed during the period when the signal OSR is at a high level.
- the potential of the node NR1 is precharged to a high level (“1”).
- the TG5 is in a high impedance state and the transistor MR1 is in a conductive state.
- the conduction state of the transistor MA1 is determined by the potential of the node FN1. If the node FN1 is at a high level, the potential of the node NR1 is lowered to a low level (“0”) because the transistor MA1 is in a conductive state. If the node FN1 is at a low level, the potential of the node NR1 is maintained at a high level. That is, the state of the flip-flop circuit 110 is restored to the state before the transition to the hibernation state.
- the storage circuit 190 can shorten the return operation period.
- FIG. 32 shows an example of returning from the power-off mode to the power-on mode.
- the potential of the power supply line for supplying the VDD is the period T on to be stabilized is shortened. In this case, it is preferable that the signal OSR rises faster than when returning from the power off mode.
- FIG. 33 shows an example of the configuration of the memory cell of the cache.
- the memory cell 120 shown in FIG. 33 has a circuit SMC 20 and a circuit BKC 20.
- the circuit SMC 20 may have a circuit configuration similar to that of a standard SRAM memory cell.
- the circuit SMC 20 shown in FIG. 33 includes an inverter circuit INV21, an inverter circuit INV22, a transistor M21, and a transistor M22.
- the circuit BKC 20 functions as a backup circuit of the circuit SMC 20.
- the circuit BKC20 includes a transistor MW11, a transistor MW12, a capacitive element CB11, and a capacitive element CB12.
- the transistors MW11 and MW12 are OS transistors.
- the circuit SMC20 has two 1T1C type holding circuits, and data is held in the node SN1 and the node SN2, respectively.
- the holding circuit including the transistor MW11 and the capacitive element CB11 has a function of backing up the data of the node NET1.
- the holding circuit including the transistor MW12 and the capacitive element CB12 has a function of backing up the data of the node NET2.
- the memory cell 120 is supplied with power potentials VDDMC and VSS.
- the memory cell 120 is electrically connected to the wiring (WL, BL, BLB, BRL).
- a signal SLC is input to the wiring WL.
- the data signal D and the data signal DB are input to the wiring BL and the wiring BLB.
- the data is read out by detecting the potentials of the wiring BL and the wiring BLB.
- the signal OSS is input to the wiring BRL.
- the signal OSS is a signal input from the PMU 60.
- FIG. 34 is an example of the timing chart of the memory cell 120.
- the PMU 60 In response to the interrupt request, the PMU 60 returns the cache 40 to the normal state.
- the signal OSS is set to a high level, and the data held in the circuit BKC20 is written back to the circuit SMC20.
- the PMU 60 performs a voltage scaling operation and a power gating operation to return the storage circuit 190 to the power-on mode.
- the signal CLK when the potential of the power line that supplies VDD becomes stable, the signal CLK is set to a high level.
- the signal OSS is returned to a low level and the data recovery operation is terminated.
- the states of the nodes SN1 and SN2 have returned to the state immediately before the hibernation state.
- Electronic devices that can use the imaging device according to one aspect of the present invention include a display device, a personal computer, an image storage device or image reproduction device provided with a recording medium, a mobile phone, a game machine including a portable type, and a portable data terminal.
- Electronic book terminals video cameras, cameras such as digital still cameras, goggles type displays (head mount displays), navigation systems, sound reproduction devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, multifunction printers , Automatic cash deposit / payment machines (ATMs), vending machines, etc. Specific examples of these electronic devices are shown in FIGS. 35A to 35F.
- FIG. 35A is an example of a mobile phone, which includes a housing 981, a display unit 982, an operation button 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, and the like.
- the mobile phone includes a touch sensor on the display unit 982. All operations such as making a phone call or inputting characters can be performed by touching the display unit 982 with a finger or a stylus.
- An imaging device according to an aspect of the present invention and an operation method thereof can be applied to the mobile phone.
- FIG. 35B is a portable data terminal, which includes a housing 911, a display unit 912, a speaker 913, a camera 919, and the like. Information can be input and output by the touch panel function of the display unit 912. In addition, characters and the like can be recognized from the image acquired by the camera 919, and the characters can be output as voice by the speaker 913.
- An imaging device according to an aspect of the present invention and an operation method thereof can be applied to the portable data terminal.
- FIG. 35C is a surveillance camera, which has a support base 951, a camera unit 952, a protective cover 953, and the like.
- the camera unit 952 is provided with a rotation mechanism or the like, and by installing it on the ceiling, it is possible to take an image of the entire surroundings.
- An image pickup apparatus according to an aspect of the present invention and an operation method thereof can be applied to an element for image acquisition in the camera unit.
- the surveillance camera is a conventional name and does not limit its use.
- a device having a function as a surveillance camera is also called a camera or a video camera.
- FIG. 35D is a video camera, which includes a first housing 971, a second housing 972, a display unit 973, an operation key 974, a lens 975, a connection unit 976, a speaker 977, a microphone 978, and the like.
- the operation key 974 and the lens 975 are provided in the first housing 971, and the display unit 973 is provided in the second housing 972.
- An imaging device according to one aspect of the present invention and an operation method thereof can be applied to the video camera.
- FIG. 35E is a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a light emitting unit 967, a lens 965, and the like.
- An imaging device according to one aspect of the present invention and an operation method thereof can be applied to the digital camera.
- FIG. 35F is a wristwatch-type information terminal, which includes a display unit 932, a housing / wristband 933, a camera 939, and the like.
- the display unit 932 includes a touch panel for operating the information terminal.
- the display unit 932 and the housing / wristband 933 have flexibility and are excellent in wearability to the body.
- An imaging device according to an aspect of the present invention and an operation method thereof can be applied to the information terminal.
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Abstract
Description
図2は、画素ブロック200および回路201を説明する図である。
図3A、図3Bは、画素100を説明する図である。
図4A、図4Bは、画素100を説明する図である。
図5は、通常の撮像動作を説明するタイミングチャートである。
図6は、モーション検出動作(差分なし)および積和演算動作を説明するタイミングチャートである。
図7は、モーション検出動作(差分あり)を説明するタイミングチャートである。
図8は、回路304を説明する図である。
図9は、回路304の動作を説明するタイミングチャートである。
図10は、回路304の動作を説明するタイミングチャートである。
図11A、図11Bは、回路301および回路302を説明する図である。
図12は、メモリセルを説明する図である。
図13A、図13Bは、ニューラルネットワークの構成例を示す図である。
図14は、撮像装置の動作を説明するフローチャートである。
図15A、図15Bは、撮像装置の動作を説明する図である。
図16A乃至図16Dは、撮像装置の画素の構成を説明する図である。
図17A乃至図17Cは、光電変換デバイスの構成を説明する図である。
図18は、画素を説明する断面図である。
図19A乃至図19Cは、Siトランジスタを説明する図である。
図20は、画素を説明する断面図である。
図21は、画素を説明する断面図である。
図22A乃至図22Dは、OSトランジスタを説明する図である。
図23は、画素を説明する断面図である。
図24A1乃至図24A3、図24B1乃至図24B3は、撮像装置を収めたパッケージ、モジュールの斜視図である。
図25Aは、メモリ回路を説明するブロック図である。図25B乃至図25Eは、メモリセルを説明する回路図である。
図26A、図26Bは、半導体装置の構成例を示すブロック図である。
図27A乃至図27Dは、半導体装置の電源管理の動作例を説明する図である。
図28は、半導体装置の電源管理の動作例を示すフローチャートである。
図29A、図29Bは、半導体装置の構成例を示すブロック図である。
図30は、プロセッサコアの構成例を示すブロック図である。
図31は、記憶回路の構成例を示す回路図である。
図32は、記憶回路の動作例を説明するタイミングチャートである。
図33は、キャッシュのメモリセルの構成例を示す回路図である。
図34は、メモリセルの動作例を説明するタイミングチャートである。
図35A乃至図35Fは、電子機器を説明する図である。
本実施の形態では、本発明の一態様である撮像装置について、図面を参照して説明する。
図1は、本発明の一態様の撮像装置を説明するブロック図である。撮像装置は、画素アレイ300と、回路201と、回路301と、回路302と、回路303と、回路304と、回路305と、を有する。なお、回路201および回路301乃至回路305は、単一の回路構成に限らず、複数の回路で構成される場合がある。または、上記いずれか複数の回路が統合されていてもよい。また、上記以外の回路が接続されてもよい。
画素100は、図3Aに示すように、光電変換デバイス101と、トランジスタ102と、トランジスタ103と、キャパシタ104と、トランジスタ105と、キャパシタ106と、トランジスタ107と、トランジスタ108と、トランジスタ109を有することができる。
図2に示すように、各画素100は、配線112で互いに電気的に接続される。回路201は、各画素100のトランジスタ107に流れる電流の和を用いて演算を行うことができる。
まず、図5に示すタイミングチャートを用いて、通常の撮像モードの説明を行う。なお、通常撮像モードでは、積和演算を行わないため、配線111の電位は常時“L”、配線124の電位は、常時“H”とし、キャパシタ106の他方の電極の電位を固定することが好ましい。また、ここでは、図3Aまたは図3Bの構成の画素100の動作について説明する。
次に、図6に示すタイミングチャートを用いて、画素100のモーション検出機能、ならびに画素ブロック200および回路201による積和演算について説明する。
図8は、回路304に用いることのできる回路の一例である。当該回路はシフトレジスタ回路であり、複数の論理回路(SR)が電気的に接続されている。それぞれの論理回路(SR)には、配線RES、配線VSS_RDRS、配線RPWC_SE[0:3]、配線RCLK[0:3]、配線RSPなどの信号線が接続され、それぞれの信号線に適切な信号電位を入力することで、当該論理回路(SR)から選択信号電位の出力を順次行うことができる。
図11Aは、回路201と接続する回路301および回路302を説明する図である。回路201から出力される積和演算結果のデータは、回路301に順次入力される。回路301には、前述したデータAとデータBとの差分を演算する機能のほかに、様々な演算機能を有していてもよい。例えば、回路301は、回路201と同等の構成とすることができる。または、回路301の機能をソフトウェア処理で代替えしてもよい。
次に、図14に示すフローチャートを用いて、本発明の一態様の撮像装置の動作方法の一例を説明する。
本実施の形態では、本発明の一態様の撮像装置の構造例などについて説明する。
図16Aは、撮像装置の画素の構造の一例を示す図であり、層561および層563の積層構造とすることができる。
次に、撮像装置の積層構造について、断面図を用いて説明する。なお、以下に示す絶縁層および導電層などの要素は一例であり、さらに他の要素が含まれていてもよい。または、以下に示す要素の一部が省かれていてもよい。また、以下に示す積層構造は、必要に応じて、貼り合わせ工程、研磨工程などを用いて形成することができる。
層563bは、シリコン基板611に設けられた機能回路を有する。ここでは、機能回路の一部として、回路201が有するキャパシタ202、トランジスタ203およびトランジスタ204を示している。キャパシタ202の一方の電極と、トランジスタ203のソースまたはドレインの一方と、トランジスタ204のゲートは電気的に接続されている。
層563aは、画素100の要素を有する。ここでは、画素100の要素の一部として、トランジスタ102およびトランジスタ108を示している。図18に示す断面図では、両者の電気的な接続は図示されていない。
層561は、光電変換デバイス101を有する。光電変換デバイス101は、層563a上に形成することができる。図18では、光電変換デバイス101として、図17Cに示す有機光導電膜を光電変換層に用いた構成を示している。なお、ここでは、層567aをカソード、層567eをアノードとする。
層560は、層561上に形成される。層560は、遮光層671、光学変換層672およびマイクロレンズアレイ673を有する。
次に、層563bと層563aの貼り合わせについて説明する。
図20は、図18に示す積層構造の変形例であり、層561が有する光電変換デバイス101の構成、および層563aの一部構成が異なり、層561と層563aとの間にも貼り合わせ面を有する構成である。
図21は、層560、561、562、563を有し、貼り合わせ面を有さない積層体の断面図の一例である。層563には、Siトランジスタが設けられる。層562には、OSトランジスタが設けられる。ここでは、層562および層563にメモリ回路の構成要素が設けられ、層563にメモリ回路の駆動回路が設けられる例を説明する。なお、層561および層560の構成は、図18に示す構成と同一であるため、ここでは説明を省略する。
層563は、シリコン基板611に設けられた機能回路を有する。ここでは、機能回路の一部として、メモリ回路の駆動回路が有するトランジスタ251、メモリ回路が有するトランジスタ252、253を示している。
層562bは、層563上に形成される。層562bは、OSトランジスタを有する。ここでは、メモリ回路の一部として、トランジスタ254を示している。
層562aは、層562b上に形成される。層562aは、OSトランジスタを有する画素100の要素を有する。ここでは、画素100の要素の一部として、トランジスタ102およびトランジスタ103を示している。
図23は、図22に示す積層構造の変形例であり、層561が有する光電変換デバイス101の構成、および層562aの一部構成が異なり、層561と層562aとの間に貼り合わせ面を有する構成である。
本実施の形態では、実施の形態2で説明した機能回路として用いることができ、画素回路と積層することのできるメモリ回路について説明する。
図25Bに、DRAM型のメモリセル321aAの回路構成例を示す。本明細書等において、OSトランジスタを用いたDRAMを、DOSRAM(Dynamic Oxide Semiconductor Random Access Memory)と呼ぶ。メモリセル321aAは、トランジスタM11と、キャパシタCsと、を有する。
図25Cに、2つのトランジスタと1つのキャパシタを有するゲインセル型(「2Tr1C型」ともいう)のメモリセル321aBの回路構成例を示す。メモリセル321aBは、トランジスタM11と、トランジスタM3と、キャパシタCsと、を有する。
本実施の形態では、実施の形態2で説明した機能回路として用いることができ、画素回路と積層することのできる半導体装置ついて説明する。
図26A、図26Bを参照して、半導体装置およびその電源管理を説明する。図26Aに示す半導体装置は、電源回路10、および処理装置(PU:Processing Unit)20を有する。PU20は命令を実行する機能を有する回路である。PU20は、1つのチップに集積された複数の機能回路を有する。PU20は、プロセッサコア30、電源管理装置(PMU)60、クロック制御回路65、パワースイッチ(PSW)70、並びに、端子80乃至端子83を有する。図26Aには、電源回路10が、PU20と異なるチップに設けられている例を示している。端子80は、電源回路10から電源電位VDDが入力される端子である。端子81は、外部から基準クロック信号CLKMが入力される端子である。端子82は、外部から信号INTが入力される端子である。信号INTは割り込み処理を要求する割り込み信号である。信号INTは、PU20およびPMU60に入力される。端子83は、PMU60で生成された制御信号が出力される端子であり、電源回路10と電気的に接続されている。
プロセッサコア30は、命令を処理することができる機能を有する回路であり、演算処理回路と呼ぶことが可能である。記憶回路31、および組み合わせ回路32等を有しており、これらにより、各種の機能回路が構成されている。例えば、記憶回路31は、レジスタに含まれる。なお、Dは入力信号、Qは出力信号を表している。
PMU60は、パワーゲーティング動作、クロックゲーティング動作、およびボルテージスケーリング動作等を制御する機能を有する。より具体的には、PMU60は、電源回路10を制御することができる機能、記憶回路31を制御することができる機能、クロック制御回路65を制御することができる機能、およびPSW70を制御することができる機能を有する。そのため、PMU60は、これら回路(10、31、65、70)を制御する制御信号を生成する機能を有する。PMU60は回路61を有する。回路61は、時間を計測することができる機能を有する。PMU60は、回路61で得られる時間に関するデータをもとに、電源管理を行うことができる機能を有する。
図29Aに、図26Aの半導体装置の変形例を示す。図29Aに示す処理装置(PU)21は、PU20にキャッシュ40、およびパワースイッチ(PSW)71を追加した構成である。キャッシュ40は、PU20と同様にパワーゲーティングおよびボルテージスケーリングが可能とされており、PU21の電源モードと連動してキャッシュ40の電源モードも変化する。PSW71は、キャッシュ40への電源電位MVDDの供給を制御する回路であり、PMU60により制御される。ここでは、PSW71を介してキャッシュ40に入力される電源電位をVDD_MEMとしている。キャッシュ40には、プロセッサコア30と同様にPMU60からの制御信号、およびクロック制御回路65からゲーテッドクロック信号が入力される。
キャッシュ40は、使用頻度の高いデータを一時的に記憶しておく機能を有する記憶装置である。キャッシュ40は、メモリアレイ41、周辺回路42、および制御回路43を有する。メモリアレイ41は、複数のメモリセル45を有する。制御回路43は、プロセッサコア30の要求に従って、キャッシュ40の動作を制御する。例えば、メモリアレイ41の書き込み動作、読み出し動作を制御する。周辺回路42は、制御回路43からの制御信号に従い、メモリアレイ41を駆動する信号を生成する機能を有する。メモリアレイ41は、データを保持するメモリセル45を有する。
図30に示すプロセッサコア180は、プロセッサコア30として用いることのできる回路の一例である。プロセッサコア180は、制御装置181、プログラムカウンタ182、パイプラインレジスタ183、パイプラインレジスタ184、レジスタファイル185、算術論理演算装置(ALU)186、およびデータバス187を有する。プロセッサコア180とPMUやキャッシュ等の周辺回路とのデータのやり取りは、データバス187を介して行われる。
図26Bに示す記憶回路31のより具体的な構成例を説明する。図31は、記憶回路の構成の一例を示す回路図である。図31に示す記憶回路190はフリップフロップ回路として機能する。
図32は、記憶回路190の動作の一例を示すタイミングチャートであり、制御信号(SLP、RESET、CLK、OSG、OSC、OSR)の波形、並びに、電源電位VDD、ノードFN1およびノードNR1の電位の変化を示す。
記憶回路190には、電源電位VDD、および信号CLKが供給されている。フリップフロップ回路110が順序回路として機能している。信号RESETは高レベルが維持されるため、NAND1およびNAND2はインバータ回路として機能する。回路BKC10では、トランジスタMC1がオフ状態であり、トランジスタMC2およびトランジスタMW1がオン状態であるため、ノードFN1の電位は高レベルにプリチャージされている。
まず、クロック信号CLKが停止される。これにより、ノードNB1のデータの書き換えが停止される。図32の例では、ノードNB1の電位レベルは、ノードNR1の電位が高レベル(”1”)であれば、低レベル(”0”)であり、低レベル(”0”)であれば高レベル(”1”)である。信号OSCが高レベルの期間に、ノードNB1のデータがノードFN1に退避される。具体的には、トランジスタMC1およびトランジスタMW1がオン状態であるため、ノードFN1とノードNB1が電気的に接続されている。信号OSGを低レベルにして、トランジスタMW1をオフ状態にすることで、ノードFN1が電気的に浮遊状態となり、回路BKC10はデータの保持状態となる。ノードFN1の電位は、ノードNR1が低レベル(“0”)であれば高レベルであり、高レベル(”1”)であれば低レベルである。
信号OSCの立下りに連動して、PMU60は、ボルテージスケーリング動作を行う。これにより記憶回路190は低電源モードに移行する。
低電源モードに移行してから一定期間経過したら、PMU60は、パワーゲーティング動作を行い、記憶回路190を電源オフモードにする。
割り込み要求に従い、PMU60は、記憶回路190を電源オンモードに復帰する。図32の例では、VDDを供給する電源線の電位が安定すると、信号CLKは高レベルになるようにしている。
信号OSRが高レベルの期間にデータ復帰動作が行われる。信号RESETを高レベルとすることで、ノードNR1の電位は高レベル(”1”)にプリチャージされる。信号OSRを高レベルとすることで、TG5がハイインピーダンス状態となり、かつトランジスタMR1が導通状態となる。トランジスタMA1の導通状態はノードFN1の電位で決まる。ノードFN1が高レベルであれば、トランジスタMA1が導通状態であるため、ノードNR1の電位は低下し、低レベル(”0”)となる。ノードFN1が低レベルであれば、ノードNR1の電位は高レベルが維持される。つまり、休止状態に移行する前の状態に、フリップフロップ回路110の状態が復帰される。
信号CLKの供給を再開することで、通常動作が可能な状態に復帰する。信号OSGを高レベルにすることで、ノードFN1は、回路PCC10によりプリチャージされ、高レベルとなる。
以下に、キャッシュ40をSRAMで構成する例を説明する。
図33にキャッシュのメモリセルの構成の一例を示す。図33に示すメモリセル120は、回路SMC20および回路BKC20を有する。回路SMC20は、標準的なSRAMのメモリセルと同様な回路構成とすればよい。図33に示す回路SMC20は、インバータ回路INV21、インバータ回路INV22、トランジスタM21、およびトランジスタM22を有する。
メモリセル120の動作の一例を説明する。図34は、メモリセル120のタイミングチャートの一例である。
回路MemC20にアクセス要求が行われ、データの書き込み読み出しが行われる。回路BKC20では、信号OSSは低レベルであるため、ノードSN1およびノードSN2が電気的に浮遊状態となっており、データ保持状態である。図34の例では、ノードSN1の電位は低レベル(”0”)であり、ノードSN2の電位は、高レベル(”1”)である。
信号OSSが高レベルにすることで、トランジスタMW11、MW12が導通状態となり、ノードSN1、SN2は、それぞれ、ノードNET1、NET2と同じ電位レベルとなる。図34の例では、ノードSN1、SN2の電位は、それぞれ、高レベル、低レベルとなる。信号OSSが低レベルとなり、回路BKC20がデータ保持状態となり、データ退避動作が終了する。
信号OSSの立下りに連動して、PMU60は、ボルテージスケーリング動作を行う。これによりキャッシュ40は低電源モードに移行する。
低電源モードに移行してから一定期間経過したら、PMU60は、パワーゲーティング動作を行い、キャッシュ40を電源オフモードにする。
割り込み要求に従い、PMU60はキャッシュ40を通常状態に復帰させる。信号OSSを高レベルにして、回路BKC20で保持されているデータを、回路SMC20に書き戻す。信号OSSが高レベルである期間中に、PMU60は、ボルテージスケーリング動作およびパワーゲーティング動作を行い、記憶回路190を電源オンモードに復帰する。図32の例では、VDDを供給する電源線の電位が安定すると、信号CLKは高レベルになるようにしている。VDDMCを供給する電源線の電位が安定したら、信号OSSを低レベルに戻し、データ復帰動作を終了させる。ノードSN1、SN2の状態は、休止状態になる直前の状態に復帰している。
VDDMCの供給が再開されることで、回路SMC20は通常動作が可能な通常モードに復帰する。
本発明の一態様に係る撮像装置を用いることができる電子機器として、表示機器、パーソナルコンピュータ、記録媒体を備えた画像記憶装置または画像再生装置、携帯電話、携帯型を含むゲーム機、携帯データ端末、電子書籍端末、ビデオカメラ、デジタルスチルカメラ等のカメラ、ゴーグル型ディスプレイ(ヘッドマウントディスプレイ)、ナビゲーションシステム、音響再生装置(カーオーディオ、デジタルオーディオプレイヤー等)、複写機、ファクシミリ、プリンタ、プリンタ複合機、現金自動預け入れ払い機(ATM)、自動販売機などが挙げられる。これら電子機器の具体例を図35A乃至図35Fに示す。
Claims (10)
- 画素と、第1の回路と、第2の回路と、を有する撮像装置であって、
前記第1の回路は、前記画素に第1の電位を供給する機能を有し、
前記画素は、第1のデータおよび第2のデータを取得する機能を有し、
前記画素は、前記第1のデータと前記第2のデータとの差分である第3のデータを生成する機能を有し、
前記画素は、前記第3のデータに前記第1の電位に基づく電位を加算して第4のデータを生成する機能を有し、
前記第2の回路は、前記画素が出力する前記第3のデータと、前記画素が出力する前記第4のデータとの差分に相当する第5のデータを生成する機能を有する撮像装置。 - 画素ブロックと、第1の回路と、第2の回路と、を有する撮像装置であって、
前記画素ブロックは、複数の画素を有し、
前記第1の回路は、前記画素に第1の電位を供給する機能を有し、
前記画素は、第1のデータおよび第2のデータを取得する機能を有し、
前記画素は、前記第1のデータと前記第2のデータとの差分である第3のデータを生成する機能を有し、
前記画素は、前記第3のデータに前記第1の電位に基づく電位を加算して第4のデータを生成する機能を有し、
前記第2の回路は、前記画素ブロックの前記複数の画素が出力する前記第3のデータの和と、前記画素ブロックの前記複数の画素が出力する前記第4のデータの和との差分に相当する第5のデータを生成する機能を有する撮像装置。 - 請求項1または2において、
前記画素は、光電変換デバイスと、第1のトランジスタと、第2のトランジスタと、第3のトランジスタと、第4のトランジスタと、第5のトランジスタと、第6のトランジスタと、第1のキャパシタと、第2のキャパシタと、を有し、
前記光電変換デバイスの一方の電極は、前記第1のトランジスタのソースまたはドレインの一方と電気的に接続され、
前記第1のトランジスタのソースまたはドレインの他方は、前記第2のトランジスタのソースまたはドレインの一方、および前記第1のキャパシタの一方の電極と電気的に接続され、
前記第1のキャパシタの他方の電極は、前記第3のトランジスタのソースまたはドレインの一方、前記第2のキャパシタの一方の電極、および前記第4のトランジスタのゲートと電気的に接続され、
前記第4のトランジスタのソースまたはドレインの一方は、前記第5のトランジスタのソースまたはドレインの一方と電気的に接続され、
前記第2のキャパシタの他方の電極は、前記第6のトランジスタのソースまたはドレインの一方と電気的に接続され、
前記第5のトランジスタのソースまたはドレインの他方は、前記第2の回路と電気的に接続され、
前記第6のトランジスタのソースまたはドレインの他方は、前記第1の回路と電気的に接続されている撮像装置。 - 請求項1乃至3のいずれか一項において、
前記第2の回路は、相関二重サンプリング回路である撮像装置。 - 請求項1乃至4のいずれか一項において、
前記画素が有するトランジスタは、チャネル形成領域に金属酸化物を有し、前記金属酸化物は、Inと、Znと、M(MはAl、Ti、Ga、Ge、Sn、Y、Zr、La、Ce、NdまたはHfの一つまたは複数)と、を有する撮像装置。 - 第1のフレームレートで撮像動作を開始する第1のステップと、
基準画像を撮像し、記憶する第2のステップと、
比較画像を撮像する第3のステップと、
前記基準画像と前記比較画像の差分データを取得する第4のステップと、
前記差分データから第2の特徴量を抽出する第5のステップと、
予め設定された第1の特徴量と、前記第2の特徴量を比較する第6のステップと、
を上記順序で行い、
前記第2の特徴量から前記第1の特徴量が検出されたと判断されたとき、
第2のフレームレートに切り替えて撮像動作を行い、
前記第2の特徴量から前記第1の特徴量が検出されないと判断されたとき、
前記第3のステップに戻る撮像装置の動作方法。 - 請求項6において、
前記第2のフレームレートは、前記第1のフレームレートより大きい撮像装置の動作方法。 - 請求項6または7において、
前記第1のフレームレートは、0.1fps以上10fps以下であって、
前記第2のフレームレートは、15fps以上240fps以下である撮像装置の動作方法。 - 請求項6乃至8のいずれか一項において、
前記第1のフレームレートで撮像動作が行われている期間中は、パワーゲーティングが行われる撮像装置の動作方法。 - 請求項1乃至5のいずれか一項に記載の撮像装置と、レンズと、を有する電子機器。
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US17/628,293 US11937007B2 (en) | 2019-07-26 | 2020-07-13 | Imaging device, operation method thereof, and electronic device |
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JP2007318262A (ja) * | 2006-05-23 | 2007-12-06 | Sanyo Electric Co Ltd | 撮像装置 |
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