WO2021016804A1 - 三维存储器及其制作方法 - Google Patents

三维存储器及其制作方法 Download PDF

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Publication number
WO2021016804A1
WO2021016804A1 PCT/CN2019/098174 CN2019098174W WO2021016804A1 WO 2021016804 A1 WO2021016804 A1 WO 2021016804A1 CN 2019098174 W CN2019098174 W CN 2019098174W WO 2021016804 A1 WO2021016804 A1 WO 2021016804A1
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WIPO (PCT)
Prior art keywords
metal wire
connection
metal
line
substrate
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PCT/CN2019/098174
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English (en)
French (fr)
Inventor
张刚
霍宗亮
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中国科学院微电子研究所
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Priority to US17/631,321 priority Critical patent/US20220262812A1/en
Priority to PCT/CN2019/098174 priority patent/WO2021016804A1/zh
Publication of WO2021016804A1 publication Critical patent/WO2021016804A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

Definitions

  • the present disclosure belongs to the technical field of semiconductor memory and integration, and relates to a three-dimensional memory and a manufacturing method thereof.
  • Three-dimensional (3D) NAND is an emerging type of flash memory, which solves the limitations imposed by planar (2D) NAND flash memory by stacking storage cells.
  • 3D NAND memory technology is currently the country's key technology.
  • the metal lines metal-1, metal-2 and the (lower) connection circuit face the difficult problem of complex circuit design and layout.
  • the present disclosure provides a three-dimensional memory and a manufacturing method thereof, so as to at least partially solve the above-mentioned technical problems.
  • a three-dimensional memory including: a memory unit and a logic control unit that are attached to each other on the front side, the logic control unit is connected to the control circuit, and is characterized in that the second metal wire of the memory unit The first metal wire and the first metal wire are respectively arranged on the upper and lower sides of the channel layer in the memory cell, and both the first metal wire and the second metal wire are electrically connected with the control circuit.
  • the second metal wire is arranged in the substrate of the memory cell and is insulated from the substrate; the first metal wire of the memory cell is arranged on the front surface of the memory cell.
  • a plurality of channel holes are provided in the channel layer of the memory cell, and each channel hole is electrically connected to the first metal line; the common selection line is electrically connected to the second metal line. Sexual connection.
  • the top of the channel hole is electrically connected to the first metal wire through a first connection hole.
  • the bottom of the common selection line is directly electrically connected to the second metal line, or the bottom of the common selection line is electrically connected to the second metal line through a second connection hole. Sexual connection.
  • the first metal wire is electrically connected to the logic control unit through a top connection circuit; the second metal wire is electrically connected to the control circuit through a bottom connection circuit.
  • a plurality of connection holes are provided on the back of the storage unit, the tops of the plurality of connection holes are connected to the control circuit, and the tops of the plurality of connection holes stop at the top connection circuit and the bottom connection circuit respectively.
  • a method for manufacturing a three-dimensional memory which includes: arranging a second metal line and a first metal line on the upper and lower sides of a channel layer in a memory cell, respectively; connecting the memory cell and the logic control unit The front faces of the are attached to each other, the logic control unit is connected to the control circuit, and both the first metal wire and the second metal wire are electrically connected to the control circuit.
  • the step of respectively arranging the second metal line and the first metal line on the upper and lower sides of the channel layer in the memory cell includes:
  • the laminated material as the channel layer is grown, and the channel hole and the common selection line are formed by patterning.
  • the bottom of the common selection line stops at the second Connecting hole
  • a first connection hole and a first metal line are formed above the structure where the channel hole and the common selection line are formed to form a memory cell in which the first metal line and the second metal line are respectively arranged on the upper and lower sides of the channel layer.
  • the front surfaces of the storage unit and the logic control unit are attached to each other, the logic control unit is connected to the control circuit, and the first metal wire and the second metal wire are electrically connected to the control circuit.
  • the steps to connect include:
  • a plurality of connection holes are made on the back of the storage unit, and the top of the plurality of connection holes is connected to the control circuit.
  • the plurality of connection holes include a third connection hole and a fourth connection hole.
  • the bottom of the third connection hole stops at the top connection circuit.
  • the bottom of the four connection holes stops at the bottom connection circuit, so that the logic control unit is connected to the control circuit through the third connection hole to realize the electrical connection between the first metal wire and the control circuit, so that the second metal wire passes through the bottom connection circuit and the first metal wire.
  • the four connecting holes are electrically connected with the control circuit.
  • the second metal line and the first metal line of the memory cell are respectively laid on the upper and lower sides of the channel layer in the memory cell, and the first metal line and the second metal line are arranged separately so that the distribution of the metal lines becomes Balance, reduce or avoid the deformation of the memory cell; at the same time, the metal wiring is simplified by dispersing the first metal line and the second metal line, so that the wiring layout of the first metal line and the second metal line and the control circuit is relatively simple In addition, the reliability of the connection is improved, and the connection reliability problem caused by the complicated layout and process problems in the prior art is avoided.
  • connection hole including the first connection hole
  • the fourth connection hole to realize the connection process between the first metal wire and the second metal wire and the control circuit
  • Figure 1 is a three-dimensional schematic diagram and a corresponding cross-sectional schematic diagram of a three-dimensional NAND memory in the prior art.
  • FIG. 2 is a schematic cross-sectional view of the three-dimensional memory according to the first embodiment of the present disclosure.
  • FIG. 3 is a schematic cross-sectional view of a three-dimensional memory according to a second embodiment of the present disclosure.
  • FIG. 4 is a flowchart of a manufacturing method for manufacturing the three-dimensional memory shown in the first embodiment according to the third embodiment of the present disclosure.
  • FIG. 5 is a flowchart of a manufacturing method for manufacturing the three-dimensional memory shown in the second embodiment according to the fourth embodiment of the present disclosure.
  • FIG. 1 is a three-dimensional schematic diagram and a corresponding cross-sectional schematic diagram of a three-dimensional NAND memory in the prior art.
  • the channel hole CH of the storage chip is connected to the metal-1 line through the C1CH connection hole, and the common selection line (ACS) is connected to the metal-2 line through the C1ACS connection hole.
  • the C1ACS connection holes and metal-1 lines are arranged alternately and insulated from each other.
  • the dashed frame indicates the metal-1 line to illustrate that there is no cross between the C1ACS connection holes and the metal-1 line, and the two are insulated from each other.
  • Metal-1 line and metal-2 line are connected through the connecting circuit and logic control chip, and then the chip operation terminal is led out through the deep hole.
  • the metal-1 line and the metal-2 line are interlaced and insulated from each other, the common selection line and the metal-2 line are correspondingly connected, and the trench hole and the metal-1 line are correspondingly connected.
  • the connections are in the same direction and area. To achieve staggered and effective connections, the corresponding metal connection and wiring are complicated, and the reliability of the connection is poor due to complex layout and process problems; 2.
  • the metal wires are all concentrated in the lower part of the storage unit ( In other words, the top, upper and lower parts of the storage unit are described in the direction of the drawings in the manual, and the top and bottom are based on the front and back of the corresponding storage unit, the top corresponds to the front of the storage unit, and the bottom corresponds to the back of the storage unit) and
  • the silicon structure (substrate) is concentrated on the upper part of the memory cell, and the structural stress imbalance causes the deformation of the memory cell.
  • the present disclosure provides a three-dimensional memory.
  • the second metal line and the first metal line of the memory cell are respectively laid on the upper and lower sides of the channel layer in the memory cell, and the first metal line and the The second metal line balances the distribution of the metal line, reducing or avoiding the deformation of the memory cell; at the same time, the metal wiring is simplified by dispersing the first metal line and the second metal line, so that the first metal line and the second metal line
  • the layout of the connection circuit between the metal wire and the control circuit is relatively simple, and the reliability of the connection is improved, and the connection reliability problem caused by the complicated layout and process problems in the prior art is avoided.
  • Figures 2 and 3 illustrate the direction of the front and back of the memory cell 1.
  • top connection circuit and “bottom connection circuit”.
  • bottom connection circuit According to the storage unit, the top and bottom are correspondingly seen after being placed face-up.
  • upper and lower are described in the upper and lower directions corresponding to the drawings in the specification.
  • each "connection hole” and “common selection line” are shown in a trapezoid shape.
  • the “top” or “bottom” is described according to the following principle: according to the etching process during preparation, the etching width of the top is higher than that of the bottom The etching width, so the corresponding long side is “top” and the corresponding short side is “bottom”.
  • the top of the channel hole 13 is the long side, the bottom is the short side, and the top of the channel hole 13 passes through the first
  • a connection hole 31 is electrically connected to the first metal line 21
  • the top of the common selection line 14 is the long side and the bottom is the short side
  • the bottom of the common selection line 14 is electrically connected to the second metal line 22 through the second connection hole 32
  • the long side of the third connecting hole 61 is the top, the short side is the bottom, the top of the third connecting hole 61 is connected to the control circuit, and the bottom of the third connecting hole 61 stops at the top connecting circuit 41.
  • a three-dimensional memory is provided.
  • FIG. 2 is a schematic cross-sectional view of the three-dimensional memory according to the first embodiment of the present disclosure.
  • the three-dimensional memory of the present disclosure includes: a storage unit 1 and a logic control unit 5 that are attached to each other on the front side.
  • the logic control unit 5 is connected to a control circuit, and is characterized in that the second storage unit 1
  • the metal wires 22 and the first metal wires 21 are respectively arranged on the upper and lower sides of the channel layer 12 in the memory cell 1, and the first metal wires 21 and the second metal wires 22 are electrically connected to the control circuit.
  • the first metal wire 21 and the second metal wire 22 are directly or indirectly led out to the chip operation terminal through a plurality of connection holes (including the third connection hole 61 and the fourth connection hole 62), thereby connecting with the control circuit connection.
  • the second metal wire 22 is arranged in the substrate 11 of the memory cell 1 and insulated from the substrate 11; the first metal wire 21 of the memory cell 1 is arranged On the front of the storage unit 1.
  • the substrate 11 is a silicon substrate or an SOI substrate.
  • a plurality of channel holes 13 are provided in the channel layer 12 of the memory cell 1, and each channel hole 13 is electrically connected to the first metal line 21;
  • the wire 14 is electrically connected to the second metal wire 22.
  • the channel layer 12 is a structure formed by a plurality of stacked layer pairs, for example, a stacked layer pair formed by a first stacked material/second stacked material, and the first stacked material 121 is silicon oxide;
  • the second laminate material 122 is silicon nitride.
  • the top of the channel hole 13 is electrically connected to the first metal wire 21 through the first connection hole 31.
  • the bottom of the common selection line 14 is electrically connected to the second metal line 22 through the second connection hole 32.
  • the first metal line 21 is electrically connected to the logic control unit 5 through a top connection circuit 41; the second metal line 22 is electrically connected to the logic control unit 5 through a bottom connection circuit 42 The control circuit is electrically connected.
  • the back of the storage unit 1 is provided with a plurality of connecting holes, the tops of the plurality of connecting holes are connected to the control circuit, and the tops of the plurality of connecting holes stop at the top connecting circuit and the bottom connecting circuit respectively.
  • the plurality of connecting holes includes a third connecting hole 61 and a fourth connecting hole 62. The tops of the third connecting hole 61 and the fourth connecting hole 62 are both connected to the control circuit, and the bottom of the third connecting hole 61 stops.
  • the bottom of the fourth connection hole 62 stops at the bottom connection circuit 42, so that the logic control unit 5 is connected to the control circuit through the third connection hole 61 to realize the electrical connection between the first metal wire 21 and the control circuit , So that the second metal wire 22 is electrically connected to the control circuit through the bottom connection circuit 42 and the fourth connection hole 62.
  • a protective layer 15 is formed on the top and sidewalls of the channel layer 12, and the material of the protective layer 15 is, for example, silicon oxide.
  • the third connection hole 61 and the fourth connection hole 62 are prepared by etching the protective layer 15.
  • the material of the substrate 51 of the logic control unit 5 is, for example, silicon oxide. Circuits are arranged on the base 51 of the logic control unit 5, and when the logic control unit 5 and the storage unit 1 are bonded together, the circuit in the base 51 of the logic control unit 5 is connected to the top connection circuit 41.
  • the second metal line and the first metal line of the memory cell 1 are respectively laid on the upper and lower sides of the channel layer in the memory cell, and the first metal line and the second metal line are separately laid.
  • the metal wire balances the distribution of the metal wire, reducing or avoiding the deformation of the memory cell; at the same time, the metal wiring is simplified by dispersing the first metal wire and the second metal wire, so that the first metal wire and the second metal wire.
  • a three-dimensional memory is provided.
  • FIG. 3 is a schematic cross-sectional view of a three-dimensional memory according to a second embodiment of the present disclosure.
  • the same components as in the first embodiment are denoted by the same reference numerals.
  • the three-dimensional memory of this embodiment is compared with the three-dimensional memory of the first embodiment. The difference is that the bottom of the common selection line 14 in the three-dimensional memory of this embodiment is directly connected to the second metal line 22. Sexual connection, there is no second connection hole 32 in the first embodiment.
  • a method for manufacturing a three-dimensional memory is provided.
  • FIG. 4 is a flowchart of a manufacturing method for manufacturing the three-dimensional memory shown in the first embodiment according to the third embodiment of the present disclosure.
  • the manufacturing method of the three-dimensional memory of the present disclosure includes:
  • Step S31 lay the second metal wire and the first metal wire on the upper and lower sides of the channel layer in the memory cell respectively;
  • step S31 includes:
  • Sub-step S31a prepare a substrate 11;
  • Sub-step S31b arranging a second metal wire 22 in the substrate 11 and insulating it from the substrate 11;
  • Sub-step S31c continue to epitaxially grow the substrate material on the substrate 11 on which the second metal wire 22 has been laid, and make a second connection hole 32 on the epitaxially grown substrate material to form a second metal wire 22 preset inside And the substrate of the second connection hole 32;
  • Sub-step S31d Growing a laminated material as the channel layer 12 on the substrate with the second metal line 22 and the second connection hole 32 preset inside, and patterning the channel hole 13 and the common selection line 14. The bottom of the common selection line 14 stops at the second connection hole 32;
  • Sub-step S31e make a first connection hole 31 and a first metal line 21 above the structure where the channel hole 13 and the common selection line 14 are formed, and form the first metal line 21 and the second metal line 22 to be respectively arranged on the channel layer 12 storage units on the upper and lower sides.
  • Step S32 bonding the front surfaces of the storage unit and the logic control unit to each other, the logic control unit is connected to the control circuit, and both the first metal wire and the second metal wire are electrically connected to the control circuit;
  • step S32 includes:
  • Sub-step S32a fabricate a top connection circuit 41 in the storage unit 1, so that the first metal wire 21 is connected to the logic control unit 5 through the top connection circuit 41;
  • Sub-step S32b fabricate the bottom connection circuit 42 in the storage unit 1;
  • Sub-step S32c attach the front surfaces of the storage unit 1 and the logic control unit 5 to each other;
  • Sub-step S32d Making a plurality of connecting holes on the back of the storage unit 1, the top of the plurality of connecting holes is connected to the control circuit, the plurality of connecting holes includes the third connecting hole 61 and the fourth connecting hole 62, the third connecting hole 61
  • the bottom part stops at the top connection circuit 41, and the bottom part of the fourth connection hole 62 stops at the bottom connection circuit 42, so that the logic control unit 5 is connected to the control circuit through the third connection hole 61 to realize the electrical connection between the first metal wire 21 and the control circuit.
  • the second metal wire 22 is electrically connected to the control circuit through the bottom connection circuit 42 and the fourth connection hole 62.
  • the above sub-steps do not have to be executed in the order of ad or ae in the embodiment.
  • the sub-step S32b and the sub-step S32c can be executed in an exchange order.
  • some sequences have their own sequence, such as :
  • the sub-step S32c must be executed after the sub-step S32a, otherwise it is very difficult to fabricate the top connection circuit after the storage unit and the logic storage circuit are bonded; similarly, the sequence of other steps can be carried out by those skilled in the art according to actual needs.
  • the sequence of the steps or sub-steps in the following manufacturing method is the same, and will not be repeated.
  • the second metal wire is laid on the substrate of the memory cell and insulated from the substrate, the first metal wire is laid on the front surface of the memory cell, and then each connection hole is formed (Including the first connection hole-the fourth connection hole), the connection process of the first metal wire and the second metal wire and the control circuit is realized, the layout is reasonable and relatively simple, and the reliability of the connection is improved.
  • the logic and the control circuit The existing technology is the same, the manufacturing process is simple, and has broad application prospects.
  • a method for manufacturing a three-dimensional memory is provided.
  • FIG. 5 is a flowchart of a manufacturing method for manufacturing the three-dimensional memory shown in the second embodiment according to the fourth embodiment of the present disclosure.
  • the manufacturing method of the three-dimensional memory of this embodiment includes:
  • Step S41 lay the second metal wire and the first metal wire on the upper and lower sides of the channel layer in the memory cell respectively;
  • step S41 includes:
  • Sub-step S41a prepare a substrate 11;
  • Sub-step S41b arranging a second metal wire 22 in the substrate 11 and insulated from the substrate 11;
  • Sub-step S41c Growing a laminated material as the channel layer 12 on the substrate 11 on which the second metal line 22 has been laid, and patterning to form the channel hole 13 and the common selection line 14. The bottom of the common selection line 14 stops On the surface of the second metal wire 22;
  • Sub-step S41d make a first connection hole 31 and a first metal line 21 above the structure where the channel hole 13 and the common selection line 14 are formed, and form the first metal line 21 and the second metal line 22 to be respectively arranged on the channel layer 12 on the upper and lower sides of the storage unit 1.
  • Step S42 bonding the front surfaces of the storage unit and the logic control unit to each other, the logic control unit is connected to the control circuit, and both the first metal wire and the second metal wire are electrically connected to the control circuit;
  • step S42 includes:
  • Sub-step S42a making a top connection circuit 41 in the storage unit 1, so that the first metal wire 21 is connected to the logic control unit 5 through the top connection circuit 41;
  • Sub-step S42b fabricate the bottom connection circuit 42 in the storage unit 1;
  • Sub-step S42c attach the front surfaces of the storage unit 1 and the logic control unit 5 to each other;
  • Sub-step S42d Making a plurality of connecting holes on the back of the storage unit 1, the top of the plurality of connecting holes is connected to the control circuit, the plurality of connecting holes includes the third connecting hole 61 and the fourth connecting hole 62, the third connecting hole 61
  • the bottom part stops at the top connection circuit 41, and the bottom part of the fourth connection hole 62 stops at the bottom connection circuit 42, so that the logic control unit 5 is connected to the control circuit through the third connection hole 61 to realize the electrical connection between the first metal wire 21 and the control circuit.
  • the second metal wire 22 is electrically connected to the control circuit through the bottom connection circuit 42 and the fourth connection hole 62.
  • the difference in the corresponding structure and the manufacturing process is that there is no process for forming the second connection hole 32 in step S41, and the bottom of the common selection line 14 is directly stopped. On the surface of the second metal wire 22.
  • the present disclosure provides a three-dimensional memory and a method for manufacturing the same.
  • the second metal wire and the first metal wire of the memory cell are respectively laid on the upper and lower sides of the channel layer in the memory cell, and the The first metal line and the second metal line balance the distribution of the metal lines, reducing or avoiding the deformation of the memory cell; at the same time, the metal wiring is simplified by dispersing the first metal line and the second metal line, so that the first The layout of the connection circuit between the metal wire and the second metal wire and the control circuit is relatively simple, and the reliability of the connection is improved, and the connection reliability problem caused by complicated layout and process problems in the prior art is avoided; in one embodiment, By laying the second metal wire in the substrate of the memory cell and insulating it from the substrate, the first metal wire is laid on the front surface of the memory cell, and then each connection hole (including the first connection hole-the first connection hole) is formed.
  • connection holes to realize the connection process between the first metal wire and the second metal wire and the control circuit, the layout is reasonable and relatively simple, and the reliability of the connection is improved.
  • the logic of the control circuit is the same as the prior art, and the manufacturing process is simple , Has a wide range of application prospects.

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Abstract

一种三维存储器及其制作方法，三维存储器包括：正面相互贴合的存储单元和逻辑控制单元，该逻辑控制单元与控制电路连接，其特征在于，所述存储单元的第二金属线和第一金属线分别布设于该存储单元中沟道层的上下两侧，第一金属线和第二金属线均与该控制电路电性连接。通过将第二金属线和第一金属线分别布设于该存储单元中沟道层的上下两侧，通过分开布设第一金属线和第二金属线使得金属线的分布变得平衡，减小或避免了存储单元的形变；同时还通过分散布置第一金属线和第二金属线简化了金属布线，使得第一金属线和第二金属线与控制电路的连接线路布局相对简单，且提高了连接可靠性，避免了现有技术中由于布局复杂和工艺问题导致的连接可靠性问题。

Description

三维存储器及其制作方法 技术领域
本公开属于半导体存储器和集成技术领域，涉及一种三维存储器及其制作方法。
背景技术
三维(3D)NAND是一种新兴的闪存类型，通过把存储单元堆叠在一起来解决平面(2D)NAND闪存带来的限制。目前三维NAND存储器技术是目前国家正在重点发展的技术。
在Xtacking三维NAND存储器架构中，金属线metal-1，metal-2和(下部)连接电路面临电路设计布设复杂的难题。
发明内容
(一)要解决的技术问题
本公开提供了一种三维存储器及其制作方法，以至少部分解决以上所提出的技术问题。
(二)技术方案
根据本公开的一个方面，提供了一种三维存储器，包括：正面相互贴合的存储单元和逻辑控制单元，该逻辑控制单元与控制电路连接，其特征在于，所述存储单元的第二金属线和第一金属线分别布设于该存储单元中沟道层的上下两侧，第一金属线和第二金属线均与该控制电路电性连接。
在本公开的一实施例中，所述第二金属线布设于该存储单元的衬底中，并与所述衬底绝缘；该存储单元的第一金属线布设于该存储单元的正面。
在本公开的一实施例中，所述存储单元的沟道层中设置有多个沟道孔，每个沟道孔分别与第一金属线电性连接；公共选择线与第二金属线电性连接。
在本公开的一实施例中，所述沟道孔的顶部通过第一连接孔与所述第一金属线电性连接。
在本公开的一实施例中，所述公共选择线的底部直接与所述第二金属线电性连接，或者，所述公共选择线的底部通过第二连接孔与所述第二金属线电性连接。
在本公开的一实施例中，所述第一金属线通过顶部连接电路与该逻辑控制单元电性连接；所述第二金属线通过底部连接电路与该控制电路电性连接。
在本公开的一实施例中，所述存储单元的背面设置有多个连接孔，多个连接孔的顶部与控制电路连接，多个连接孔的顶部分别停止于顶部连接电路和底部连接电路。
根据本公开的另一个方面，提供了一种三维存储器的制作方法，包括：在存储单元中沟道层的上下两侧分别布设第二金属线和第一金属线；将存储单元和逻辑控制单元的正面相互贴合，该逻辑控制单元与控制电路连接，将第一金属线和第二金属线均与该控制电路电性连接。
在本公开的一实施例中，所述在存储单元中沟道层的上下两侧分别布设第二金属线和第一金属线的步骤包括：
准备一衬底；
在衬底中布设第二金属线，并与所述衬底绝缘；
在布设完第二金属线的衬底上继续外延生长衬底材料并在该外延生长的衬底材料上制作第二连接孔，形成内部预设有第二金属线和第二连接孔的衬底；
在内部预设有第二金属线和第二连接孔的衬底上生长作为沟道层的叠层材料，并且图案化形成沟道孔和公共选择线，该公共选择线的底部停止于第二连接孔；
在形成有沟道孔和公共选择线的结构上方制作第一连接孔和第一金属线，形成第一金属线和第二金属线分别布设于沟道层的上下两侧的存储单元；或者该步骤包括：
准备一衬底；
在衬底中布设第二金属线，并与所述衬底绝缘；
在布设完第二金属线的衬底上生长作为沟道层的叠层材料，并且图案化形成沟道孔和公共选择线，该公共选择线的底部停止于第二金属线的表面；
在形成有沟道孔和公共选择线的结构上方制作第一连接孔和第一金属线，形成第一金属线和第二金属线分别布设于沟道层的上下两侧的存 储单元。
在本公开的一实施例中，所述将存储单元和逻辑控制单元的正面相互贴合，该逻辑控制单元与控制电路连接，将第一金属线和第二金属线均与该控制电路电性连接的步骤包括：
在存储单元中制作顶部连接电路，使得第一金属线通过顶部连接电路连接至该逻辑控制单元；
在存储单元中制作底部连接电路；
将存储单元和逻辑控制单元的正面相互贴合；
在存储单元的背面制作多个连接孔，多个连接孔的顶部与控制电路连接，多个连接孔包括第三连接孔和第四连接孔，第三连接孔的底部停止于顶部连接电路，第四连接孔的底部停止于底部连接电路，使得该逻辑控制单元通过第三连接孔与控制电路连接，实现第一金属线与控制电路的电性连接，使得第二金属线通过底部连接电路以及第四连接孔与控制电路电性连接。
(三)有益效果
从上述技术方案可以看出，本公开提供的三维存储器及其制作方法，具有以下有益效果：
1、通过将存储单元的第二金属线和第一金属线分别布设于该存储单元中沟道层的上下两侧，通过分开布设第一金属线和第二金属线使得金属线的分布变得平衡，减小或避免了存储单元的形变；同时还通过分散布置第一金属线和第二金属线简化了金属布线，使得第一金属线和第二金属线与控制电路的连接线路布局相对简单，且提高了连接的可靠性，避免了现有技术中由于布局复杂和工艺问题导致的连接可靠性问题。
2、通过将第二金属线布设于该存储单元的衬底中，并与所述衬底绝缘，将第一金属线布设于该存储单元的正面，然后形成各个连接孔(包括第一连接孔-第四连接孔)，实现第一金属线和第二金属线与控制电路的连接工艺，布局合理且相对简单，提高了连接的可靠性，另外，控制电路的逻辑与现有技术相同，制作工艺简单，具有广泛的应用前景。
附图说明
图1为现有技术中三维NAND存储器的三维立体示意图和对应的剖 面示意图。
图2为根据本公开第一实施例所示的三维存储器的剖面示意图。
图3为根据本公开第二实施例所示的三维存储器的剖面示意图。
图4为根据本公开第三实施例所示的用于制作第一实施例所示的三维存储器的制作方法流程图。
图5为根据本公开第四实施例所示的用于制作第二实施例所示的三维存储器的制作方法流程图。
【符号说明】
1-存储单元；
11-衬底；
12-沟道层；
121-第一叠层材料；             122-第二叠层材料；
13-沟道孔；                    14-公共选择线；
15-保护层；
21-第一金属线；                22-第二金属线；
31-第一连接孔；                32-第二连接孔；
41-顶部连接电路；              42-底部连接电路；
61-第三连接孔；                62-第四连接孔；
5-逻辑控制单元；
51-基底。
具体实施方式
图1为现有技术中三维NAND存储器的三维立体示意图和对应的剖面示意图。参照图1所示，在已有的Xtacking三维NAND存储器架构中，存储单元和逻辑控制单元正面-正面贴合后，存储单元的背面向上露出。存储晶元的沟道孔CH通过C1CH连接孔连接metal-1线，而公共选择线(ACS)通过C1ACS连接孔连接metal-2线。其中，C1ACS连接孔和metal-1线交错排列，彼此绝缘，图1中以虚线框示意metal-1线，以说明C1ACS连接孔和metal-1线之间并无交叉，二者彼此绝缘。Metal-1线和metal-2线都通过连接电路和逻辑控制晶元连接，然后通过深孔引出芯片操作终端。
申请人发现上述结构存在两个主要问题：1、metal-1线和metal-2线 相互交错且彼此绝缘，公共选择线和metal-2线对应连接，沟道孔和metal-1线对应连接，连接均处于同一个方向和区域，要实现彼此错开以及有效的连接，对应金属连接和布线复杂，由于布局复杂和工艺问题导致连接的可靠性较差；2、金属线全部集中在存储单元下部(或者说存储单元顶部，上部和下部是按照说明书附图的方向进行说明，而顶部和底部是以对应的存储单元的正面和背面来说的，顶部对应存储单元正面，底部对应存储单元背面)而硅结构(衬底)集中在存储单元上部，该结构应力不平衡引起存储单元的形变。
本公开提出一种三维存储器，该三维存储器中，通过将存储单元的第二金属线和第一金属线分别布设于该存储单元中沟道层的上下两侧，通过分开布设第一金属线和第二金属线使得金属线的分布变得平衡，减小或避免了存储单元的形变；同时还通过分散布置第一金属线和第二金属线简化了金属布线，使得第一金属线和第二金属线与控制电路的连接线路布局相对简单，且提高了连接的可靠性，避免了现有技术中由于布局复杂和工艺问题导致的连接可靠性问题。
为使本公开的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本公开进一步详细说明。
需要说明的是，图2和图3示意了存储单元1的正面和背面的方向，与之对应，全文中关于存储单元的结构描述中，描述为“顶部连接电路”和“底部连接电路”是按照存储单元按照正面朝上放置后观察对应看到的顶部和底部，描述为“上部”和“下部”是按照说明书附图对应的上下方向进行描述的。
图中以梯形示意各个“连接孔”以及“公共选择线”，其“顶部”或“底部”按照如下原则描述：按照制备时的刻蚀工艺来说，顶部的刻蚀宽度要高于底部的刻蚀宽度，因此对应长边为“顶部”，对应短边为“底部”，比如在图2中，沟道孔13的顶部为长边，底部为短边，沟道孔13的顶部通过第一连接孔31与第一金属线21电性连接；公共选择线14的顶部为长边，底部为短边，公共选择线14的底部通过第二连接孔32与第二金属线22电性连接；同理，第三连接孔61的长边为顶部，短边为底部，第三连接孔61的顶部与控制电路连接，第三连接孔61的底部停止于顶部连接 电路41。
第一实施例
在本公开的第一个示例性实施例中，提供了一种三维存储器。
图2为根据本公开第一实施例所示的三维存储器的剖面示意图。
参照图2所示，本公开的三维存储器，包括：正面相互贴合的存储单元1和逻辑控制单元5，该逻辑控制单元5与控制电路连接，其特征在于，所述存储单元1的第二金属线22和第一金属线21分别布设于该存储单元1中沟道层12的上下两侧，第一金属线21和第二金属线22均与该控制电路电性连接。
图2-图3中，第一金属线21和第二金属线22通过多个连接孔(包含第三连接孔61和第四连接孔62)直接或间接引出至芯片操作终端，从而与控制电路连接。
本实施例中，如图2所示，所述第二金属线22布设于该存储单元1的衬底11中，并与所述衬底11绝缘；该存储单元1的第一金属线21布设于该存储单元1的正面。
在一实施例中，衬底11为硅衬底或者SOI衬底。
本实施例中，如图2所示，所述存储单元1的沟道层12中设置有多个沟道孔13，每个沟道孔13分别与第一金属线21电性连接；公共选择线14与第二金属线22电性连接。
在一实施例中，沟道层12是由多个叠层对形成的结构，例如由第一叠层材料/第二叠层材料形成的叠层对，第一叠层材料121为氧化硅；第二叠层材料122为氮化硅。
在本公开的一实施例中，如图2所示，所述沟道孔13的顶部通过第一连接孔31与所述第一金属线21电性连接。
在本公开的一实施例中，如图2所示，所述公共选择线14的底部通过第二连接孔32与所述第二金属线22电性连接。
在本公开的一实施例中，如图2所示，所述第一金属线21通过顶部连接电路41与该逻辑控制单元5电性连接；所述第二金属线22通过底部连接电路42与该控制电路电性连接。
本实施例中，所述存储单元1的背面设置有多个连接孔，多个连接孔 的顶部与控制电路连接，多个连接孔的顶部分别停止于顶部连接电路和底部连接电路。如图2所示，多个连接孔包括第三连接孔61和第四连接孔62，第三连接孔61和第四连接孔62的顶部均与控制电路连接，第三连接孔61的底部停止于顶部连接电路41，第四连接孔62的底部停止于底部连接电路42，使得该逻辑控制单元5通过第三连接孔61与控制电路连接，实现第一金属线21与控制电路的电性连接，使得第二金属线22通过底部连接电路42以及第四连接孔62与控制电路电性连接。
在一实施例中，参照图2所示，在沟道层12的顶部以及侧壁形成有保护层15，该保护层15的材料例如为氧化硅。第三连接孔61和第四连接孔62通过刻蚀保护层15制备得到。
本实施例中，参照图2所示，逻辑控制单元5的基底51的材料例如为氧化硅。在逻辑控制单元5的基底51布设有电路，在逻辑控制单元5和存储单元1正面-正面相贴合时，对应逻辑控制单元5的基底51中的电路与顶部连接电路41实现连接。
综上所述，本实施例中，通过将存储单元1的第二金属线和第一金属线分别布设于该存储单元中沟道层的上下两侧，通过分开布设第一金属线和第二金属线使得金属线的分布变得平衡，减小或避免了存储单元的形变；同时还通过分散布置第一金属线和第二金属线简化了金属布线，使得第一金属线和第二金属线与控制电路的连接线路布局相对简单，且提高了连接的可靠性，避免了现有技术中由于布局复杂和工艺问题导致的连接可靠性问题。
第二实施例
在本公开的第二个示例性实施例中，提供了一种三维存储器。
图3为根据本公开第二实施例所示的三维存储器的剖面示意图。本实施例中与第一实施例相同的部件采用相同的附图标记进行表示。
参照图3所示，本实施例的三维存储器与第一实施例的三维存储器相比，区别之处在于：本实施例的三维存储器中的公共选择线14的底部直接与第二金属线22电性连接，不存在第一实施例中的第二连接孔32。
第三实施例
在本公开的第三个示例性实施例中，提供了一种三维存储器的制作方 法。
图4为根据本公开第三实施例所示的用于制作第一实施例所示的三维存储器的制作方法流程图。
参照图4所示，本公开的三维存储器的制作方法，包括：
步骤S31：在存储单元中沟道层的上下两侧分别布设第二金属线和第一金属线；
本实施例中，步骤S31包括：
子步骤S31a：准备一衬底11；
子步骤S31b：在衬底中11布设第二金属线22，并与所述衬底11绝缘；
子步骤S31c：在布设完第二金属线22的衬底11上继续外延生长衬底材料并在该外延生长的衬底材料上制作第二连接孔32，形成内部预设有第二金属线22和第二连接孔32的衬底；
子步骤S31d：在内部预设有第二金属线22和第二连接孔32的衬底上生长作为沟道层12的叠层材料，并且图案化形成沟道孔13和公共选择线14，该公共选择线14的底部停止于第二连接孔32；
子步骤S31e：在形成有沟道孔13和公共选择线14的结构上方制作第一连接孔31和第一金属线21，形成第一金属线21和第二金属线22分别布设于沟道层12的上下两侧的存储单元。
步骤S32：将存储单元和逻辑控制单元的正面相互贴合，该逻辑控制单元与控制电路连接，将第一金属线和第二金属线均与该控制电路电性连接；
本实施例中，步骤S32包括：
子步骤S32a：在存储单元1中制作顶部连接电路41，使得第一金属线21通过顶部连接电路41连接至该逻辑控制单元5；
子步骤S32b：在存储单元1中制作底部连接电路42；
子步骤S32c：将存储单元1和逻辑控制单元5的正面相互贴合；
子步骤S32d：在存储单元1的背面制作多个连接孔，多个连接孔的顶部与控制电路连接，多个连接孔包括第三连接孔61和第四连接孔62，第三连接孔61的底部停止于顶部连接电路41，第四连接孔62的底部停止 于底部连接电路42，使得该逻辑控制单元5通过第三连接孔61与控制电路连接，实现第一金属线21与控制电路的电性连接，使得第二金属线22通过底部连接电路42以及第四连接孔62与控制电路电性连接。
需要说明的是，上述子步骤不是必须按照实施例中的a-d或a-e的顺序先后执行，比如：子步骤S32b和子步骤S32c可以交换顺序执行，根据实际工艺的需要，有些顺序本身存在先后顺序，比如：子步骤S32c必须在子步骤S32a之后执行，否则存储单元和逻辑存储电路贴合之后再制作顶部连接电路具有很大的难度；类似的，其他步骤的顺序本领域技术人员根据实际需要可以进行先后顺序的调整或者增加常规工艺，下文的制作方法中各个步骤或子步骤的顺序与之相同，不再赘述。
本实施例的制作方法中，通过将第二金属线布设于该存储单元的衬底中，并与所述衬底绝缘，将第一金属线布设于该存储单元的正面，然后形成各个连接孔(包括第一连接孔-第四连接孔)，实现第一金属线和第二金属线与控制电路的连接工艺，布局合理且相对简单，提高了连接的可靠性，另外，控制电路的逻辑与现有技术相同，制作工艺简单，具有广泛的应用前景。
第四实施例
在本公开的第四个示例性实施例中，提供了一种三维存储器的制作方法。
图5为根据本公开第四实施例所示的用于制作第二实施例所示的三维存储器的制作方法流程图。
参照图5所示，本实施例的三维存储器的制作方法，包括：
步骤S41：在存储单元中沟道层的上下两侧分别布设第二金属线和第一金属线；
本实施例中，步骤S41包括：
子步骤S41a：准备一衬底11；
子步骤S41b：在衬底11中布设第二金属线22，并与所述衬底11绝缘；
子步骤S41c：在布设完第二金属线22的衬底11上生长作为沟道层12的叠层材料，并且图案化形成沟道孔13和公共选择线14，该公共选择 线14的底部停止于第二金属线22的表面；
子步骤S41d：在形成有沟道孔13和公共选择线14的结构上方制作第一连接孔31和第一金属线21，形成第一金属线21和第二金属线22分别布设于沟道层12的上下两侧的存储单元1。
步骤S42：将存储单元和逻辑控制单元的正面相互贴合，该逻辑控制单元与控制电路连接，将第一金属线和第二金属线均与该控制电路电性连接；
本实施例中，步骤S42包括：
子步骤S42a：在存储单元1中制作顶部连接电路41，使得第一金属线21通过顶部连接电路41连接至该逻辑控制单元5；
子步骤S42b：在存储单元1中制作底部连接电路42；
子步骤S42c：将存储单元1和逻辑控制单元5的正面相互贴合；
子步骤S42d：在存储单元1的背面制作多个连接孔，多个连接孔的顶部与控制电路连接，多个连接孔包括第三连接孔61和第四连接孔62，第三连接孔61的底部停止于顶部连接电路41，第四连接孔62的底部停止于底部连接电路42，使得该逻辑控制单元5通过第三连接孔61与控制电路连接，实现第一金属线21与控制电路的电性连接，使得第二金属线22通过底部连接电路42以及第四连接孔62与控制电路电性连接。
第四个实施例和第三个实施例的制作方法中，对应结构的区别，制作工艺的区别在于：步骤S41中不存在形成第二连接孔32的工艺，直接将公共选择线14的底部停止于第二金属线22的表面。
综上所述，本公开提供了一种三维存储器及其制作方法，通过将存储单元的第二金属线和第一金属线分别布设于该存储单元中沟道层的上下两侧，通过分开布设第一金属线和第二金属线使得金属线的分布变得平衡，减小或避免了存储单元的形变；同时还通过分散布置第一金属线和第二金属线简化了金属布线，使得第一金属线和第二金属线与控制电路的连接线路布局相对简单，且提高了连接的可靠性，避免了现有技术中由于布局复杂和工艺问题导致的连接可靠性问题；在一实施例中，通过将第二金属线布设于该存储单元的衬底中，并与所述衬底绝缘，将第一金属线布设于该存储单元的正面，然后形成各个连接孔(包括第一连接孔-第四连接孔)， 实现第一金属线和第二金属线与控制电路的连接工艺，布局合理且相对简单，提高了连接的可靠性，另外，控制电路的逻辑与现有技术相同，制作工艺简单，具有广泛的应用前景。
贯穿附图，相同的元素由相同或相近的附图标记来表示。在可能导致对本公开的理解造成混淆时，将省略常规结构或构造。并且图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。另外，在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。
说明书与权利要求中所使用的序数例如“第一”、“第二”、“第三”等的用词，以修饰相应的元件，其本身并不意味着该元件有任何的序数，也不代表某一元件与另一元件的顺序、或是制造方法上的顺序，该些序数的使用仅用来使具有某命名的一元件得以和另一具有相同命名的元件能做出清楚区分。
再者，单词“包含”或“包括”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。
除非存在技术障碍或矛盾，本发明的上述实施方式中的各个特征可以自由组合以形成另外的实施例，这些另外的实施例均在本发明的保护范围中。
以上所述的具体实施例，对本公开的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本公开的具体实施例而已，并不用于限制本公开，凡在本公开的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (10)

  1. 一种三维存储器，包括：正面相互贴合的存储单元和逻辑控制单元，该逻辑控制单元与控制电路连接，其特征在于，所述存储单元的第二金属线和第一金属线分别布设于该存储单元中沟道层的上下两侧，第一金属线和第二金属线均与该控制电路电性连接。
  2. 根据权利要求1所述的三维存储器，其特征在于，所述第二金属线布设于该存储单元的衬底中，并与所述衬底绝缘；该存储单元的第一金属线布设于该存储单元的正面。
  3. 根据权利要求1所述的三维存储器，其特征在于，所述存储单元的沟道层中设置有多个沟道孔，每个沟道孔分别与第一金属线电性连接；公共选择线与第二金属线电性连接。
  4. 根据权利要求3所述的三维存储器，其特征在于，所述沟道孔的顶部通过第一连接孔与所述第一金属线电性连接。
  5. 根据权利要求3所述的三维存储器，其特征在于，所述公共选择线的底部直接与所述第二金属线电性连接，或者，所述公共选择线的底部通过第二连接孔与所述第二金属线电性连接。
  6. 根据权利要求1所述的三维存储器，其特征在于，所述第一金属线通过顶部连接电路与该逻辑控制单元电性连接；所述第二金属线通过底部连接电路与该控制电路电性连接。
  7. 根据权利要求6所述的三维存储器，其特征在于，所述存储单元的背面设置有多个连接孔，多个连接孔的顶部与控制电路连接，多个连接孔的顶部分别停止于顶部连接电路和底部连接电路。
  8. 一种三维存储器的制作方法，其特征在于，包括：
    在存储单元中沟道层的上下两侧分别布设第二金属线和第一金属线；
    将存储单元和逻辑控制单元的正面相互贴合，该逻辑控制单元与控制电路连接，将第一金属线和第二金属线均与该控制电路电性连接。
  9. 根据权利要求8所述的制作方法，其特征在于，
    所述在存储单元中沟道层的上下两侧分别布设第二金属线和第一金属线的步骤包括：
    准备一衬底；
    在衬底中布设第二金属线，并与所述衬底绝缘；
    在布设完第二金属线的衬底上继续外延生长衬底材料并在该外延生长的衬底材料上制作第二连接孔，形成内部预设有第二金属线和第二连接孔的衬底；
    在内部预设有第二金属线和第二连接孔的衬底上生长作为沟道层的叠层材料，并且图案化形成沟道孔和公共选择线，该公共选择线的底部停止于第二连接孔；
    在形成有沟道孔和公共选择线的结构上方制作第一连接孔和第一金属线，形成第一金属线和第二金属线分别布设于沟道层的上下两侧的存储单元；或者该步骤包括：
    准备一衬底；
    在衬底中布设第二金属线，并与所述衬底绝缘；
    在布设完第二金属线的衬底上生长作为沟道层的叠层材料，并且图案化形成沟道孔和公共选择线，该公共选择线的底部停止于第二金属线的表面；
    在形成有沟道孔和公共选择线的结构上方制作第一连接孔和第一金属线，形成第一金属线和第二金属线分别布设于沟道层的上下两侧的存储单元。
  10. 根据权利要求9所述的制作方法，其特征在于，所述将存储单元和逻辑控制单元的正面相互贴合，该逻辑控制单元与控制电路连接，将第一金属线和第二金属线均与该控制电路电性连接的步骤包括：
    在存储单元中制作顶部连接电路，使得第一金属线通过顶部连接电路连接至该逻辑控制单元；
    在存储单元中制作底部连接电路；
    将存储单元和逻辑控制单元的正面相互贴合；
    在存储单元的背面制作多个连接孔，多个连接孔的顶部与控制电路连接，多个连接孔包括第三连接孔和第四连接孔，第三连接孔的底部停止于顶部连接电路，第四连接孔的底部停止于底部连接电路，使得该逻辑控制单元通过第三连接孔与控制电路连接，实现第一金属线与控制电路的电性 连接，使得第二金属线通过底部连接电路以及第四连接孔与控制电路电性连接。
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