WO2021010754A1 - 인쇄회로기판 - Google Patents

인쇄회로기판 Download PDF

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Publication number
WO2021010754A1
WO2021010754A1 PCT/KR2020/009340 KR2020009340W WO2021010754A1 WO 2021010754 A1 WO2021010754 A1 WO 2021010754A1 KR 2020009340 W KR2020009340 W KR 2020009340W WO 2021010754 A1 WO2021010754 A1 WO 2021010754A1
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WO
WIPO (PCT)
Prior art keywords
insulating layer
circuit pattern
disposed
height
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2020/009340
Other languages
English (en)
French (fr)
Korean (ko)
Inventor
유도혁
라세웅
명세호
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LG Innotek Co Ltd
Original Assignee
LG Innotek Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LG Innotek Co Ltd filed Critical LG Innotek Co Ltd
Priority to CN202080051614.6A priority Critical patent/CN114128409A/zh
Priority to JP2022502583A priority patent/JP7654628B2/ja
Priority to US17/628,178 priority patent/US20220264750A1/en
Publication of WO2021010754A1 publication Critical patent/WO2021010754A1/ko
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0373—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement containing additives, e.g. fillers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/202—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using self-supporting metal foil pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing of the conductive pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0209—Inorganic, non-metallic particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0212—Resin particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1377—Protective layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/465—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer

Definitions

  • the embodiment relates to a printed circuit board, and more particularly, to a printed circuit board having a buried structure in which a circuit pattern disposed on an outermost layer is buried in an insulating layer, and a method of manufacturing the same.
  • a circuit line width of a package substrate or a printed circuit board on which a semiconductor chip is mounted has been reduced to several micrometers or less.
  • an embedded trace substrate (hereinafter referred to as'ETS') method of embedding copper foil in an insulating layer has been used in the art.
  • the ETS method is advantageous in minimizing the circuit pitch because there is no circuit loss due to etching because the copper foil circuit is manufactured in a buried form in the insulating layer instead of forming it on the surface of the insulating layer.
  • a conventional printed circuit board including a microcircuit pattern has a structure in which the outermost circuit pattern protrudes above the insulating layer, and thus the outermost circuit pattern easily collapses.
  • a printed circuit board having a new structure and a method of manufacturing the same are provided.
  • a printed circuit board capable of improving reliability by having a structure in which a circuit pattern disposed at the outermost side is buried in an insulating layer and a method of manufacturing the same is provided.
  • the printed circuit board includes a first insulating layer; A first circuit pattern disposed inside or under the first insulating layer; A second circuit pattern disposed on an upper surface of the first insulating layer; And a second insulating layer disposed on the upper surface of the first insulating layer and surrounding a second circuit pattern, wherein the second circuit pattern and the second insulating layer are formed of the first insulating layer. It is disposed to protrude above the second surface, and the height of the second circuit pattern is different from the height of the second insulating layer.
  • the second insulating layer includes a resin and an inorganic filler disposed in the resin.
  • the inorganic filler is exposed to the upper surface of the second insulating layer.
  • the inorganic filler of the second insulating layer is disposed on the upper surface of the second circuit pattern.
  • the lower surface of the second circuit pattern is located on the same plane as the lower surface of the second insulating layer.
  • an upper surface of the second circuit pattern is positioned higher than an upper surface of the second insulating layer.
  • the height of the second insulating layer is within a range of 20% to 99% of the height of the second circuit pattern.
  • the second circuit pattern is disposed on the second surface of the first insulating layer, a side surface of which is in contact with the second insulating layer, and is disposed on the first part, and the second insulation And a second portion protruding above the upper surface of the layer, and the width of the second portion decreases from bottom to top.
  • the printed circuit board includes a first insulating layer; A first circuit pattern disposed on the first surface of the first insulating layer; A second circuit pattern disposed on the second surface of the first insulating layer; And a second insulating layer disposed on the second surface of the first insulating layer and surrounding a second circuit pattern, wherein the second insulating layer includes a resin and an inorganic filler disposed in the resin. And, at least a part of the inorganic filler is exposed to the upper surface of the second insulating layer.
  • the inorganic filler of the second insulating layer is disposed on the upper surface of the second circuit pattern.
  • the second circuit pattern and the second insulating layer are disposed to protrude above the second surface of the first insulating layer, and the height of the second circuit pattern is higher than that of the second insulating layer.
  • the height of the second insulating layer is within a range of 20% to 99% of the height of the second circuit pattern.
  • the second circuit pattern is disposed on the second surface of the first insulating layer, a side surface of which is in contact with the second insulating layer, and is disposed on the first part, and the second insulation And a second portion protruding above the upper surface of the layer, and the width of the second portion decreases from bottom to top.
  • the second circuit pattern is a fine pattern
  • the width of the second circuit pattern is in the range of 6 ⁇ m to 15 ⁇ m
  • the interval of the second circuit pattern is in the range of 8 ⁇ m to 15 ⁇ m.
  • a method of manufacturing a printed circuit board includes a first insulating layer, a first circuit pattern buried under the first insulating layer, and an upper surface of the first insulating layer by being disposed on the upper surface of the first insulating layer.
  • the inorganic filler of the second insulating layer remains on the upper surface of the second circuit pattern.
  • the removal is performed such that the height of the second insulating layer is within a range of 20% to 99% of the height of the second circuit pattern.
  • the second circuit pattern is disposed on the upper surface of the first insulating layer, a side surface of the first part in contact with the second insulating layer, the first part, and the second insulating layer And a second portion protruding above the upper surface, and the width of the second portion decreases from bottom to top.
  • a second circuit pattern supporting a side portion of the second circuit pattern on the first insulating layer To form an insulating layer. Accordingly, problems such as collapse or friction of the protruding second circuit pattern may be solved by miniaturization of the second circuit pattern, and thus product reliability may be improved.
  • the upper surface of the second insulating layer is positioned lower than the upper surface of the second circuit pattern. That is, the height of the second insulating layer in the embodiment is lower than the height of the second circuit pattern. Accordingly, it is possible to solve the problem that the exposed area of the surface of the second circuit pattern is reduced due to the second insulating layer remaining on the surface of the second circuit pattern, and accordingly, the problem of reducing the component mounting area. .
  • the second insulating layer is etched so that the upper surface of the second insulating layer is positioned lower than the upper surface of the second circuit pattern.
  • an inorganic filler is present in the second insulating layer.
  • the inorganic filler may protrude and be disposed on the surface of the second insulating layer in the final product. Accordingly, the surface area of the second insulating layer or the surface roughness of the second insulating layer may be increased by protruding the inorganic filler, and accordingly, a protective layer such as a solder resist disposed on the second insulating layer and Can improve the adhesion.
  • FIG. 1 is a diagram showing a printed circuit board according to a comparative example.
  • FIG. 2 is a view showing a printed circuit board according to an embodiment.
  • FIG. 3 is an enlarged view of an enlarged area B of FIG. 2.
  • 4A is a view showing a printed circuit board according to a comparative example.
  • 4B is a view referred to for explanation of a problem occurring according to the height of the second insulating layer.
  • 4C is a view showing a printed circuit board according to the present embodiment.
  • FIG. 5 is a diagram illustrating a shape change of a second circuit pattern according to an exemplary embodiment.
  • FIG. 6 is a view for explaining a problem according to the height of the second insulating layer.
  • 7A is a view showing the surface of a printed circuit board formed by sand blasting.
  • 7B is a view showing the surface of a printed circuit board formed by plasma.
  • FIG 8 to 10 are views illustrating a method of manufacturing a printed circuit board according to an embodiment in order of processes.
  • FIG. 1 is a diagram showing a printed circuit board according to a comparative example.
  • the printed circuit board according to the comparative example includes a circuit pattern manufactured by the ETS method.
  • the printed circuit board manufactured by the ETS method includes an insulating layer 10, a first circuit pattern 20, and a second circuit pattern 30.
  • the first circuit pattern 20 is buried in the insulating layer 10.
  • the first circuit pattern 20 is buried in the lower region of the insulating layer 10. Accordingly, the lower surface of the first circuit pattern 20 is disposed on the same plane as the lower surface of the insulating layer 10.
  • a second circuit pattern 30 is disposed on the upper surface of the insulating layer 10.
  • the second circuit pattern 30 has a structure protruding above the upper surface of the insulating layer 10.
  • a printed circuit board including only one insulating layer 10 and having a two-layer structure based on the circuit pattern layer is illustrated, but the number of layers of the circuit pattern of the printed circuit board may be further increased.
  • the second circuit pattern 30 disposed at the outermost side has a structure protruding above the surface of the insulating layer 10.
  • circuit patterns are gradually becoming finer.
  • the outermost layer must be implemented by the ETS method. That is, in the case of a fine circuit pattern in which the outermost circuit pattern has a width of 15 ⁇ m and the spacing of each circuit pattern is spaced apart from 15 ⁇ m or less, the circuit pattern should be formed by the ETS method to be stable. The formation of is possible.
  • the structure protrudes above the upper surface of the insulating layer 10.
  • the protruding second circuit pattern 30 may have a width of 15 ⁇ m or less.
  • the protruding second circuit pattern 30 has a width exceeding 15 ⁇ m, it may be resistant to external impact.
  • the width of the second circuit pattern 30 of the outermost layer is decreasing, and accordingly, the second circuit pattern 30 is In the case of having a structure protruding above the upper surface of the layer 10, the second circuit pattern 30 easily collapses due to external impact.
  • the second circuit pattern 30 of the outermost layer has an extremely fine pattern shape, and accordingly, a problem arises that it is easily collapsed or rubbed by a small external impact.
  • the embodiment is to provide a printed circuit board having a new structure and a control method thereof capable of solving the reliability problem of a fine pattern disposed on the outermost side.
  • FIG. 2 is a view showing a printed circuit board according to an embodiment
  • FIG. 3 is an enlarged view of area B of FIG. 2.
  • the printed circuit board 100 includes a first insulating layer 110, a second insulating layer 140, a first circuit pattern 120 and a second circuit pattern 130. .
  • the printed circuit board 100 has a two-layer structure with the insulating layer 10 as the center of the circuit pattern layer, but this is only an example, and the number of circuit pattern layers may further increase. There will be.
  • the first circuit pattern 120 in FIG. 2 may be a first outermost layer disposed at the bottom of the plurality of circuit pattern layers, and the second circuit pattern 140 is a first circuit pattern 120 disposed at the top of the plurality of circuit pattern layers. 2 May be the outermost layer.
  • the first insulating layer 110 is a substrate on which an electric circuit capable of changing wiring is arranged, and may include all of a printed circuit board, a wiring board, and an insulating substrate made of an insulating material capable of forming circuit patterns on a surface.
  • the first insulating layer 110 may be rigid or flexible.
  • the first insulating layer 110 may include glass or plastic.
  • the first insulating layer 110 includes chemically strengthened/semi-tempered glass such as soda lime glass or aluminosilicate glass, or includes polyimide (PI), polyethylene terephthalate (polyethylene) It may contain reinforced or soft plastics such as terephthalate, PET), propylene glycol (PPG) polycarbonate (PC), or sapphire.
  • PI polyimide
  • PPG propylene glycol
  • PC propylene glycol
  • the first insulating layer 110 may include a photoisotropic film.
  • the first insulating layer 110 may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), a photoisotropic polycarbonate (PC), or a photoisotropic polymethylmethacrylate (PMMA). I can.
  • the first insulating layer 110 may be bent while having a partially curved surface. That is, the first insulating layer 110 may be bent while partially having a flat surface and partially having a curved surface. In detail, the first insulating layer 110 may be bent while having a curved end or a surface including a random curvature, and may be bent or bent.
  • the first insulating layer 110 may be a flexible substrate having a flexible characteristic.
  • the first insulating layer 110 may be a curved or bent substrate.
  • the first insulating layer 110 represents an electrical wiring connecting circuit components based on a circuit design as a wiring diagram, and an electrical conductor may be reproduced on an insulating material.
  • the first insulating layer 110 mounts electrical components and forms a wiring that connects them in a circuit, and mechanically fixes components other than the electrical connection function of the components.
  • a circuit pattern may be disposed on the surface of the first insulating layer 110.
  • the first circuit pattern 120 may be disposed under the first insulating layer 10.
  • a second circuit pattern 140 may be disposed on the first insulating layer 110.
  • the first circuit pattern 120 may be buried under the first insulating layer 110.
  • the lower surface of the first circuit pattern 120 may be positioned on the lower surface of the first insulating layer 110 and the doil plane.
  • the second circuit pattern 120 may be disposed on the upper surface of the first insulating layer 110.
  • the second circuit pattern 130 may be disposed to have a structure protruding above the upper surface of the first insulating layer 110.
  • the lower surface of the second circuit pattern 130 may be disposed in direct contact with the upper surface of the first insulating layer 110.
  • the first circuit pattern 120 and the second circuit pattern 130 are wirings that transmit electrical signals, and may be formed of a metal material having high electrical conductivity.
  • the first circuit pattern 120 and the second circuit pattern 130 are gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and It may be formed of at least one metal material selected from zinc (Zn).
  • the first circuit pattern 120 and the second circuit pattern 130 are gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu) having excellent bonding strength.
  • Zinc (Zn) may be formed of a paste or solder paste including at least one metal material selected from.
  • the first circuit pattern 120 and the second circuit pattern 130 may be formed of copper (Cu) having high electrical conductivity and relatively low cost.
  • the first circuit pattern 120 and the second circuit pattern 130 are a conventional manufacturing process of a printed circuit board, such as an additive process, a subtractive process, and a modified semi-additive process (MSAP). And SAP (Semi Additive Process) method, etc., and detailed descriptions are omitted here.
  • the second insulating layer 140 may be disposed on the first insulating layer 110.
  • the second insulating layer 140 may be disposed between the second circuit patterns 130 on the first insulating layer 110. That is, the second circuit pattern 130 may be disposed on the first insulating layer 110 at a predetermined interval.
  • the second insulating layer 140 may be disposed to cover a region of the upper surface of the first insulating layer 110 to which the second circuit pattern 130 is not disposed.
  • the second insulating layer 140 may have a structure in which the second circuit pattern 130 directly contacts.
  • the side surface of the second insulating layer 140 may directly contact the side surface of the second circuit pattern 130.
  • the second insulating layer 140 may be a support insulating layer that surrounds the second circuit pattern 130 and supports the second circuit pattern 130.
  • the second insulating layer 140 may have a structure in which a resin and a filler are mixed. That is, the second insulating layer 140 may be an insulating layer without ABF, RCC, or other glass fibers.
  • the second insulating layer 140 surrounds the second circuit pattern 130 on the first insulating layer 110 and directly contacts the side surface of the second circuit pattern 130 as described above. To form.
  • the second circuit pattern 130 of a fine pattern can be supported by the second insulating layer 140, and accordingly, the second circuit pattern 130 can be stably protected from an external impact. .
  • the second circuit pattern 130 when the second circuit pattern 130 is not a fine pattern, the second circuit pattern 130 may be resistant to external impact, and thus the second insulating layer 140 may be unnecessary.
  • the second circuit pattern 130 when the second circuit pattern 130 is a fine pattern, there is a problem that it is easily collapsed by an external impact, and accordingly, the second circuit pattern 130 is stably maintained using the second insulating layer 140. Be able to support.
  • the width of the second circuit pattern 130 may have a range of 6 ⁇ m to 15 ⁇ m. It is difficult to form the second circuit pattern 130 to have a width of less than 6 ⁇ m, and in the case of the second circuit pattern 130 having a width of less than 6 ⁇ m, it is too vulnerable to external shocks, so there is a problem in reliability I can.
  • the width of the second circuit pattern 130 may be 15 ⁇ m or less. In this case, the width of the second circuit pattern 130 may be greater than 15 ⁇ m.
  • the second circuit pattern 130 is larger than 15 ⁇ m, the need for the second insulating layer 140 is low, and even without the second insulating layer 140, the second circuit pattern 130 It does not collapse easily.
  • the interval between the second circuit patterns 130 is in the range of 8 ⁇ m to 15 ⁇ m.
  • the height H2 of the second insulating layer 140 may be smaller than the height H1 of the second circuit pattern 130. That is, the upper surface of the second insulating layer 140 may be positioned lower than the upper surface of the second circuit pattern 130. In addition, the lower surface of the second insulating layer 140 may be positioned on the same plane as the lower surface of the second circuit pattern 130.
  • the height H2 of the second insulating layer 140 and the height H1 of the second circuit pattern 130 may be the same.
  • a part of the second insulating layer 140 may be the second circuit pattern It may remain on the 130, and accordingly, a problem may occur in the function of the second circuit pattern 130.
  • the functional problem may mean a reliability problem in electrical connection with the device when the second circuit pattern 130 functions as a pad connected to an element (not shown). Accordingly, the height H2 of the second insulating layer 140 is lower than the height H1 of the second circuit pattern 130 to solve the above reliability problem.
  • the height H2 of the second insulating layer 140 is 20% or more compared to the height H1 of the second circuit pattern 130. That is, when the height H2 of the second insulating layer 140 is less than 20% of the height H1 of the second circuit pattern 130, the second circuit pattern is formed by the second insulating layer 140. The 130 cannot be stably supported, and accordingly, a collapse problem of the second circuit pattern 130 may occur.
  • the height H2 of the second insulating layer 140 is set to be 99% or less of the height of the second circuit pattern 130. That is, when the height H2 of the second insulating layer 140 exceeds 99% of the height H1 of the second circuit pattern 130, the second circuit pattern 130 2 A portion of the resin of the insulating layer 140 may remain, and a reliability problem may arise.
  • a solder resist is disposed on the first insulating layer 110 instead of the second insulating layer 140.
  • a solder resist is disposed in a state in which the second insulating layer 140 is not disposed, a situation in which the second circuit pattern 130 collapses during the application of the solder resist may occur.
  • the solder resist is removed while the solder resist is applied on the second circuit pattern 130, the possibility of cracking is very high due to the characteristics of the solder resist, and thus a problem may occur in the reliability of the printed circuit board. have.
  • the solder resist may be disposed after stably supporting the second circuit pattern 130 of the fine pattern by preferentially disposing the second insulating layer 140.
  • a solder resist may be additionally disposed on the second insulating layer 140.
  • the printed circuit board has an exposed area exposing a pad connected to a chip mounted or external substrate (eg, a main board).
  • a chip mounted or external substrate eg, a main board.
  • the structure in FIGS. 2 and 3 shows a portion of the entire area of the printed circuit board corresponding to the exposed area.
  • the printed circuit board includes a region that is externally covered by a solder resist.
  • a region covered by the solder resist is omitted.
  • the solder resist may be included.
  • the printed circuit board may include a first region and a second region.
  • the first area is an area in which the surface of the second circuit pattern is to be exposed to the outside
  • the second area is an area in which the surface of the second circuit pattern is to be covered by a solder resist.
  • the support insulating layer may be disposed in a space between the second circuit patterns of the box.
  • solder resist may be disposed to have a predetermined height in a region corresponding to the second region among the disposed supporting insulating layers.
  • solder resist may be disposed to cover the second circuit pattern located in the second region.
  • the filler in the process of removing the supporting insulating layer, may be exposed to the upper surface.
  • the filler may impart a predetermined roughness to the surface of the supporting insulating layer.
  • the solder resist may be disposed on an upper surface of the supporting insulating layer located in the second region. In this case, the bonding strength between the supporting insulating layer and the solder resist may be improved by the roughness of the supporting insulating layer applied by the filler.
  • FIG. 4A is a view showing a printed circuit board according to a comparative example
  • FIG. 4B is a view referred to for explanation of a problem occurring according to the height of a second insulating layer
  • 4C is a view showing a printed circuit board according to the present embodiment.
  • the second circuit pattern 30 is disposed on the insulating layer 10.
  • the second circuit pattern 30 has a structure protruding above the upper surface of the insulating layer 10.
  • the printed circuit board 100 includes a first insulating layer 110 and a second insulating layer disposed on the first insulating layer 110 and surrounding the second circuit pattern 130.
  • (140A) can be deployed.
  • the height of the second insulating layer 140A may be equal to or greater than the height of the second circuit pattern 130.
  • the second insulating layer 140A may remain on the surface of some of the areas C of the second circuit pattern 130, Accordingly, the surface area of the second circuit pattern 130 exposed to the outside may be reduced. In addition, when the surface area of the second circuit pattern 130 is reduced, a mounting defect of the device may not occur due to a reduction in a component mounting area for mounting the device.
  • the printed circuit board 100 has a first insulating layer 110 and a second circuit pattern 130 on the first insulating layer 110. ) May be disposed surrounding the second insulating layer 140.
  • the height of the second insulating layer 140 may be smaller than the height of the second circuit pattern 130.
  • the height of the second insulating layer 140 may have a range between 20% and 99% of the height of the second circuit pattern 130.
  • a second insulating layer supporting the side portion of the second circuit pattern is formed on the first insulation. Accordingly, problems such as collapse or friction of the protruding second circuit pattern may be solved by miniaturization of the second circuit pattern, and thus product reliability may be improved.
  • the upper surface of the second insulating layer is positioned lower than the upper surface of the second circuit pattern. That is, the height of the second insulating layer in the embodiment is lower than the height of the second circuit pattern. Accordingly, it is possible to solve the problem that the exposed area of the surface of the second circuit pattern is reduced due to the second insulating layer remaining on the surface of the second circuit pattern, and accordingly, the problem of reducing the component mounting area. .
  • FIG. 5 is a diagram illustrating a shape change of a second circuit pattern 130 according to an exemplary embodiment.
  • the printed circuit board 100 includes a second circuit pattern 130 disposed on the first insulating layer 110.
  • a second insulating layer 140 disposed in an area between the second circuit patterns 130 may be included on the first insulating layer 110.
  • the second insulating layer 140 has a height in the range of 20% to 99% of the height of the second circuit pattern 130.
  • the height of the second insulating layer 140 is 80% of the height of the second circuit pattern 130
  • an upper area of 20% of the total area of the second circuit pattern 130 is It may be removed together during the etching process of the second insulating layer 140.
  • the second circuit pattern 130 may include a first portion 131 disposed on the first insulating layer 110 and a second portion 132 disposed on the first portion 131.
  • the first part 131 is protected by the second insulating layer 140, and thus, the areas of the upper and lower surfaces may be the same.
  • the second part 132 may be partially removed from the upper part in the etching process of the second insulating layer 140, and accordingly, the area of the upper surface may be smaller than the area of the lower surface.
  • the cross section of the second portion 132 may have a trapezoidal shape.
  • the side surfaces of the second portion 132 may be arranged to be inclined with a certain inclination.
  • FIG. 6 is a view for explaining a problem according to the height of the second insulating layer.
  • the printed circuit board 100 includes a first insulating layer 110 and a second insulating layer 140B disposed on the first insulating layer 110 and surrounding the second circuit pattern 130. Can be placed.
  • the height of the second insulating layer 140B may be smaller than the height of the second circuit pattern 130.
  • the height of the second insulating layer 140B may be less than 20% of the height of the second circuit pattern 130.
  • the upper area of the second circuit pattern 130 may be removed together in the etching process of the second insulating layer 140.
  • the uppermost area may have a triangular pyramid shape.
  • the upper region of the second circuit pattern 130 may have a triangular shape. Accordingly, a mounting area for mounting a device on the second circuit pattern 130 is not secured, and thus, a mounting failure occurs.
  • the second insulating layer 140 in the embodiment may have a height of 20% to 99% compared to the height H1 of the second circuit pattern 130 as described above by an etching process.
  • the second insulating layer 140 may include a resin and an inorganic filler.
  • the inorganic filler disposed inside the second insulating layer 140 may be exposed on the surface by the etching.
  • the etching of the second insulating layer 140 may be performed by sand blasting, and otherwise, it may be performed by a plasma process.
  • FIG. 7A is a view showing the surface of a printed circuit board formed by sand blasting
  • FIG. 7B is a view showing the surface of a printed circuit board formed by plasma.
  • FIG. 7A(a) is an SEM photograph in which the surfaces of the second insulating layer 140 and the second circuit pattern 130 were enlarged 3000 times.
  • (b) of 7a is an SEM photograph in which the surface of the second circuit pattern 130 is enlarged 10000 times.
  • an inorganic filler 150a may be disposed in the second insulating layer 140, and as the sand blasting process of the second insulating layer 140 proceeds, The inorganic filler 150a may be exposed.
  • the inorganic filler 150a included in the second insulating layer 140 also remains on the surface of the second circuit pattern 130.
  • FIG. 7B (a) is an SEM photograph of a 3000 times magnification of the surfaces of the second insulating layer 140 and the second circuit pattern 130 formed by the plasma process.
  • (b) of 7b is an SEM photograph in which the surface of the second circuit pattern 130 is enlarged 10000 times.
  • an inorganic filler 150a may be disposed in the second insulating layer 140, and as the plasma process of the second insulating layer 140 proceeds, The inorganic filler 150a may be exposed.
  • the second insulating layer is disposed so that the upper surface of the second insulating layer is lower than the upper surface of the second circuit pattern. Etch In this case, an inorganic filler is present in the second insulating layer. In addition, by the etching of the second insulating layer, the inorganic filler may protrude and be disposed on the surface of the second insulating layer in the final product.
  • the surface area of the second insulating layer or the surface roughness of the second insulating layer may be increased by protruding the inorganic filler, and accordingly, a protective layer such as a solder resist disposed on the second insulating layer and Can improve the adhesion.
  • FIG 8 to 10 are views illustrating a method of manufacturing a printed circuit board according to an embodiment in order of processes.
  • the circuit pattern 130 is formed.
  • the first circuit pattern 120 and the second circuit pattern 130 may be formed by the ETS method.
  • the manufacturing process of the printed circuit board may start from preparing a separation carrier (not shown).
  • a first circuit pattern 120 may be formed on the separation carrier.
  • the first circuit pattern 120 is an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP), which are conventional manufacturing processes for printed circuit boards. And the like, and detailed description is omitted here.
  • the first circuit pattern 120 is a wiring that transmits an electrical signal, and may be formed of a metal material having high electrical conductivity.
  • the first circuit pattern 120 is at least selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). It can be formed of a single metallic material.
  • the first circuit pattern 120 is selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding power. It may be formed of a paste or solder paste including at least one metal material.
  • the first circuit pattern 120 may be formed of copper (Cu) having high electrical conductivity and relatively low cost.
  • the first circuit pattern 120 When the first circuit pattern 120 is formed, a first insulating layer 110 covering the first circuit pattern 120 is formed on the separation carrier. Accordingly, the first circuit pattern 120 may have a structure buried in the lower region of the first insulating layer 110.
  • a second circuit pattern 130 may be formed on the first insulating layer 110.
  • a second insulating layer 140 is formed on the first insulating layer 110.
  • the second insulating layer 140 may be disposed to cover the second circuit pattern 130.
  • the second insulating layer 140 may have a height greater than that of the second circuit pattern 130 and may be disposed on the first insulating layer 110.
  • a sand blasting process or a plasma process is performed to etch the second insulating layer 140.
  • the height H2 of the second insulating layer 140 is 20% to 99 compared to the height H1 of the second circuit pattern 130. Have a %.
  • the second circuit pattern is formed by the second insulating layer 140.
  • the 130 cannot be stably supported, and accordingly, a collapse problem of the second circuit pattern 130 may occur.
  • the height H2 of the second insulating layer 140 is set to be 99% or less of the height of the second circuit pattern 130. That is, when the height H2 of the second insulating layer 140 exceeds 99% of the height H1 of the second circuit pattern 130, the second circuit pattern 130 2 A portion of the resin of the insulating layer 140 may remain, and a reliability problem may arise.
  • the inorganic filler 150a may remain on the surface of the second insulating layer 140, and a part of the inorganic filler 150a may remain on the surface of the second circuit pattern 130.
  • a second circuit pattern supporting a side portion of the second circuit pattern on the first insulating layer To form an insulating layer. Accordingly, problems such as collapse or friction of the protruding second circuit pattern may be solved by miniaturization of the second circuit pattern, and thus product reliability may be improved.
  • the upper surface of the second insulating layer is positioned lower than the upper surface of the second circuit pattern. That is, the height of the second insulating layer in the embodiment is lower than the height of the second circuit pattern. Accordingly, it is possible to solve the problem that the exposed area of the surface of the second circuit pattern is reduced due to the second insulating layer remaining on the surface of the second circuit pattern, and accordingly, the problem of reducing the component mounting area. .
  • the second insulating layer is etched so that the upper surface of the second insulating layer is positioned lower than the upper surface of the second circuit pattern.
  • an inorganic filler is present in the second insulating layer.
  • the inorganic filler may protrude and be disposed on the surface of the second insulating layer in the final product. Accordingly, the surface area of the second insulating layer or the surface roughness of the second insulating layer may be increased by protruding the inorganic filler, and accordingly, a protective layer such as a solder resist disposed on the second insulating layer and Can improve the adhesion.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
PCT/KR2020/009340 2019-07-15 2020-07-15 인쇄회로기판 Ceased WO2021010754A1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202080051614.6A CN114128409A (zh) 2019-07-15 2020-07-15 印刷电路板
JP2022502583A JP7654628B2 (ja) 2019-07-15 2020-07-15 プリント回路基板
US17/628,178 US20220264750A1 (en) 2019-07-15 2020-07-15 Printed circuit board

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2019-0085102 2019-07-15
KR1020190085102A KR102872350B1 (ko) 2019-07-15 2019-07-15 회로기판

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WO2021010754A1 true WO2021010754A1 (ko) 2021-01-21

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JP (1) JP7654628B2 (https=)
KR (1) KR102872350B1 (https=)
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WO (1) WO2021010754A1 (https=)

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KR20220103965A (ko) * 2019-11-19 2022-07-25 도판 인사츠 가부시키가이샤 포장체의 제조 방법, 포장재용 필름 그리고 이것을 구비하는 적층 필름 및 포장재

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US20220264750A1 (en) 2022-08-18
KR20210008671A (ko) 2021-01-25
JP7654628B2 (ja) 2025-04-01
CN114128409A (zh) 2022-03-01
JP2022540683A (ja) 2022-09-16

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