WO2020240815A1 - 表示装置およびその駆動方法 - Google Patents

表示装置およびその駆動方法 Download PDF

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Publication number
WO2020240815A1
WO2020240815A1 PCT/JP2019/021699 JP2019021699W WO2020240815A1 WO 2020240815 A1 WO2020240815 A1 WO 2020240815A1 JP 2019021699 W JP2019021699 W JP 2019021699W WO 2020240815 A1 WO2020240815 A1 WO 2020240815A1
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Prior art keywords
circuit
temperature detection
temperature
data signal
signal lines
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PCT/JP2019/021699
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English (en)
French (fr)
Japanese (ja)
Inventor
守屋　政明
上野　雅史
直樹 塩原
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シャープ株式会社
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Priority to US17/609,290 priority Critical patent/US11854478B2/en
Priority to PCT/JP2019/021699 priority patent/WO2020240815A1/ja
Priority to CN201980096085.9A priority patent/CN113853645B/zh
Publication of WO2020240815A1 publication Critical patent/WO2020240815A1/ja

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0285—Improving the quality of display appearance using tables for spatial correction of display data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/041—Temperature compensation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present invention relates to a display device, and more particularly to a current-driven display device including a display element driven by a current such as an organic EL (Electro Luminescence) display device and a driving method thereof.
  • a current-driven display device including a display element driven by a current such as an organic EL (Electro Luminescence) display device and a driving method thereof.
  • An organic EL display device is known as a thin, high image quality, low power consumption display device.
  • the active matrix type organic EL display device includes a plurality of pixel circuits arranged two-dimensionally, and each pixel circuit includes an organic EL element, a drive transistor, and a holding capacitor.
  • the organic EL element is a self-luminous display element whose brightness changes according to a driving current.
  • the drive transistor controls the drive current flowing through the organic EL element according to the data voltage written in the holding capacitor.
  • a thin film transistor (hereinafter abbreviated as "TFT") is used as a drive transistor in a pixel circuit.
  • TFT thin film transistor
  • amorphous silicon TFTs, low-temperature polysilicon TFTs, oxide TFTs (also referred to as “oxide semiconductor TFTs”) and the like are used as drive transistors.
  • the oxide TFT is a TFT in which a semiconductor layer is formed of an oxide semiconductor.
  • In—Ga—Zn—O indium gallium zinc oxide
  • the gain of a MOS (Metal-Oxide-Semiconductor) transistor such as a TFT is determined by mobility, channel width, channel length, gate insulating film capacitance, etc., and the amount of current flowing through the MOS transistor is the gate-source voltage and gain. , It changes according to the threshold voltage and the like.
  • the threshold voltage, mobility, and the like vary, and as a result, the amount of drive current flowing through the organic EL element also varies. As a result, the displayed image has uneven brightness, and the display quality is deteriorated.
  • the drive current to be supplied from the drive transistor to the organic EL element is taken out of the pixel circuit and measured, and based on the measurement result.
  • Some are configured to correct the data voltage to be written to each pixel circuit so that the characteristic variation is compensated for.
  • the method of compensating for the variation in the characteristics of the drive transistor by such a configuration will be referred to as an "external compensation method" below.
  • Patent Document 1 International Publication No. 2014/021201 discloses an organic EL display device adopting such an external compensation method.
  • the data driver transmits the first and second measurement data corresponding to the first and second measurement data voltages to the controller 10, and the controller is based on the first and second measurement data.
  • the threshold voltage correction data and the gain correction data are updated, and the video data is corrected based on the threshold voltage correction data and the gain correction data.
  • both the threshold voltage compensation and the gain compensation of the drive transistor are performed for each pixel circuit while displaying the display.
  • the current flowing through the drive transistor in each pixel circuit is measured, and the data voltage to be written to the pixel circuit is determined based on the measurement result (hereinafter referred to as "current monitor result").
  • current monitor result the measurement result
  • the current monitor result fluctuates depending on the temperature. Therefore, in order to accurately perform such external compensation, it is necessary to correct the current monitor result according to the temperature distribution of the display panel in which a plurality of pixel circuits are arranged two-dimensionally.
  • Patent Document 2 and Patent Document 3 disclose a display device provided with a circuit for detecting temperature for each pixel circuit.
  • a circuit for temperature detection is provided for each pixel circuit in this way, the configuration of the display device becomes complicated, which is disadvantageous in improving the definition of the displayed image.
  • the display device is A display unit including a plurality of data signal lines, a plurality of scanning signal lines intersecting the plurality of data signal lines, and a plurality of pixel circuits arranged along the plurality of data signal lines and the plurality of scanning signal lines.
  • a data signal line drive circuit that drives the plurality of data signal lines
  • a scanning signal line drive circuit that selectively drives the plurality of scanning signal lines
  • An external compensation circuit that measures the current flowing through each pixel circuit and compensates for fluctuations in the characteristics of each pixel circuit.
  • Two or more temperature detection circuits arranged so as to correspond to two or more intersections of the plurality of data signal lines and the plurality of scanning signal lines.
  • Each pixel circuit It includes a display element driven by an electric current, a holding capacitor, and a driving transistor that controls the driving current of the display element according to the voltage held in the holding capacitor. When the corresponding scan signal line is selected, the voltage of the corresponding data signal line is configured to be written to the holding capacitor.
  • Each temperature detection circuit includes a temperature detection transistor. The temperature measurement circuit obtains the temperature of the temperature detection circuit by measuring the current flowing through the temperature detection transistor in each temperature detection circuit. The external compensation circuit estimates the temperature distribution in the display unit based on the temperature of each temperature detection circuit obtained by the temperature measurement circuit, and corrects the current measurement result in each pixel circuit based on the estimated temperature distribution. Then, the fluctuation of the characteristics of each pixel circuit is compensated based on the corrected measurement result.
  • the driving method includes a plurality of data signal lines, a plurality of scanning signal lines intersecting the plurality of data signal lines, and the plurality of data signal lines and the plurality of scanning.
  • a method of driving a display device including a display unit including a plurality of pixel circuits arranged along a signal line.
  • the display unit includes two or more temperature detection circuits arranged so as to correspond to two or more intersections of the plurality of data signal lines and the plurality of scanning signal lines.
  • Each pixel circuit It includes a display element driven by an electric current, a holding capacitor, and a driving transistor that controls the driving current of the display element according to the voltage held in the holding capacitor.
  • Each temperature detection circuit includes a temperature detection transistor.
  • the driving method is The data signal line driving step for driving the plurality of data signal lines, and A scanning signal line driving step that selectively drives the plurality of scanning signal lines, and An external compensation step that measures the current flowing through each pixel circuit and compensates for fluctuations in the characteristics of each pixel circuit.
  • Each temperature detection circuit includes a temperature measurement step of obtaining the temperature of the temperature detection circuit by measuring the current flowing through the temperature detection transistor. In the external compensation step, the temperature distribution in the display unit is estimated based on the temperature of each temperature detection circuit obtained in the temperature measurement step, and the current measurement result in each pixel circuit is corrected based on the estimated temperature distribution. Then, the fluctuation of the characteristics of each pixel circuit is compensated based on the corrected measurement result.
  • two or more temperature detection circuits correspond to two or more of the intersections of the plurality of data signal lines and the plurality of scanning signal lines in the display unit.
  • the temperature of the temperature detection circuit can be obtained by measuring the current flowing through the temperature detection transistor in each temperature detection circuit.
  • the temperature distribution in the display unit is estimated based on the temperature of each temperature detection circuit obtained in this way, and the current value of the pixel circuit measured for compensation for fluctuations in the characteristics of each pixel circuit based on the temperature distribution. (Current monitor result) is corrected. Based on the current value corrected in this way, that is, the current monitor result after temperature compensation, fluctuations in the characteristics of each pixel circuit are compensated.
  • the temperature distribution in the display unit is taken into consideration by using a smaller number of temperature detection circuits than before, instead of providing a circuit for detecting the temperature for each pixel circuit. It is possible to compensate for the characteristics of the pixel circuit (specifically, the characteristics of the drive transistor). In this way, accurate external compensation can be performed in consideration of the temperature distribution in the display unit while suppressing the complexity of the configuration.
  • FIG. 6 is a timing chart (A, B, C) showing an operation example of the organic EL display device according to the first embodiment. It is a timing chart which shows the change of the signal in the normal display mode in the said 1st Embodiment. It is a circuit diagram which shows the current flow in the program period about the pixel circuit in the 1st Embodiment. It is a circuit diagram which shows the current flow in the program period about the temperature detection circuit in the 1st Embodiment. It is a circuit diagram which shows the flow of the electric current in the light emission period in the said 1st Embodiment. It is a timing chart which shows the signal change in the characteristic detection mode in the said 1st Embodiment.
  • the gate terminal corresponds to the control terminal
  • one of the drain terminal and the source terminal corresponds to the first conduction terminal
  • the other corresponds to the second conduction terminal.
  • the transistors in each embodiment will be described as being N-channel type, the present invention is not limited thereto.
  • the transistor in each embodiment is, for example, a thin film transistor, but the present invention is not limited thereto.
  • connection means "electrical connection” unless otherwise specified, and is not limited to the case where it means a direct connection without departing from the gist of the present invention. It also includes the case of meaning an indirect connection via an element.
  • FIG. 1 is a block diagram showing an overall configuration of an active matrix type organic EL display device according to a first embodiment of the present invention.
  • This organic EL display device includes a display control circuit 100, a data side drive circuit 200, a scanning side drive circuit 400, and a display panel 500 as a display unit (hereinafter referred to as "display unit 500").
  • the data side drive circuit 200 includes a series-parallel conversion unit 202, a DA conversion unit 204, an AD conversion unit 206, and an input / output buffer unit 208.
  • One or both of the scanning side drive circuit 400 and the data side drive circuit 200 may be integrally formed with the display unit 500.
  • a high level power supply voltage EL VDD and a low level power supply voltage ELVSS which will be described later, to be supplied to the display unit 500, a display control circuit 100, a data side drive circuit 200, and a scanning side drive circuit 400
  • a power supply circuit (not shown) that generates a power supply voltage (not shown) to be supplied is included.
  • the organic EL display device has a function of compensating for variation and deterioration of the characteristics of the drive transistor in the pixel circuit by an external compensation method (more generally, the difference in characteristics between the pixel circuits in the display unit 500 and each of them. It has a function to compensate for fluctuations in the characteristics of the pixel circuit), and as operation modes, it has a normal display mode in which an image is displayed on the display unit 500 based on an external input signal Sin, and a drive in each pixel circuit for external compensation. It has a characteristic detection mode that measures the current flowing through the transistor (details will be described later).
  • the switching of the operation mode between the normal display mode and the characteristic detection mode may be realized by including the mode control signal Cm that specifies the operation mode in the input signal Sin, or in order to manually switch the operation mode.
  • the switch may be provided in the organic EL display device, and the mode control signal Cm may be generated according to the operation of the switch.
  • N (N is an integer of 2 or more) scanning signal lines GL1 (1) to GL1 (N) and N monitor control lines GL2 (1) to GL2 (N) are arranged.
  • a large number of pixel circuits 10 are arranged in a matrix along M data signal lines DL (1) to DL (M) and N scanning signal lines GL1 (1) to GL1 (N). Have been placed.
  • Each pixel circuit 10 is connected to any of M data signal lines DL (1) to DL (M) and is connected to any of N scanning signal lines GL1 (1) to GL1 (N). It is also connected to any of N monitor control lines GL2 (1) to GL2 (N). However, none of the pixel circuits 10 is connected to the M data signal lines DL (1) to DL (M) at a ratio of one data signal line to the m data signal lines (for the entire display unit 500). (Q) are included, and each of these q data signal lines DL (m), DL (2 m), ..., DL (q ⁇ m) has a temperature detection circuit 12 for each n scan signal lines.
  • the display unit 500 is provided with a power supply line (not shown) common to each pixel circuit 10 and each temperature detection circuit 12. That is, the first power supply line (hereinafter referred to as “high level power supply line”) for supplying the high level power supply voltage EL VDD for driving the organic EL element (also referred to as “OLED") described later is the same as the high level power supply voltage. (Indicated by the symbol “EL VDD”) and the second power supply line for supplying the low-level power supply voltage ELVSS for driving the organic EL element (hereinafter referred to as “low-level power supply line", the same code as the low-level power supply voltage. (Represented by "ELVSS”) is arranged.
  • the display control circuit 100 receives an input signal Sin including image data representing an image to be displayed and timing control information for displaying the image from the outside of the display device, and based on this input signal Sin, the data side control signal Scd and the scanning side.
  • the control signal Scs is generated, and the data side control signal Scd is output to the data side drive circuit 200, and the scanning side control signal Scs is output to the scanning side drive circuit 400.
  • the display control circuit 100 receives the measurement data MD from the data side drive circuit 200 in the characteristic detection mode (details will be described later).
  • FIG. 2 is a block diagram showing the configuration of the display control circuit 100.
  • the display control circuit 100 includes a data side signal generation circuit 110, a scanning side signal generation circuit 120, a RAM (RadomAccessMemory) 140, a flash memory 150 as a non-volatile memory, and a control unit 160.
  • the control unit 160 controls the data side signal generation circuit 110, the scanning side signal generation circuit 120, the RAM 140, and the flash memory 150 based on the input signal Sin from the outside.
  • the data side signal generation circuit 110 generates the above-mentioned data side control signal Scd to be given to the data side drive circuit 200 under the control of the control unit 160, and the scanning side signal generation circuit 120 is controlled by the control unit 160.
  • the RAM 140 includes an area as a gain correction memory 141, an area as a threshold voltage correction memory 142, and an area as a work memory 143.
  • the control unit 160 performs writing and reading of data to be stored in the RAM 140 and writing and reading of data to be stored in the flash memory 150.
  • the data side control signal Scd includes image data V1 representing an image to be displayed on the display unit 500, and this image data V1 is generated by performing correction processing on the image data V0 included in the input signal Sin. ..
  • the RAM 140 stores two types of correction data (gain correction data and threshold voltage correction data described later) used for correction of the image data V0 for each pixel circuit 10.
  • the display control circuit 100 generates the image data V1 by correcting the image data V0 using the correction data stored in the RAM 140. Further, the display control circuit 100 updates the correction data stored in the RAM 140 based on the measurement data MD received from the data side drive circuit 200. When the power is turned off, the display control circuit 100 reads the correction data stored in the RAM 140 and writes it in the flash memory 150. When the power is turned on, the display control circuit 100 reads the correction data stored in the flash memory 150 and writes it in the RAM 140.
  • the data side drive circuit 200 functions as a data signal line drive circuit and also as a current measurement circuit, and the current in each pixel circuit 10 is connected to the data signal line DL (j). Measure through.
  • the scanning side drive circuit 400 sets the scanning signal lines GL1 (1) to GL1 (N) by 1 in each frame period based on the scanning side control signal Scs as the scanning signal line driving circuit.
  • a predetermined period corresponding to the horizontal period is sequentially selected, and an active signal (high level voltage) is applied to the selected scanning signal line GL1 (is) as the scanning signal G1 (is) (1 ⁇ is ⁇ N).
  • an inactive signal is applied to the non-selected scanning signal line GL1 (in) as the scanning signal G1 (in) (1 ⁇ in ⁇ N and in ⁇ is).
  • the pixel circuits Pix (is, 1) to Pix (is, m-1), Pix (is, m + 1) to Pix (is, 2 ⁇ m-) connected to the selected scanning signal line GL1 (is). 1), ..., Pix (is, q ⁇ m + 1) to Pix (is, q ⁇ m + m-1) are collectively selected.
  • the data signal lines DL (1) to DL (M) were applied from the data side drive circuit 200, respectively.
  • Each of the voltages of the data signals D (1) to D (M) (hereinafter, these voltages may be simply referred to as "data voltage” without distinction) is the data signal line DL to which the voltage is applied. It is written as pixel data in (j) and the pixel circuit Pix (is, j) connected to the selected scanning signal line GL1 (is).
  • j is 1 to m-1, m + 1 to 2, m-1, ..., Q ⁇ m + 1 to q ⁇ m + m-1.
  • the voltage of D (q ⁇ m) is the voltage of q temperature detection circuits Tmp ((k-1) n + 1, m), Tmp ((k-1) n + 1,2 ⁇ m), ..., Tmp (( It is written as a data voltage in k-1) n + 1, q ⁇ m), respectively.
  • the scanning side drive circuit 400 selectively drives the scanning signal lines GL1 (1) to GL1 (N) based on the scanning side control signal Scs as the scanning signal line driving circuit, and drives the monitor control line.
  • the monitor control lines GL2 (1) to GL2 (N) are selectively driven based on the scanning side control signal Scs. That is, the scanning signal lines GL1 (1) to GL1 (N) are sequentially selected, and the monitor control lines GL2 (1) to GL2 (N) are sequentially selected for the scanning signal lines GL1 (1) to GL1 (N). )
  • the monitor control lines GL2 (1) to GL2 (N) are sequentially selected (see FIG. 12 described later).
  • An active signal (high level voltage) is applied as the monitor control signal G2 (is) to the selected monitor control line GL2 (is) (1 ⁇ is ⁇ N), and the non-selected monitor control line GL2 (is) (
  • An inactive signal (low level voltage) is applied to in) as the monitor control signal G2 (in) (1 ⁇ in ⁇ N and in ⁇ is).
  • the pixel circuit s Pix (is, 1) to Pix (is, m-1) and Pix (is, m + 1) to Pix (is, 2 ⁇ m-) connected to the selected monitor control line GL2 (is).
  • the temperature detection circuit Tmp ((k-1) n + 1, m), Tmp ((k-1) n + 1,2 ⁇ m), ..., Tmp ((k-1) n + 1, q ⁇ m) are also selected.
  • the flowing current is also measured by being taken out by the data side drive circuit 200 via the temperature detection data signal lines DL (m), DL (2 ⁇ m), ..., DL (q ⁇ m), respectively. See below).
  • FIG. 3 shows the pixel circuit 10 in the present embodiment, that is, the pixel circuit connected to the i-th scanning signal line GL1 (i) and the j-th data signal line DL (j) (hereinafter, “pixels in the i-th row and j-th column”). It is a circuit diagram which shows the electrical structure of Pix (i, j) (also referred to as "circuit").
  • the pixel circuit 10 includes an organic EL element OL as one light emitting display element, three N-channel transistors, and one capacitor Cst.
  • the transistor T1 functions as an input transistor whose gate terminal is connected to the scanning signal line GL1 (i) to select a pixel, and the transistor T2 is a current to the organic EL element OL according to the voltage held in the capacitor Cst.
  • the transistor T3 functions as a drive transistor that controls the supply of the drive transistor, and the transistor T3 is a monitor that controls whether or not its gate terminal is connected to the monitor control line GL2 (i) to measure current for detecting the characteristics of the drive transistor. Functions as a control transistor.
  • the input transistor T1 and the monitor control transistor T3 operate as switching elements.
  • the drain terminal of the drive transistor T2 is connected to the high-level power supply line EL VDD, the source terminal is connected to the low-level power supply line ELVSS via the organic EL element OL, and the gate terminal is input. It is connected to the data signal line DL (j) via the transistor T1. Further, the source terminal of the drive transistor T2 is connected to the data signal line DL (j) via the monitor control transistor T3.
  • FIG. 4 shows the temperature detection circuit 12 in the present embodiment, that is, the temperature detection circuit connected to the i-th scanning signal line GL1 (i) and the j-th data signal line DL (j) (hereinafter, “i-row, j-th column”). It is a circuit diagram which shows the electrical structure of Tmp (i, j) (also referred to as "the temperature detection circuit”).
  • the temperature detection circuit 12 has the same configuration as the pixel circuit 10 shown in FIG. 3, except that it does not include the organic EL element OL, and has an input transistor T1, a drive transistor T2, a monitor control transistor T3, and a capacitor Cst. Includes.
  • the transistor T2 in the temperature detection circuit 12 functions as a temperature detection transistor.
  • FIG. 5 is a cross-sectional view for explaining an implementation example of the temperature detection circuit 12 in the present embodiment.
  • the thin film transistor hereinafter referred to as “temperature detection TFT” as a component of the temperature detection circuit 12 is an inorganic film (moisture proof film) similar to the thin film transistor (TFT) in the pixel circuit of the top emission type organic EL display device.
  • TFT thin film transistor
  • It is laminated on 512 and is located below the anode 520 of the organic EL element in the pixel circuit 10. That is, a semiconductor layer for a temperature detection TFT is formed on an inorganic insulating film 512 as a moisture-proof layer formed on an insulator substrate 510 formed of a glass substrate or a resin material such as polyimide.
  • This semiconductor layer is composed of an intrinsic semiconductor 522 as a channel region, a conductor 521a as a source region formed so as to face each other via the channel region, and a conductor 521b as a drain region.
  • a gate insulating film GI is further formed on the semiconductor layer having such a structure, and a gate electrode G is formed on the gate insulating film GI.
  • the first inorganic insulating film 514 and the second inorganic insulating film 516 are sequentially formed so as to cover the gate electrode G.
  • Metal layers for electrical connection with other elements are formed on the second inorganic insulating film 516, and these metal layers are formed by contact holes with a conductor 521a as a source region and a conductor 521b as a drain region.
  • An insulating layer 518 as a flattening film is formed on the second inorganic insulating film 516 so as to cover a metal layer (not shown).
  • the data side drive circuit 200 in this embodiment includes a series-parallel conversion unit 202, a DA conversion unit 204, an AD conversion unit 206, and an input / output buffer unit 208.
  • the data side control signal Scd generated based on the input signal Sin is given to the data side drive circuit 200.
  • the data side control signal Scd includes a serial format digital image signal corresponding to the image data V1, and the serial format digital image signal is in parallel format one display line at a time in the serial-parallel conversion unit 202. It is converted to a digital image signal and latched.
  • the latched digital image signal for one line is converted into an analog voltage signal for one line by the DA conversion unit 204.
  • FIG. 6 is a circuit diagram for explaining the detailed configuration of the data side drive circuit 200 in the present embodiment, and is among the input / output buffer unit 208, the AD conversion unit 206, and the DA conversion unit 204 in the data side drive circuit 200.
  • the detailed configuration of the portion corresponding to one data signal line DL (j) is shown together with the series-parallel conversion unit 202.
  • the data side drive circuit 200 has an input / output buffer 28, a DA converter (DAC) 20, and an AD converter (ADC) 24 as circuit parts corresponding to one data signal line DL (j). And is included.
  • DAC DA converter
  • ADC AD converter
  • the digital image signal Vm (i, j, P) is a data voltage to be applied to the pixel circuit Pix (i, j) in order to display pixels with a gradation value P in the pixel circuit Pix (i, j). It is a digital signal indicating.
  • the data side control signal Scd described above includes an input / output control signal DWT in addition to the serial format digital image signal, and this input / output control signal DWT is input to the input / output buffer 28.
  • the input / output buffer 28 includes an operational amplifier 21, a capacitor 22, a first switch 23a, and a second switch 23b.
  • the inverting input terminal of the operational amplifier 21 is connected to the data signal line DL (j), and the non-inverting input terminal of the operational amplifier 21 is connected to the second switch 23b as a selection switch.
  • the non-inverting input terminal of the operational amplifier 21 is connected to the output terminal of the DA converter 20 when the input / output control signal DWT is at high level (H level), and the input output control signal DWT is at low level (H level). When it is (L level), it is connected to the low level power supply line ELVSS.
  • the capacitor 22 is provided between the inverting input terminal and the output terminal of the operational amplifier 21, and the output terminal of the operational amplifier 21 is connected to the inverting input terminal of the operational amplifier 21 via the capacitor 22.
  • the first switch 23a is provided between the inverting input terminal and the output terminal of the operational amplifier 21, and is connected in parallel with the capacitor 22.
  • the capacitor 22 functions as a current-voltage conversion element.
  • the first switch 23a is in the ON state when the input / output control signal DWT is at the H level, and is in the OFF state when the input / output control signal DWT is at the L level.
  • the output terminal of the operational capacitor 21 is connected to the input terminal of the AD converter 24, and when the input / output control signal DWT is at the L level, a digital signal indicating the current flowing through the data signal line DL (j) (“current monitor signal” Im (i, j, P) is output from the AD converter 24.
  • the input / output buffer 28 having such a configuration, when the input / output control signal DWT is at H level, the first switch 23a is in the ON state, and the output terminal and the inverting input terminal of the operational amplifier 21 are directly connected (short circuit). Will be). Further, the non-inverting input terminal of the operational amplifier 21 is connected to the output terminal of the DA converter 20 by the second switch 23b. At this time, the input / output buffer 28 functions as a voltage hollower, and the digital signal Vm (i, j, P) input to the DA converter 20 is converted into an analog voltage signal, and the data signal line DL ( It is given to j).
  • the first switch 23a is in the off state, and the output terminal of the operational amplifier 21 is connected to the inverting input terminal via the capacitor 22. Further, the non-inverting input terminal of the operational amplifier 21 is connected to the low level power supply line ELVSS by the second switch 23b.
  • the operational amplifier 21 and the capacitor 22 function as integrators. That is, the operational capacitor 21 outputs a voltage corresponding to the integrated value of the current flowing through the data signal line DL (j) connected to the inverting input terminal, and this voltage is converted into a digital signal by the AD converter 24 and the current.
  • the organic EL display device has, as operation modes, a normal display mode for displaying an image on the display unit 500 based on the input signal Sin, and a current flowing through the drive transistor T2 in each pixel circuit 10. It has a characteristic detection mode that measures and detects transistor characteristics.
  • operation modes a normal display mode for displaying an image on the display unit 500 based on the input signal Sin, and a current flowing through the drive transistor T2 in each pixel circuit 10.
  • It has a characteristic detection mode that measures and detects transistor characteristics.
  • the data voltage written in the pixel circuit Pix (i, j) in order to display the pixels with the gradation value P in the pixel circuit 10 in the i-th row and the j-th column, that is, the pixel circuit Pix (i, j) is calculated.
  • the digital image signal Vm (i, j, P) indicating the data voltage it is indicated by the reference numeral “Vm (i, j, P)”.
  • This data voltage Vm (i, j, P) is obtained by performing threshold voltage compensation and gain compensation of the drive transistor T2 in the pixel circuit Pix (i, j) with respect to the data voltage corresponding to the gradation value P. This is the obtained voltage (details will be described later with reference to FIG.
  • FIG. 7A is a timing chart showing a first operation example of the organic EL display device according to the present embodiment.
  • the organic EL display device according to the present embodiment operates in the normal display mode when the power switch is turned on, and switches the operation mode to the characteristic detection mode when the power switch is turned off. As shown in FIG.
  • the data voltage Vm (i, j, P1) corresponding to the first gradation value P1 is set to each pixel circuit Pix ( By writing to i, j) and each temperature detection circuit Tmp (i, j) and measuring the current flowing through the transistor T2 in each pixel circuit Pix (i, j) and each temperature detection circuit Tmp (i, j). 1 Obtain the measured value Im (i, j, P1). Next, the temperature Tm (it, jt) is detected based on the first measured value Im (it, jt, P1), which is the current measured value obtained for each temperature detection circuit Tmp (it, jt), and all temperatures are detected.
  • the estimated temperature Tmp (ip, jp) in each pixel circuit (ip, jp) is obtained by interpolation processing based on the temperature Tm (it, jp) of the circuit Tmp (it, jp).
  • the first measured value Im (ip, jp, P1) is subjected to temperature compensation using the estimated temperature Tmp (ip, jp) to compensate the first temperature.
  • the second detection period TM2 starts, and the following operations are performed in the second detection period TM2.
  • the data voltage Vm (i, j, P2) corresponding to the second gradation value P2 is written to each pixel circuit Pix (i, j), and each pixel circuit Pix (i, j) and each temperature detection circuit Tmp (
  • the second measured value Im (i, j, P2) is obtained by measuring the current flowing through the transistor T2 in i, j).
  • temperature compensation is applied to the second measured value Im (ip, jp, P2) using the estimated temperature Tmp (ip, jp) in each pixel circuit (ip, jp) obtained in the first detection period TM1.
  • the second temperature compensation measurement value Imc (ip, jp, P2) is obtained.
  • the first temperature compensation measurement value Imc (ip, jp, P1) obtained in the first detection period TM1 and the second obtained in the second detection period TM2.
  • the correction data stored in the display control circuit 100 is updated based on the temperature compensation measurement value Imc (ip, jp, P2) (see FIG. 2).
  • the first gradation value P1 and the second gradation value P2 are selected so that the correction data can be appropriately updated (details will be described later).
  • each temperature detection circuit Tmp (it, jt) may be detected by writing a data voltage to the temperature detection circuit Tmp (it, jt) and measuring the current flowing through the transistor T2 in the temperature detection circuit Tmp (it, jt).
  • each temperature detection circuit Tmp (it, jt) can be set as a temperature detection value by using the average value of the temperatures detected in each of the first and second detection periods TM1 and TM2 as the temperature detection value.
  • the accuracy of temperature detection by (it, jt) can be improved.
  • FIG. 7B is a timing chart showing a second operation example of the organic EL display device according to the present embodiment. Also in this operation example, the organic EL display device according to the present embodiment operates in the normal display mode when the power switch is turned on, and switches the operation mode to the characteristic detection mode when the power switch is turned off. As shown in FIG.
  • the data voltage Vm (it, jt, P1) corresponding to the first gradation value P1 is set to each temperature detection circuit Tmp (
  • the first measured value Im (it, jt, P1) is obtained by writing to it, jt) and measuring the current flowing through the transistor T2 in each temperature detection circuit Tmp (it, jt).
  • the temperature Tm (i, j) is detected for each temperature detection circuit Tmp (it, jt) based on the first measured value Im (it, jt, P1), and all the temperature detection circuits Tmp (it, jt) are detected. ),
  • the estimated temperature Tmp (ip, jp) in each pixel circuit (ip, jp) is obtained by interpolation processing based on the temperature Tm (i, j).
  • the first detection period TM1 starts, and the following operations are performed in the first detection period TM1.
  • the data voltage Vm (ip, jp, P1) corresponding to the first gradation value P1 is written in each pixel circuit Pix (ip, jp), and the current flowing through the transistor T2 in each pixel circuit Pix (ip, jp) is transmitted.
  • the first measured value Im (ip, jp, P1) is obtained.
  • the first temperature is compensated for the first measured value Im (ip, jp, P1) using the estimated temperature Tmp (ip, jp).
  • Compensation measurement value Imc (ip, jp, P1) is obtained. After that, for each pixel circuit Pix (ip, jp), the threshold voltage correction data Vt (ip, jp) is updated using the first temperature compensation measurement value Imc (ip, jp, P1).
  • the second detection period TM2 starts, and the following operations are performed in the second detection period TM2.
  • the data voltage Vm (ip, jp, P2) corresponding to the second gradation value P2 is written in each pixel circuit Pix (ip, jp), and the current flowing through the transistor T2 in each pixel circuit Pix (ip, jp) is transmitted.
  • the second measured value Im (i, j, P2) is obtained by the measurement.
  • the second temperature is compensated for the second measured value Im (ip, jp, P2) using the estimated temperature Tmp (ip, jp).
  • Compensation measurement value Imc (ip, jp, P2) is obtained. Then, for each pixel circuit Pix (ip, jp), the gain correction data B2R (ip, jp) is updated using the second temperature compensation measurement value Imc (ip, jp, P2).
  • the threshold voltage correction data Vt (ip, jp) is updated in the first detection period TM1 based on the first temperature compensation measurement value Imc (ip, jp, P1).
  • the gain correction data B2R (ip, jp) is updated in the second detection period TM2 based on the second temperature compensation measurement value Imc (ip, jp, P2).
  • the first operation example it was necessary to temporarily store the first measured value Im (ip, jp, P1) of the all-pixel circuit Pix (ip.jp), but in this operation example , Such storage of the first measured value Im (ip, jp, P1) and the like becomes unnecessary. However, in this operation example, the amount of processing in the characteristic detection mode is larger than that in the first operation example.
  • FIG. 7C is a timing chart showing a third operation example of the organic EL display device according to the present embodiment. Also in this operation example, the organic EL display device according to the present embodiment operates in the normal display mode when the power switch is turned on, and switches the operation mode to the characteristic detection mode when the power switch is turned off. As shown in FIG. 7 (C), in the characteristic detection mode, first, in the temperature detection period TMT, each pixel circuit (ip, jp) is operated by the same operation as the second operation example (FIG. 7 (B)). Estimated temperature Tmp (ip, jp) in.
  • the first detection period TM1 starts.
  • the first detection period TM1 is performed by the same operation as that of the first detection period TM1 in the second operation example, and the estimated temperature Tmp (ip, jp) is used for each pixel circuit Pix (ip, jp).
  • the temperature compensation measured value Imc (ip, jp, P1) is obtained.
  • the correction data such as the threshold voltage correction data Vt (ip, jp) is not updated.
  • the second detection period TM2 starts.
  • the estimated temperature Tmp (ip, jp) is used for each pixel circuit Pix (ip, jp) by the same operation as the second detection period TM2 in the second operation example.
  • the correction data such as the threshold voltage correction data Vt (ip, jp) is not updated.
  • the correction update period TMU starts.
  • the first and second temperature compensation measurement values Imc (ip, jp, P1) and Imc (ip, jp, P2) are used to obtain a threshold value.
  • the voltage correction data Vt (ip, jp) is updated and the gain correction data B2R (ip, jp) is updated (details will be described later).
  • the operation may be performed.
  • the data voltage Vm (it, jt, P1) corresponding to the first gradation value P1 is written to each temperature detection circuit Tmp (it, jt), and each temperature detection circuit Tmp (it, jt).
  • the second measured value Im (it, jt, P1) may be obtained by measuring the current flowing through the transistor T2.
  • the second temperature Tm'(it, jt) is detected for each temperature detection circuit Tmp (it, jt) based on the second measured value Im (it, jt, P1), and all the temperature detection circuits Tmp (it, jt) are detected.
  • the second estimated temperature Tmp'(ip, jp) in each pixel circuit (ip, jp) may be obtained by interpolation processing based on the second temperature Tm'(it, jp) of it, jt). Further, in the second detection period TM2, for each pixel circuit Pix (ip, jp), the temperature is relative to the second measured value Im (ip, jp, P2) using the second estimated temperature Tmp'(ip, jp). By applying compensation, the second temperature compensation measurement value Imc (ip, jp, P2) may be obtained.
  • the data voltage written in each temperature detection circuit Tmp (it, jt) during each temperature detection period corresponds to the first gradation value P1. It does not have to be the same value as the data voltage Vm (it, jt, P1).
  • the data voltage written in each temperature detection circuit Tmp (it, jt) during the temperature detection period may be appropriately determined in consideration of the temperature characteristics of the temperature detection transistor T2 in the temperature detection circuit 12.
  • FIG. 8 is a timing chart showing changes in signals in the normal display mode according to the present embodiment.
  • FIG. 9 is a diagram showing a current flow during a program period described later with respect to the pixel circuit Pix (i, j) in the present embodiment.
  • FIG. 10 is a diagram showing a current flow during a program period described later for the temperature detection circuit in this embodiment.
  • FIG. 11 is a diagram showing a current flow during the light emission period in the present embodiment.
  • the input / output control signal DWT is always at the H level, and the monitor control signal G2 (i) is always at the L level.
  • program period A1 a process of writing the data voltage Vm (i, j, P) to the pixel circuit Pix (i, j) is performed.
  • the scanning signal G1 (i) is at the L level.
  • the transistors T1 and T3 are in the off state, and the drive current IL corresponding to the voltage held in the capacitor Cst flows through the transistor T2 and the organic EL element OL (see FIG. 11). ).
  • the organic EL element OL emits light with a brightness corresponding to the drive current IL at this time.
  • the scanning signal G1 (i) changes to H level.
  • the transistor T1 is turned on.
  • the data voltage Vm (i, j, P) is applied as the data signal D (j) to the data signal line DL (j) by the action of the operational amplifier 21. Therefore, as shown in FIG. 9, a data voltage Vm (i, j, P) is applied to one end (lower terminal) of the capacitor Cst via the data signal line DL (j) and the transistor T1, and the capacitor A high level power supply voltage EL VDD is applied to the other end (upper terminal) of the Cst. Therefore, in the program period A1, the capacitor Cst is charged to the voltage Vc represented by the following equation (1).
  • Vc EL VDD-Vm (i, j, P) ... (1)
  • the data signal line DL (j) is a temperature detection data signal line and the temperature detection circuit Tmp (i, j) is connected to the scanning signal line GL1 (i) (j is m, 2 m, ... , Q ⁇ m, and i is any of 1, n + 1, 2n + 1, ..., P ⁇ n + 1)
  • the capacitor Cst in the temperature detection circuit Tmp (i, j) is also the above formula ( The voltage Vc shown in 1) is charged (see FIGS. 1 and 10).
  • the scanning signal G1 (i) changes to the L level.
  • the transistor T1 is turned off, and the voltage Vc shown in the equation (1) is held in the capacitor Cst.
  • the source terminal of the transistor T2 is electrically disconnected from the data signal line DL (j). Therefore, in the pixel circuit Pix (i, j), after time t12, as shown in FIG. 11, a drive current IL flowing through the transistor T2 flows through the organic EL element OL, and the organic EL element OL has a brightness corresponding to the drive current IL. It emits light with. Since the transistor T2 operates in the saturation region, the drive current IL is given by the following equation (3).
  • the gain ⁇ of the transistor T1 included in the equation (3) is given by the following equation (4).
  • ⁇ ⁇ ⁇ (W / L) ⁇ Cox... (4)
  • Vt, ⁇ , W, L, and Cox are the threshold voltage, mobility, gate width, gate length, and gate insulating film per unit area of the transistor T2, respectively. Represents capacity.
  • Vgs is a gate-source voltage of the transistor T2, and when the voltage of the anode of the organic EL element OL (hereinafter referred to as “anode voltage”) is Va.
  • the details of the first operation example ((A) of FIG. 7) in the characteristic detection mode in the present embodiment will be described.
  • the scanning signal lines GL1 (1) to GL1 (N) are sequentially selected for each predetermined period, and the scanning signal lines GL1 (1) to GL1 (N) are sequentially selected.
  • the monitor control lines GL2 (1) to GL2 (N) are sequentially selected for a predetermined period so that the monitor control lines GL2 (1) to GL2 (N) follow each other.
  • the scanning signal lines GL1 (1) to GL1 (N) are sequentially selected for each predetermined period, and the scanning signal lines GL1 (1) to GL1 (
  • the monitor control lines GL2 (1) to GL2 (N) are sequentially selected for a predetermined period so that the monitor control lines GL2 (1) to GL2 (N) follow the sequential selection of N).
  • the period during which the i-th scanning signal line GL1 (i) is selected and the i-th monitor control line GL2 (i) are selected with reference to FIGS. 12 to 14 together with FIGS. 9 and 10 described above.
  • FIG. 12 is a timing chart showing changes in signals in the characteristic detection mode according to the present embodiment.
  • FIG. 13 is a circuit diagram showing a current flow in the current measurement period for the pixel circuit 10 in the present embodiment.
  • FIG. 14 is a circuit diagram showing a current flow during the current measurement period for the temperature detection circuit 12 in the present embodiment.
  • first program period B1 the scanning signal G1 (i) is at the H level, the transistor T1 is in the ON state, and monitor control is performed.
  • the signal G2 (i) is at the L level and the transistor T3 is in the off state, and a process of writing the data voltage Vm (i, j, P1) corresponding to the first gradation value P1 is performed.
  • first measurement period B2 At times t22 to t23 (hereinafter referred to as "first measurement period B2"), the scanning signal G1 (i) is at the L level and the transistor T1 is in the off state, and the monitor control signal G2 (i) is at the H level and the transistor T3. Is on, and at this time, the input / output buffer 28 operates as a current measurement circuit. Further, as shown in FIG. 12, in the second detection period TM2, the scanning signal G1 (i) is at the H level and the transistor T1 is in the ON state during the time t24 to t25 (hereinafter referred to as “second program period B3”).
  • the control signal G2 (i) is at the L level and the transistor T3 is in the off state, and a process of writing the data voltage Vm (i, j, P2) corresponding to the second gradation value P2 is performed.
  • second measurement period B4 the scanning signal G1 (i) is at the L level and the transistor T1 is in the off state, and the monitor control signal G2 (i) is at the H level and the transistor T3. Is on, and at this time, the input / output buffer 28 operates as a current measurement circuit.
  • the first gradation value P1 and the second gradation value P2 are determined so as to satisfy P1 ⁇ P2 within the range of the gradation values that the image data V0 can take. For example, when the range of gradation values that the image data V0 can take is 0 to 255, the first gradation value P1 is determined to be 80, and the second gradation value P2 is determined to be 160.
  • the drive current when the data voltage corresponding to the first gradation value P1 is written as the first measurement voltage Vm (i, j, P1) and the first measurement voltage Vm (i, j, P1) is the first.
  • the measurement data corresponding to the first drive current Im (i, j, P1) is referred to as the first measurement data, and is expressed as Im (i, j, P1) using the same symbol.
  • the measurement data corresponding to the second drive current Im (i, j, P2) is referred to as the second measurement data, and is expressed as Im (i, j, P2) using the same symbol.
  • the scanning signal G1 (i) and the input / output control signal DWT are at H level.
  • the scanning signal G1 (i) and the input / output control signal DWT are at the L level. Therefore, in the first and second program periods B1 and B3, as shown in FIG. 9, the first switch 23a is turned on, and the non-inverting input terminal of the operational amplifier 21 is set to the output terminal of the DA converter 20 by the second switch 23b.
  • the operational amplifier 21 By being connected to, the operational amplifier 21 functions as a buffer amplifier (voltage hollower).
  • the first switch 23a is turned off, and the operational amplifier 21 and the capacitor 22 function as an integrating amplifier.
  • the voltage of the data signal line DL (j) is equal to the low level power supply voltage ELVSS due to the virtual short circuit.
  • the scanning signal G1 (i) changes to the H level, and the transistor T2 is turned on accordingly.
  • the first measurement voltage Vm (i, j, P1) is input to the non-inverting input terminal of the operational amplifier 21.
  • the operational amplifier 21 functions as a buffer amplifier as described above (see FIG. 9). Therefore, in the first program period B1, the first measurement voltage Vm (i, j, P1) is applied to the data signal line DL (j). Therefore, in the first program period B1, the capacitor Cst in the pixel circuit Pix (i, j) is charged to the voltage Vc shown in the following equation (5).
  • Vc EL VDD-Vm (i, j, P1) ...
  • the data signal line DL (j) is a temperature detection data signal line and the temperature detection circuit Tmp (i, j) is connected to the scanning signal line GL1 (i) (j is m, 2 m, ... , Q ⁇ m and i is any one of 1, n + 1, 2n + 1, ..., P ⁇ n + 1), and the capacitor Cst in the temperature detection circuit Tmp (i, j) is also the above equation (5).
  • the voltage Vc shown in is charged (see FIGS. 1 and 10).
  • the scanning signal G1 (i) and the input / output control signal DWT change to the L level.
  • the first switch 23a is turned off, and the operational amplifier 21 and the capacitor 22 function as an integrating amplifier.
  • the non-inverting input terminal of the operational amplifier 21 is connected to the low-level power supply line ELVSS by the second switch 23b, so that the voltage of the inverting input terminal of the operational amplifier 21, that is, the data signal
  • the voltage of the line DL (j) becomes equal to the low level power supply voltage ELVSS due to the virtual short circuit. Therefore, the anode of the organic EL element OL in the pixel circuit Pix (i, j) has a voltage equal to the low level power supply voltage ELVSS, and no current flows through the organic EL element OL.
  • the monitor control signal G2 (i) since the monitor control signal G2 (i) is at the H level, a current path is formed via the transistor T3 in the on state.
  • the first drive current Im (i, j, P1) flowing through the transistor T2 is the data signal line DL (as shown in FIG. 13). It flows to j).
  • the input / output buffer 28 in the data side drive circuit 200 measures the first drive current Im (i, j, P1) flowing from the pixel circuit Pix (i, j) to the data signal line DL (j), and measures the value.
  • the first measurement data Im (i, j, P1) shown is output.
  • the input / output buffer 28 functions as a current measurement circuit that measures the current flowing through the pixel circuit Pix (i, j) (drive transistor T2).
  • j is an integer other than m, 2m, ..., Q ⁇ m that satisfies 1 ⁇ j ⁇ M.
  • the data signal line DL (j) is a temperature detection data signal line and the temperature detection circuit Tmp (i, j) is connected to the scanning signal line GL1 (i) (j is m, 2 m, ... , Q ⁇ m and i is any one of 1, n + 1, 2n + 1, ..., P ⁇ n + 1), as shown in FIG. 14, the temperature detection circuit Tmp (i, j).
  • the operation of the pixel circuit Pix (i, j) and the data side drive circuit 200 in the second program period B3 is the same as the operation in the first program period B1. Temperature detection in the second program period B3 when the data signal line DL (j) is the data signal line for temperature detection and the temperature detection circuit Tmp (i, j) is connected to the scanning signal line GL1 (i).
  • the operation of the circuit Tmp (i, j) and the data side drive circuit 200 is the same as the operation in the first program period B1.
  • the operation of the pixel circuit Pix (i, j) and the data side drive circuit 200 in the second measurement period B4 is the same as the operation in the first measurement period B2.
  • the operation of the circuit Tmp (i, j) and the data side drive circuit 200 is the same as the operation in the first measurement period B2.
  • the second measurement voltage Vm (i, j, P2) is written in the pixel circuit Pix (i, j) and the temperature detection Tmp (i, j), and in the second measurement period B4, the second measurement voltage Vm (i, j, P2) is written. 2
  • the drive current Im (i, j, P2) is measured, and the second measurement data Im (i, j, P2) indicating the value is output.
  • the scanning signal lines GL1 (1) to GL1 (N) are sequentially selected in the first detection period TM1 at the timing shown in FIG. 12, and accordingly.
  • Monitor control lines GL2 (1) to GL2 (N) are also sequentially selected, and also in the second detection period TM2, scanning signal lines GL1 (1) to GL1 (N) are sequentially selected, and accordingly.
  • Monitor control lines GL2 (1) to GL2 (N) are also sequentially selected.
  • the first detection period TM1 and the second detection period TM2 are integrated into one detection period, and each scanning signal line GL1 (i) is selected twice in the one detection period.
  • each monitor control line GL2 (i) twice the first and second measurement data Im (i, j, P1) and Im (i, j, P2) are acquired. You may.
  • FIG. 15 is a block diagram for explaining the correction process in the present embodiment, and shows the characteristics (gain and threshold voltage in this case) of the drive transistor T2 in each pixel circuit Pix (i, j) of the display control circuit 100.
  • the configuration of the part to be corrected to compensate for the variation and deterioration is shown.
  • the portion of the display control circuit 100 that performs the correction constitutes an external compensation circuit together with the data side drive circuit 200 that has a function of measuring the current flowing through each pixel circuit 10 (drive transistor) in the characteristic detection mode.
  • the display control circuit 100 uses a part of the storage area of the RAM 140 as the gain correction memory 141 and the other part of the storage area of the RAM 140 as the threshold voltage correction memory 142 (see FIG. 2).
  • the gain correction memory 141 stores data for performing gain compensation for the drive transistor T2 in the pixel circuit 10 (hereinafter referred to as “gain correction data”).
  • the threshold voltage correction memory 142 stores data indicating the value of the threshold voltage of the drive transistor T2 in the pixel circuit 10 (hereinafter referred to as “threshold voltage correction data”). Further, the display control circuit 100 uses the other part of the storage area of the RAM 140 as the working memory 143.
  • the gain correction memory 141 stores N ⁇ (Mq) gain correction data
  • the threshold voltage correction memory 142 stores N ⁇ (M).
  • -Q) Stores threshold voltage correction data.
  • the gain correction data corresponding to the pixel circuit Pix (i, j) is referred to as B2R (i, j)
  • the threshold voltage correction data corresponding to the pixel circuit Pix (i, j) is referred to as Vt (i, j).
  • the gain correction data B2R (i, j) are all set to "1"
  • the threshold voltage correction data Vt (i, j) are all set to the same value.
  • these correction data B2R (i, j) and Vt (i, j) are updated by the characteristic compensation process described later in the characteristic detection mode (see FIGS. 18 and 19).
  • the display control circuit 100 includes a first LUT (Look up Table) 101, a multiplier 102, an adder 103, a subtractor 104, a second LUT 105, and a CPU 106.
  • a logic circuit corresponding to the characteristic compensation process shown in FIG. 18 described later may be used.
  • the first LUT 101 stores the possible gradation value and the voltage value of the image data V0 included in the input signal Sin in association with each other.
  • the first LUT 101 outputs the voltage value Vd (P) corresponding to the gradation value P.
  • the multiplier 102 multiplies the voltage value Vd (P) output from the first LUT 101 and the gain correction data B2R (i, j) read from the gain correction memory 141.
  • the adder 103 adds the output of the multiplier 102 and the threshold voltage correction data Vt (i, j) read from the threshold voltage correction memory 142, and obtains the obtained value as the image data Vm (i, j, Output as P).
  • the image data Vm (i, j, P) is given by the following equation (6).
  • Vm (i, j, P) Vd (P) ⁇ B2R (i, j) + Vt (i, j)... (6)
  • Eq. (7) ( ⁇ / 2) x ⁇ Vd (P) x B2R (i, j) + Vt (i, j)-(Vt + Va) ⁇ 2 ... (7) Therefore, by changing the gain correction data B2R (i, j) and the threshold voltage correction data Vt (i, j) according to the state of the drive transistor T2, both the threshold voltage compensation and the gain compensation are performed for each pixel circuit 10. It can be carried out.
  • the threshold voltage compensation here means compensation for the voltage Vt + Va including not only the threshold voltage Vt of the drive transistor T2 but also the anode voltage Va corresponding to the forward voltage Vf of the organic EL element OL. ..
  • the image data Vm (i, j, P) is temporarily stored in, for example, a buffer memory (not shown), and then sent from the display control circuit 100 to the data side drive circuit 200 under the control of the CPU 106. After that, using such image data Vm (i, j, P) for each pixel circuit Pix (i, j), the above-described operation of the data side drive circuit 200 and the scanning side drive circuit 400 in the normal display mode. (See FIGS. 8, 9, and 11), the image indicated by the input signal Sin is displayed on the display unit 500.
  • correction processing in characteristic detection mode In the correction process in the present embodiment, the correction data (threshold voltage correction data and gain correction data) are updated based on the temperature-compensated current monitor result in the characteristic detection mode.
  • the correction process in such a characteristic detection mode will be described.
  • the second LUT 105 converts the first gradation value P1 into the first ideal characteristic value IO (P1) shown in the following equation (12), and the second gradation value P2 is shown in the following equation (13). Converted to the second ideal characteristic value IO (P2).
  • IO (P1) Iw ⁇ P1 2.2 ... (12)
  • IO (P2) Iw ⁇ P2 2.2 ... (13)
  • the image data Vm (i, j, P1) based on the first gradation value P1 and the image data Vm (i, j, P2) based on the second gradation value are driven on the data side in the same manner as described above. It is sent to the circuit 200.
  • the CPU 106 receives the first measurement data Im (i, j, P1) and the second measurement data Im (i, j, P2) from the data side drive circuit 200 as the corresponding current measurement data.
  • i is 1, n + 1,2n + 1, ..., P ⁇ n + 1.
  • the first and second measurement data in which j is any of m, 2 m, ..., Q ⁇ m indicate the measured value of the current flowing through the transistor T2 in the temperature detection circuit Tmp (i, j).
  • the temperature Tm (i, j) in the temperature detection circuit Tmp (i, j) is obtained by using the first measured value of the current flowing through the transistor T2 in each temperature detection circuit Tmp (i, j).
  • the row number of the temperature detection circuit 12 is indicated separately from the row number of the pixel circuit 10
  • “it” is used instead of “i”
  • the column number of the temperature detection circuit 12 is used in the pixel circuit 10.
  • "jt" shall be used instead of "j".
  • FIG. 16 is a characteristic diagram showing the temperature dependence of the voltage-current characteristics of the transistor T2 included in the temperature detection circuit Tmp (it, jt) in the present embodiment (hereinafter referred to as “transistor temperature characteristics”) (transistor T2). Changes in the temperature characteristics due to variations in the threshold voltage and gain are small and negligible).
  • the temperature Tm (it, jt) of the temperature detection circuit Tmp (it, jt) can be obtained based on the characteristic diagram of FIG.
  • Temperature compensation is performed for two current measurement values consisting of the values Im (ip, jp, P1) and the second measurement value Im (ip, jp, P2), and the current monitor results with temperature compensation are used.
  • the external compensation method compensates for variations and deterioration of the characteristics (threshold voltage and gain) of the drive transistor T2 in each pixel circuit 10.
  • the characteristic compensation processing of the pixel circuit 10 including the temperature compensation for such a current monitor result that is, the characteristic compensation processing of the drive transistor in the pixel circuit 10 (hereinafter, referred to as “transistor characteristic compensation processing” or simply “characteristic compensation processing”).
  • each temperature detection circuit Tmp (i, j) in the present embodiment is obtained as follows.
  • each pixel circuit Pix (i, j) or each temperature detection circuit Tmp (i, j) is indicated by Vm (i, j, P)
  • Vm (i, j, P) the data voltage to be written in each pixel circuit Pix (i, j) or each temperature detection circuit Tmp (i, j)
  • Vgs Vm (i, j, P) -Va (FIG. 13).
  • the drain current Id of the transistor T2 is a measured value Im of the current of the pixel circuit Pix (i, j) in which the data voltage Vm (i, j, P) is written or the temperature detection circuit Tmp (i, j). Corresponds to (i, j, P).
  • the temperature Tm ( The third LUT 108 associated with it, jp) and the estimated temperature Tmp (ip, jp) of the pixel circuit Pix (ip, jp) determined from the temperature Tm (it, jp) of each temperature detection circuit Tmp (it, jp).
  • the fourth LUT 109 which associates the temperature compensation coefficient rc with the combination of the data voltage Vm (ip, jp, P1) to be written to the pixel circuit Pix (ip, jp), is realized by using the RAM 140 or the flash memory 150. .. That is, the third LUT 108 and the fourth LUT 109 are prepared in advance using the RAM 140 or the flash memory 150 based on the transistor temperature characteristics shown in FIG.
  • the first measured value Im (it, jt, P1) of the temperature detection circuit Tmp (it, jt) is measured by the input / output buffer 28 that functions as the current measurement circuit in the data side drive circuit 200. Therefore, the input / output buffer 28 and the third LUT 108 realize a temperature measurement circuit for measuring the temperature Tm (it, jt) of the temperature detection circuit Tmp (i, j) (FIG. 14, J). 16 and 17). If the data voltage to be written to the temperature detection circuit Tmp (i, j) is constant, the input / output buffer 28 having a function of measuring the current flowing through the temperature detection circuit Tmp (i, j) is regarded as a temperature measurement circuit. You can also do it.
  • the temperature compensation coefficient rc is the first and second measured values Im (ip, jp) for each pixel circuit (ip, jp) in order to obtain the current value at a predetermined standard temperature (for example, 25 ° C.). It is a coefficient to be multiplied by jp, P1) and Im (ip, jp, P2).
  • the temperature characteristics of the transistor T2 can be regarded as substantially the same in the pixel circuit Pix (ip, jp) and the temperature detection circuit Tmp (it, jp), and the fourth LUT 109 is also based on the temperature characteristics of FIG.
  • the same temperature characteristics of the transistor T2 of the pixel circuit Pix (ip, jp) may be investigated in advance, and the fourth LUT 109 may be created based on the temperature characteristics.
  • FIG. 17 shows the above-mentioned third and fourth LUTs 108 and 109, and the CPU 106 performs the first and second measurements for each pixel circuit 10 by the temperature compensation processing using these the third and fourth LUTs 108 and 109.
  • the temperature dependence of the values Im (ip, jp, P1), Im (ip, jp, P2), that is, the temperature dependence of the current monitor result is compensated.
  • the transistor characteristic compensation process in the present embodiment includes a temperature compensation process for such a current monitor result.
  • FIG. 18 is a flowchart showing a transistor characteristic compensation process for one screen based on the first operation example ((A) of FIG. 7) in the present embodiment.
  • the CPU 106 operates as follows by loading a predetermined program stored in the flash memory 150 into the RAM 140 and executing the program.
  • the first measured value Im (i, j, P1) which is the current measured value for the pixel circuit 10 and the temperature detection circuit 12, is sequentially received from the data side drive circuit 200, and the received current measurement is performed.
  • the value (hereinafter, also referred to as “input measured value”) is temporarily stored in the working memory 143 in the RAM 140 (step S10).
  • input measured value is temporarily stored in the working memory 143 in the RAM 140 (step S10).
  • step S12 it is determined whether or not the current measured value (input measured value) input in the immediately preceding step S10 is the first measured value for the temperature detection circuit 12 (step S12). As a result of this determination, if the input measured value is the first measured value for the temperature detection circuit 12, the process proceeds to step S16, and if the input measured value is not the first measured value for the temperature detection circuit 12, that is, the first measurement value for the pixel circuit 10. If it is one measured value, the process proceeds to step S22.
  • step S16 the temperature detection circuit Tmp (it, jt) is used by the third LUT 108 from the combination of the first measured value Im (it, jt, P1) which is the input measured value and the corresponding data voltage Vm (it, jt, P1). ) Temperature Tm (it, jt).
  • step S18 it is determined whether or not the temperatures of all the temperature detection circuits 12 have been obtained by this step S16 (step S18). As a result of this determination, if the temperature of any of the temperature detection circuits 12 has not been obtained, the process returns to step S10, and if the temperatures of all the temperature detection circuits 12 have been obtained, the process proceeds to step S20.
  • each pixel circuit Pix (ip, jp) is subjected to interpolation processing based on the arrangement of the pixel circuit 10 and the temperature detection circuit 12 shown in FIG. 1 from the temperature Tm (it, jp) obtained for all the temperature detection circuits 12.
  • Estimated temperature Tmp (ip, jp) is obtained. This interpolation process corresponds to estimating the temperature distribution in the display unit 500 based on the temperature Tm (it, jt) obtained for all the temperature detection circuits 12.
  • step S22 it is determined whether or not the first measured value for all the pixel circuits 10 and all the temperature detection circuits 12 has been received. As a result of this determination, when the first measurement value for all the pixel circuits 10 and all the temperature detection circuits 12 is not received, that is, the first measurement value for any pixel circuit 10 or any temperature detection circuit 12 If the above is not received, the process returns to step S10. After that, steps S10 to S22 are repeatedly executed until all the first measured values for all the pixel circuits 10 and all the temperature detection circuits 12 are received, and in step S22, the first measurement values for all the pixel circuits 10 and all the temperature detection circuits 12 are executed. 1 When it is determined that all the measured values have been received, the process proceeds to step S24.
  • the relevant pixel circuit Pix (i, j) is concerned.
  • the temperature compensation coefficient rc is obtained from the combination of the estimated temperature Tmp (i, j) of the pixel circuit and the first data voltage Vm (i, j, P1) written in the pixel circuit by the fourth LUT109. Then, the first temperature compensation measurement value Imc (i, j, P1) is obtained by multiplying this temperature compensation coefficient rc by the first measurement value Im (i, j, P1) of the pixel circuit.
  • Imc (i, j, P1) rc ⁇ Im (i, j, P1) ... (14) Is.
  • the first temperature compensation measurement value Imc (i, j, P1) measures the drain current with respect to the first gradation value P1 of the drive transistor T2 in the pixel circuit at a standard temperature (25 ° C.). The current measurement value at that time is shown.
  • the CPU 106 After receiving the first measured values for all the pixel circuits 10 and all the temperature detection circuits 12, the CPU 106 sequentially receives the second measured values Im (ip, jp, P2) for all the pixel circuits 10. When the CPU 106 receives one second measured value for the pixel circuit 10 in step S26, it temporarily stores it in the working memory 143 and proceeds to step S28.
  • step S28 for each pixel circuit Pix (i, j), the estimated temperature Tmp (i, j) of the pixel circuit is combined with the second data voltage Vm (i, j, P2) written in the pixel circuit.
  • the temperature compensation coefficient rc is obtained from the fourth LUT109.
  • the second temperature compensation measurement value Imc (i, j, P2) is a current measurement value when the drain current with respect to the second gradation value P2 of the drive transistor T2 in the pixel circuit is measured at a standard temperature (25 ° C.). Shown.
  • step S30 it is determined whether or not the second temperature compensation measurement value Imc (i, j, P2) of all the pixel circuits 10 has been obtained (step S30). As a result of this determination, if the second temperature compensation measurement value Imc (i, j, P2) of any of the pixel circuits 10 is not obtained, the process returns to step S26, and the second temperature compensation measurement value of all the pixel circuits 10 is obtained. When Imc (i, j, P2) is obtained, the process proceeds to step S32.
  • step S32 the first ideal characteristic value IO (P1) and the second ideal characteristic value IO (P2) are received from the above-mentioned second LUT 105 (see FIG. 15).
  • the threshold voltage correction data Vt (1) according to the comparison result between the first ideal characteristic value IO (P1) and the first temperature compensation measurement value Imc (i, j, P1) i, j) is updated (step S34). That is, when the following equation (16) is satisfied, ⁇ V is added to the threshold voltage correction data Vt (i, j), and when the following equation (17) is satisfied, the threshold voltage correction data Vt (i, j) ⁇ V is subtracted from, and the threshold voltage correction data Vt (i, j) is not updated when the following equation (18) is satisfied.
  • ⁇ V is a predetermined fixed value.
  • step S34 for each pixel circuit Pix (i, j), gain correction data is obtained according to the comparison result between the second ideal characteristic value IO (P2) and the second temperature compensation measurement value Imc (i, j, P2).
  • Update B2R (i, j) That is, when the following equation (19) is satisfied, ⁇ B is added to the gain correction data B2R (i, j), and when the following equation (20) is satisfied, the gain correction data B2R (i, j) to ⁇ B Is subtracted, and the gain correction data B2R (i, j) is not updated when the following equation (21) is satisfied.
  • ⁇ B is a predetermined fixed value.
  • IO (P2) -Imc (i, j, P2)> 0 ... (19) IO (P2) -Imc (i, j, P2) ⁇ 0 ... (20) IO (P2) -Imc (i, j, P2) 0 ... (21)
  • the data voltage Vd (P) corresponding to each gradation value P of the image data V0 included in the input signal Sin is the correction data stored for each pixel circuit.
  • the characteristics of the drive transistor T2 in each pixel circuit Pix (i, j). Variations and deterioration of (threshold voltage, gain) are compensated.
  • each of the data voltages (Vm (i, j, P1), Vm (i, j, P2)) corresponding to the predetermined gradation values (P1, P2) is written.
  • the current flowing through the drive transistor of the pixel circuit Pix (i, j) is measured (see FIG. 13), and the current measurement values obtained by the measurement (Im (i, j, P1), Im (i, j, P2)).
  • the correction data is updated based on (see FIGS. 15 and 18).
  • the data voltage is also written in the temperature detection circuit Tmp (it, jt) provided in the display unit 500, and the current flowing through the transistor T2 of the temperature detection circuit Tmp (it, jt) is measured (FIG.
  • the temperature Tm (it, jt) is obtained based on the measurement result. From each temperature Tm (it, jp) obtained in this way, the estimated temperature Tmp (ip, jp) of each pixel circuit Pix (ip, jp) can be obtained. Based on each estimated temperature Tmp (ip, jp) obtained, the current measurement values (Im (i, j, P1), Im (i, j, P2)) are temperature-compensated, whereby the first and second Temperature compensation measured values Imcc (i, j, P1) and Imcc (i, j, P2) are obtained. Such first and second temperature compensation measurement values Imcc (i, j, P1) and Imc (i, j, P2) are used for updating the correction data (FIGS. 17 and 18).
  • the present embodiment even if the temperature of each pixel circuit changes according to the display content immediately before the organic EL display device transitions from the normal display mode to the characteristic detection mode, the characteristics (threshold voltage and threshold voltage) of the drive transistor T2 It is possible to accurately compensate for variations in gain) and deterioration. That is, unlike the conventional example in which the current measurement for external compensation is performed after a long time has elapsed for the temperature of the display unit 500 to become uniform, even immediately after the image display on the display unit 500, the current measurement is performed. Accurate transistor characteristic compensation can be performed in consideration of the temperature distribution in the display unit at the current time.
  • the transistor characteristics are compensated by considering the temperature distribution in the display unit 500 by a smaller number of temperature detection circuits 12 than before, instead of providing a circuit for detecting the temperature for each pixel circuit. (See FIG. 1). In this way, according to the present embodiment, in the organic EL display device, accurate external compensation can be performed in consideration of the temperature distribution in the display unit while suppressing the complexity of the configuration.
  • the pixel circuit when the second gradation value P2 is higher than the first gradation value P1, the pixel circuit generates heat in the second detection period TM2, and the first detection period TM1 and the second detection period TM2 There may be a temperature difference between them. According to the present embodiment, even in such a case, the temperature is obtained in each of the first and second detection periods TM1 and TM2, and the measured value of the drive current in the pixel circuit is corrected (temperature compensation). (See FIG. 12), more accurate external compensation can be performed.
  • FIG. 18 shows a characteristic compensation process based on the first operation example (FIG. 7 (A)), but instead of the characteristic compensation process of FIG. 18, a second operation example (FIG. 7 (B)) is shown. ) Or the characteristic compensation process based on the third operation example ((C) of FIG. 7) may be performed.
  • the characteristic compensation process based on the second operation example ((B) of FIG. 7) is specifically as shown in FIG.
  • FIG. 19 is a flowchart showing a transistor characteristic compensation process for one screen in the second operation example of the present embodiment.
  • the CPU 106 operates as follows by loading a predetermined program stored in the flash memory 150 into the RAM 140 and executing the program.
  • the CPU 106 first sequentially calculates the measured values Im (it, jp, Pt) of the currents in all the temperature detection circuits 12 from the data side drive circuit 200. Then, the first measured value Im (ip, jp, P1) in all the pixel circuits 10 is sequentially received, and then the second measured value Im (ip, jp, P2) in all the pixel circuits 10 is received. Are received in sequence.
  • step S50 When the CPU 106 first receives one measured value Im (it, jt, Pt) in step S50, the received measured value (hereinafter referred to as “input measured value”) Im (it, jt, Pt) and the corresponding data.
  • the temperature Tm (it, jt) of the temperature detection circuit Tmp (it, jt) is obtained by the third LUT 108 from the combination with the voltage Vm (it, jt, Pt).
  • step S52 it is determined whether or not the temperatures of all the temperature detection circuits 12 have been obtained by the immediately preceding step S50 (step S52). As a result of this determination, if the temperature of any of the temperature detection circuits 12 has not been obtained, the process returns to step S50, and if the temperatures of all the temperature detection circuits 12 have been obtained, the process proceeds to step S56.
  • each pixel circuit Pix (ip, jp) is subjected to interpolation processing based on the arrangement of the pixel circuit 10 and the temperature detection circuit 12 shown in FIG. 1 from the temperature Tm (it, jp) obtained for all the temperature detection circuits 12. ) Estimated temperature Tmp (ip, jp) is obtained.
  • the first ideal characteristic value IO (P1) and the second ideal characteristic value IO (P2) are received from the second LUT 105 described above (step S58) (see FIG. 15).
  • step S34 of FIG. 18 for each pixel circuit Pix (i, j), a comparison result between the first ideal characteristic value IO (P1) and the first temperature compensation measurement value Imc (i, j, P1).
  • the threshold voltage correction data Vt (i, j) is updated according to the above (step S64).
  • step S66 it is determined whether or not the first temperature compensation measurement value Imc (i, j, P1) of the all-pixel circuit 10 is obtained. As a result of this determination, if the first temperature compensation measurement value Imc (i, j, P1) of any of the pixel circuits 10 is not obtained, the process returns to step S60, and the first temperature compensation measurement value of all the pixel circuits 10 is obtained. If Imc (i, j, P1) is obtained, the process proceeds to step S68.
  • step S34 of FIG. 18 the comparison result between the second ideal characteristic value IO (P2) and the second temperature compensation measurement value Imc (i, j, P2) for each pixel circuit Pix (i, j)
  • the gain correction data B2R (i, j) is updated according to the above (step S72).
  • step S74 it is determined whether or not the second temperature compensation measurement value Imc (i, j, P2) of the all-pixel circuit 10 is obtained (step S74). As a result of this determination, if the second temperature compensation measurement value Imc (i, j, P2) of any of the pixel circuits 10 is not obtained, the process returns to step S68 and the second temperature compensation measurement value of all the pixel circuits 10 is obtained. When Imc (i, j, P2) is obtained, the characteristic compensation process is terminated.
  • the correction data is updated only to the first temperature compensation measurement value Imc (i, j, P1). It is composed of the update of the threshold voltage correction data Vt (i, j) based on the update and the update of the gain correction data B2R (i, j) based only on the second temperature compensation measurement value Imc (i, j, P2) (FIG. 18 step S34, FIG. 19 steps S64, S72).
  • the correction data is updated by the first temperature compensation measurement value Imc (i, j, P1) and the second temperature compensation measurement. It is performed as follows based on both values Imcc (i, j, P2).
  • the first measured value Im (i, j, P1) is obtained in the first detection period TM1.
  • the first temperature-compensated measured value Imc (i, j, P1) by applying temperature compensation to the measured value and obtaining the second measured value Im (i, j, P2) in the second detection period TM2.
  • a second temperature-compensated measured value Imcc (i, j, P2) is obtained by applying temperature compensation to the measured value.
  • the drive current obtained by writing the first measurement gradation voltage Vmp1 calculated by the following equation (21) to the pixel circuit Pix (i, j) as pixel data ( The current flowing through the drive transistor T2) is measured, and during the second detection period TM2, the second measurement gradation voltage Vmp2 calculated by the following equation (22) is applied to the pixel circuit Pix (i, j) as pixel data.
  • the drive current obtained by writing as is measured.
  • Vmp1 Vcw ⁇ Vn (P1) ⁇ B (i, j) + Vth (i, j)... (21)
  • Vmp2 Vcw ⁇ Vn (P2) ⁇ B (i, j) + Vth (i, j)... (22)
  • Vcw is the difference between the gradation voltage corresponding to the minimum gradation and the gradation voltage corresponding to the maximum gradation (that is, the range of the gradation voltage).
  • Vn (P1) is a value obtained by normalizing the first gradation value P1 to a value in the range of 0 to 1
  • Vn (P2) is a value obtained by normalizing the second gradation value P2 to a value in the range of 0 to 1.
  • B (i, j) is a normalization coefficient for the pixel circuit Pix (i, j) of the i-th row and the j-th column calculated by the following equation (23).
  • Vth (i, j) is an offset value for the pixel circuit Pix (i, j) in the i-th row and the j-th column.
  • B ⁇ ( ⁇ 0 / ⁇ )... (23)
  • ⁇ 0 is the average value of the gain values for all the pixel circuits 10
  • ⁇ is the gain value for the pixel circuits Pix (i, j) in the i-th row and the j-th column.
  • the measured value is subjected to temperature compensation, and the offset value is based on the measured value after the temperature compensation.
  • the Vth and the gain value ⁇ are calculated.
  • the following equation (24) showing the relationship between the drain current (drive current) Id of the drive transistor T2 and the gate-source voltage Vgs is used.
  • Id ( ⁇ / 2) ⁇ (Vgs-Vth) 2 ... (24) Specifically, the equation obtained by substituting the measurement result (value after temperature compensation) based on the first gradation value P1 into the above equation (24) and the measurement result based on the second gradation value P2 (value after temperature compensation).
  • IOp1 is a drive current (value after temperature compensation) as a measurement result based on the first gradation value P1 and corresponds to the first temperature compensation measurement value Imc (i, j, P1), and IOp2.
  • Vgsp1 is a gate-source voltage based on the first gradation value P1
  • Vgsp2 is a gate-source voltage based on the second gradation value P2.
  • the source terminal of the drive transistor T2 in the pixel circuit Pix (i, j) in which the drive current is measured is maintained at the low level power supply voltage ELVSS (see FIG. 13).
  • this low level power supply voltage ELVSS will be described as “0”.
  • Vgsp1 is given by the following equation (27), and Vgsp2 is given by the following equation (28).
  • Vgsp1 Vmp1 ... (27)
  • Vgsp2 Vmp2 ... (28)
  • the threshold voltage correction data Vt (i, j) and the gain correction memory in the threshold voltage correction memory 142 are used by using the offset value Vth and the gain value ⁇ calculated as described above.
  • the gain correction data B2R (i, j) in 141 is updated (see FIG. 2).
  • the offset value Vth corresponds to the threshold voltage correction data Vt (i, j)
  • the normalization coefficient B ⁇ ( ⁇ 0 / ⁇ ) given by the above equation (23) is the gain correction data B2R (i). , J).
  • FIG. 20 is a block diagram showing an overall configuration of an active matrix type organic EL display device according to a second embodiment of the present invention. Since this organic EL display device has substantially the same configuration as the organic EL display device according to the first embodiment except for the display unit 500, the same reference code is assigned to the same or corresponding portion. A detailed explanation will be omitted.
  • M data signal lines DL (M is an integer of 2 or more) are displayed on the display unit 500.
  • M N scanning signal lines GL1 (1) to GL1 (N) intersecting them (N is an integer of 2 or more), and N monitor control lines GL2 (1) to GL2. (N) and are arranged.
  • N monitor control lines GL2 (1) to GL2.
  • a large number of pixel circuits 10 are arranged in a matrix along M data signal lines DL (1) to DL (M) and N scanning signal lines GL1 (1) to GL1 (N). Have been placed.
  • Each pixel circuit 10 is connected to any of M data signal lines DL (1) to DL (M) and is connected to any of N scanning signal lines GL1 (1) to GL1 (N). It is also connected to any of N monitor control lines GL2 (1) to GL2 (N). However, none of the pixel circuits 10 is connected to the M data signal lines DL (1) to DL (M), and the temperature detection data signal line is one in m data signal lines (display unit).
  • the temperature detection circuit 12 is connected to each of the q data signal lines DL (m), DL (2 m), ..., DL (q ⁇ m) for temperature detection. ing. In FIG. 20, the temperature detection circuit 12 is drawn as a shaded rectangle.
  • the temperature detection circuit 12 has a distance from the data side drive circuit 200 of a predetermined value or less.
  • the data signal lines are arranged at intervals shorter than the arrangement interval in the data signal line extending direction in the area Rb other than the display area Ra (hereinafter referred to as "display area Rb"). That is, in the example shown in FIG.
  • the distance from the side (display unit end) to which the data side drive circuit 200 is connected (hereinafter referred to as “distance from the data side drive circuit”) is 30 mm or less.
  • a certain area is the display area Ra
  • the area where the distance from the data side drive circuit exceeds 30 mm is the display area Rb
  • the arrangement interval of the temperature detection circuit 12 in the data signal line extending direction is, for example, in the display area Rb. It is about 20 mm to 40 mm, but in the display area Ra, it is, for example, about 5 mm to 10 mm.
  • the operation of the data side drive circuit 200 is accompanied by heat generation. Therefore, in the display unit 500, the temperature gradient (in the data signal line extending direction) is larger in the region where the distance from the data side drive circuit 200 is short than in the region where the data signal line is extended. It will be sudden.
  • the arrangement interval of the temperature detection circuit 12 in the data signal line extending direction in the display area Ra where the distance from the data side drive circuit 200 is 30 mm or less is set to the data side drive circuit. It is shorter than the arrangement interval in the data signal line extending direction of the temperature detection circuit 12 in the display region Rb where the distance from the distance exceeds 30 mm.
  • the inventor of the present application selected the distance of 30 mm from the data side drive circuit as a numerical value for specifying the display region Ra in which the arrangement interval in the data signal line extending direction of the temperature detection circuit 12 should be shortened. From experience, it is preferable to correct the current monitor result based on the temperature distribution obtained by the temperature detection circuit 12 arranged based on the numerical value in order to accurately perform the external compensation.
  • the temperature detection circuits 12 are arranged at short intervals in the data signal line extending direction. Therefore, a more accurate temperature distribution (estimated temperature in each pixel circuit 10) is obtained based on the temperature detected by each temperature detection circuit 12, the current monitor result is corrected based on this temperature distribution, and the corrected current is corrected. External compensation (compensation for variation and deterioration of the characteristics of the drive transistor in each pixel circuit 10) is performed using the monitor result. Therefore, the external compensation can be performed more accurately than in the first embodiment.
  • FIG. 21 is a block diagram showing an overall configuration of an active matrix type organic EL display device according to a third embodiment of the present invention. Since this organic EL display device has substantially the same configuration as the organic EL display device according to the first embodiment except for the data side drive circuit 200 and the display unit 500, the same or corresponding portions. The same reference numerals are given to the above, and detailed description thereof will be omitted.
  • the display unit 500 (data signal line) is driven by using a plurality of data drivers, and usually one data driver is one. It is realized by one IC (Integrated Circuit) chip.
  • the display unit 500 (data signal line) is driven by a plurality of data drivers. That is, the data signal line in the display unit 500 is driven by a plurality of sub-drive circuits. More specifically, the data signal lines in the display unit 500 are grouped into a plurality of sets of data signal line groups with two or more predetermined number of data signal lines adjacent to each other as one set, and the data side drive circuit 200 includes the plurality of data signal lines.
  • a set of data signal line groups includes a plurality of data drivers as a plurality of sub-drive circuits having a one-to-one correspondence, and each data driver is connected to the corresponding data signal line group to connect the corresponding data signal line group. Drive.
  • the data side drive circuit 200 is composed of three data drivers 200a, 200b, 200c, and the data signal line in the display unit 500 is driven by these three data drivers 200a, 200b, 200c.
  • the three series-parallel conversion units 202, 202, and 202 included in each of the three data drivers 200a, 200b, and 200c are vertically connected to each other, whereby these three data are connected.
  • the data-side drive circuit 200 including the drivers 200a, 200b, and 200c operates substantially in the same manner as the data-side drive circuit 200 in the first embodiment and has the same function.
  • M data signal lines DL are displayed on the display unit 500.
  • M data signal lines DL (M is an integer of 2 or more) are displayed on the display unit 500.
  • N scanning signal lines GL1 (1) to GL1 (N) intersecting them (N is an integer of 2 or more)
  • a large number of pixel circuits 10 are arranged in a matrix along M data signal lines DL (1) to DL (M) and N scanning signal lines GL1 (1) to GL1 (N). Have been placed.
  • Each pixel circuit 10 is connected to any of M data signal lines DL (1) to DL (M) and is connected to any of N scanning signal lines GL1 (1) to GL1 (N). It is also connected to any of N monitor control lines GL2 (1) to GL2 (N). However, none of the pixel circuits 10 is connected to the M data signal lines DL (1) to DL (M).
  • the ratio of one temperature detection data signal line to m M / 3 data signal lines. (3 lines in the entire display unit 500) are included, and a temperature detection circuit 12 is connected to each of these three temperature detection data signal lines. In FIG. 21, the temperature detection circuit 12 is drawn as a shaded rectangle.
  • the first data driver 200a drives the data signal lines DL (1) to DL (m)
  • the second data driver 200b drives the data signal lines DL (m + 1) to DL (2m).
  • the data signal line of the book is a temperature detection data signal line to which the pixel circuit 10 is not connected and only the temperature detection circuit 12 is connected.
  • the temperature detection data signal line in each data driver 200x shall be one of the m / 3rd to 2m / 3rd data signal lines among the m data signal lines connected to the data driver 200x. Is preferable.
  • the temperature distribution in the area in charge is obtained (specifically, the estimated temperature of each pixel circuit 10 in the area in charge is obtained). Therefore, for each data driver 200x, the current monitor result is corrected based on the estimated temperature of each pixel circuit 10 in the area in charge, and external compensation using the corrected current monitor result (characteristics of the drive transistor in each pixel circuit 10). Compensation for variation and deterioration) is performed. In this way, the temperature distribution of the region in charge can be obtained for each data driver 200x, and external compensation can be appropriately performed.
  • one row of temperature detection circuits 12 (a predetermined number of temperature detection circuits 12 connected to one temperature detection data signal line) are provided for one data driver 200x. Is. Therefore, as compared with the case where a plurality of rows of temperature detection circuits 12 are provided for one data driver 200x, it is possible to simplify or reduce the circuit for processing the temperature information including the temperature obtained by the temperature detection circuit 12. it can.
  • one data driver 200x may be provided with two or more rows of temperature detection circuits 12. That is, two or more temperature detection data signal lines may be connected to one data driver 200x, and even in such a case, the temperature distribution of the area in charge is obtained for each data driver 200x and appropriately external. Compensation can be made.
  • FIG. 22 is a block diagram showing an overall configuration of an active matrix type organic EL display device according to a fourth embodiment of the present invention. Since this organic EL display device has substantially the same configuration as the organic EL display device according to the first embodiment except for the data side drive circuit 200 and the display unit 500, the same or corresponding portions. The same reference numerals are given to the above, and detailed description thereof will be omitted.
  • the white data signal line DLw (j), the red data signal line DLr (i), the green data signal line DLg (i), and the blue data signal are displayed on the display unit 500.
  • Data signal lines DLw (1), DLr (1), DLg (1), DLb (1) of M group (M is an integer of 2 or more) including four data signal lines composed of lines DLb (i) as one set.
  • M is an integer of 2 or more
  • N monitor control lines GL2 (1) to GL2 (N) are arranged.
  • FIG. 23 is a circuit diagram showing the electrical configurations of the pixel circuits PxW, PxR, PxG, PxB and the temperature detection circuit 12 in this embodiment.
  • the display unit 500 is configured to display a color image, and the display unit 500 is provided with a pixel forming unit 15 for forming each pixel in the color image to be displayed.
  • Each pixel forming unit 15 is composed of four pixel circuits including a white pixel circuit PxW, a red pixel circuit PxR, a green pixel circuit PxG, and a blue pixel circuit PxB that are adjacent to each other in the extending direction of the scanning signal line.
  • the white pixel circuit PxW, the red pixel circuit PxR, the green pixel circuit PxG, and the blue pixel circuit PxB emit white light, red light, green light, and blue light, respectively, when lit.
  • Each white pixel circuit PxW is connected to any of M white data signal lines DLw (1) to DLw (M)
  • each red pixel circuit PxR is connected to M red data signal lines DLr (1) to DLr.
  • each green pixel circuit PxG is connected to any of M green data signal lines DLg (1) to DLg (M)
  • each blue pixel circuit PxB is connected to M lines. It is connected to any of the blue data signal lines DLb (1) to DLb (M).
  • each pixel circuit PxW, PxR, PxG, and PxB corresponding to each pixel for displaying a color image and adjacent to each other are connected to any one of the M monitor signal lines MoL in the display unit 500.
  • the four pixel circuits PxW, PxR, PxG, and PxB constituting each pixel forming unit 15 are connected to any of the M monitor signal lines MoL, and the four pixel circuits PxW, PxR, PxG, When one temperature detection circuit 12 is provided correspondingly to PxB, the temperature detection circuit 12 is also connected to the monitor signal line MoL.
  • the white data signal line DLw Is also connected to the corresponding temperature detection circuit 12.
  • the data side drive circuit 200 in the present embodiment is the same as the first embodiment (see FIG. 1), and the series-parallel conversion unit 202, the DA conversion unit 204, the AD conversion unit 206, and the input / output A buffer unit 208 is provided.
  • the data side drive circuit 200 in the present embodiment from the white data signal line DLw (j), the red data signal line DLr (i), the green data signal line DLg (i), and the blue data signal line DLb (i).
  • Data signal lines of M sets of four data signal lines DLw (1), DLr (1), DLg (1), DLb (1) to DLw (M), DLr (M), DLg ( M) and DLb (M) are connected, and as shown in FIG. 22, one data signal line DLw (j), DLr (j), DLg (j), and DLb (j) are provided.
  • the M monitor signal lines MoL are also connected. Therefore, the specific configuration of the data side drive circuit 200 is different from that of the first embodiment. Hereinafter, this point will be described with reference to FIGS. 24 and 25.
  • FIG. 24 describes a detailed configuration of a portion to which one data signal line DLx (j) (x is any of w, r, g, and b) of the data side drive circuit 200 in the present embodiment is connected. It is a circuit diagram for.
  • FIG. 25 is a circuit diagram for explaining a detailed configuration of a portion to which one monitor signal line MoL is connected in the data side drive circuit 200 in the present embodiment.
  • each data signal line DL (j) is in the characteristic detection mode. It also functions as a monitor signal line for measuring the current in the pixel circuit Pix (i, j). Therefore, the portion of the data-side drive circuit 200 to which one data signal line DL (j) is connected is configured as shown in FIG.
  • the data side drive circuit 200 includes an output buffer 28a and a DA converter (DAC) 20 as a circuit portion corresponding to one data signal line DLx (j).
  • the DA converter 20 has an output terminal Txj for the j-th X color signal (X is any of W, R, G, and B among the digital image signals for one line from the series-parallel conversion unit 202, and x.
  • the digital image signal Vmx (i, j, P) provides a data voltage to be applied to the pixel circuit PxX in order to display a pixel with a gradation value P in the X color pixel circuit PxX of the i-th row and j-group. It is a digital signal to show.
  • the output buffer 28a is a voltage holer configured by using the operational amplifier 21, the output terminal of the operational amplifier 21 is connected to the inverting input terminal and the data signal line DLx (j), and the non-inverting input terminal is the output of the DA converter 20. It is connected to the end.
  • the input end of the DA converter 20 is connected to the corresponding terminal in the series-parallel conversion unit 202, that is, the j-th X color signal output terminal Txj.
  • the digital signal Vm (i, j, P) input to the DA converter 20 is converted into an analog voltage signal and given to the data signal line DLx (j) with a low output impedance.
  • the portion to which one monitor signal line MoL of the data side drive circuit 200 is connected is configured as shown in FIG. 25. That is, the data side drive circuit 200 includes an input buffer 28b and an AD converter 24 as a circuit portion corresponding to one monitor signal line MoL.
  • the input buffer 28b includes an operational amplifier 21 and a capacitor 22.
  • the inverting input terminal of the operational amplifier 21 is connected to the monitor signal line MoL
  • the non-inverting input terminal is connected to the low level power supply line ELVSS
  • the output terminal is connected to the inverting input terminal via the capacitor 22.
  • the current output from the temperature detection circuit 12 (current flowing through the pixel circuit PxX or the transistor T2 of the temperature detection circuit 12) connected to the pixel forming unit 15 of the j-th column is transmitted via the monitor signal line MoL. It is given to the input buffer 28b.
  • the input buffer 28b generates a voltage signal indicating this current, and the voltage signal is converted into a digital signal Im (i, j, P) by the AD converter 24 to the corresponding input terminal Tmo in the series-parallel conversion unit 202. Given.
  • one monitor signal line MoL is shared by the four pixel circuits PxW, PxW, PxR, PxG, and PxB constituting one pixel forming unit 15.
  • the same monitor control line GL2 (i) is connected to the four pixel circuits PxW, PxW, PxR, PxG, and PxB.
  • the monitor control line GL2 (i) in order to measure the current for each pixel circuit PxX in order to perform external compensation for each pixel circuit PxX (X is any of W, R, G, and B), for example, the monitor control line GL2 (i).
  • ⁇ N) may be driven as follows. That is, in the characteristic detection mode, only one of the four pixel circuits PxW, PxW, PxR, PxG, and PxB constituting each pixel forming unit 15 corresponds to the first gradation value P1 or the second gradation value P2.
  • the data voltage corresponding to the black voltage (voltage at which the drive current does not flow) is written to the other pixel circuits, and corresponds to the first gradation value P1 or the second gradation value P2.
  • the four pixel circuits PxW, PxW, PxR, PxG, and PxB constituting one pixel forming unit 15 are close to each other, the following alternative example of the driving method in the characteristic detection mode can be considered. That is, the characteristics (threshold voltage and gain) of the drive transistor T2 in the four pixel circuits PxW, PxW, PxR, PxG, and PxB are considered to be the same, and the four pixel circuits PxW, PxW, PxR, PxG, and PxB are used.
  • the same correction data (threshold voltage correction data and gain correction data) are used for the four pixel circuits PxW, PxW, PxR, PxG, and PxB, and the four pixel circuits PxW, PxW, PxR, and PxG are used.
  • PxB (every pixel forming unit 15), external compensation is performed.
  • the present embodiment even in an organic EL display device that forms one pixel in a color image by a plurality of pixel circuits (four pixel circuits PxW, PxR, PxG, PxB in the configuration of FIG. 22).
  • the temperature distribution of the display unit 500 (specifically, the estimated temperature in each pixel circuit PxW, PxR, PxG, PxB) is obtained based on the temperature detected by the temperature detection circuit 12, and each pixel circuit PxW, PxR, PxG, PxB.
  • the current monitor result of is corrected based on the estimated temperature of the pixel circuit.
  • External compensation compensation for variation and deterioration of drive transistor characteristics in each pixel circuit PxW, PxR, PxG, PxB
  • the corrected current monitor result that is, the current monitor result after temperature compensation. Therefore, according to the present embodiment, the same effect as that of the first embodiment can be obtained even in an organic EL display device that forms one pixel in a color image by a plurality of pixel circuits.
  • one temperature detection circuit 12 is provided for a plurality of pixel circuits (four pixel circuits PxW, PxR, PxG, PxB in the configuration of FIG. 22) corresponding to one pixel in a color image.
  • the monitor signal line MoL is provided separately from the data signal line, and one monitor signal line MoL is shared by the plurality of pixel circuits and the one temperature detection circuit 12. Therefore, the configuration of the data side drive circuit 200 is simplified and the required circuit amount is also reduced (see FIGS. 23 to 25).
  • one pixel in the color image is formed by four pixel circuits PxW, PxR, PxG, and PxB corresponding to the four primary colors.
  • PxW, PxR, PxG, and PxB corresponding to the four primary colors.
  • three primary colors consisting of red, green, and blue one in the color image is formed by three pixel circuits PxR, PxG, and PxB corresponding to the three primary colors. It may be configured so that pixels are formed.
  • one temperature detection circuit 12 is provided for every two or more pixel circuits 10 adjacent to the extending direction (horizontal direction) of the scanning signal line regardless of the number of primary colors for displaying a color image.
  • the monitor signal line may be arranged in the same manner as described above.
  • the pixel circuit 10 is configured as shown in FIG. 3, and the pixel circuits PxW, PxR, PxG, and PxB are configured as shown in FIG. 23, but the pixel circuit 10 and the pixel circuit PxW , PxR, PxG, PxB are not limited to the configurations shown in these figures.
  • a display element driven by an electric current a holding capacitor that holds a data voltage for controlling the drive current of the display element, and a holding capacitor that controls the drive current of the display element according to the data voltage held in the holding capacitor.
  • It is a pixel circuit including a drive transistor, and may be configured so that the current flowing through the drive transistor is taken out from the display unit 500.
  • the configuration of the temperature detection circuit 12 is not limited to the configuration shown in FIG. 4 or 23, and may be the same configuration as the pixel circuit except that a display element such as an organic EL element driven by a current is not included. Just do it.
  • the threshold voltage and the gain are taken up as the transistor characteristics for which the variation and deterioration should be compensated, but the variation of the transistor characteristics including one of these or other characteristic parameters in addition to these is taken up. It may be configured to compensate.
  • the operation in each of the above embodiments is not limited to the operation examples shown in FIGS. 7, 8, 12, 18, and 19, and is the configuration shown in FIGS. 1, 20, 21, or 22.
  • the estimated temperature of each pixel circuit is obtained on the premise of, temperature compensation is applied to the current monitor result of each pixel circuit based on the estimated temperature, and the characteristics of the drive transistor in each pixel circuit are obtained based on the current monitor result after temperature compensation.
  • the operation may be such that processing for compensating for variation and deterioration is performed.
  • the operation mode is switched from the normal display mode to the characteristic detection mode when the power switch of the display device is turned off. However, as described above, the operation mode is changed. The switching may be performed by other means.
  • an organic EL display device As an example, but the present invention is not limited to the organic EL display device, and a display element driven by an electric current is used. It is applicable if it is the display device used.
  • the display element that can be used here is a display element whose brightness or transmission rate is controlled by a current, and is, for example, an organic EL element, that is, an organic light emitting diode (OLED), an inorganic light emitting diode, or the like. Quantum dot light emitting diode (QLED) or the like can be used.
  • OLED organic light emitting diode
  • QLED Quantum dot light emitting diode

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