WO2020228204A1 - Micro LED显示面板及显示装置 - Google Patents

Micro LED显示面板及显示装置 Download PDF

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Publication number
WO2020228204A1
WO2020228204A1 PCT/CN2019/105882 CN2019105882W WO2020228204A1 WO 2020228204 A1 WO2020228204 A1 WO 2020228204A1 CN 2019105882 W CN2019105882 W CN 2019105882W WO 2020228204 A1 WO2020228204 A1 WO 2020228204A1
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thin film
film transistor
row
pixel area
goa
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PCT/CN2019/105882
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English (en)
French (fr)
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周依芳
徐铉植
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020228204A1 publication Critical patent/WO2020228204A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays

Definitions

  • This application relates to the field of display technology, and in particular to a Micro LED display panel and a display device.
  • Micro-LED is a display technology that miniaturizes and matrixes the LED structure, drives and addresses each pixel individually. Because Micro-LED technology is superior to LCD and OLED technology in terms of brightness, life, contrast, response time, energy consumption, viewing angle and resolution, it is regarded as a new generation display technology that can surpass OLED and traditional LED. .
  • the Micro LED display panel needs to be provided with GOA circuits on the periphery of the display area, resulting in the existence of a frame in the Micro LED display panel, a small effective display area, and a relatively low screen occupation.
  • This application provides a Micro LED display panel and a display device, which can increase the screen-to-body ratio.
  • This application provides a Micro LED display panel, including: GOA driving circuit, multiple data lines, multiple scan lines, and multiple pixel units;
  • the plurality of scan lines and the plurality of data lines are arranged in a crisscross pattern, and a pixel area is enclosed between two adjacent scan lines and two adjacent data lines to form a plurality of pixel areas arranged in an array, Each said pixel area is provided with one said pixel unit;
  • the GOA driving circuit includes a plurality of cascaded GOA units, and a first-level GOA unit is arranged in the pixel area of each row, wherein the GOA unit between the scan line of the nth row and the scan line of the n+1th row is the nth Level GOA unit, and the nth level GOA unit is respectively connected to the nth row scan line and the n+1th row scan line.
  • a display device includes any of the above-mentioned Micro LED display panels.
  • each GOA unit of the GOA driving circuit is respectively arranged in the pixel area, thereby reducing the frame size and increasing the screen-to-body ratio.
  • Fig. 1 is a structural diagram of a Micro LED display panel in some embodiments of the present application.
  • Fig. 2 is a circuit structure diagram of an N-th GOA unit in some embodiments of the present application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present invention, “plurality” means two or more than two, unless specifically defined otherwise.
  • the "above” or “below” of the first feature of the second feature may include the first and second features in direct contact, or may include the first and second features Not in direct contact but through other features between them.
  • “above”, “above” and “above” the second feature of the first feature include the first feature being directly above and obliquely above the second feature, or it simply means that the level of the first feature is higher than the second feature.
  • the “below”, “below” and “below” the first feature of the second feature include the first feature directly below and obliquely below the second feature, or it simply means that the level of the first feature is smaller than the second feature.
  • FIG. 1 is a structural diagram of a Micro LED display panel in some embodiments of the present invention.
  • the Micro LED display panel includes: GOA driving circuit, multiple data lines Dm, multiple scan lines G(n), multiple pixel units, low level lines VSS, and clock signal lines CK.
  • the plurality of scan lines G(n) and the plurality of data lines Dm are arranged in a crisscross pattern, and a pixel area is enclosed between two adjacent scan lines G(n) and two adjacent data lines Dm 100 to form a plurality of pixel regions 100 arranged in an array, and each pixel region 100 is provided with one pixel unit.
  • the GOA driving circuit includes a plurality of cascaded GOA units 200, each row of the pixel area 100 is provided with a first-level GOA unit 200, wherein the nth row scan line G(n) and the n+1th row scan
  • the GOA unit 200 between the line G(n+1) is an nth level GOA unit, and the nth level GOA unit is connected to the nth scan line G(n) and the n+1th scan line G respectively. (N+1) connection.
  • the GOA unit includes a plurality of thin film transistors, and the plurality of thin film transistors are respectively located in different pixel regions.
  • the GOA unit is formed by connecting thin film transistors, which belongs to the prior art, and various connection methods can be used to form various GOA units.
  • the nth-level GOA unit includes a first thin film transistor T11, a second thin film transistor T21, a third thin film transistor T31, and a fourth thin film transistor T41; the gate of the first thin film transistor T11 and The drain of the first thin film transistor T11 is connected to the scan signal output terminal of the previous stage, and the source of the first thin film transistor T11 is connected to the drain of the fourth thin film transistor T41 and the second The gates of the two thin film transistors T21 are connected; the drain of the second thin film transistor T21 is connected to the clock signal, the source of the second thin film transistor T21 is connected to the scan line of the nth row, and the third thin film transistor T31 The gate of the third thin film transistor T31 is connected to the n+1th level scan line, the drain of the third thin film transistor T31 is connected to the scan line of the nth row, and the source of the third thin film transistor T31 and the fourth thin film The source of the transistor T41 is connected to a low-level signal.
  • the fourth thin film transistor T41 is located in the pixel area 100 of the mth column
  • the first thin film transistor T11 is located in the pixel area 100 of the m+1th column
  • the second thin film transistor T21 is located in the pixel area of the m+2th column.
  • the third thin film transistor T31 is located in the pixel region 100 in the m+3th column.
  • the m is equal to 1.
  • the low-level signal line VSS is used to provide a low-level signal.
  • the low-level signal line VSS extends along the direction of the scan line.
  • the source of the third thin film transistor T31 and the fourth thin film transistor The source of T41 is electrically connected to the low-level signal line VSS.
  • the clock signal line CK is used to provide a clock signal, the clock signal line CK extends along the direction of the data line, and the drain of the second thin film transistor is connected to the clock signal line.
  • the fourth thin film transistor of the GOA unit of each row is located in the pixel area of the mth column
  • the first thin film transistor of the GOA unit of each row is located in the pixel area of the m+1th column
  • the GOA unit of each row The second thin film transistor is located in the pixel area of the m+2th column
  • the third thin film transistor of the GOA unit of each row is located in the pixel area of the m+3th column.
  • the first thin film transistor T11, the second thin film transistor T21, the third thin film transistor T31, and the fourth thin film transistor T41 are all NMOS transistors and are oxide semiconductor thin film transistors.
  • each GOA unit of the GOA driving circuit is respectively arranged in the pixel area, thereby reducing the frame size and increasing the screen-to-body ratio.
  • the present application also provides a display device, including any of the above-mentioned Micro LED display panels.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种Micro LED显示面板，包括：GOA驱动电路、多条数据线Dm、多条扫描线G(n)以及多个像素单元；多条扫描线G(n)和多条数据线Dm纵横交错设置，且相邻两条扫描线G(n)和相邻两条数据线Dm之间围成像素区(100)以形成多个阵列排布的像素区(100)，每一像素区(100)设置有一像素单元；GOA驱动电路包括多个级联的GOA单元(200)，每一行像素区内(100)设置一级GOA单元(200)，其中，第n行扫描线G(n)与第n+1行扫描线G(n+1)之间的GOA单元(200)为第n级GOA单元(200)，且第n级GOA单元(200)分别与第n行扫描线G(n)与第n+1行扫描线G(n+1)连接。通过将GOA驱动电路的各个GOA单元(200)分别设置到像素区(100)内，从而减小了边框尺寸，提高了屏占比。

Description

Micro LED显示面板及显示装置 技术领域
本申请涉及显示技术领域，特别涉及一种Micro LED显示面板及显示装置。
 背景技术
Micro-LED是一种将LED结构微小化和矩阵化，对每一个像素点单独驱动和定址控 制的显示技术。由于Micro-LED技术的亮度、寿命、对比度、反应时间、能耗、可视角度和分辨率等各种指标均优于LCD和OLED技术，被视为能超越OLED 及传统LED的新一代显示技术。
 技术问题
现有技术中，Micro LED显示面板都需要在其显示区域的四周边缘设置GOA电路，导致Micro LED显示面板存在边框，有效显示面积较小，屏占比较低。
因此，现有技术存在缺陷，急需改进。
 技术解决方案
本申请提供一种Micro LED显示面板及显示装置，可以提高屏占比。
本申请提供了一种Micro LED显示面板，包括：GOA驱动电路、多条数据线、多条扫描线以及多个像素单元；
所述多条扫描线和所述多条数据线纵横交错设置，且相邻两条所述扫描线和相邻两条数据线之间围成像素区以形成多个阵列排布的像素区，每一所述像素区设置有一所述像素单元；
所述GOA驱动电路包括多个级联的GOA单元，每一行所述像素区内设置一级GOA单元，其中，第n行扫描线与第n+1行扫描线之间的GOA单元为第n级GOA单元，且所述第n级GOA单元分别与所述第n行扫描线与第n+1行扫描线连接。
一种显示装置，包括上述任一项所述的Micro LED显示面板。
 有益效果
本申请通过将GOA驱动电路的各个GOA单元分别设置到像素区内，从而减小了边框尺寸，提高了屏占比。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请一些实施例中的一种Micro LED显示面板的结构图。
图2是本申请一些实施例中的第N级GOA单元的电路结构图。
 本发明的最佳实施方式
下面详细描述本发明的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
请同时参阅图1以及图2，图1是本发明一些实施例中的一种Micro LED显示面板的结构图。该Micro LED显示面板包括：GOA驱动电路、多条数据线Dm、多条扫描线G（n）、多个像素单元、低电平线VSS、时钟信号线CK。
其中，该多条扫描线G（n）和所述多条数据线Dm纵横交错设置，且相邻两条所述扫描线G（n）和相邻两条数据线Dm之间围成像素区100以形成多个阵列排布的像素区100，每一所述像素区设100置有一所述像素单元。
具体地，该GOA驱动电路包括多个级联的GOA单元200，每一行所述像素区100内设置一级GOA单元200，其中，第n行扫描线G（n）与第n+1行扫描线G（n+1）之间的GOA单元200为第n级GOA单元，且所述第n级GOA单元分别与所述第n行扫描线G（n）与第n+1行扫描线G（n+1）连接。
在一些实施例中，该GOA单元包括多个薄膜晶体管，所述多个薄膜晶体管分别位于不同的像素区内。GOA单元采用薄膜晶体管连接形成属于现有技术，其可以采用各种连接方式形成各种GOA单元。
具体地，在本实施例中，该第n级GOA单元包括第一薄膜晶体管T11、第二薄膜晶体管T21、第三薄膜晶体管T31以及第四薄膜晶体管T41；该第一薄膜晶体管T11的栅极与所述第一薄膜晶体管T11的漏极连接并与上一级的扫描信号输出端连接，所述第一薄膜晶体管T11的源极分别与所述第四薄膜晶体T41管的漏极以及所述第二薄膜晶体管T21的栅极连接；所述第二薄膜晶体管T21的漏极接入时钟信号，所述第二薄膜晶体管T21的源极与第n行的扫描线连接，所述第三薄膜晶体管T31的栅极与第n+1级扫描线连接，所述第三薄膜晶体管T31的漏极与所述第n行的扫描线连接，所述第三薄膜晶体管T31的源极以及所述第四薄膜晶体管T41的源极接入低电平信号。
其中，该第四薄膜晶体管T41位于第m列像素区100内，所述第一薄膜晶体管T11位于第m+1列像素区100内，所述第二薄膜晶体管T21位于第m+2列像素区100内，所述第三薄膜晶体管T31位于第m+3列像素区100内。其中，该m等于1。
该低电平信号线VSS用于提供低电平信号，所述低电平信号线VSS沿着所述扫描线的方向延伸，所述第三薄膜晶体管T31的源极以及所述第四薄膜晶体管T41的源极与所述低电平信号线VSS电连接。
该时钟信号线CK用于提供时钟信号，时钟信号线CK沿着所述数据线的方向延伸，所述第二薄膜晶体管的漏极与所述时钟信号线连接。
其中，每一行的GOA单元的所述第四薄膜晶体管位于第m列像素区内，每一行的GOA单元的所述第一薄膜晶体管位于第m+1列像素区内，每一行的GOA单元的所述第二薄膜晶体管位于第m+2列像素区内，每一行的GOA单元的所述第三薄膜晶体管位于第m+3列像素区内。从而可以减少时钟信号线的条数，使得所有GOA单元可以共用该条时钟信号线。
在一些实施例中，该第一薄膜晶体管T11、第二薄膜晶体管T21、第三薄膜晶体管T31以及第四薄膜晶体管T41均为NMOS管，且为氧化物半导体薄膜晶体管。
本申请通过将GOA驱动电路的各个GOA单元分别设置到像素区内，从而减小了边框尺寸，提高了屏占比。
本申请还提供了一种显示装置，包括上述任一项所述的Micro LED显示面板。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (11)

  1. 一种Micro LED显示面板，其中，包括：GOA驱动电路、多条数据线、多条扫描线以及多个像素单元；
    所述多条扫描线和所述多条数据线纵横交错设置，且相邻两条所述扫描线和相邻两条数据线之间围成像素区以形成多个阵列排布的像素区，每一所述像素区设置有一所述像素单元；
    所述GOA驱动电路包括多个级联的GOA单元，每一行所述像素区内设置一级GOA单元，其中，第n行扫描线与第n+1行扫描线之间的GOA单元为第n级GOA单元，且所述第n级GOA单元分别与所述第n行扫描线与第n+1行扫描线连接;
    所述GOA单元包括多个薄膜晶体管，所述多个薄膜晶体管分别位于不同的像素区内;
    所述第n级GOA单元包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管；
    所述第一薄膜晶体管的栅极与所述第一薄膜晶体管的漏极连接并与上一级的扫描信号输出端连接，所述第一薄膜晶体管的源极分别与所述第四薄膜晶体管的漏极以及所述第二薄膜晶体管的栅极连接；所述第二薄膜晶体管的漏极接入时钟信号，所述第二薄膜晶体管的源极与第n行的扫描线连接，所述第三薄膜晶体管的栅极与第n+1级扫描线连接，所述第三薄膜晶体管的漏极与所述第n行的扫描线连接，所述第三薄膜晶体管的源极以及所述第四薄膜晶体管的源极接入低电平信号；
    所述第四薄膜晶体管位于第m列像素区内，所述第一薄膜晶体管位于第m+1列像素区内，所述第二薄膜晶体管位于第m+2列像素区内，所述第三薄膜晶体管位于第m+3列像素区；所述m等于1；
    所述Micro LED显示面板还包括用于提供低电平信号的低电平信号线，所述低电平信号线沿着所述扫描线的方向延伸，所述第三薄膜晶体管的源极以及所述第四薄膜晶体管的源极与所述低电平信号线电连接。
  2. 一种Micro LED显示面板，其中，包括：GOA驱动电路、多条数据线、多条扫描线以及多个像素单元；
    所述多条扫描线和所述多条数据线纵横交错设置，且相邻两条所述扫描线和相邻两条数据线之间围成像素区以形成多个阵列排布的像素区，每一所述像素区设置有一所述像素单元；
    所述GOA驱动电路包括多个级联的GOA单元，每一行所述像素区内设置一级GOA单元，其中，第n行扫描线与第n+1行扫描线之间的GOA单元为第n级GOA单元，且所述第n级GOA单元分别与所述第n行扫描线与第n+1行扫描线连接。
  3. 根据权利要求2所述的Micro LED显示面板，其中，所述GOA单元包括多个薄膜晶体管，所述多个薄膜晶体管分别位于不同的像素区内。
  4. 根据权利要求3所述的Micro LED显示面板，其中，所述第n级GOA单元包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管；
    所述第一薄膜晶体管的栅极与所述第一薄膜晶体管的漏极连接并与上一级的扫描信号输出端连接，所述第一薄膜晶体管的源极分别与所述第四薄膜晶体管的漏极以及所述第二薄膜晶体管的栅极连接；所述第二薄膜晶体管的漏极接入时钟信号，所述第二薄膜晶体管的源极与第n行的扫描线连接，所述第三薄膜晶体管的栅极与第n+1级扫描线连接，所述第三薄膜晶体管的漏极与所述第n行的扫描线连接，所述第三薄膜晶体管的源极以及所述第四薄膜晶体管的源极接入低电平信号。
  5. 根据权利要求4所述的Micro LED显示面板，其中，所述第四薄膜晶体管位于第m列像素区内，所述第一薄膜晶体管位于第m+1列像素区内，所述第二薄膜晶体管位于第m+2列像素区内，所述第三薄膜晶体管位于第m+3列像素区内。
  6. 根据权利要求5所述的Micro LED显示面板，其中，所述m等于1。
  7. 根据权利要求5所述的Micro LED显示面板，其中，所述Micro LED显示面板还包括用于提供低电平信号的低电平信号线，所述低电平信号线沿着所述扫描线的方向延伸，所述第三薄膜晶体管的源极以及所述第四薄膜晶体管的源极与所述低电平信号线电连接。
  8. 根据权利要求7所述的Micro LED显示面板，其中，所述Micro LED显示面板还包括用于提供时钟信号的时钟信号线，所述时钟信号线沿着所述数据线的方向延伸，所述第二薄膜晶体管的漏极与所述时钟信号线连接。
  9. 根据权利要求5所述的Micro LED显示面板，其中，每一行的GOA单元的所述第四薄膜晶体管位于第m列像素区内，每一行的GOA单元的所述第一薄膜晶体管位于第m+1列像素区内，每一行的GOA单元的所述第二薄膜晶体管位于第m+2列像素区内，每一行的GOA单元的所述第三薄膜晶体管位于第m+3列像素区内。
  10. 根据权利要求5所述的Micro LED显示面板，其中，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管均为氧化物半导体薄膜晶体管。
  11. 一种显示装置，其中，包括如权利要求2所述的Micro LED显示面板。
PCT/CN2019/105882 2019-05-10 2019-09-16 Micro LED显示面板及显示装置 WO2020228204A1 (zh)

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