WO2020224612A1 - 自动侦测并卡控晶圆上缺陷的方法和系统 - Google Patents

自动侦测并卡控晶圆上缺陷的方法和系统 Download PDF

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Publication number
WO2020224612A1
WO2020224612A1 PCT/CN2020/088889 CN2020088889W WO2020224612A1 WO 2020224612 A1 WO2020224612 A1 WO 2020224612A1 CN 2020088889 W CN2020088889 W CN 2020088889W WO 2020224612 A1 WO2020224612 A1 WO 2020224612A1
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Prior art keywords
defect
defects
wafers
predetermined
wafer
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PCT/CN2020/088889
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English (en)
French (fr)
Inventor
郑加镇
陈建铭
卢健平
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徐州鑫晶半导体科技有限公司
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Priority claimed from CN201910376534.7A external-priority patent/CN110223929B/zh
Priority claimed from CN202010257939.1A external-priority patent/CN111524822B/zh
Application filed by 徐州鑫晶半导体科技有限公司 filed Critical 徐州鑫晶半导体科技有限公司
Priority to EP20802392.9A priority Critical patent/EP3968363A4/en
Priority to US17/609,419 priority patent/US20220223481A1/en
Priority to KR1020217040124A priority patent/KR20220010509A/ko
Priority to JP2021566323A priority patent/JP7329077B2/ja
Publication of WO2020224612A1 publication Critical patent/WO2020224612A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/8851—Scan or image signal processing specially adapted therefor, e.g. for scan signal adjustment, for detecting different kinds of defects, for compensating for structures, markings, edges
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G01N21/9501—Semiconductor wafers
    • G01N21/9503—Wafer edge inspection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/0002—Inspection of images, e.g. flaw detection
    • G06T7/0004—Industrial image inspection
    • G06T7/001—Industrial image inspection using an image reference approach
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/8851—Scan or image signal processing specially adapted therefor, e.g. for scan signal adjustment, for detecting different kinds of defects, for compensating for structures, markings, edges
    • G01N2021/8887—Scan or image signal processing specially adapted therefor, e.g. for scan signal adjustment, for detecting different kinds of defects, for compensating for structures, markings, edges based on image processing techniques
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/30—Subject of image; Context of image processing
    • G06T2207/30108—Industrial image inspection
    • G06T2207/30148—Semiconductor; IC; Wafer

Definitions

  • the present disclosure relates to the technical field of wafer inspection, and in particular, to a method and system for automatically detecting and controlling defects on a wafer.
  • contamination during the processing process or the processing itself will also cause many defects, such as saw marks formed after wire cutting, grinding marks formed by uneven single/double-sided grinding, Bumps or defects (PID) formed after polishing, dislocation slips (slip) produced after heat treatment, wear or scratches caused by the manipulator during transportation, etc.
  • defects such as saw marks formed after wire cutting, grinding marks formed by uneven single/double-sided grinding, Bumps or defects (PID) formed after polishing, dislocation slips (slip) produced after heat treatment, wear or scratches caused by the manipulator during transportation, etc.
  • PID defects
  • slip dislocation slips
  • an objective of the present disclosure is to provide a method and system for automatically detecting and controlling defects on a wafer that can better guarantee the quality of the output chips.
  • the present disclosure provides a method for automatically detecting and controlling defects on a wafer.
  • the method includes: providing at least one stacked wafer; and constructing a defect distribution map based on defect information on each of the wafers, the defect information including defect quantity, defect type, and defect location Divide at least one predetermined area in the defect distribution map; determine the number of predetermined defects in each predetermined area based on the defect location; compare the number of predetermined defects in each predetermined area with Set a threshold for comparison, and based on the comparison result, determine the detection result.
  • the distribution of defects can also be controlled to avoid problems caused by concentrated defect distribution, so as to better guarantee the quality of the produced chips, and pass the reservation
  • the selection of defect types can effectively reflect the problems in the wafer processing process, and is of great significance for guiding the wafer manufacturing process.
  • a two-dimensional defect distribution map is constructed based on the number of defects on the first surface of one wafer and the positions of the defects.
  • the outer circumference of the first surface forms a first circle, a plurality of second circles concentric with the first circle, and a plurality of diameters passing through the center of the first circle The intersection defines a plurality of the predetermined areas.
  • the predetermined area is a circular area delineated according to a predetermined radius with one defect as a center, and each defect corresponds to one predetermined area.
  • the area of each of the predetermined regions is 0.5% to 5% of the total area of the two-dimensional defect distribution map.
  • the number of the predetermined defects is the sum of the numbers of all the defects in the predetermined area.
  • determining the detection result includes: determining the predetermined area where the number of the predetermined defects is less than a set threshold value as a qualified area, and determining the number of the predetermined defects greater than or equal to the The predetermined area where the threshold is set is determined as a non-conforming area.
  • a three-dimensional defect distribution map is constructed based on the three-dimensional space occupied by the plurality of wafers and the number of defects on the plurality of wafers and the defect positions.
  • the predetermined area is a three-dimensional space occupied by a plurality of wafers.
  • each of the predetermined regions is a cylindrical region defined by a predetermined bottom radius with a diameter passing through one defect and parallel to the stacking direction of a plurality of wafers as a central axis.
  • Each of the defects corresponds to one of the predetermined areas.
  • the number of the predetermined defects is the number of defects with the same defect position on different wafers.
  • the determined detection result includes any one of the following: the predetermined area where the number of the predetermined defects is less than a set threshold is determined as a qualified area, and the number of the predetermined defects The predetermined area that is greater than or equal to the set threshold is determined to be an unqualified area; a plurality of stacked wafers are derived from the same ingot, and the number of predetermined defects is greater than or equal to the set threshold, and the predetermined The defect originates from the preparation and processing process of the wafer.
  • the volume of each predetermined area is 0.5% to 5% of the total volume of the three-dimensional space occupied by the plurality of wafers.
  • the predetermined area is a three-dimensional space occupied by a plurality of the wafers
  • the method includes: acquiring images of a plurality of the wafers, and the plurality of wafers are from the same ingot , And positioning points are respectively formed on the edges of the plurality of wafers; the images of the plurality of wafers are subjected to stereoscopic superposition processing, and the stereoscopic superposition processing is performed based on the positioning points, so as to obtain the The superimposed images of the multiple wafers; looking for defects on the superimposed images to determine whether there are continuous defects, the continuous defects appearing at the same position on at least two wafers, wherein the continuous defects Existence is an indication that the defect originates from the preparation and processing process of the wafer.
  • the images of the multiple wafers are obtained by performing image processing on the multiple wafers or reconstructing a data set of the multiple wafers.
  • the continuous defect occurs on at least 3 wafers, preferably at least 5 wafers.
  • the continuous defect is located on the edge of the wafer, and the continuous defect is determined by the following steps: constructing an XYZ space rectangular coordinate system, and placing the surface of the superimposed image perpendicular to the Z axis Set, determine the arc segment corresponding to each defect on the edge of the wafer, and use the center point of the arc segment as the characteristic point of the defect; determine that the characteristic point is in the XYZ space rectangular coordinate system
  • two defects corresponding to two characteristic points satisfying at least one of the following conditions are regarded as the continuous defects: (1) the x-axis of the two characteristic points The coordinate difference between the y-axis and the y-axis are respectively smaller than the first predetermined threshold; (2) the projections of the arc segments corresponding to the two characterizing points on the surface of the superimposed image have at least a part of overlap.
  • the first predetermined threshold is determined based on the length of the arc segment corresponding to the two characteristic points.
  • the first predetermined threshold is less than 50% of the length of the smaller arc segment of the arc segments corresponding to the two characterizing points.
  • the continuous defect is located inside the wafer, and the method includes: constructing an XYZ space rectangular coordinate system; acquiring a data set of the multiple wafers, and based on the data set The structure of the multiple wafers is reconstructed in the XYZ space rectangular coordinate system; the defect area is determined on each surface of the multiple wafers; the center point of the defect area is determined as the Characterization points of the defective area; on two adjacent wafers, two defective areas corresponding to two center points that meet at least one of the following conditions are regarded as the continuous defect: (1) the two centers The coordinate differences of the x-axis and the y-axis of the points are respectively smaller than a second predetermined threshold; (2) the projections of the defect regions corresponding to the two center points on the surface of the superimposed image overlap at least partially.
  • the second predetermined threshold is determined by the longest line segment that can be determined between the two defective regions.
  • the second predetermined threshold is less than 50% of the longest line segment.
  • the defect area is formed by a plurality of defect points.
  • the present disclosure provides a system for automatically detecting and controlling defects on a wafer.
  • the system includes: a patterning unit that constructs a defect distribution map based on at least one defect information on the wafer, the defect information including the number of defects, the type of the defect, and the position of the defect; a partition unit , The partition unit is connected to the patterning unit, and is used to partition at least one predetermined area in the defect distribution map; the statistics unit is connected to the patterning unit and the partition unit and is used to count each The number of predetermined defects in each of the predetermined areas; a comparison unit, the comparison unit is connected to the statistical unit, and is used to compare the number of predetermined defects in each of the predetermined areas with a set threshold, And based on the comparison result, determine the test result.
  • the system can automatically detect defects on the wafer, and perform partition statistics and card control on the defects on at least one wafer, so as to ensure the quality of the produced chips and improve the yield rate.
  • the aforementioned system can effectively execute the aforementioned method.
  • FIG. 1 is a schematic diagram of a two-dimensional defect distribution diagram according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of the division of a two-dimensional defect distribution map according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of the division of a two-dimensional defect distribution map according to another embodiment of the present disclosure.
  • Fig. 4 is a schematic diagram of a three-dimensional defect distribution diagram according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a system for detecting and controlling defects on a wafer according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a system for detecting and controlling defects on a wafer according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a system for detecting and controlling defects on a wafer according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic flowchart of a method for obtaining superimposed images of multiple wafers in a method for detecting and controlling defects on a wafer according to an embodiment of the present disclosure.
  • 9 is a method for detecting and controlling defects on a wafer according to an embodiment of the present disclosure to obtain superimposed images of multiple wafers.
  • FIG. 10 is a method for detecting and controlling defects on a wafer according to another embodiment of the present disclosure to obtain superimposed images of multiple wafers.
  • FIG. 11 is a method for detecting and controlling defects on a wafer according to another embodiment of the present disclosure to obtain superimposed images of multiple wafers.
  • FIG. 12 is a method for detecting and controlling defects on a wafer according to another embodiment of the present disclosure to obtain superimposed images of multiple wafers.
  • FIG. 13 is a method for detecting and controlling defects on a wafer according to another embodiment of the present disclosure to obtain superimposed images of multiple wafers.
  • the wafer inspection is usually based on the type and quantity of defects. For example, 10 particle defects are controlled. These 10 particle defects may be scattered on the surface of the entire wafer, or concentrated in a certain area, or continuous Defects (front and back), etc., if they are scattered, they may have less impact on the quality of the produced chips. If they are concentrated in one area, they may seriously affect the quality of the produced chips in the areas where the defects are concentrated.
  • the inspection method does not take into account the impact of defect distribution on the quality of the produced chips.
  • the current inspection equipment is single-chip inspection, and it is difficult to monitor the causes of defects from a single wafer.
  • those wafers with edge defects still meet customer specifications, and it is more difficult to detect continuous problems that may be caused by improper processing. If a method can be used to quickly find the problems in the process, it may be Fundamentally reduce the chance of such defects recurring.
  • the inventor proposed a detection and card control method that considers the type of defects, the number of defects, and the distribution of defects at the same time.
  • a single wafer can be used to output the inspection results (TFF, Klarf, CSV, image and other formats). Automatically judge the number of defects, defect types, defect location distribution and other conditions to ensure the quality of the produced chips or effectively reflect the problems in the wafer processing process.
  • the present disclosure provides a method for automatically detecting and controlling defects on a wafer.
  • the method includes: providing at least one stacked wafer; and constructing a defect distribution map based on defect information on each of the wafers, the defect information including defect quantity, defect type, and defect location Divide at least one predetermined area in the defect distribution map; determine the number of predetermined defects in each predetermined area based on the defect location; compare the number of predetermined defects in each predetermined area with Set a threshold for comparison, and based on the comparison result, determine the detection result.
  • the distribution of defects can also be controlled to avoid problems caused by concentrated defect distribution, thereby better ensuring the quality of the produced wafers, and at the same time , It can also effectively reflect the problems in the wafer processing process through the defect distribution, which has a guiding significance for the wafer manufacturing process.
  • the specific material of the wafer can be silicon wafer, sapphire, silicon carbide, etc.
  • the specific size of the wafer is not particularly limited, and can be a wafer of any size, specifically, including but not limited to diameter Wafers of 100mm, 150mm, 200mm, 300mm, 400mm, 450mm, 660mm, etc.
  • the thickness of the wafer can be tens of microns or hundreds of microns, such as 18 microns, 20 microns, 52 microns, 67 microns, 600 microns , 725 microns, 755 microns, 770 microns, etc., can be flexibly selected according to actual needs, so I won’t repeat them here.
  • the method can detect and control defects on a wafer, and only one wafer is required at this time; in other embodiments, the method can also detect multiple wafers at the same time. Multiple wafers are stacked and arranged. Specifically, the centers of the multiple wafers are on a straight line, and the orientation of the multiple wafers is the same, that is, when producing wafers, positioning marks (such as positioning points, positioning grooves, etc.), and alignment marks on multiple wafers that are stacked are aligned in the stacking direction. In this way, the positions of multiple defects on the wafer can be directly located in one coordinate system, which is convenient for analysis and statistics.
  • the method can detect and control different types of defects on the wafer, such as cop (crystal primary particles), pits (etch pits), particles (particles), scratches (scratches), slips (Slippage), bright field defects, pin hole (air pocket), etc., you can choose to detect and control only certain types of defects, certain types of defects, or all types of defects according to your needs .
  • cop crystal primary particles
  • pits etch pits
  • particles particles
  • scratches scratches
  • slips slips
  • bright field defects pin hole (air pocket), etc.
  • the method can detect and control defects in a two-dimensional plane, or detect and control defects in a three-dimensional space.
  • a two-dimensional defect distribution map is constructed based on the defect information on the first surface of the wafer.
  • the first surface of the wafer refers to a circular surface of the wafer, and correspondingly, the above-mentioned two-dimensional defect distribution map is a circular two-dimensional plane corresponding to the first surface, and the two-dimensional plane is marked with the All defects on the surface and their locations.
  • the circular two-dimensional defect distribution map can be referred to as shown in FIG. 1, the points in the circular area are defects 1, and the points with different colors are different types of defects.
  • the two-dimensional defect distribution map can be partitioned by different partitioning methods, and the partitioning method should be able to better reflect the distribution of defects on the two-dimensional circular plane.
  • the outer circumference of the first surface forms a first circle 10, a plurality of second circles 20 concentric with the first circle 10 and a plurality of second circles 20 passing through the first circle 10
  • the diameter 11 of the center of the circle 10 intersects to define a plurality of the predetermined regions 30.
  • the predetermined area 30 is defined by a predetermined radius with one of the defects as the center. Each defect corresponds to a predetermined area.
  • each defect may occupy a certain area instead of a point.
  • taking a defect as the center of the circle can be any point in the defect as the center of the circle. In some specific embodiments, it can be formed by the outer periphery of the defect.
  • the geometric center of the figure is the center of the circle.
  • the above-mentioned multiple second circles have different radii and can be gradually contracted from the first circle, and the difference between the radii of two adjacent second circles is not particularly limited, and it can be flexible according to actual partitioning needs.
  • choose, and the difference between the radii of any two adjacent second circles can be the same or different; and the multiple diameters are diameters in different directions, and there is a certain angle between two adjacent diameters,
  • the size of the included angle can also be flexibly selected according to the needs of the partition, and the included angle before any two adjacent diameters can be the same or different.
  • the smaller the area of each predetermined area, the better, and the multiple predetermined areas should be divided as evenly as possible on the entire two-dimensional defect distribution map , But the smaller the area of the predetermined area, the more complicated the statistics.
  • the area of each predetermined area can be 0.5% to 5% of the total area of the two-dimensional defect distribution map (specifically, 0.5%, 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, 5%, etc.).
  • the area of each predetermined area can be the same or different, and can be selected according to actual needs.
  • the "predetermined defect” mentioned herein refers to a defect that meets certain conditions.
  • the specific conditions to be met can be selected according to actual needs, for example, including but not limited to a certain type of defect, and a certain number of types.
  • the number of the predetermined defects is the sum of the numbers of all the defects in the predetermined area. That is, after dividing multiple predetermined areas in the two-dimensional defect distribution map, the number of all types of defects in each predetermined area is counted, and then the number of all types of defects obtained by the statistics is compared with the set threshold.
  • determining the detection result may include: determining the predetermined area where the number of the predetermined defects is less than a set threshold as a qualified area, and determining the number of the predetermined defects The predetermined area that is greater than or equal to the set threshold is determined as a non-conforming area.
  • the threshold value set herein can be set artificially according to different usage requirements.
  • the threshold value can be relatively small, while for products with relatively loose quality requirements, the threshold value can be set. It is relatively large and can be adjusted flexibly according to actual needs.
  • the method for detecting and controlling defects on a wafer may include the following steps: providing a wafer with a diameter of 300 mm, and constructing a two-dimensional defect distribution map based on the number and location of defects on the wafer (Refer to FIG. 1), a predetermined area is divided by the intersection between a plurality of second circles 20 and a plurality of first circles concentric with the first circle formed by the outer circumference of the wafer (refer to FIG. 2), wherein, The radii of the multiple second circles are 65mm, 93mm, 113mm, 131mm and 148mm respectively, and the angle between two adjacent ones is 15 degrees.
  • the predetermined area with the number of all types of defects less than the set threshold of 4 is determined as a qualified area, and the number of all types of defects is greater than or equal to 4
  • the predetermined area is judged to be an unqualified area (refer to the black frame area in FIG. 2), in which points with different shades of color are different types of defects.
  • the method for detecting and controlling defects on a wafer may include the following steps: providing a wafer with a diameter of 300mm, and constructing a two-dimensional defect distribution based on the number and location of defects on the wafer Figure (refer to Figure 1), with each defect in the obtained two-dimensional defect distribution map as the center, a circular predetermined area is delineated according to a predetermined radius of 20mm (refer to Figure 3), and each defect corresponds to one of the predetermined areas, Then count the number of all types of defects in each predetermined area, set a threshold of 6, compare the number of all types of defects in each predetermined area with the set threshold of 6, and the number of all types of defects is less than the set threshold of 6.
  • the predetermined area is judged to be a qualified area, and the predetermined area with the number of all types of defects greater than or equal to 6 is judged to be an unqualified area (refer to the black frame area in FIG. 3), where points with different color shades are different types of defects.
  • a three-dimensional defect distribution map is constructed based on the three-dimensional space occupied by the plurality of stacked wafers and the defect information on the plurality of wafers.
  • the three-dimensional defect distribution map corresponds to a cylindrical three-dimensional space, and the specific size is the same as the volume occupied by a plurality of stacked wafers, wherein all the defects on the plurality of wafers and their positions are marked.
  • the cylindrical three-dimensional defect distribution map can be referred to as shown in FIG. 4, the points in the cylindrical space are defects 1, and the points with different shades are different types of defects.
  • the general principle of zoning is the same as detecting and controlling defects on a two-dimensional plane, except that each predetermined area is also a three-dimensional space.
  • the three-dimensional space occupied by multiple wafers may constitute a predetermined area.
  • each of the predetermined areas is to pass through one defect and interact with multiple wafers.
  • the straight line parallel to the stacking direction is the central axis, and the cylindrical area is defined according to the predetermined bottom radius, and each defect corresponds to one predetermined area.
  • a defect will occupy a certain area.
  • a straight line that passes through one defect and is parallel to the stacking direction of multiple wafers is used as the central axis.
  • the straight line can pass through the geometric center of the figure formed by the outer circumference of the defect.
  • the predetermined bottom radius of each predetermined area can be flexibly adjusted according to actual needs, as long as it can better reflect the distribution of defects, and the predetermined bottom radius of multiple predetermined areas can be the same or different .
  • the volume of each predetermined area is 0.5% to 5% of the total volume of the three-dimensional space occupied by the plurality of wafers (specifically, 0.5%, 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, 5%, etc.).
  • the predetermined number of defects is the number of defects with the same defect position on different wafers (or called continuous defects). That is to say, after dividing multiple predetermined areas in the three-dimensional defect distribution map, count the defects on each wafer in the area, and then compare whether the positions of the defects on different wafers are the same, and the recording positions are the same and located in different
  • the number of defects on the wafer (where the defects of the same position are aligned in the stacking direction of multiple wafers, or the orthographic projection of the defects of the same position on the bottom surface of the cylindrical space occupied by the multiple wafers is at least Partially overlap).
  • the defect that the orthographic projections on different wafers and the bottom surface of the cylindrical space occupied by multiple stacked wafers at least partially overlap can be regarded as the same defect position on different wafers. Defects.
  • the predetermined defect is located on the edge of the wafer, and defects with the same defect position on different wafers are determined by the following steps:
  • the two defects corresponding to the two characterizing points can be regarded as different defects on the wafer. Defects in the same location.
  • the two characterization points when the projections of the arc segments corresponding to the two characterization points on the bottom surface of the cylindrical space occupied by the plurality of stacked wafers overlap at least partially, the two characterization points
  • the two corresponding defects can be regarded as defects with the same defect position on different wafers.
  • the length of the overlapping portion is at least 50% of the length of the shorter arc segment.
  • the arc segments corresponding to the two characterizing points are occupied by multiple stacked wafers
  • the projections on the bottom surface of the cylindrical space also overlap at least partially. Then the two defects corresponding to the two characteristic points can be regarded as defects with the same defect position on different wafers.
  • the projections of the arc segments corresponding to the two characterizing points on the bottom surface of the cylindrical space occupied by the multiple stacked wafers have at least a partial overlap, which can also be understood as two arc segments Part of the X coordinate and part of the Y coordinate are the same.
  • the above-mentioned first predetermined threshold is determined based on the length of the arc segment corresponding to the two characteristic points. Specifically, the first predetermined threshold is less than 50% of the length of the smaller arc segment of the arc segments corresponding to the two characterizing points. Therefore, specifically, when the coordinate difference between the x-axis and the y-axis of the two characterizing points is smaller, it means that the two defect arc segments overlap more, and the position of the two defects is closer, and the correlation is greater. Furthermore, analyzing the predetermined defects is more meaningful for optimizing and adjusting the preparation process of the wafer.
  • the predetermined defect is located inside the wafer, and the method for determining defects with the same defect position on different wafers may include:
  • the present disclosure regards a plurality of densely distributed defects on a wafer as a defect area, if the defects are on multiple consecutive wafers If the defect area appears at the same position, the multiple defect areas are defects with the same defect position on different wafers.
  • two adjacent defect areas are not completely the same, it can be judged whether they are defects with the same defect position on different wafers according to the coordinate difference of the center point of the defect area. For example, when the coordinate difference between the x-axis and the y-axis of the two center points is smaller than the second predetermined threshold value, it can be regarded as a defect with the same defect position on different wafers.
  • the second predetermined threshold is determined by the longest line segment that can be determined between the two defective regions. That is, each defective area may be an irregular area, and the distance between the two furthest points on the edge of the irregular area is set as the longest line segment.
  • the second predetermined threshold is less than 50% of the longest line segment.
  • the coordinate difference between the x-axis and the y-axis of the two center points is smaller than the second predetermined threshold value.
  • the coordinate difference between the x-axis and the y-axis of the two center points is smaller, it means that the overlap area of the two defective regions is more, and the closer the positions of the two defective regions are, the greater the correlation.
  • analyzing the defects with the same defect position on the different wafers is more meaningful for optimizing and adjusting the preparation process of the wafer.
  • the defect area on the above-mentioned wafer is formed by multiple defects. At least 1% of the defects in the two defect regions determined to be the same defects on the Z-axis direction of the wafers are identical, that is, at least 1% of the defects are similar in the Z-axis The x coordinate and y coordinate.
  • the defect regions corresponding to the two center points are in a cylindrical shape occupied by a plurality of stacked wafers.
  • the projections on the bottom surface of the space overlap at least partially.
  • the overlapping area is at least 50% of the area of the smaller defect region.
  • determining the detection result includes: determining the predetermined area where the number of the predetermined defects is less than a set threshold as a qualified area, and determining the predetermined area The predetermined area where the number of defects is greater than or equal to the set threshold is determined to be an unqualified area; in other embodiments, multiple stacked wafers are derived from the same ingot, and the detection result is determined based on the comparison result It includes: the number of the predetermined defects is greater than or equal to the set threshold, and it is determined that the predetermined defects originate from the preparation and processing process of the wafer.
  • the method for detecting and controlling defects on a wafer may include the following steps: providing multiple 300mm stacked multiple wafers based on the three-dimensional space occupied by the multiple stacked wafers
  • a three-dimensional defect distribution map (refer to Figure 4) is constructed from the space and the number of defects on the multiple wafers and the defect locations, and then predetermined areas are divided in the three-dimensional defect distribution map, where each predetermined area is One of the defects and a straight line parallel to the stacking direction of a plurality of the wafers is the central axis, and a cylindrical area defined by a predetermined bottom radius of 2mm, each of the defects corresponds to one of the predetermined areas, and then each Compare the number of defects with the same defect position on different wafers in the predetermined area with the set threshold 2.
  • the predetermined area with the same defect position on different wafers less than the set threshold is judged as a qualified area, and A predetermined area where the number of defects with the same defect position on different wafers is greater than or equal to the set threshold 2 is determined as a defective area (refer to the predetermined area 30 shown in FIG. 4).
  • the method for detecting and controlling defects on a wafer may include the following steps: providing a plurality of 300mm stacked multiple wafers, based on the amount occupied by the multiple stacked wafers The three-dimensional space, the number of defects on the multiple wafers and the location of the defects construct a three-dimensional defect distribution map, the space occupied by multiple wafers is regarded as a predetermined area, and then the different wafers in the predetermined area are counted The number of defects with the same defect position is compared with the set threshold 2. If the number of defects with the same defect position on different wafers is greater than or equal to 2, it is determined that the predetermined defect originates from the preparation and processing process of the wafer .
  • the number of defects, types of defects, and defect locations on each wafer can be detected by conventional methods, such as crystal primary particles, pits, particles, scratches, bright field defects, and slippage. , It can be detected by laser scanning (such as KLA SP series, Hitachi LS series laser scanning equipment), SIRD detection, infrared scanning, etc.
  • the stomata can be detected by infrared scanning, X-ray, etc., and the equipment will output the detection data after detection .
  • the inspection data may be an image of the wafer or all defect information documents.
  • a defect distribution map may be constructed directly based on the image (defect image, inspection image) or defect information document of the above-mentioned wafer.
  • the method for detecting and controlling defects on a wafer may include the following steps: taking the space occupied by a plurality of wafers as a predetermined area, and acquiring images of the plurality of wafers.
  • the circles come from the same crystal rod, and positioning points are respectively formed on the edges of the multiple wafers; the images of the multiple wafers are subjected to stereoscopic superposition processing, and the stereoscopic superposition processing is based on the positioning points
  • search for defects on the superimposed images to determine whether there are continuous defects that occur at the same position on at least two wafers, wherein, The existence of the continuous defect is an indication that the defect originates from the preparation and processing process of the wafer.
  • the method of the above-mentioned embodiment of the present disclosure can more conveniently and clearly discover the commonality and correlation between the defects on each wafer, thereby facilitating the statistical analysis of the defects. Due to the defects generated in the wafer manufacturing process, it may be caused by improper processing equipment or manufacturing process. Therefore, this method can be used to monitor the distribution of defects on the wafers of each production batch. If it is continuously generated, it can be found and corrected in real time as soon as possible, so as to increase productivity and reduce losses.
  • the three-dimensional superimposition processing is performed based on the positioning point, so as to obtain superimposed images of the multiple wafers.
  • the three-dimensional superimposition processing method may be parallel alignment processing, oblique alignment processing, rotation alignment processing, and the like.
  • the three-dimensional superimposition processing in the following embodiments is described by a parallel alignment processing method, and the protection of this technical solution is not limited by the specific alignment method.
  • images of multiple wafers are obtained by performing image processing on multiple wafers or reconstructing a data set of multiple wafers. That is, after a wafer is manufactured, it is scanned to obtain a three-dimensional image of the single wafer, or a three-dimensional image of the single wafer obtained by reconstructing a wafer data set.
  • positioning points are respectively formed on the edge of the image of each wafer, and based on the positioning points on each image, the images of multiple wafers are aligned in the original order in order to obtain a superposition of multiple wafers. image.
  • an OPENGL platform or a DirectX platform can be used to produce superimposed images of multiple wafers.
  • the production of an overlay image can be performed in the following steps: select the type of overlay image and load the selected image file or data file; image file processing and cropping or conversion of the image file from the data file; image file transparency processing; A 3D space is created, and the 3D space is used to load and overlay image files to obtain an overlay image (refer to FIG. 8).
  • the image files in the above steps may include processing parameters and surface parameters.
  • processing parameters can include: thickness, curvature, warpage, flatness, nano-topography, etc.
  • surface parameters can include: scratches, cracks, line marks, pores, chipping notches, etc.
  • FIG. 9 is the superposition of wafer thickness images
  • FIG. 10 is the superposition of nanotopological images of the wafer surface
  • FIG. 11 is the superposition of wafer SPV images
  • FIG. 12 is the superposition of 3D wafer thickness images.
  • the correlation of defects can be found. For example, the same defect appears at the same position on several consecutive wafers. Furthermore, this continuous defect can be correlated and defined as a continuous defect, and the cause of the continuous defect can be further analyzed which step in the wafer preparation process comes from, so as to optimize or adjust the preparation process. guide.
  • the above-mentioned continuous defect needs to appear on at least 3 wafers.
  • the defects that only appear on one or two wafers are accidental or may appear randomly, so they are not of analytical value and cannot be confirmed as continuous defects.
  • the above-mentioned continuous defects preferably appear on at least 5 wafers. Therefore, it can be considered that the defect is generated during the wafer preparation process. Analysis of its causes is more valuable to optimize and adjust the preparation process.
  • the method for determining the continuous defect is the same as the method for determining the defect with the same defect position on a different wafer, and will not be repeated here.
  • the above method of the present disclosure can automatically monitor the surface defect distribution of wafers, effectively intercept wafers with specific defects on the surface, and can achieve the effect of taking into account the defect distribution that cannot be achieved by the current detection methods for the number of surface defects of card silicon wafers. Avoid the abnormality of specific defective wafers in the client and affect the yield of the client, and effectively improve customer satisfaction.
  • the present disclosure provides a system for automatically detecting and controlling defects on a wafer.
  • the system includes: a patterning unit 100, which constructs a defect distribution map based on at least one defect information on the wafer; a partitioning unit 200, and the partitioning unit 200 and The patterning unit 100 is connected to divide at least one predetermined area in the defect distribution map; the statistics unit 300 is connected to the patterning unit 100 and the partitioning unit 200 to count each The number of predetermined defects in the predetermined area; a comparison unit 400, the comparison unit 400 is connected to the statistics unit 300, and is used to compare the number of the predetermined defects in each predetermined area with a set threshold Compare and determine the test result based on the comparison result.
  • the system can automatically detect defects on the wafer, and perform partition statistics and card control on the defects on at least one wafer, so as to ensure the quality of the produced wafers and improve the yield rate.
  • the system may further include a result output unit 500, which is connected to the comparison unit 400 and is configured to output the detection result. Therefore, it is convenient for technicians to read the test results.
  • the aforementioned system can effectively execute the aforementioned method, wherein the specific working process of each unit can be performed with reference to the aforementioned method, which will not be repeated here.
  • the detection data file obtained by the above detection can be directly input into the composition unit to construct the defect distribution map, and then proceed to the subsequent steps.
  • the system may further include a detection unit 600 for detecting defects on the wafer.
  • the detection unit 600 is connected to the patterning unit to automatically detect defects on the wafer and generate inspection data. , Output to the composition unit, and then proceed to the subsequent steps in sequence.

Abstract

一种自动侦测并卡控晶圆上缺陷的方法和系统，该方法包括：提供至少一个层叠设置的晶圆；基于每个所述晶圆上的缺陷信息，构建缺陷分布图；在所述缺陷分布图中划分至少一个预定区域（30）；基于缺陷位置，确定每个所述预定区域（30）中的预定缺陷的数量；将每个所述预定区域（30）中的所述预定缺陷的数量与设定阈值进行比较，基于比较结果，确定检测结果。

Description

自动侦测并卡控晶圆上缺陷的方法和系统
优先权信息
本公开要求于2019年5月7日提交至中国专利局、申请号为201910376534.7，和于2020年4月3日提交至中国专利局、申请号为202010257939.1的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及晶圆检测技术领域，具体的，涉及自动侦测并卡控晶圆上缺陷的方法和系统。
背景技术
晶圆制造工序中，晶圆表面可能会产生各种缺陷如cop(晶体原生颗粒)、pits(蚀坑)、particles(颗粒)、scratches(刮伤)、slip(滑移)、bright field defects(亮场缺陷)、pin hole(air pocket)(气孔)等，目前，会采用多种检测设备来检测晶圆的缺陷，但只根据单一设备的检测结果进行单一缺陷的判定，这种检测和判定方法不足以确保产出的晶圆质量，导致后续芯片的不良率仍然较高。
另外，因加工制程中受到污染或加工本身亦会造成很多缺陷的产生，如线切割后形成的切痕(saw mark)、单/双面研磨由不均匀而形成的磨痕(grinding mark)、抛光后形成的凸起(bump)或缺陷(PID)、热处理后产生的位错滑移(slip)、在运输过程中因机械手造成的磨损或划痕等。上述的缺陷类型可能发生在晶圆各个位置，大多处在晶圆的边缘处。因为检测设备皆是单片检测，很难从单片晶圆上的缺陷信息找到其产生的原因。特别是那些具有边缘缺陷的晶圆仍符合客户规格，更难监测到其可能因加工制程不当而连续产生的问题。
因而，目前的晶圆检测相关技术仍有待改进。
公开内容
本公开旨在至少在一定程度上解决相关技术中的技术问题之一。为此，本公开的一个目的在于提出一种能够更好的保证产出芯片质量的自动侦测并卡控晶圆上缺陷的方法和系统。
在本公开的一个方面，本公开提供了一种自动侦测并卡控晶圆上缺陷的方法。根据本公开的实施例，该方法包括：提供至少一个层叠设置的晶圆；基于每个所述晶圆上的缺陷信息，构建缺陷分布图，所述缺陷信息包括缺陷数量、缺陷种类和缺陷位置；在所述缺陷分布图中划分至少一个预定区域；基于所述缺陷位置，确定每个所述预定区域中的预定缺陷的数量；将每个所述预定区域中的所述预定缺陷的数量与设定阈值进行比较，并基于比较结果，确定检测结果。通过该方法，在卡控晶圆上的缺陷数量和缺陷种类的同时，还可以卡控缺陷的分布情况，避免缺陷分布集中导致的问题，从而更好地保证产出芯片的品质，且通过预定缺陷种类的选择，可以有效反映晶圆加工制程中存在的问题，对于指导晶圆制造工艺具有重要意义。
根据本公开的实施例，基于一个所述晶圆的第一表面上的所述缺陷数量和所述缺陷位置构建二维缺陷分布图。
根据本公开的实施例，所述第一表面的外周线构成第一圆形，多个与所述第一圆形同心的第二圆形和多个过所述第一圆形的圆心的直径相交限定出多个所述预定区域。
根据本公开的实施例，所述预定区域为以一个所述缺陷为圆心、按照预定半径划定的圆形区域，每个缺陷对应一个所述预定区域。
根据本公开的实施例，每个所述预定区域的面积为所述二维缺陷分布图的总面积的0.5％～5％。
根据本公开的实施例，所述预定缺陷的数量为所述预定区域中的所有缺陷的数量之和。
根据本公开的实施例，基于所述比较结果，确定检测结果包括：将所述预定缺陷的数量小于设定阈值的所述预定区域判定为合格区域，将所述预定缺陷的数量大于等于所述设定阈值的所述预定区域判定为不合格区域。
根据本公开的实施例，基于多个所述晶圆所占据的立体空间以及多个所述晶圆上的所述缺陷数量和所述缺陷位置构建三维缺陷分布图。
根据本公开的实施例，所述预定区域为多个所述晶圆所占据的立体空间。
根据本公开的实施例，每个所述预定区域为以经过一个所述缺陷且与多个所述晶圆的层叠方向平行的直径为中心轴线，按照预定底面半径划定的圆柱形区域，每个所述缺陷对应一个所述预定区域。
根据本公开的实施例，所述预定缺陷的数量为不同的所述晶圆上所述缺陷位置相同的缺陷的数量。
根据本公开的实施例，基于所述比较结果，确定检测结果包括以下任意一种：将所述预定缺陷的数量小于设定阈值的所述预定区域判定为合格区域，将所述预定缺陷的数量大 于等于所述设定阈值的所述预定区域判定为不合格区域；多个层叠设置的晶圆来源于同一个晶棒，所述预定缺陷的数量大于等于所述设定阈值，判定所述预定缺陷来源于所述晶圆的制备加工制程。
根据本公开的实施例，每个所述预定区域的体积为多个所述晶圆所占据的立体空间的总体积的0.5％～5％。
根据本公开的实施例，所述预定区域为多个所述晶圆所占据的立体空间，所述方法包括：获取多个所述晶圆的图像，所述多个晶圆来自于同一晶棒，并且多个所述晶圆的边缘上分别形成有定位点；将多个所述晶圆的图像进行立体化叠加处理，所述立体化叠加处理是基于所述定位点进行的，以便获得所述多个晶圆的叠加图像；在所述叠加图像上寻找缺陷，确定是否存在连续型缺陷，所述连续型缺陷出现在至少两个晶圆的相同位置上，其中，所述连续型缺陷的存在是所述缺陷来源于所述晶圆的制备加工制程的指示。
根据本公开的实施例，所述多个晶圆的所述图像是通过对所述多个晶圆进行影像处理或者对所述多个晶圆的数据集进行重构获得的。
根据本公开的实施例，所述连续型缺陷出现在至少3个晶圆上，优选至少5个晶圆上。
根据本公开的实施例，所述连续型缺陷位于所述晶圆的边缘上，并且连续型缺陷是通过下列步骤确定的：构建X-Y-Z空间直角坐标系，并将所述叠加图像的表面垂直Z轴设置，确定各缺陷在所述晶圆的边缘上对应的弧线段，将所述弧线段的中心点作为所述缺陷的表征点；确定所述表征点在所述X-Y-Z空间直角坐标系中的坐标；在相邻的两个晶圆上，将满足下列条件至少之一的两个表征点所对应的两个缺陷作为所述连续型缺陷：(1)所述两个表征点的x轴和y轴的坐标差异分别小于第一预定阈值；(2)所述两个表征点所对应的弧线段在所述叠加图像的表面上的投影存在至少一部分重叠。
根据本公开的实施例，所述第一预定阈值是基于所述两个表征点所对应弧线段的长度确定的。
根据本公开的实施例，所述第一预定阈值小于所述两个表征点所对应弧线段中较小弧线段长度的50％。
根据本公开的实施例，所述连续型缺陷位于所述晶圆的内部，并且所述方法包括：构建X-Y-Z空间直角坐标系；获取所述多个晶圆的数据集，并且基于所述数据集在所述X-Y-Z空间直角坐标系中对所述多个晶圆的结构进行重构；分别在所述多个晶圆的每一个表面上确定缺陷区域；确定所述缺陷区域的中心点作为所述缺陷区域的表征点；在相邻的两个晶 圆上，将满足下列条件至少之一的两个中心点所对应的两个缺陷区域作为所述连续型缺陷：(1)所述两个中心点的x轴和y轴的坐标差异分别小于第二预定阈值；(2)所述两个中心点所对应的缺陷区域在与所述叠加图像的表面上的投影存在至少一部分重叠。
根据本公开的实施例，第二预定阈值是由两个缺陷区域的所能确定的最长线段确定的。
根据本公开的实施例，所述第二预定阈值小于所述最长线段的50％。
根据本公开的实施例，所述缺陷区域是通过多个缺陷点构成的。
在本公开的另一方面，本公开提供了一种自动侦测并卡控晶圆上缺陷的系统。根据本公开的实施例，该系统包括：构图单元，所述构图单元基于至少一个所述晶圆上的缺陷信息构建缺陷分布图，所述缺陷信息包括缺陷数量、缺陷种类和缺陷位置；分区单元，所述分区单元与所述构图单元相连，用于在所述缺陷分布图中划分至少一个预定区域；统计单元，所述统计单元与所述构图单元和所述分区单元相连，用于统计每个所述预定区域中的预定缺陷的数量；比较单元，所述比较单元与所述统计单元相连，用于将每个所述预定区域中的所述预定缺陷的数量与设定阈值进行比较，并基于比较结果，确定检测结果。该系统可以自动侦测晶圆上的缺陷，并对至少一个晶圆上的缺陷进行分区统计和卡控，从而能够很好地保证产出芯片的质量，提高良率。
根据本公开的实施例，前面所述的系统可以有效执行前面所述的方法。
附图说明
图1是本公开一个实施例的二维缺陷分布图的示意图。
图2是本公开一个实施例的二维缺陷分布图的分区示意图。
图3是本公开另一个实施例的二维缺陷分布图的分区示意图。
图4本公开一个实施例的三维缺陷分布图的示意图。
图5是本公开一个实施例的侦测和卡控晶圆上缺陷的系统的结构示意图。
图6是本公开一个实施例的侦测和卡控晶圆上缺陷的系统的结构示意图。
图7是本公开一个实施例的侦测和卡控晶圆上缺陷的系统的结构示意图。
图8是本公开一个实施例的侦测和卡控晶圆上缺陷的方法中获得多个晶圆的叠加图像的方法流程示意图。
图9是本公开一个实施例的侦测和卡控晶圆上缺陷的方法获得多个晶圆的叠加图像。
图10是本公开另一个实施例的侦测和卡控晶圆上缺陷的方法获得多个晶圆的叠加图像。
图11本公开另一个实施例的侦测和卡控晶圆上缺陷的方法获得多个晶圆的叠加图像。
图12是本公开另一个实施例的侦测和卡控晶圆上缺陷的方法获得多个晶圆的叠加图像。
图13是本公开另一个实施例的侦测和卡控晶圆上缺陷的方法获得多个晶圆的叠加图像。
具体实施方式
下面详细描述本公开的实施例。下面描述的实施例是示例性的，仅用于解释本公开，而不能理解为对本公开的限制。实施例中未注明具体技术或条件的，按照本领域内的文献所描述的技术或条件或者按照产品说明书进行。所用试剂或仪器未注明生产厂商者，均为可以通过市购获得的常规产品。
本公开是基于公开人的以下发现和认识而完成的：
针对目前虽然对晶圆进行检测，但是仍不能很好地保证产出晶圆质量问题，也不能有效反映晶圆加工制程中存在的问题，发明人进行了深入分析，发现主要原因之一在于目前的晶圆检测通常只依据缺陷种类及数量进行卡控，例如卡控10个颗粒缺陷，这10个颗粒缺陷可能是散布于整片晶圆表面，也可能集中于某一区域，或是连续型缺陷(前后片)等等，如果分散分布，则对产出芯片的质量影响可能较小，而如果集中分布在一个区域中，则可能会严重影响缺陷集中分布区域产出芯片的质量，即目前的检测方法未考虑到缺陷分布情况对产出芯片质量的影响。另外，目前检测设备皆是单片检测，很难从单片晶圆存在缺陷监测其产生的原因。特别是那些具有边缘缺陷的晶圆仍符合客户规格，更难监测到其可能因加工制程不当而连续产生的问题，若能够通过某种方法来快速地找到工艺制程所存在的问题，则可能从根本上降低此类缺陷重复出现的几率。基于上述发现，发明人经过研究后提出一种同时考虑缺陷种类、缺陷数量和缺陷分布的检测和卡控方法，具体可以利用单一晶圆输出检测结果(TFF，Klarf，CSV，图像等格式)，针对缺陷数量、缺陷种类、缺陷位置分布等条件进行自动判断，以确保产出的芯片质量或者有效反映晶圆加工制程中的问题。
有鉴于此，在本公开的一个方面，本公开提供了一种自动侦测并卡控晶圆上缺陷的方法。根据本公开的实施例，该方法包括：提供至少一个层叠设置的晶圆；基于每个所述晶圆上的缺陷信息，构建缺陷分布图，所述缺陷信息包括缺陷数量、缺陷种类和缺陷位置；在所述缺陷分布图中划分至少一个预定区域；基于所述缺陷位置，确定每个所述预定区域中的预定缺陷的数量；将每个所述预定区域中的所述预定缺陷的数量与设定阈值进行比较， 并基于比较结果，确定检测结果。通过该方法，在卡控晶圆上的缺陷数量和缺陷种类的同时，还可以卡控缺陷的分布情况，避免缺陷分布集中导致的问题，从而更好地保证产出的晶圆的品质，同时，还可以通过缺陷分布情况有效反应晶圆加工制程存在的问题从而对晶圆制造工艺具有指导意义。
根据本公开的实施例，晶圆的具体材质为可以硅晶圆、蓝宝石、碳化硅等，而晶圆的具体尺寸没有特别限制，可以为任意尺寸的晶圆，具体的，包括但不限于直径为100mm、150mm、200mm、300mm、400mm、450mm、660mm等的晶圆，而晶圆的厚度可以为数十微米或者数百微米，具体如18微米、20微米、52微米、67微米、600微米、725微米、755微米、770微米等等，均可以根据实际需要灵活选择，在此不再一一赘述。
一些实施例中，该方法可以侦测和卡控一个晶圆上的缺陷，此时只需要提供一个晶圆即可；另一些实施例中，该方法也可以同时检测多个晶圆，此时将多个晶圆层叠设置，具体的，多个晶圆的圆心位于一条直线上，且多个晶圆的方位是一致的，即生产晶圆时，会在晶圆的特定位置设置定位标记(如定位点、定位槽等)，而层叠设置的多个晶圆上的对位标记在层叠方向上是对齐设置的。如此，多个对晶圆上的缺陷的位置是可以直接在一个坐标系中进行定位的，便于进行分析统计。
根据本公开的实施例，该方法可以侦测和卡控晶圆上不同种类的缺陷，具体如cop(晶体原生颗粒)、pits(蚀坑)、particles(颗粒)、scratches(刮伤)、slip(滑移)、bright field defects(亮场缺陷)、pin hole(air pocket)(气孔)等，具体可以根据需要选择仅侦测和卡控某一种缺陷、某几种缺陷或者全部种类的缺陷。
根据本公开的实施例，根据不同需要，该方法中可以侦测和卡控二维平面上的缺陷，也可以侦测和卡控三维立体空间中的缺陷。
一种实施方式中，基于一个所述晶圆的第一表面上的所述缺陷信息构建二维缺陷分布图。其中，晶圆的第一表面是指晶圆的一个圆形表面，相应的，上述二维缺陷分布图则为与第一表面对应的一个圆形二维平面，该二维平面中标注了该表面上所有的缺陷及其位置。一个具体实施例中，圆形二维缺陷分布图可以参照图1所示，圆形区域中的点为缺陷1，颜色深浅不同的点为不同种类的缺陷。
根据本公开的实施例，可以通过不同的划分方式对二维缺陷分布图进行分区，分区方式应尽量能够更好的体现缺陷在二维圆形平面上的分布情况。一些具体实施例中，参照图2，所述第一表面的外周线构成第一圆形10，多个与所述第一圆形10同心的第二圆形20和多个过所述第一圆形10的圆心的直径11相交限定出多个所述预定区域30。另一些具体实施例中，参照图3(图3中仅示出了4个预定区域，未示出全部预定区域)，所述预定区 域30为以一个所述缺陷为圆心、按照预定半径划定的圆形区域，每个缺陷对应一个所述预定区域。通过上述分区方式，可以更好的侦测和卡控缺陷集中分布的情况，进而能够更好的保证产出芯片的质量。
需要说明的是，每个缺陷可能会占据一定面积，而非一个点，本文中以一个缺陷为圆心可以是以缺陷中的任一点为圆心，一些具体实施例中，可以以缺陷外周线构成的图形的几何中心为圆心。
可以理解，上述多个第二圆形的半径不同，可以从第一圆形逐渐内缩，而相邻两个第二圆形的半径之间的差值没有特别限制，可以根据实际分区需要灵活选择，且任意相邻两个第二圆形的半径之间的差值可以相同，也可以不同；而上述多个直径是不同方向的直径，相邻两个直径之间具有一定的夹角，该夹角的大小也可以根据分区需要灵活选择，且任意相邻的两个直径之前的夹角可以相同，也可以不同。
根据本公开的实施例，为了更好的侦测和卡控缺陷的分布情况，每个预定区域的面积越小越好，且多个预定区域应尽量均匀的分在整个二维缺陷分布图上，但是预定区域面积越小，统计越复杂，综合考虑不同因素，可以使得每个所述预定区域的面积为所述二维缺陷分布图的总面积的0.5％～5％(具体如0.5％、1％、1.5％、2％、2.5％、3％、3.5％、4％、4.5％、5％等)。而每个预定区域的面积可以相同，也可以不同，具体可以根据实际需要进行选择。
根据本公开的实施例，本文中所述的“预定缺陷”是指满足一定条件的缺陷，具体满足的条件可以根据实际需要进行选择，例如包括但不限于某一种类的缺陷、某几个种类的缺陷的和等等。一些具体实施例中，侦测和卡控二维平面上的缺陷时，所述预定缺陷的数量为所述预定区域中的所有缺陷的数量之和。也就是说，在二维缺陷分布图中划分好多个预定区域后，统计每个预定区域中所有种类的缺陷的数量，然后将统计得到的所有种类的缺陷的数量与设定阈值进行比较。
具体的，针对二维缺陷分布图，基于所述比较结果，确定检测结果可以包括：将所述预定缺陷的数量小于设定阈值的所述预定区域判定为合格区域，将所述预定缺陷的数量大于等于所述设定阈值的所述预定区域判定为不合格区域。
根据本公开的实施例，本文中设定阈值可以根据不同的使用要求人为设定，对于质量要求较高的产品，设定阈值可以比较小，而对于质量要求相对宽松的产品，设定阈值可以相对较大，具体根据实际需要灵活调整即可。
一个具体实施例中，该侦测和卡控晶圆上缺陷的方法可以包括以下步骤：提供一个直径为300mm的晶圆，基于该晶圆上的缺陷数量和缺陷位置，构建二维缺陷分布图(参照图 1)，采用与晶圆的外周线构成的第一圆形同心的多个第二圆形20和多个第一圆形的之间相交划分预定区域(参照图2)，其中，多个第二圆形的半径分别为65mm、93mm、113mm、131mm和148mm，相邻两个之间的夹角为15度，然后统计每个预定区域中的所有种类缺陷的数量，设定阈值为4，将每个预定区域中的所有种类缺陷的数量与设定阈值4比较，所有种类缺陷的数量小于设定阈值4的预定区域判定为合格区域，而所有种类缺陷的数量大于等于4的预定区域判定为不合格区域(参照图2中黑色框区)，其中，颜色深浅不同的点为不同种类的缺陷。
另一个具体实施例中，该侦测和卡控晶圆上缺陷的方法可以包括以下步骤：提供一个直径为300mm的晶圆，基于该晶圆上的缺陷数量和缺陷位置，构建二维缺陷分布图(参照图1)，以得到的二维缺陷分布图中的每一个缺陷为圆心、按照预定半径20mm划定圆形的预定区域(参照图3)，每个缺陷对应一个所述预定区域，然后统计每个预定区域中的所有种类缺陷的数量，设定阈值为6，将每个预定区域中的所有种类缺陷的数量与设定阈值6比较，所有种类缺陷的数量小于设定阈值6的预定区域判定为合格区域，而所有种类缺陷的数量大于等于6的预定区域判定为不合格区域(参照图3中黑色框区)，其中，颜色深浅不同的点为不同种类的缺陷。
另一种实施方式中，基于多个层叠设置的所述晶圆所占据的立体空间以及多个所述晶圆上的所述缺陷信息构建三维缺陷分布图。具体的，该三维缺陷分布图对应一个圆柱形的立体空间，具体尺寸与多个层叠设置的晶圆所占据的体积相同，其中，标出了多个晶圆上的所有缺陷及其位置。一个具体实施例中，圆柱形三维缺陷分布图可以参照图4所示，圆柱形空间中的点为缺陷1，颜色深浅不同的点为不同种类的缺陷。
根据本公开的实施例，侦测和卡控三维立体空间中的缺陷时，分区的总体原则与侦测和卡控二维平面上的缺陷一致，只是每个预定区域同样为一个立体空间。一些具体实施例中，多个晶圆所占据的立体空间可以构成一个预定区域。另一些具体实施例中，参照图4(图4中仅示出一个预定区域，未示出全部预定区域)，每个所述预定区域为以经过一个所述缺陷且与多个所述晶圆的层叠方向平行的直线为中心轴线，按照预定底面半径划定的圆柱形区域，每个所述缺陷对应一个所述预定区域。通过上述分区方式，可以更好的侦测和卡控缺陷集中分布的情况，进而能够更好的保证产出芯片的质量。
需要说明的是，如前所述，缺陷会占据一定的面积，本文中以经过一个所述缺陷且与多个所述晶圆的层叠方向平行的直线为中心轴线，可以为该直线经过缺陷中的任意一点，具体的，该直线可以经过该缺陷的外周线构成的图形的几何中心。
根据本公开的实施例，每个预定区域的预定底面半径可以根据实际需要灵活调整，只 要能够更好地体现缺陷的分布情况即可，且多个预定区域的预定底面半径可以相同，也可以不同。一些具体实施例中，为了更好的体现缺陷分布情况，每个所述预定区域的体积为多个所述晶圆所占据的立体空间的总体积的0.5％～5％(具体如0.5％、1％、1.5％、2％、2.5％、3％、3.5％、4％、4.5％、5％等)。由此，既能够有效卡控多个晶圆上的缺陷，且分区合理，统计工作量不会过大。
一些具体实施例中，侦测和卡控三维立体空间中的缺陷时，所述预定缺陷的数量为不同的所述晶圆上所述缺陷位置相同的缺陷的数量(或称连续型缺陷)。也就是说，在三维缺陷分布图中划分好多个预定区域后，统计该区域中每个晶圆上的缺陷，然后比对不同晶圆上的缺陷的位置是否相同，记录位置相同、且位于不同晶圆上的缺陷的数量(其中，位置相同的缺陷在多个晶圆从层叠的方向上对齐，或者说位置相同的缺陷在多个对晶圆占据的圆柱形空间的底面上的正投影至少部分重叠)。由此，除了侦测和卡控晶圆上的缺陷，还可以反应晶圆生产线上可能存在的问题，即如果多个晶圆均在同一位置出现缺陷，那很可能是晶圆生产线上与该位置对应的工序存在问题。
根据本公开的实施例，可以将位于不同晶圆上、且在多个层叠设置的晶圆所占据的圆柱形空间的底面上的正投影至少部分重叠的缺点作为不同的晶圆上缺陷位置相同的缺陷。
根据本公开的一个实施例，所述预定缺陷位于所述晶圆的边缘上，并且不同的晶圆上缺陷位置相同的缺陷是通过下列步骤确定的：
构建X-Y-Z空间直角坐标系，并将多个层叠设置的晶圆所占据的圆柱形空间的底面垂直Z轴设置，确定各缺陷在所述晶圆的边缘上对应的弧线段，将所述弧线段的中心点作为所述缺陷的表征点；确定所述表征点在所述X-Y-Z空间直角坐标系中的坐标。在相邻的两个晶圆上，将满足下列条件至少之一的两个表征点所对应的两个缺陷作为不同的晶圆上缺陷位置相同的缺陷：
(1)所述两个表征点的x轴和y轴的坐标差异分别小于第一预定阈值；
(2)所述两个表征点所对应的弧线段在多个层叠设置的晶圆所占据的圆柱形空间的底面上的投影存在至少一部分重叠。
因此，根据本公开的一个实施例，当两个表征点x轴和y轴的坐标差异分别小于第一预定阈值，则该两个表征点所对应的两个缺陷可以作为不同的晶圆上缺陷位置相同的缺陷。
根据本公开的另一个实施例，当两个表征点所对应的弧线段在多个层叠设置的晶圆所占据的圆柱形空间的底面上的投影存在至少一部分重叠，则该两个表征点所对应的两个缺陷可以作为不同的晶圆上缺陷位置相同的缺陷。具体的，该重叠部分的长度为其中较短弧线段长度的至少50％。
根据本公开的再一个实施例，当两个表征点x轴和y轴的坐标差异分别小于第一预定阈值，并且两个表征点所对应的弧线段在多个层叠设置的晶圆所占据的圆柱形空间的底面上的投影还存在至少一部分重叠。则该两个表征点所对应的两个缺陷可以作为不同的晶圆上缺陷位置相同的缺陷。
根据本公开具体实施例，两个表征点所对应的弧线段在多个层叠设置的晶圆所占据的圆柱形空间的底面上的投影存在至少一部分重叠，也可以理解为两个弧线段的部分X坐标和部分Y坐标相同。
根据本公开具体实施例，上述第一预定阈值是基于所述两个表征点所对应弧线段的长度确定。具体地，所述第一预定阈值小于所述两个表征点所对应弧线段中较小弧线段长度的50％。因此，具体地，当两个表征点x轴和y轴的坐标差异越小，说明两个缺陷弧线段的重叠越多，那么两个缺陷的位置越接近，关联性越大。进而分析该预定缺陷对优化和调整晶圆的制备工艺更加有意义。
根据本公开的一个实施例，所述预定缺陷位于所述晶圆的内部，用于确定不同的晶圆上缺陷位置相同的缺陷的方法可以包括：
构建X-Y-Z空间直角坐标系；并将多个层叠设置的晶圆所占据的圆柱形空间的底面垂直Z轴设置，分别在所述多个晶圆的每一个表面上确定缺陷区域；确定所述缺陷区域的中心点作为所述缺陷区域的表征点(如图13所示的晶圆表面缺陷图像的堆叠)；
在多个晶圆上，将满足下列条件至少之一的两个中心点所对应的两个缺陷区域作为不同的晶圆上缺陷位置相同的缺陷：
(1)所述两个中心点的x轴和y轴的坐标差异分别小于第二预定阈值；
(2)所述两个中心点所对应的缺陷区域在多个层叠设置的晶圆所占据的圆柱形空间的底面上的投影存在至少一部分重叠。
因此，当不同的晶圆上缺陷位置相同的缺陷位于所述晶圆的内部时，本公开将一个晶圆上分布比较密集的多个缺陷作为一个缺陷区域，若在连续的多个晶圆上相同位置上都出现了该缺陷区域，则将该多个缺陷区域为不同的晶圆上缺陷位置相同的缺陷。而当相邻的两个缺陷区域之间并不是完全相同时，可以根据缺陷区域中心点的坐标差异判断其是否为不同的晶圆上缺陷位置相同的缺陷。例如当两个中心点的x轴和y轴的坐标差异分别小于第二预定阈值时，可以认为是不同的晶圆上缺陷位置相同的缺陷。也可以根据两个缺陷区域是否有重叠判断其是否为不同的晶圆上缺陷位置相同的缺陷。例如，若两个晶圆上的两个缺陷区域在多个层叠设置的晶圆所占据的圆柱形空间的底面上的投影存在至少一部分重叠时，可以认为是不同的晶圆上缺陷位置相同的缺陷。由此可以对该不同的晶圆上缺陷位 置相同的缺陷进行分析，用于指导晶圆制备工艺的优化，以便从根源上提高晶圆品质。
根据本公开的一个实施例，第二预定阈值是由两个缺陷区域的所能确定的最长线段确定的。即每个缺陷区域可能为不规则的区域，将该不规则区域边缘上最远的两个点之间的距离设定为最长线段。该第二预定阈值小于最长线段的50％。而两个中心点的x轴和y轴的坐标差异分别小于第二预定阈值时。具体地，当两个中心点的x轴和y轴的坐标差异越小，说明两个缺陷区域的重叠面积越多，那么两个缺陷区域的位置越接近，关联性越大。进而分析该不同的晶圆上缺陷位置相同的缺陷对优化和调整晶圆的制备工艺更加有意义。
根据本公开的具体实施例，上述晶圆上的缺陷区域是通过多个缺陷构成的。而上述被确定为在Z轴方向上不同的晶圆上缺陷位置相同的缺陷的两个缺陷区域内至少有1％的缺陷是完全相同的，即至少有1％的缺陷在Z轴上具有相似的x坐标和y坐标。
根据本公开的具体实施例，上述用于确定不同的晶圆上缺陷位置相同的缺陷的方法中，所述两个中心点所对应的缺陷区域在多个层叠设置的晶圆所占据的圆柱形空间的底面上的投影存在至少一部分重叠。具体的，该重叠的面积为其中较小缺陷区域面积的至少50％。由此可以保证该两个缺陷区域的关联性，进而更加准确地用于分析产生该缺陷的原因，以便对制备晶圆的方法做出指导，提高晶圆的品质。
具体的，针对三维缺陷分布图，一些实施例中，基于所述比较结果，确定检测结果包括：将所述预定缺陷的数量小于设定阈值的所述预定区域判定为合格区域，将所述预定缺陷的数量大于等于所述设定阈值的所述预定区域判定为不合格区域；另一些实施例中，多个层叠设置的晶圆来源于同一个晶棒，基于所述比较结果，确定检测结果包括：所述预定缺陷的数量大于等于所述设定阈值，判定所述预定缺陷来源于所述晶圆的制备加工制程。
一个具体实施例中，该侦测和卡控晶圆上缺陷的方法可以包括以下步骤：提供多个300mm且层叠设置的多个晶圆，基于多个层叠设置的所述晶圆所占据的立体空间以及多个所述晶圆上的所述缺陷数量和所述缺陷位置构建三维缺陷分布图(参照图4)，然后在三维缺陷分布图中划分预定区域，其中，每个预定区域为以经过一个所述缺陷且与多个所述晶圆的层叠方向平行的直线为中心轴线，按照预定底面半径2mm划定的圆柱形区域，每个所述缺陷对应一个所述预定区域，然后统计每个预定区域中不同的晶圆上缺陷位置相同的缺陷的数量，将其与设定阈值2比较，不同的晶圆上缺陷位置相同的缺陷的数量小于设定阈值的预定区域判定为合格区域，而不同的晶圆上缺陷位置相同的缺陷的数量大于等于设定阈值2的预定区域判定为不合格区域(参照图4中示出的预定区域30)。
另一个具体实施例中，该侦测和卡控晶圆上缺陷的方法可以包括以下步骤：提供多个300mm且层叠设置的多个晶圆，基于多个层叠设置的所述晶圆所占据的立体空间以及多个 所述晶圆上的所述缺陷数量和所述缺陷位置构建三维缺陷分布图，将多个晶圆占据的空间作为一个预定区域，然后统计该预定区域中不同的晶圆上缺陷位置相同的缺陷的数量，将其与设定阈值2比较，如果不同的晶圆上缺陷位置相同的缺陷的数量大于等于2，则判定所述预定缺陷来源于所述晶圆的制备加工制程。
根据本公开的实施例中，每个晶圆上的缺陷数量、缺陷种类和缺陷位置可以采用常规方法进行检测，例如晶体原生颗粒、蚀坑、颗粒、刮伤、亮场缺陷和滑移等缺陷，可以通过激光扫描(如采用KLA SP系列，Hitachi LS系列激光扫描设备)、SIRD检测、红外扫描等方式进行检测，气孔可以通过红外扫描、X射线等方式进行检测，检测后设备会输出检测数据。其中，检测数据可以为晶圆的图像，也可以为所有的缺陷信息文档，该方法中可以直接基于上述晶圆的图像(缺陷图像，检测图像)或者缺陷信息文档构建缺陷分布图。
另一个具体实施例中，该侦测和卡控晶圆上缺陷的方法可以包括以下步骤：将多个晶圆占据的空间作为一个预定区域，获取多个晶圆的图像，所述多个晶圆来自于同一晶棒，并且所述多个晶圆的边缘上分别形成有定位点；将所述多个晶圆的图像进行立体化叠加处理，所述立体化叠加处理是基于所述定位点进行的，以便获得所述多个晶圆的叠加图像；在所述叠加图像上寻找缺陷，确定是否存在连续型缺陷，所述连续型缺陷出现在至少两个晶圆的相同位置上，其中，所述连续型缺陷的存在是所述缺陷来源于所述晶圆的制备加工制程的指示。目前现有检测晶圆的方法多是对单片晶圆进行检测。而发明人发现，单片检测使得晶圆的缺陷更加独立化，不便于对缺陷进行统计分析，甚至可能对无形中存在关联的缺陷进行了分隔。因此，发明人认为，对单片晶圆的检测无法发现多片晶圆之间存在缺陷的共性和关联性，从而增加分析产生该缺陷原因的难度。为此，提出将来自同一晶棒的多个晶圆的图像整合成叠加图像，并在叠加图像上寻找缺陷，确定是否存在连续型缺陷，连续缺陷出现在至少两个晶圆的相同位置上，其中，该连续型缺陷的存在是缺陷来源于晶圆的制备工艺的指示。因此，本公开上述实施例的方法能够更加方便清晰地发现各晶圆上缺陷之间存在的共性和关联性，进而便于对缺陷的进行统计分析。由于晶圆制程中产生的缺陷，可能是因为加工设备或制程不当致使连续产生。因此，该方法可用于监控各生产批次晶圆上缺陷分布状况，若是连续产生，可实时尽早发现并修正，使生产率提升、损失降低。
具体的，获取多个晶圆的图像，所述多个晶圆来自于同一晶棒，并且所述多个晶圆的边缘上分别形成有定位点；将所述多个晶圆的图像进行立体化叠加对齐处理，所述立体化 叠加处理是基于所述定位点进行的，以便获得所述多个晶圆的叠加图像。该立体化叠加处理方式可以为平行对齐处理、倾斜对齐处理、旋转对齐处理等方式。以下实施例中立体化叠加处理采用平行对齐处理方式来描述，该技术方案的保护不受具体对齐方式的限制。
根据本公开的实施例，多个晶圆的图像是通过对多个晶圆进行影像处理或者对多个晶圆的数据集进行重构获得的。即在制造一个晶圆后，对其进行扫描以获得该单片晶圆的立体图像，或者根据一个晶圆数据集进行重构获得的该单片晶圆的立体图像。
具体地，每一个晶圆的图像边缘上分别形成有定位点，基于每个图像上的定位点，将多个晶圆的图像按照原有顺序进行平行对齐处理，以便获得多个晶圆的叠加图像。
根据本公开的具体实施例，可以采用OPENGL平台或者DirectX平台制作多个晶圆的叠加图像。
根据本公开的一个具体实施例，制作叠加图像可以按照下列步骤进行：选择叠图种类并载入选择图档或者资料档；图档处理裁切或由资料档转换图档；图档透明处理；创建3D空间，使用所述3D空间载入并叠加图档获得叠加图像(参考图8)。
根据本公开的具体实施例，上述步骤中图档可以包括加工参数和表面参数。其中，加工参数可以包括：厚度、弯曲度、翘曲度、平坦度、纳米形貌、等；表面参数可以包括：刮伤、裂纹、线痕、气孔、崩边缺口、等。
根据本公开的具体实施例，通过上述方法制备得到的叠加图像如图9-12所示。其中，具体地，图9为晶圆厚度图像的叠加；图10为晶圆表面纳米拓扑图像的叠加；图11为晶圆SPV图像的叠加；图12为3D晶圆厚度图像的叠加。
具体的，在所述叠加图像上寻找缺陷，确定是否存在连续型缺陷，所述连续型缺陷出现在至少两个晶圆的相同位置上，其中，所述连续型缺陷的存在是所述缺陷来源于所述晶圆的制备工艺的指示。
由此，通过观察多个晶圆的叠加形成叠加图像，可以发现缺陷的关联性。例如在连续几个晶圆上相同位置处，都出现相同缺陷。进而可以将这个连续的缺陷建立关联性，并将其定义为连续型缺陷，进一步分析产生该连续型缺陷的原因是来自晶圆制备工艺中的哪一步骤，从而对制备工艺的优化或者调整提供指导。
根据本公开的一个实施例，上述连续型缺陷需要出现在至少3个晶圆上。而仅出现在一个或者两个晶圆上的缺陷具有偶然性，也可能随机出现的，所以不具有分析的价值，进 而不能够将其确认为连续型缺陷。
根据本公开的具体实施例，上述连续型缺陷优选出现在至少5个晶圆上。由此可以认为该缺陷的产生是制备晶圆过程中产生的。分析其产生的原因对优化和调整制备工艺更有价值。
需要说明的是，该连续型缺陷的确定方法与前文不同的晶圆上缺陷位置相同的缺陷的确定方法一致，在此不再赘述。
本公开的上述方法，可以自动监控晶圆表面缺陷分布，有效拦截表面存在特定缺陷的晶圆，可以实现目前卡控硅片表面缺陷数量的检测方法所无法实现的兼顾缺陷分布的效果，进而可以避免特定缺陷晶圆在客户端出现异常、影响客户端良率的问题，有效提高客户满意度。
在本公开的另一方面，本公开提供了一种自动侦测并卡控晶圆上缺陷的系统。根据本公开的实施例，参照图5，该系统包括：构图单元100，所述构图单元100基于至少一个所述晶圆上的缺陷信息构建缺陷分布图；分区单元200，所述分区单元200与所述构图单元100相连，用于在所述缺陷分布图中划分至少一个预定区域；统计单元300，所述统计单元300与所述构图单元100和所述分区单元200相连，用于统计每个所述预定区域中的预定缺陷的数量；比较单元400，所述比较单元400与所述统计单元300相连，用于将每个所述预定区域中的所述预定缺陷的数量与设定阈值进行比较，并基于比较结果，确定检测结果。该系统可以自动侦测晶圆上的缺陷，并对至少一个晶圆上的缺陷进行分区统计和卡控，从而能够很好地保证产出晶圆的质量，提高良率。
根据本公开的实施例，参照图6，该系统还可以包括结果输出单元500，所述结果输出单元与所述比较单元400相连，用于将所述检测结果输出。由此，可以方便技术人员阅读检测结果。
根据本公开的实施例，前面所述的系统可以有效执行前面所述的方法，其中，各个单元的具体工作过程均可参照前面描述的方法进行，在此不再一一赘述。
一些实施例中，可以直接将上述检测得到的检测数据文档输入构图单元，进行缺陷分布图的构建，然后进行后续步骤。另一些实施例中，参照图7，该系统还可以包括用于检测晶圆上的缺陷的检测单元600，该检测单元600与构图单元相连，可以自动检测晶圆上的缺陷，并生成检测数据，输出至构图单元，然后依次进行后续步骤。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包 含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (20)

  1. 一种自动侦测并卡控晶圆上缺陷的方法，其特征在于，包括：
    提供至少一个层叠设置的晶圆；
    基于每个所述晶圆上的缺陷信息，构建缺陷分布图，所述缺陷信息包括缺陷数量、缺陷种类和缺陷位置；
    在所述缺陷分布图中划分至少一个预定区域；
    基于所述缺陷位置，确定每个所述预定区域中的预定缺陷的数量；
    将每个所述预定区域中的所述预定缺陷的数量与设定阈值进行比较，并基于比较结果，确定检测结果。
  2. 根据权利要求1所述的方法，其特征在于，基于一个所述晶圆的第一表面上的所述缺陷信息构建二维缺陷分布图。
  3. 根据权利要求2所述的方法，其特征在于，所述预定区域满足以下条件的任意一种：
    所述第一表面的外周线构成第一圆形，多个与所述第一圆形同心的第二圆形和多个所述第一圆形的直径相交限定出多个所述预定区域；
    所述预定区域为以一个所述缺陷为圆心、按照预定半径划定的圆形区域，每个缺陷对应一个所述预定区域。
  4. 根据权利要求2或3所述的方法，其特征在于，所述预定缺陷的数量为所述预定区域中的所有缺陷的数量之和；
    任选地，基于所述比较结果，确定检测结果包括：将所述预定缺陷的数量小于设定阈值的所述预定区域判定为合格区域，将所述预定缺陷的数量大于等于所述设定阈值的所述预定区域判定为不合格区域。
  5. 根据权利要求2～4中任一项所述的方法，其特征在于，每个所述预定区域的面积为所述二维缺陷分布图的总面积的0.5％～5％。
  6. 根据权利要求1所述的方法，其特征在于，基于多个所述晶圆所占据的立体空间以及多个所述晶圆上的所述缺陷信息构建三维缺陷分布图；
    任选地，每个所述预定区域的体积为多个所述晶圆所占据的立体空间的总体积的0.5％～5％。
  7. 根据权利要求6所述的方法，其特征在于，所述预定区域满足以下条件的任意一种：
    所述预定区域为多个所述晶圆所占据的立体空间；
    每个所述预定区域为以经过一个所述缺陷且与多个所述晶圆的层叠方向平行的直线为中心轴线，按照预定底面半径划定的圆柱形区域，每个所述缺陷对应一个所述预定区域。
  8. 根据权利要求6或7所述的方法，其特征在于，所述预定缺陷的数量为不同的所述晶圆上所述缺陷位置相同的缺陷的数量；
    任选地，基于所述比较结果，确定检测结果包括以下任意一种：
    将所述预定缺陷的数量小于设定阈值的所述预定区域判定为合格区域，将所述预定缺陷的数量大于等于所述设定阈值的所述预定区域判定为不合格区域；
    多个层叠设置的晶圆来源于同一个晶棒，所述预定缺陷的数量大于等于所述设定阈值，判定所述预定缺陷来源于所述晶圆的制备加工制程。
  9. 根据权利要求1、6-8中任一项所述的方法，其特征在于，所述预定区域为多个所述晶圆所占据的立体空间，所述方法包括：
    获取多个所述晶圆的图像，所述多个晶圆来自于同一晶棒，并且多个所述晶圆的边缘上分别形成有定位点；
    将多个所述晶圆的图像进行立体化叠加处理，所述立体化叠加处理是基于所述定位点进行的，以便获得所述多个晶圆的叠加图像；
    在所述叠加图像上寻找缺陷，确定是否存在连续型缺陷，所述连续型缺陷出现在至少两个晶圆的相同位置上，其中，所述连续型缺陷的存在是所述缺陷来源于所述晶圆的制备加工制程的指示。
  10. 根据权利要求9所述的方法，其特征在于，所述多个晶圆的所述图像是通过对所述多个晶圆进行影像处理或者对所述多个晶圆的数据集进行重构获得的。
  11. 根据权利要求9或10所述的方法，其特征在于，所述连续型缺陷出现在至少3个晶圆上，优选至少5个晶圆上。
  12. 根据权利要求9-11中任一项所述的方法，其特征在于，所述连续型缺陷位于所述晶圆的边缘上，并且连续型缺陷是通过下列步骤确定的：
    构建X-Y-Z空间直角坐标系，并将所述叠加图像的表面垂直Z轴设置，
    确定各缺陷在所述晶圆的边缘上对应的弧线段，将所述弧线段的中心点作为所述缺陷的表征点；
    确定所述表征点在所述X-Y-Z空间直角坐标系中的坐标；
    在相邻的两个晶圆上，将满足下列条件至少之一的两个表征点所对应的两个缺陷作为所述连续型缺陷：
    (1)所述两个表征点的x轴和y轴的坐标差异分别小于第一预定阈值；
    (2)所述两个表征点所对应的弧线段在所述叠加图像的表面上的投影存在至少一部分重叠。
  13. 根据权利要求12所述的方法，其特征在于，所述第一预定阈值是基于所述两个表征点所对应弧线段的长度确定的。
  14. 根据权利要求12或13所述的方法，其特征在于，所述第一预定阈值小于所述两个表征点所对应弧线段中较小弧线段长度的50％。
  15. 根据权利要求9所述的方法，其特征在于，所述连续型缺陷位于所述晶圆的内部，并且所述方法包括：
    构建X-Y-Z空间直角坐标系；
    获取所述多个晶圆的数据集，并且基于所述数据集在所述X-Y-Z空间直角坐标系中对所述多个晶圆的结构进行重构；
    分别在所述多个晶圆的每一个表面上确定缺陷区域；
    确定所述缺陷区域的中心点作为所述缺陷区域的表征点；
    在相邻的两个晶圆上，将满足下列条件至少之一的两个中心点所对应的两个缺陷区域作为所述连续型缺陷：
    (1)所述两个中心点的x轴和y轴的坐标差异分别小于第二预定阈值；
    (2)所述两个中心点所对应的缺陷区域在与所述叠加图像的表面上的投影存在至少一部分重叠。
  16. 根据权利要求15所述的方法，其特征在于，第二预定阈值是由两个缺陷区域的所能确定的最长线段确定的。
  17. 根据权利要求15或16所述的方法，其特征在于，所述第二预定阈值小于所述最长线段的50％。
  18. 根据权利要求15-17中任一项所述的方法，其特征在于，所述缺陷区域是通过多个缺陷点构成的。
  19. 一种自动侦测并卡控晶圆上缺陷的系统，其特征在于，包括：
    构图单元，所述构图单元基于至少一个所述晶圆上的缺陷信息构建缺陷分布图，所述缺陷信息包括缺陷数量、缺陷种类和缺陷位置；
    分区单元，所述分区单元与所述构图单元相连，用于在所述缺陷分布图中划分至少一 个预定区域；
    统计单元，所述统计单元与所述构图单元和所述分区单元相连，用于统计每个所述预定区域中的预定缺陷的数量；
    比较单元，所述比较单元与所述统计单元相连，用于将每个所述预定区域中的所述预定缺陷的数量与设定阈值进行比较，并基于比较结果，确定检测结果。
  20. 根据权利要求19所述的系统，其特征在于，用于执行权利要求1～18中任一项所述的方法。
PCT/CN2020/088889 2019-05-07 2020-05-07 自动侦测并卡控晶圆上缺陷的方法和系统 WO2020224612A1 (zh)

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