WO2020224591A1 - 阵列基板及其制作方法和显示装置 - Google Patents

阵列基板及其制作方法和显示装置 Download PDF

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Publication number
WO2020224591A1
WO2020224591A1 PCT/CN2020/088775 CN2020088775W WO2020224591A1 WO 2020224591 A1 WO2020224591 A1 WO 2020224591A1 CN 2020088775 W CN2020088775 W CN 2020088775W WO 2020224591 A1 WO2020224591 A1 WO 2020224591A1
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Prior art keywords
electrode
sub
pixel electrode
thin film
common
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PCT/CN2020/088775
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English (en)
French (fr)
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杨艳娜
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Publication of WO2020224591A1 publication Critical patent/WO2020224591A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers

Definitions

  • This application relates to the field of display technology, and in particular to an array substrate, a manufacturing method thereof, and a display device.
  • Liquid crystal display is one of the most widely used displays.
  • the LCD includes a pair of panels provided with field generating electrodes (such as pixel electrodes and common electrodes) and a liquid crystal layer arranged between the two panels.
  • field generating electrodes such as pixel electrodes and common electrodes
  • an electric field is generated in the liquid crystal layer.
  • the liquid crystal molecules are deflected under the action of an electric field to control the transmission of light, so that the LCD can display images.
  • Liquid crystal displays include a variety of display modes. Among them, the VA mode is a common display mode with advantages such as high contrast, wide viewing angle, and no frictional alignment. In the VA mode, pixels usually have dark lines due to poor orientation of liquid crystal molecules. In order to improve the viewing angle performance of the panel, polymer stabilized vertical alignment (PSVA) type pixels are gradually applied to the design of large-size TV panels, but there are also dark lines in the PSVA type pixel design.
  • PSVA polymer stabilized vertical alignment
  • An array substrate includes a base substrate, scan lines, data lines, common electrode lines, and a plurality of pixel units arranged on the base substrate.
  • the pixel unit includes at least two thin film transistors, a main pixel electrode, a secondary A pixel electrode and a common electrode, the at least two thin film transistors are arranged above the scan line, and are electrically connected to the main pixel electrode and the sub-pixel electrode, respectively, and the main pixel electrode and the sub-pixel electrode are respectively It is arranged on both sides of the scan line, and a common electrode is not arranged in the area between the main pixel electrode of at least one of the pixel units and the sub-pixel electrode of the adjacent pixel unit.
  • a method for manufacturing an array substrate includes the steps of forming scan lines, data lines, common electrodes, and common electrode lines, forming at least two thin film transistors, and forming main pixel electrodes and sub-pixel electrodes.
  • Forming thin film transistors includes forming The step of gate, source, drain and active layer, wherein the at least two thin film transistors are arranged above the scan line and are electrically connected to the main pixel electrode and the sub pixel electrode, respectively, The main pixel electrode and the sub-pixel electrode are respectively arranged on both sides of the scan line, and the area between the main pixel electrode of at least one of the pixel units and the sub-pixel electrode of the adjacent pixel unit is not set in common electrode.
  • a display device includes an array substrate, the array substrate includes a base substrate, and scan lines, data lines, common electrode lines, and a plurality of pixel units provided on the base substrate.
  • the pixel unit Comprising at least two thin film transistors, a main pixel electrode, a sub pixel electrode, and a common electrode, the at least two thin film transistors are arranged above the scan line and are electrically connected to the main pixel electrode and the sub pixel electrode, The main pixel electrode and the sub-pixel electrode are respectively arranged on both sides of the scan line, and the area between the main pixel electrode of the pixel unit and the sub-pixel electrode of the adjacent pixel unit is not set in common electrode.
  • FIG. 1 is a top view of an array substrate provided by an embodiment of the application
  • FIG. 2 is a schematic cross-sectional structure diagram of an array substrate provided by an embodiment of the application.
  • FIG. 3 is a top view of another array substrate provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of electric field distribution when there is no common electrode between adjacent pixel units and when there is a common electrode provided by an embodiment of the application.
  • the array substrate includes a base substrate 900 and scan lines 100, data lines 200, common electrode lines 300, and a plurality of Pixel unit.
  • the pixel unit includes at least two thin film transistors, a main pixel electrode 400, a sub-pixel electrode 500, and a common electrode 600. At least two thin film transistors are arranged above the scan line 100 and are electrically connected to the main pixel electrode 400 and the sub pixel electrode 500, respectively.
  • the main pixel electrode 400 and the sub pixel electrode 500 are respectively arranged on both sides of the scan line 100, and the area between the main pixel electrode 400 of at least one pixel unit and the sub pixel electrode 500 of the adjacent pixel unit is not provided with a common electrode 600.
  • the common electrode 600 is not provided in the area between the main pixel electrode 400 of the pixel unit and the sub-pixel electrode 500 of the adjacent pixel unit, thereby reducing the voltage of the common electrode 600 to the adjacent two.
  • the interference of the orientation of the liquid crystal molecules in the area between the pixel units solves the problem of the common electrode 600 causing the liquid crystal orientation to be disordered and produces dark lines, and improves the light transmittance and image display quality in the area.
  • the common electrode 600 includes a first common sub-electrode 610 and a second common sub-electrode (not shown) that are perpendicular to each other, and the first common sub-electrode 610 and the data line 200 parallel.
  • the first common sub-electrode 610 in the extension direction of the first common sub-electrode 610, between the projection of the distal end of the first common sub-electrode 610 on the bottom substrate and the projection of the distal end of the main pixel electrode 400 on the base substrate 900 The distance is 5-8 ⁇ m.
  • the distal end of the first common sub-electrode 610 is an end of the first common sub-electrode 610 away from the scan line 100
  • the distal end of the main pixel electrode 400 is an end of the main pixel electrode 400 away from the scan line 100.
  • a storage capacitor is formed by the overlapped portion of the common electrode 600 and the pixel electrode, and the storage capacitor is used to maintain the driving voltage of the pixel unit when the gate of the thin film transistor is turned off.
  • the first common sub-electrode 610 corresponds to the main pixel electrode 400 and the sub-pixel electrode 500. Therefore, in the area between the main pixel electrode 400 of the pixel unit and the sub-pixel electrode 500 of the adjacent pixel unit, when the liquid crystal molecules are subjected to double When the common voltage is applied, the problem of poor orientation of the liquid crystal molecules is serious, and the dark streak phenomenon is also serious.
  • the phenomenon that the liquid crystal molecules are subjected to a double common voltage can be avoided, thereby improving the gap between the vertical backbones of two adjacent pixel units.
  • the poor orientation of the liquid crystal molecules in the area further improving light transmittance and image display quality.
  • the main pixel electrode 400 and the sub-pixel electrode 500 both include a peripheral connecting portion 410, a plurality of strip-shaped main stems 420, and a plurality of strip-shaped pixel sub-electrodes 430 connected to the main stem 420.
  • the backbone includes a horizontal backbone 421 and a vertical backbone 422 that are perpendicular to each other.
  • the horizontal backbone 421 and the vertical backbone 422 divide the pixel unit into a plurality of display domain regions, and the pixel sub-electrodes 430 are located in the display domain regions.
  • the trunk of the pixel electrode covers the common electrode 600, and the projection distance of the distal end of the vertical trunk 422 of the main pixel and the distal end of the corresponding first common sub-electrode 610 on the base substrate 900 is 5-8 ⁇ m.
  • the distal end of the vertical backbone 422 of the main pixel is one end of the vertical backbone 422 of the main pixel away from the scan line 100.
  • the first common sub-electrode 610 in this embodiment corresponds to the vertical backbone 422 of the main pixel electrode 400 and the vertical backbone 422 of the sub-pixel electrode 500, so the vertical backbone 422 and the vertical backbone of the main pixel electrode 400 of the pixel unit In the area between the vertical backbone 422 of the sub-pixel electrode 500 of the adjacent pixel unit, the liquid crystal molecules are affected by the double common voltage, and the problem of poor orientation of the liquid crystal molecules is more serious.
  • the phenomenon that the liquid crystal molecules are subjected to a double common voltage can be avoided, thereby improving the area between the vertical backbones 422 of two adjacent pixel units.
  • the poor orientation of the liquid crystal molecules further improves the light transmittance and image display quality.
  • the projection distance of the distal end of the vertical backbone 422 of the main pixel and the distal end of the corresponding first common sub-electrode 610 on the base substrate 900 is 6 ⁇ m. It can be understood that shrinking the distal end of the first common sub-electrode 610 by 6 ⁇ m can effectively reduce the problem of poor orientation of liquid crystal molecules generated in the area between the vertical backbones 422 of two adjacent pixel units, and it will not If a common sub-electrode 610 is too short, the overlap area between the main pixel electrode 400 and the common electrode 600 is too small, resulting in a small main storage capacitance and affecting the display effect.
  • the pixel unit includes a first thin film transistor TFT_1, a second thin film transistor TFT_2, and a third thin film transistor TFT_3;
  • the source of the first thin film transistor TFT_1 is connected to the data line 200, and the drain of the first thin film transistor TFT_1 is connected to the main pixel electrode 400, and is used to provide a data driving signal to the main pixel electrode 400;
  • the source of the second thin film transistor is connected to the data line 200, and the drain of the second thin film transistor is connected to the sub-pixel electrode 500 for providing data driving signals for the sub-pixel electrode 500;
  • the source of the third thin film transistor TFT_3 is connected to the source of the second thin film transistor TFT_2, and the drain of the third thin film transistor TFT_3 is connected to the common electrode line 300 for the voltage of the data driving signal on the sub-pixel electrode 500.
  • the gate of the first thin film transistor TFT_1, the gate of the second thin film transistor TFT_2, and the gate of the third thin film transistor TFT_3 are connected to the same scan line 100, and the first thin film transistor The drain of TFT_1 and the drain of the second thin film transistor TFT_2 are connected to the same data line 200.
  • a main storage capacitor is formed between the main pixel electrode 400 and the common electrode 600, and a secondary storage capacitor is formed between the sub-pixel electrode 500 and the common electrode 600.
  • the scan line 100 is turned on, the first thin film transistor TFT_1, the second thin film transistor TFT_2, and the third thin film transistor TFT_3 are turned on simultaneously, and the data line 200 charges the main pixel electrode 400 and the sub pixel electrode 500 with data driving signals.
  • the third thin film transistor TFT_3 transfers a part of the charge on the sub-pixel electrode 500 to the common electrode line 300, so that the voltage across the primary storage capacitor is greater than the voltage across the secondary storage capacitor, thereby reducing the brightness of the area corresponding to the sub-pixel electrode 500 The brightness of the area corresponding to the main pixel electrode 400.
  • the deflection angles of the liquid crystal molecules in the area corresponding to the main pixel electrode 400 and the area corresponding to the sub-pixel electrode 500 are also different, thereby improving the large viewing angle of the VA liquid crystal display.
  • the first conductive channel formed between the source and drain of the first thin film transistor TFT_1 is U-shaped
  • the second conductive channel formed between the source and drain of the second thin film transistor TFT_2 The channel is U-shaped
  • the third conductive channel formed between the source and drain of the third thin film transistor TFT_3 is in-line.
  • the source of the first thin film transistor TFT_1 and the source of the second thin film transistor TFT_2 can be designed to be U-shaped, so as to realize the U-shaped design of the thin film transistor and reduce the cost of the first thin film transistor TFT_1 and the second thin film transistor TFT_2.
  • the length of the source and drain in the extending direction along the scan line 100 that is, the distance between the width of the conductive channel in the extending direction along the scan line 100 is reduced) to reduce the space required for wiring and realize the narrowness of the display panel Border design.
  • the ratio of the width to the length of the first conductive channel is greater than the ratio of the width to the length of the second conductive channel. It can be understood that the characteristics of the thin film transistor are related to the ratio of the width to the length of the conductive channel. The larger the ratio of the width to the length of the conductive channel, the better the performance of the thin film transistor.
  • the ratio of the width to length of the first conductive channel and the ratio of the width to length of the second conductive channel By designing the ratio of the width to length of the first conductive channel and the ratio of the width to length of the second conductive channel, the brightness of the area corresponding to the sub-pixel electrode 500 can be lower than the brightness of the area corresponding to the main pixel electrode 400, further improving VA The phenomenon of large viewing role deviation of the type liquid crystal display.
  • the array substrate further includes a gate insulating layer 700 and a passivation layer 800.
  • the gate insulating layer 700 is provided between the gate of the thin film transistor and the layer where the source and drain electrodes are provided in the same layer
  • the passivation layer 800 is provided between the layer where the main pixel electrode and the sub-pixel electrode are located and the layer where the source and drain electrodes are located. between.
  • an embodiment of the present application also provides a method for manufacturing an array substrate.
  • the method includes the steps of forming scan lines 100, data lines 200, common electrodes 600, and common electrode lines 300, forming thin film transistors, and forming main
  • forming a thin film transistor includes the steps of forming a gate electrode, a source electrode, a drain electrode, and an active layer. At least two thin film transistors are arranged above the scan line 100 and are electrically connected to the main pixel electrode 400 and the sub pixel electrode 500 respectively.
  • the main pixel electrode 400 and the sub-pixel electrode 500 are respectively arranged on both sides of the scan line 100, and the area between the main pixel electrode 400 of at least one pixel unit and the sub-pixel electrode 500 of the adjacent pixel unit is not provided with a common electrode 600.
  • the common electrode 600 includes a first common sub-electrode 610 and a second common sub-electrode perpendicular to each other, and the first common sub-electrode 610 is parallel to the data line 200.
  • the first common sub-electrode 610 is parallel to the data line 200.
  • the distance is 5-8 ⁇ m.
  • the distal end of the first common sub-electrode 610 is an end of the first common sub-electrode 610 away from the scan line 100
  • the distal end of the main pixel electrode 400 is an end of the main pixel electrode 400 away from the scan line 100.
  • the manufacturing method of the array substrate is as follows:
  • Step 1 forming the common electrode 600, the common electrode line 300, the gate of the first thin film transistor TFT_1, the gate of the second thin film crystal, the gate of the third thin film transistor TFT_3, and the scan line 100 on the base substrate 900.
  • the step of forming the common electrode 600, the common electrode line 300, the gate electrode and the scan line 100 on the base substrate 900 includes: depositing a layer of metal film on the base substrate 900, and then through the first patterning The process is processed to form a pattern including the scan line 100, the gate, the common electrode 600 and the common electrode line 300, and the scan line 100, the gate and the common electrode 600 are spaced apart.
  • the common electrode 600 includes a first common sub-electrode 610 and a second common sub-electrode perpendicular to each other, and the first common sub-electrode 610 is parallel to the data line 200.
  • the first common sub-electrode 610 is parallel to the data line 200.
  • the distance is 5-8 ⁇ m.
  • the distal end of the first common sub-electrode 610 is an end of the first common sub-electrode 610 away from the scan line 100
  • the distal end of the main pixel electrode 400 is an end of the main pixel electrode 400 away from the scan line 100.
  • the patterning process may include only a photolithography process, or, a photolithography process and an etching step, and may also include printing, inkjet, and other processes for forming predetermined patterns.
  • the photolithography process refers to the process of forming patterns using photoresist, mask, exposure machine, etc., including film formation, exposure, and development.
  • the corresponding patterning process can be selected according to the structure formed in this application.
  • Step two forming the common electrode 600, the common electrode line 300, the gate of the first thin film transistor TFT_1, the gate of the second thin film transistor TFT_2, the gate of the third thin film transistor TFT_3, and the base substrate 900 of the scan line 100
  • a gate insulating layer is formed.
  • a silicon nitride (SiNx) or silicon oxide (SiOx) layer is deposited on the base substrate 900 after step 1 is completed to form a gate insulating layer.
  • a first through hole is provided in the gate insulating layer, and the drain of the third thin film transistor TFT_3 and the common electrode 600 are electrically connected through the first through hole.
  • Step 3 An active layer is formed on the base substrate 900 where the gate insulating layer is formed.
  • a plasma-enhanced chemical vapor deposition method or other similar methods is used to form an amorphous silicon thin film layer above the gate insulating layer, and then a laser annealing process or a solid phase crystallization process is used to crystallize the amorphous silicon To form a polysilicon thin film layer, and through the second patterning process, a pattern containing a low-temperature polysilicon active layer is formed.
  • Step 4 Form the data line 200, the source and drain of the first thin film transistor TFT_1, the source and drain of the second thin film transistor TFT_2, and the source of the third thin film transistor TFT_3 on the base substrate 900 where the active layer is formed. Pole and drain.
  • the source and drain electrodes, and the metal layer of the data line 200 are deposited first, and after photoresist coating and mask exposure are used, patterns of the data line 200, source and drain electrodes are formed by etching.
  • the etching method may be dry etching or wet etching, and the method is not limited.
  • the first conductive channel formed between the source and drain of the first thin film transistor TFT_1 is U-shaped
  • the second conductive channel formed between the source and drain of the second thin film transistor TFT_2 is U-shaped
  • the third conductive channel formed between the source and drain of the thin film transistor TFT_3 is in-line.
  • Step 5 forming the data line 200, the source and drain of the first thin film transistor TFT_1, the source and drain of the second thin film transistor TFT_2, and the source and drain of the third thin film transistor TFT_3 on the base substrate 900
  • a passivation layer is formed, and a second through hole and a third through hole penetrating the passivation layer are formed.
  • the main pixel electrode 400 and the drain of the first thin film transistor TFT_1 are electrically connected through the second through hole, and the sub-pixel electrode 500 and the drain of the second thin film transistor TFT_2 are electrically connected through the third through hole.
  • the first thin film transistor TFT_1, the second thin film transistor TFT_2 and the third thin film transistor TFT_3 are protected by a passivation layer to prevent the first thin film transistor TFT_1, the second thin film transistor TFT_2 and the third thin film transistor TFT_3 from being corroded.
  • Step 6 forming the main pixel electrode 400 and the sub-pixel electrode 500 on the base substrate 900 on which the passivation layer is formed. That is, on the base substrate 900 after step 5 is completed, a layer of indium tin oxide ITO transparent conductive film is deposited on the passivation layer using magnetron sputtering, and the patterning process is followed by coating photoresist and exposure and development. After performing wet etching and stripping, a pattern including pixel electrodes is formed. The through hole is filled with conductive material for forming the pixel electrode, and the pixel electrode is electrically connected to the drain through the through hole. After the above steps, the array substrate provided by the embodiment of the present application is formed.
  • the main pixel electrode 400 and the sub-pixel electrode 500 both include a peripheral connecting portion 410, a plurality of strip-shaped backbones, and a plurality of strip-shaped pixel sub-electrodes 430 connected to the backbones.
  • the backbone includes a horizontal backbone 421 and a vertical backbone 422 that are perpendicular to each other.
  • the horizontal backbone 421 and the vertical backbone 422 divide the pixel unit into a plurality of display domain regions, and the pixel sub-electrodes 430 are located in the display domain regions.
  • this application also provides a display device, which includes the array substrate of any one of the foregoing embodiments.
  • the display device may be any product or component with display function such as liquid crystal panel, electronic paper, OLED panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc.
  • the embodiments of the present application provide an array substrate, a manufacturing method thereof, and a display device.
  • the array substrate includes a base substrate 900 and scan lines 100, data lines 200, common electrode lines 300, and a plurality of pixel units disposed on the base substrate 900.
  • the pixel unit includes a thin film transistor, a main pixel electrode 400, a sub-pixel electrode 500, and a common electrode 600, and the area between the main pixel electrode 400 of at least one pixel unit and the sub-pixel electrode 500 of the adjacent pixel unit is not set in common. Electrode 600.
  • the common electrode 600 is not provided in the area between the main pixel electrode 400 of the pixel unit and the sub-pixel electrode 500 of the adjacent pixel unit.
  • the voltage of the common electrode 600 is reduced to the main pixel electrode 400 of the pixel unit. Interference with the area between the sub-pixel electrode 500 of the adjacent pixel unit, thereby solving the problem of the common electrode 600 causing the liquid crystal orientation disorder and generating dark lines, and improving the light transmittance and picture display quality in this area .

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板，包括衬底基板(900)以及设置在衬底基板(900)上的扫描线(100)、数据线(200)、公共电极线(300)以及多个像素单元，像素单元包括至少两个薄膜晶体管、主像素电极(400)、次像素电极(500)和公共电极(600)，至少两个薄膜晶体管设置在扫描线(100)的上方，分别与主像素电极(400)和次像素电极(500)电连接，主像素电极(400)和次像素电极(500)分别设置在扫描线(100)的两侧，并且至少一个像素单元的主像素电极(400)和与之相邻的像素单元的次像素电极(500)之间的区域不设置公共电极(600)。

Description

阵列基板及其制作方法和显示装置
本申请要求于2019年05月06日提交中国专利局，申请号为2019103699275，申请名称为“阵列基板及其制作方法和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，特别是涉及一种阵列基板及其制作方法和显示装置。
背景技术
液晶显示(Liquid Crystal Display,LCD)器是最广泛使用的显示器之一，LCD包括设置有场发生电极(如像素电极和公共电极)的一对面板以及设置在两个面板之间的液晶层。当施加电压到场发生电极时，液晶层中会产生电场。液晶分子在电场作用下进行偏转，用以控制光的透过情况，从而使LCD显示图像。液晶显示器包括多种显示模式，其中，VA模式是一种具有高对比度、宽视角、无需摩擦配向等优势的常见显示模式。而在VA模式中像素通常会由于液晶分子导向不良而产生暗纹。为了提升面板视角表现，聚合物稳定的垂直排列(Polmer Stabilized Vertivally Aligned，PSVA)型像素逐渐应用于大尺寸电视面板的设计，但在该PSVA型像素设计中也存在暗纹。
发明内容
一种阵列基板，包括衬底基板以及设置在所述衬底基板上的扫描线、数据线、公共电极线以及多个像素单元，所述像素单元包括至少两个薄膜晶体管、主像素电极、次像素电极和公共电极，所述至少两个薄膜晶体管设置在 所述扫描线的上方，分别与所述主像素电极和所述次像素电极电连接，所述主像素电极和所述次像素电极分别设置在所述扫描线的两侧，并且至少一个所述像素单元的主像素电极和与之相邻的像素单元的次像素电极之间的区域不设置公共电极。
一种阵列基板的制作方法，包括形成扫描线、数据线、公共电极和公共电极线的步骤、形成至少两个薄膜晶体管的步骤以及形成主像素电极和次像素电极的步骤，形成薄膜晶体管包括形成栅极、源极、漏极和有源层的步骤，其中所述至少两个薄膜晶体管设置在所述扫描线的上方，分别与所述主像素电极和所述次像素电极电连接，所述主像素电极和所述次像素电极分别设置在所述扫描线的两侧，且至少一个所述像素单元的主像素电极和与之相邻的像素单元的次像素电极之间的区域不设置公共电极。
一种显示装置，所述显示装置包括阵列基板，所述阵列基板包括衬底基板以及设置在所述衬底基板上的扫描线、数据线、公共电极线以及多个像素单元，所述像素单元包括至少两个薄膜晶体管、主像素电极、次像素电极和公共电极，所述至少两个薄膜晶体管设置在所述扫描线的上方，分别与所述主像素电极和所述次像素电极电连接，所述主像素电极和所述次像素电极分别设置在所述扫描线的两侧，并且所述像素单元的主像素电极和与之相邻的像素单元的次像素电极之间的区域不设置公共电极。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种阵列基板的俯视图；
图2为本申请实施例提供的一种阵列基板的剖面结构示意图；
图3为本申请实施例提供的另一种阵列基板的俯视图；
图4为本申请实施例提供的相邻像素单元间无公共电极时和存在公共电极时的电场分布图示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处描述的具体实施例用以解释本申请，并不用于限定本申请。
本申请实施例提供了一种阵列基板，请参考图1和图2，阵列基板包括衬底基板900以及设置在衬底基板900上的扫描线100、数据线200、公共电极线300以及多个像素单元。像素单元包括至少两个薄膜晶体管、主像素电极400、次像素电极500和公共电极600。至少两个薄膜晶体管设置在扫描线100的上方，分别与主像素电极400和次像素电极500电连接。主像素电极400和次像素电极500分别设置在扫描线100的两侧，并且至少一个像素单元的主像素电极400和与之相邻的像素单元的次像素电极500之间的区域不设置公共电极600。
可以理解，在3T_8domain的PSVA型像素设计中，主要是通过给同一个子像素的两个区(主(main)像素区和次(sub)像素区)施加不同电压，使同一个像素单元内的main显示区的4个显示畴区与sub显示区的4个显示畴区的液晶分子的转动角度不一样，从而改善色偏问题。但在PSVA型像素设计中，在沿数据线200延伸的方向上，相邻的两个像素单元之间(即一个像素单元的主像素电极400和与该像素单元相邻的次像素电极500之间)，区域液晶分子受公共电极600电压的影响，容易产生导向不良，从而产生暗纹。本实施例中，通过在像素单元的主像素电极400和与之相邻的像素单元的次像素电极500之间的区域不设置公共电极600，从而降低了公共电极600的电压对相邻的两个像素单元之间区域内的液晶分子导向的干扰，进而解决了 公共电极600引起液晶导向紊乱而产生暗纹的问题，提高了该区域内的透光率和画面显示质量。
在其中一个实施例中，请参见图3和图4，公共电极600包括相互垂直的第一公共子电极610和第二公共子电极(未显示)，且第一公共子电极610与数据线200平行。同一像素单元内，在第一公共子电极610的延伸方向上，第一公共子电极610的远端在沉底基板上投影与主像素电极400的远端在衬底基板900上的投影之间的距离为5～8μm。第一公共子电极610的远端为第一公共子电极610远离扫描线100的一端，主像素电极400的远端为主像素电极400远离扫描线100的一端。
可以理解，对于3T_8domain像素设计的阵列基板，通过公共电极600和像素电极交叠的部分形成存储电容，存储电容用于在薄膜晶体管的栅极关闭时维持像素单元的驱动电压。第一公共子电极610对应于主像素电极400和次像素电极500，因此在像素单元的主像素电极400和与之相邻的像素单元的次像素电极500之间的区域，当液晶分子受到双重公共电压的作用时，液晶分子不良导向问题严重，同时暗纹现象也比较严重。本实施例中通过将第一公共子电极610的远端内缩5～8μm，可避免产生液晶分子受两重公共电压的现象，从而改善在相邻的两个像素单元的竖直主干之间的区域产生的液晶分子不良导向问题，进一步提高光透过率和画面显示质量。
在其中一个实施例中，主像素电极400和次像素电极500均包括周边连接部410、多个条状主干420以及与主干420连接的多个条状像素子电极430。主干包括相互垂直的水平主干421和竖直主干422。水平主干421和竖直主干422将像素单元分成多个显示畴区，像素子电极430位于显示畴区内。像素电极的主干覆盖公共电极600，且主像素的竖直主干422的远端和与之对应的第一公共子电极610的远端在衬底基板900上的投影距离为5～8μm。主像素的竖直主干422的远端为主像素的竖直主干422远离扫描线100的一端。
可以理解，本实施例中第一公共子电极610对应于主像素电极400的竖直主干422和次像素电极500的竖直主干422，因此在像素单元的主像素电极400的竖直主干422和与之相邻的像素单元的次像素电极500的竖直主干422之间的区域，液晶分子受到两重公共电压的作用，液晶分子不良导向问题比较严重。通过将第一公共子电极610的远端内缩5～8μm，可避免产生液晶分子受两重公共电压的现象，从而改善在相邻的两个像素单元的竖直主干422之间的区域产生的液晶分子不良导向问题，进一步提高光透过率和画面显示质量。
在其中一个实施例中，主像素的竖直主干422的远端和与之对应的第一公共子电极610的远端在衬底基板900上的投影距离为6μm。可以理解，将第一公共子电极610的远端内缩6μm，可有效降低相邻的两个像素单元的竖直主干422之间的区域产生的液晶分子不良导向问题，而且还不会因为第一公共子电极610过短造成主像素电极400与公共电极600之间的重叠面积过小，导致主存储电容较小而影响显示效果。
在其中一个实施例中，像素单元包括第一薄膜晶体管TFT_1、第二薄膜晶体管TFT_2和第三薄膜晶体管TFT_3；
第一薄膜晶体管TFT_1的源极与数据线200连接，第一薄膜晶体管TFT_1的漏极与主像素电极400连接，用于为主像素电极400提供数据驱动信号；
第二薄膜晶体管的源极与数据线200连接，第二薄膜晶体管的漏极与次像素电极500连接，用于为次像素电极500提供数据驱动信号；以及
第三薄膜晶体管TFT_3的源极与第二薄膜晶体管TFT_2的源极，第三薄膜晶体管TFT_3的漏极与公共电极线300连接，用于为次像素电极500上的数据驱动信号的电压。
在其中一个实施例中，在一个像素单元中，第一薄膜晶体管TFT_1的栅极、第二薄膜晶体管TFT_2的栅极和第三薄膜晶体管TFT_3的栅极连接同一条扫描线100，第一薄膜晶体管TFT_1的漏极和第二薄膜晶体管TFT_2的漏 极连接同一条数据线200。
在显示过程中，主像素电极400与公共电极600之间形成主存储电容，次像素电极500与公共电极600之间形成次存储电容。当扫描线100打开时，第一薄膜晶体管TFT_1、第二薄膜晶体管TFT_2和第三薄膜晶体管TFT_3同时打开，数据线200向主像素电极400和次像素电极500充入数据驱动信号。同时，第三薄膜晶体管TFT_3将次像素电极500上的一部分电荷传输至公共电极线300上，使得主存储电容两端的电压大于次存储电容两端的电压，进而使次像素电极500对应区域的亮度低于主像素电极400对应区域的亮度。并且，主像素电极400对应区域与次像素电极500对应区域中液晶分子的偏转角度也不同，从而改善了VA型液晶显示器的大视角色偏现象。
在其中一个实施例中，第一薄膜晶体管TFT_1的源极和漏极之间形成的第一导电沟道为U型，第二薄膜晶体管TFT_2的源极和漏极之间形成的第二导电沟道为U型，第三薄膜晶体管TFT_3的源极和漏极之间形成的第三导电沟道为一字型。具体设计中，可以将第一薄膜晶体管TFT_1的源极和第二薄膜晶体管TFT_2的源极设计为U型，从而实现薄膜晶体管的U型设计，减少第一薄膜晶体管TFT_1和第二薄膜晶体管TFT_2的源极和漏极在沿扫描线100延伸方向上的长度(即减小导电沟道的宽度在沿扫描线100延伸方向上的距离)，以减小布线所需的空间，实现显示面板的窄边框设计。
在其中一个实施例中，第一导电沟道的宽度与长度的比值大于第二导电沟道的宽度与长度的比值。可以理解，薄膜晶体管的特性与导电沟道的宽度与长度的比值有关，导电沟道的宽度与长度的比值越大，薄膜晶体管的性能越好。通过设计第一导电沟道的宽度与长度的比值以及第二导电沟道的宽度与长度的比值，可使次像素电极500对应区域的亮度低于主像素电极400对应区域的亮度，进一步改善VA型液晶显示器的大视角色偏现象。
在其中一个实施例中，阵列基板还包括栅绝缘层700和钝化层800。栅绝缘层700设置在薄膜晶体管的栅极与同层设置的源极和漏极所在层之间， 钝化层800设置在主像素电极和次像素电极所在层与源极和漏极所在层之间。
基于同一发明构思，本申请实施例还提供了一种阵列基板的制作方法，方法包括形成扫描线100、数据线200、公共电极600和公共电极线300的步骤、形成薄膜晶体管的步骤以及形成主像素电极400和次像素电极500的步骤，形成薄膜晶体管包括形成栅极、源极、漏极和有源层的步骤。其中至少两个薄膜晶体管设置在扫描线100的上方，分别与主像素电极400和次像素电极500电连接。主像素电极400和次像素电极500分别设置在扫描线100的两侧，且至少一个像素单元的主像素电极400和与之相邻的像素单元的次像素电极500之间的区域不设置公共电极600。
在其中一个实施例中，公共电极600包括相互垂直的第一公共子电极610和第二公共子电极，且第一公共子电极610与数据线200平行。同一像素单元内，在第一公共子电极610的延伸方向上，第一公共子电极610的远端在沉底基板上投影与主像素电极400的远端在衬底基板900上的投影之间的距离为5～8μm。第一公共子电极610的远端为第一公共子电极610远离扫描线100的一端，主像素电极400的远端为主像素电极400远离扫描线100的一端。
可以理解，本实施例中通过将第一公共子电极610的远端内缩5～8μm，避免产生液晶分子受两重公共电压的现象，从而改善在相邻的两个像素单元的竖直主干422之间的区域产生的液晶分子不良导向问题，进一步提高光透过率和画面显示质量。
以上述3T_8domain像素设计的PSVA型阵列基板为例，阵列基板的制作方法具体以下几个步骤：
步骤一，在衬底基板900上形成公共电极600、公共电极线300、第一薄膜晶体管TFT_1的栅极、第二薄膜晶体的栅极、第三薄膜晶体管TFT_3的栅极和扫描线100。本实施例中，在衬底基板900上形成公共电极600、公共电 极线300、栅极和扫描线100的步骤，包括：在衬底基板900上沉积一层金属薄膜，然后通过第一次构图工艺处理，形成包含扫描线100、栅极、公共电极600和公共电极线300的图形，扫描线100、栅极和公共电极600相隔设置。公共电极600包括相互垂直的第一公共子电极610和第二公共子电极，且第一公共子电极610与数据线200平行。同一像素单元内，在第一公共子电极610的延伸方向上，第一公共子电极610的远端在沉底基板上投影与主像素电极400的远端在衬底基板900上的投影之间的距离为5～8μm。第一公共子电极610的远端为第一公共子电极610远离扫描线100的一端，主像素电极400的远端主像素电极400远离扫描线100的一端。
在本申请中，构图工艺，可只包括光刻工艺，或，包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺。光刻工艺是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本申请中所形成的结构选择相应的构图工艺。
步骤二，在形成公共电极600、公共电极线300、第一薄膜晶体管TFT_1的栅极、第二薄膜晶体管TFT_2的栅极、第三薄膜晶体管TFT_3的栅极和扫描线100的衬底基板900上形成栅绝缘层。本实施例中，在完成步骤一的衬底基板900上沉积氮化硅(SiNx)或氧化硅(SiOx)层，形成栅绝缘层。栅绝缘层中设置有第一通孔，第三薄膜晶体管TFT_3的漏极与公共电极600通过第一通孔实现电连接。
步骤三，在形成栅绝缘层的衬底基板900上形成有源层。本实施例中，通过等离子体增强化学气相沉积法或其他类似方法，在栅绝缘层的上方形成非晶硅薄膜层，然后通过激光退火工艺或固相结晶工艺等工艺过程，使得非晶硅结晶化，形成多晶硅薄膜层，并通过第二次构图工艺处理形成包含低温多晶硅有源层的图形。
步骤四，在形成有源层的衬底基板900上形成数据线200、第一薄膜晶体管TFT_1的源极和漏极、第二薄膜晶体管TFT_2的源极和漏极以及第三薄 膜晶体管TFT_3的源极和漏极。本实施例中，首先沉积源极和漏极、以及数据线200的金属层，采用光阻剂涂胶和掩膜曝光后，再通过刻蚀形成数据线200、源极和漏极的图案。其中刻蚀的方法可以为干法刻蚀或湿法刻蚀，方法不做限定。第一薄膜晶体管TFT_1的源极和漏极之间形成的第一导电沟道为U型，第二薄膜晶体管TFT_2的源极和漏极之间形成的第二导电沟道为U型，第三薄膜晶体管TFT_3的源极和漏极之间形成的第三导电沟道为一字型。
步骤五，在形成数据线200、第一薄膜晶体管TFT_1的源极和漏极、第二薄膜晶体管TFT_2的源极和漏极以及第三薄膜晶体管TFT_3的源极和漏极的衬底基板900上形成钝化层，并形成贯穿钝化层的第二通孔和第三通孔。主像素电极400与第一薄膜晶体管TFT_1的漏极通过第二通孔实现电连接，次像素电极500与第二薄膜晶体管TFT_2的漏极通过第三通孔实现电连接。本实施例中，通过钝化层保护第一薄膜晶体管TFT_1、第二薄膜晶体管TFT_2和第三薄膜晶体管TFT_3，防止第一薄膜晶体管TFT_1、第二薄膜晶体管TFT_2和第三薄膜晶体管TFT_3受到腐蚀。
步骤六，在形成钝化层的衬底基板900上形成主像素电极400和次像素电极500。即，在完成步骤五的衬底基板900上，使用磁控溅射法在钝化层上沉积一层氧化铟锡ITO透明导电薄膜，通过构图工艺，即经涂覆光刻胶并曝光显影后，再进行湿刻、剥离后，形成包括像素电极的图形。通孔中填充有用于形成像素电极的导电材料，像素电极通过通孔与漏极电连接。经过上述步骤，即形成本申请实施例提供的阵列基板。本实施例中，主像素电极400和次像素电极500均包括周边连接部410、多个条状主干以及与主干连接的多个条状像素子电极430。主干包括相互垂直的水平主干421和竖直主干422，水平主干421和竖直主干422将像素单元分成多个显示畴区，像素子电极430位于显示畴区内。
基于同一发明构思，本申请还提供了一种显示装置，显示装置包括上述任一实施例的阵列基板。其中，显示装置可以为：液晶面板、电子纸、OLED 面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
综上，本申请提实施例供了一种阵列基板及其制作方法和显示装置。阵列基板包括衬底基板900以及设置在衬底基板900上的扫描线100、数据线200、公共电极线300以及多个像素单元。像素单元包括薄膜晶体管、主像素电极400、次像素电极500和公共电极600，并且至少一个像素单元的主像素电极400和与之相邻的像素单元的次像素电极500之间的区域不设置公共电极600。本申请中，像素单元的主像素电极400和与之相邻的像素单元的次像素电极500之间的区域不设置公共电极600，因此降低了公共电极600的电压对像素单元的主像素电极400和与之相邻的像素单元的次像素电极500之间的区域的干扰，从而解决了公共电极600引起液晶导向紊乱而产生暗纹的问题，提高了该区域内的透光率和画面显示质量。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (18)

  1. 一种阵列基板，包括衬底基板以及设置在所述衬底基板上的扫描线、数据线、公共电极线以及多个像素单元，所述像素单元包括至少两个薄膜晶体管、主像素电极、次像素电极和公共电极，所述至少两个薄膜晶体管设置在所述扫描线的上方，分别与所述主像素电极和所述次像素电极电连接，所述主像素电极和所述次像素电极分别设置在所述扫描线的两侧，并且所述像素单元的主像素电极和与之相邻的像素单元的次像素电极之间的区域不设置公共电极。
  2. 如权利要求1所述的阵列基板，其中，所述公共电极包括相互垂直的第一公共子电极和第二公共子电极，且所述第一公共子电极与所述数据线平行。
  3. 如权利要求2所述的阵列基板，其中，在同一像素单元内的所述第一公共子电极的延伸方向上，所述第一公共子电极的远端在所述沉底基板上投影与所述主像素电极的远端在所述衬底基板上的投影之间的距离为5～8μm，其中，所述第一公共子电极的远端为所述第一公共子电极远离所述扫描线的一端，所述主像素电极的远端为所述主像素电极远离所述扫描线的一端。
  4. 如权利要求3所述的阵列基板，其中，所述主像素电极和所述次像素电极均包括周边连接部、多个条状主干以及与所述主干连接的多个条状像素子电极，所述主干包括相互垂直的水平主干和竖直主干，所述水平主干和所述竖直主干将所述像素单元分成多个显示畴区，所述像素子电极位于所述显示畴区内。
  5. 如权利要求4所述的阵列基板，其中，所述像素电极的主干覆盖所述公共电极，且所述主像素的竖直主干的远端和与之对应的所述第一公共子电极的远端在所述衬底基板上的投影距离为5～8μm，其中所述主像素的竖直主干的远端为所述主像素的竖直主干远离所述扫描线的一端。
  6. 如权利要求5所述的阵列基板，其中，所述主像素的竖直主干的远端和与之对应的所述第一公共子电极的远端在所述衬底基板上的投影距离为6μm。
  7. 如权利要求1所述的阵列基板，其中，所述像素单元包括第一薄膜晶体管、第二薄膜晶体管和第三薄膜晶体管；
    所述第一薄膜晶体管的源极与所述数据线连接，所述第一薄膜晶体管的漏极与所述主像素电极连接，用于为所述主像素电极提供数据驱动信号；
    所述第二薄膜晶体管的源极与所述数据线连接，所述第二薄膜晶体管的漏极与所述次像素电极连接，用于为所述次像素电极提供数据驱动信号；以及
    所述第三薄膜晶体管的源极与所述第二薄膜晶体管的源极，所述第三薄膜晶体管的漏极与所述公共电极线连接，用于为所述次像素电极上的数据驱动信号的电压。
  8. 如权利要求7所述的阵列基板，其中，在一个所述像素单元中，所述第一薄膜晶体管的栅极、所述第二薄膜晶体管的栅极和所述第三薄膜晶体管的栅极连接同一条扫描线，所述第一薄膜晶体管的漏极和所述第二薄膜晶体管的漏极连接同一条数据线。
  9. 如权利要求7所述的阵列基板，其中，所述第一薄膜晶体管的源极和漏极之间形成的第一导电沟道为U型，所述第二薄膜晶体管的源极和漏极之间形成的第二导电沟道为U型，所述第三薄膜晶体管的源极和漏极之间形成的第三导电沟道为一字型。
  10. 如权利要求9所述的阵列基板，其中，所述第一导电沟道的宽度与长度的比值大于所述第二导电沟道的宽度与长度的比值。
  11. 如权利要求7所述的阵列基板，其中，在显示过程中，所述主像素电极与所述公共电极之间形成主存储电容，所述次像素电极与所述公共电极之间形成次存储电容。
  12. 如权利要求11所述的阵列基板，其中，所述第三薄膜晶体管将所述次像素电极上的一部分电荷传输至所述公共电极线上，使得所述主存储电容两端的电压大于所述次存储电容两端的电压。
  13. 如权利要求1所述的阵列基板，其中，与所述主像素电极对应的区域中的液晶分子的偏转角度不同于与所述次像素电极对应的区域中的液晶分子的偏转角度。
  14. 如权利要求1所述的阵列基板，其中，所述阵列基板还包括栅绝缘层和钝化层，所述栅绝缘层设置在薄膜晶体管的栅极与同层设置的源极和漏极所在层之间，所述钝化层设置在所述主像素电极和所述次像素电极所在层与源极和漏极所在层之间。
  15. 一种阵列基板的制作方法，包括形成扫描线、数据线、公共电极和公共电极线的步骤、形成至少两个薄膜晶体管的步骤以及形成主像素电极和次像素电极的步骤，形成薄膜晶体管包括形成栅极、源极、漏极和有源层的步骤，其中所述至少两个薄膜晶体管设置在所述扫描线的上方，分别与所述主像素电极和所述次像素电极电连接，所述主像素电极和所述次像素电极分别设置在所述扫描线的两侧，且至少一个所述像素单元的主像素电极和与之相邻的像素单元的次像素电极之间的区域不设置公共电极。
  16. 如权利要求15所述的阵列基板的制作方法，其中，所述公共电极包括相互垂直的第一公共子电极和第二公共子电极，且所述第一公共子电极与所述数据线平行。
  17. 如权利要求16所述的阵列基板的制作方法，其中，在所述第一公共子电极的延伸方向上，所述第一公共子电极的远端在所述沉底基板上投影与所述主像素电极的远端在所述衬底基板上的投影之间的距离为5～8μm，其中所述第一公共子电极的远端为所述第一公共子电极远离所述扫描线的一端，所述主像素电极的远端为所述主像素电极远离所述扫描线的一端。
  18. 一种显示装置，所述显示装置包括阵列基板，所述阵列基板包括衬 底基板以及设置在所述衬底基板上的扫描线、数据线、公共电极线以及多个像素单元，所述像素单元包括至少两个薄膜晶体管、主像素电极、次像素电极和公共电极，所述至少两个薄膜晶体管设置在所述扫描线的上方，分别与所述主像素电极和所述次像素电极电连接，所述主像素电极和所述次像素电极分别设置在所述扫描线的两侧，并且所述像素单元的主像素电极和与之相邻的像素单元的次像素电极之间的区域不设置公共电极。
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CN115151859A (zh) * 2020-12-04 2022-10-04 京东方科技集团股份有限公司 阵列基板及显示面板
CN115151859B (zh) * 2020-12-04 2023-10-20 京东方科技集团股份有限公司 阵列基板及显示面板
CN113655649A (zh) * 2021-07-22 2021-11-16 京东方科技集团股份有限公司 显示面板及其制备方法、显示设备、显示系统、显示方法
CN113655649B (zh) * 2021-07-22 2023-10-24 京东方科技集团股份有限公司 显示面板及其制备方法、显示设备、显示系统、显示方法

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