WO2020224480A1 - 一种防止分层窜锡的封装及制造方法 - Google Patents

一种防止分层窜锡的封装及制造方法 Download PDF

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Publication number
WO2020224480A1
WO2020224480A1 PCT/CN2020/087365 CN2020087365W WO2020224480A1 WO 2020224480 A1 WO2020224480 A1 WO 2020224480A1 CN 2020087365 W CN2020087365 W CN 2020087365W WO 2020224480 A1 WO2020224480 A1 WO 2020224480A1
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WIPO (PCT)
Prior art keywords
protrusion
layer
substrate
circuit device
tin
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PCT/CN2020/087365
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English (en)
French (fr)
Inventor
张立
佘勇
叶润清
史洪宾
龙浩晖
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华为技术有限公司
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Publication of WO2020224480A1 publication Critical patent/WO2020224480A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Definitions

  • the invention relates to the technical field of circuit packaging, in particular to a packaging and manufacturing method for preventing delamination of tin channeling.
  • the above problems are solved by selecting EMC models with stronger adhesion to the substrate or PI layer, or EMC models with lower high temperature modulus.
  • the two sides of EMC are the chip PI layer and the substrate, the material The properties are different. If delamination failure occurs on both sides, there is no guarantee that EMC models with increased adhesion to the materials on both sides can be selected.
  • replacing the EMC model not only affects the delamination, but also involves the reliability of the overall package's temperature shock resistance, humidity stress, and temperature stress. While solving the delamination problem, it cannot guarantee that other reliability thresholds will not be reduced.
  • the embodiment of the present invention provides a packaging and manufacturing method for preventing delamination of tin channeling, which can increase the contact area with the plastic compound and reduce the contact area between the plastic compound and the electronic device by providing a protruding structure on the electronic device and/or substrate.
  • the probability of delamination of the contact surface between the substrates increases the difficulty of tin channeling and reduces the risk of short-circuit failure.
  • the first aspect of the present application provides a package that prevents delamination of tin channeling, which includes a substrate, a molding compound, and a circuit device.
  • the molding compound may be epoxy molding compounds (EMC).
  • EMC epoxy molding compounds
  • the circuit device It can be a chip, an inductor, or a capacitor.
  • the circuit device is connected to the substrate through solder joints, and the plastic molding compound is filled and arranged between the circuit device and the substrate.
  • the plastic compound There is a groove adapted to the protrusion.
  • the direction of the protrusion is the protrusion toward the direction of the molding compound. Since the molding compound is filled and arranged between the circuit device and the substrate, the molding compound is provided with a corresponding groove corresponding to each protrusion, thereby realizing the integration of the molding compound and the substrate.
  • the bonding of the circuit device and/or the substrate, as a result, the first contact surface and/or the second contact surface is changed from the horizontal plane in the prior art to a zigzag surface, thereby realizing the connection between the molding compound and the circuit device and/or substrate At the same time, it extends the interface path between two adjacent solder joints.
  • the larger contact area between the molding compound and the circuit device and/or the substrate will reduce the first contact surface and/or the second
  • the peeling stress of the two contact surfaces changes from pure vertical stress to horizontal stress, which increases the difficulty of delamination, thereby reducing the possibility of delamination;
  • the extension of the interface path between two adjacent solder joints Even if delamination occurs, the tin liquid formed by two adjacent melted solder joints needs to go through a longer path to be connected to become a tin bridge, thus reducing the possibility of tin channeling.
  • the first contact surface includes a first bonding layer and a first protruding layer that are integrally arranged, and the first contact surface may be a polyimide resin layer Or a ceramic layer, the first protrusion layer includes at least one first protrusion, wherein one side of the first bonding layer is bonded to the circuit device, and the other side of the first bonding layer is provided with the first protrusion Layer, the at least one first protrusion of the first protrusion layer corresponds to at least one first groove provided on the molding compound one-to-one and is adapted to each other, so as to realize the adhesion of the first contact surface and the molding compound .
  • the improved first contact surface in the embodiment of the present application is a tortuous path, and the contact area is increased.
  • the integrated first bonding layer In the first protruding layer the first bonding layer is bonded to the circuit device, which does not affect the realization of the original function of the first contact surface, but the first protruding layer is added on the basis of the first bonding layer to realize the The first contact surface changes from a horizontal plane to the purpose of a tortuous path.
  • the second contact surface is a green oil layer
  • the green oil layer includes an integrated second bonding layer and a second protruding layer
  • the second protruding layer is Comprising at least one second protrusion, wherein one side of the second bonding layer is bonded to the substrate, the other side of the second bonding layer is provided with the second protrusion layer, and the at least A second protrusion and at least one second groove provided on the plastic compound are in one-to-one correspondence and are adapted to each other, so as to realize the adhesion between the second contact surface and the plastic compound.
  • the improved second contact surface in the embodiment of the present application is a tortuous path, and the contact area is increased.
  • the second bonding layer is integrated
  • the second bonding layer is basically bonded, and does not affect the realization of the original function of the second contact surface, but the second protruding layer is added on the basis of the second bonding layer to realize the The second contact surface changes from a horizontal plane to the purpose of a tortuous path.
  • the shape of the protrusion is any one of a rectangle, an inverted trapezoid, or a triangle.
  • the protrusion in order to increase the contact area between the first contact surface or the second contact surface and the molding compound, can have various shapes.
  • the rectangular structure can effectively increase the contact area while facilitating processing, and the inverted trapezoid can Provide a larger contact area, the triangle can improve the processing efficiency.
  • the circuit device is any one of a chip, a capacitor, or an inductor.
  • chips, capacitors, and inductors are common components in packaging, where the chip may be wafer level chip scale packaging (WLCSP), and the method provided in this embodiment can be applied Circuit devices including chips, capacitors and inductors.
  • WLCSP wafer level chip scale packaging
  • a package for preventing delamination of tin channeling including: a substrate, a molding compound, and a circuit device.
  • the circuit device is connected to the substrate through solder joints, and the molding compound is filled and arranged on the circuit device and the substrate.
  • the two solder joints connecting the circuit device and the substrate the first contact surface of the circuit device and the plastic compound, or the second contact of the substrate and the plastic compound
  • At least one of the contact surfaces is provided with a protrusion
  • the molding compound is provided with a groove adapted to the protrusion.
  • connection interface between the plastic compound and the circuit device and/or substrate is changed from a single parallel interface to a tortuous interface, so that the peeling stress between the plastic compound and the circuit device or substrate is changed from the vertical direction to In the horizontal direction, the contact area increases at the same time, which increases the bonding force, thereby increasing the difficulty of delamination between the plastic compound and the circuit device or substrate; at the same time, the tortuous interface between the plastic compound and the circuit device or substrate increases by two The interface connection path of the side solder joints increases the difficulty of soldering short circuit and reduces the risk of short circuit failure.
  • a second aspect of the present application provides a package manufacturing method for preventing delamination of tin channeling, including: processing the first surface of the circuit device to obtain the first protrusion; and/or processing the second surface of the substrate to obtain the Two protrusions; wherein, the processing can be photolithography, laser engraving, or compression molding; the first surface of the circuit device is welded to the second surface of the substrate by solder joints, wherein any two adjacent welding The first protrusion and/or the second protrusion are arranged between the dots; a plastic molding compound is filled between the circuit device and the substrate to obtain a package that prevents delamination of tin channeling.
  • the surfaces of the circuit device and the substrate facing the molding compound are processed respectively to obtain the first protrusion and the second protrusion structure, and then the circuit device and the substrate are soldered, and the molding compound is filled, so that the molding compound and the circuit device Or the contact surface of the substrate changes from a horizontal plane in the prior art to a curved surface; on the one hand, a larger contact area between the molding compound and the circuit device and/or the substrate reduces the peeling stress of the first surface and/or the second surface
  • the simple vertical stress becomes horizontal stress, which increases the difficulty of delamination, thereby reducing the possibility of delamination; on the other hand, the extension of the interface path between two adjacent solder joints, even if delamination occurs,
  • the tin liquid formed by the two adjacent molten solder joints needs to go through a longer path to be connected to become a tin bridge, thus reducing the possibility of tin channeling.
  • the circuit device is a chip
  • processing on the first surface of the circuit device to obtain the first protrusion includes:
  • the polyimide resin PI layer on the surface is subjected to photolithography to obtain a first protrusion layer, and the first protrusion layer includes at least one first protrusion.
  • the PI layer of polyimide resin is a material covering the surface of the chip, and photolithography is directly performed on the surface of the PI layer. On the one hand, it does not affect the realization of the original function of the PI layer. At the same time, the PI layer is combined with the molding compound. The contact surface has changed from a horizontal plane to a horizontal plane.
  • the method before performing photolithography on the polyimide resin PI layer covering the first surface of the chip, the method further includes : Coating a first PI layer and a second PI layer in sequence on the first surface of the chip; performing photolithography on the polyimide resin PI layer covering the first surface of the chip includes: The second PI layer is subjected to photolithography to obtain the first protruding layer.
  • the first PI layer and the second PI layer are sequentially coated on the surface of the chip, wherein the thickness of the first PI layer and the second PI layer are equal to the thickness of the PI layer in the prior art, wherein the first PI layer
  • the layer is used as the first bonding layer to protect the chip and function as the original PI layer.
  • the second PI layer leaves a plurality of protrusions, thereby forming an integrally arranged on the first PI layer Protruding layer.
  • the circuit device is a capacitor
  • processing on the first surface of the circuit device to obtain the first protrusion includes: on the first surface of the capacitor
  • the ceramic layer is laser engraved to obtain a first protrusion layer, and the first protrusion layer includes at least one first protrusion.
  • the ceramic layer is a contact layer provided on the surface of the capacitor device in contact with the plastic molding compound. Therefore, the surface of the ceramic layer is engraved by laser engraving to obtain the first protrusion layer. Thereby, at least one protrusion is provided on the first surface to increase the contact area between the first surface and the molding compound.
  • the circuit device is an inductor
  • processing the first surface of the circuit device to obtain the first protrusion includes: performing compression molding processing on the inductor , Obtaining a first protruding layer on the first surface of the inductor, the first protruding layer including at least one first protrusion; connecting the side of the first surface without the first protruding layer to the inductor to obtain The inductance of the first protruding layer is provided on the first surface.
  • the inductor is a device made by compression molding. Therefore, in order to obtain the first protruding layer on the surface of the inductor, it is only necessary to improve the mold of the compression mold during the compression molding process, and then directly pass the compression molding process.
  • the inductance device with the first protruding layer on the first surface is obtained by molding.
  • the processing the second surface of the substrate to obtain the second protrusions includes: performing photolithography on the green oil layer covering the second surface of the substrate , A second protrusion layer is obtained, and the second protrusion layer includes at least one second protrusion.
  • the green oil used in the green oil layer is an acrylic oligomer.
  • a protective layer it is coated on the circuit and substrate that do not need to be soldered on the substrate, or used as a solder resist. The purpose is to protect the formed circuit pattern for a long time and directly perform photoetching on the surface of the green oil layer. On the one hand, it does not affect the realization of the original function of the green oil layer, and at the same time, the contact surface between the green oil layer and the molding compound is changed from a horizontal plane to a horizontal plane.
  • the green oil layer covering the second surface of the substrate is subjected to photolithography to obtain the second protrusion layer
  • the method includes: sequentially coating a first green oil layer and a second green oil layer on the second surface of the substrate; performing photolithography on the green oil layer on the second surface of the substrate to obtain a second protruding layer, including: The second green oil layer is subjected to photolithography to obtain the second protruding layer.
  • the first green oil layer and the second green oil layer are sequentially coated on the basic surface, wherein the thickness of the first green oil layer and the second green oil layer are equal to the thickness of the green oil layer in the prior art, wherein the first green oil layer
  • the oil layer is used as the second bonding layer to protect the chip and function as the original green oil layer.
  • the second green oil layer leaves many protrusions, thus forming an integrally arranged on the first green oil layer. Protruding layer.
  • processing the first surface of the circuit device to obtain the first protrusion includes: Processing the first surface of the circuit device to obtain the first protrusion in a rectangular, inverted trapezoidal or triangular shape; processing the second surface of the substrate to obtain the second protrusion includes: processing the second surface of the substrate , To obtain the second protrusion in a rectangular, inverted trapezoidal or triangular shape.
  • the protrusion in order to increase the contact area between the first surface or the second surface and the molding compound, can have various shapes. Among them, the rectangular structure can effectively increase the contact area while facilitating processing, and the inverted trapezoid can provide more The large ground contact area and triangle can improve the processing efficiency. During the processing, the surface of the circuit device or the substrate is processed accordingly to obtain the desired target pattern.
  • a package manufacturing method for preventing delamination of tin delamination which is characterized in that it comprises: processing the first surface of the circuit device to obtain the first protrusion; and/or, the second surface of the substrate The surface is processed to obtain the second protrusion; the first surface of the circuit device is welded to the second surface of the substrate by soldering; the plastic molding compound is filled between the circuit device and the substrate to prevent delamination of tin channeling Package.
  • connection between the substrate and the circuit device is realized by soldering spot welding, and the plastic molding compound is filled between the circuit device and the substrate to prevent delamination
  • the tin-shifting package makes the connection interface between the plastic compound and the circuit device and/or substrate change from a single parallel interface to a tortuous interface.
  • FIG. 1 is a schematic diagram of circuit packaging in the prior art
  • Fig. 2 is a schematic diagram of delamination of tin delamination in circuit packaging in the prior art
  • FIG. 3 is a schematic diagram of the structure of a circuit package in the prior art
  • FIG. 4 is a schematic structural diagram of a package for preventing delamination of tin in an embodiment of the application
  • FIG. 5 is a schematic diagram of the structure of the first contact surface in the package for preventing delamination of tin channeling in an embodiment of the application;
  • FIG. 6 is a schematic diagram of the structure of the second contact surface in the package for preventing delamination of tin channeling in an embodiment of the application;
  • FIG. 7 is a flowchart of a package manufacturing method for preventing delamination of tin in an embodiment of the application.
  • the embodiment of the present invention provides a packaging and manufacturing method for preventing delamination of tin channeling, which can increase the contact area with EMC and reduce the probability of delamination of the molding compound by providing protruding structures on the electronic device and/or substrate , Increase the difficulty of tin channeling short circuit, reduce the risk of short circuit failure.
  • SIP solders circuit devices 100 such as chips 101, capacitors 102, or inductors 103 to a substrate 200 through solder joints 400, and then fills the space between the substrate 200 and the circuit device 100 with a molding compound 300 (epoxy molding compound, EMC) to get the system-in-package SIP.
  • a molding compound 300 epoxy molding compound, EMC
  • the first contact surface where the molding compound 300 is bonded to the circuit device 100, or the second contact surface where the molding compound 300 is bonded to the substrate 200 is often layered during the reflow soldering process. This in turn causes the solder joints 400 on both sides to form a tin-crossing bridge 500 along the layered interface, and eventually short-circuit failure. This type of layered tin-crossing failure is often difficult to completely solve, which becomes an important board-level application of this type of package. One of the challenges.
  • FIG. 3 is a SIP that has not been improved in the prior art, including a substrate 200, a circuit device 100, and a molding compound 300.
  • the substrate 200 and the circuit device 100 are soldered Spot 400 soldering, the molding compound 300 is filled between the substrate 200 and the circuit device 100, and the substrate 200 and the circuit device 100 are packaged together to form a complete SIP, where the molding compound 300 can be epoxy molded Material (epoxy molding compound, EMC), between any two solder joints 400, the contact surface between the plastic compound 300 and the circuit device 100 is the first contact surface, and the contact surface between the plastic compound 300 and the substrate 200 is the second contact surface.
  • EMC epoxy molding compound
  • the substrate 200 and the molding compound 300 can be in contact through the green oil layer 201. Since the first contact surface and the second contact surface are both horizontal, the molding compound 300 and the circuit device 100 are on the first and second contact surfaces. Or the bonding force of the substrate 200 is the stress in the vertical direction. During the reflow soldering process, the circuit device 100 that has been soldered on the substrate 200 may crack on the first contact surface or the second contact surface due to the increase in temperature. Lead to the occurrence of stratified tin channeling.
  • the above problems are solved by selecting EMC models with stronger adhesion to the first and second contact surfaces, or EMC models with lower high temperature modulus.
  • the two contact surfaces are attached to the circuit device 100 and the substrate 200 respectively.
  • the material properties are different. If the delamination failure occurs on both sides, there is no guarantee that the EMC model with increased adhesion to the materials on both sides can be selected.
  • replacing the EMC model not only affects the delamination, but also involves the reliability of the overall package's temperature shock resistance, humidity stress, and temperature stress. While solving the delamination problem, it cannot guarantee that other reliability thresholds will not be reduced.
  • the embodiments of the present application provide a package that prevents delamination of tin flooding, which can provide a protruding structure on the circuit device 100 and/or the substrate 200, so as to increase the contact area with EMC and reduce the occurrence of the molding compound 300.
  • the probability of stratification increases the difficulty of tinning short circuit and reduces the risk of short circuit failure.
  • the package for preventing delamination of tin channeling provided by the embodiment of the present application includes a substrate 200, a molding compound 300, and a circuit device 100.
  • the circuit device 100 is connected to the substrate 200 through solder joints 400.
  • the molding compound 300 is filled and arranged between the circuit device 100 and the substrate 200, wherein, between any two adjacent solder joints 400 connecting the circuit device 100 and the substrate 200:
  • the first contact surface of the circuit device 100 and the molding compound 300, or at least one of the second contact surfaces of the substrate 200 and the molding compound 300 is provided with protrusions, and the molding compound 300 A groove adapted to the protrusion is provided.
  • the direction of the protrusion is a protrusion toward the direction of the molding compound 300. Since the molding compound 300 is filled between the circuit device 100 and the substrate 200, the molding compound 300 is provided with a corresponding groove corresponding to each protrusion.
  • the first contact surface and/or the second contact surface are changed from the horizontal plane in the prior art to the curved surface, thereby realizing the plastic packaging
  • the contact area between the material 300 and the circuit device 100 and/or the substrate 200 is larger, and at the same time, the interface path between the two adjacent solder joints 400 is extended; on the one hand, the molding compound 300 and the circuit device 100 and/or the substrate 200
  • the larger contact area between the first contact surface and/or the second contact surface changes the peeling stress of the first contact surface and/or the second contact surface from pure vertical stress to horizontal stress, which increases the difficulty of delamination and reduces the possibility of delamination;
  • first contact surface and the second contact surface are only added with protrusions on the original basis, and the structure of the first contact surface and the second contact surface itself remains unchanged. For ease of understanding, this situation will be described in detail below in conjunction with the drawings.
  • the first contact surface includes a first bonding layer 110 and a first protruding layer 120 integrally arranged, and the first protruding layer 120 includes at least one first protrusion 121,
  • one side of the first bonding layer 110 is bonded to the circuit device 100, the other side of the first bonding layer 110 is provided with the first protruding layer 120, and the at least one of the first protruding layer 120
  • the first protrusions 121 correspond to at least one first groove provided on the molding compound 300 one-to-one and are adapted to each other, so as to realize the adhesion between the first contact surface and the molding compound 300.
  • the distance between two adjacent solder joints 400 is 100 ⁇ m
  • the first protrusion layer 120 includes two first protrusions 121 with an interval of 20 ⁇ m.
  • the shape of the first protrusions 121 is 20 ⁇ m*20 ⁇ m square, then At this time, the length of the first contact surface becomes 180 ⁇ m.
  • the contact area of the first contact surface improved by the embodiment of the present application is increased by 1.8 times; two solder joints 400 The path is changed from the straight path of the original plan to the tortuous path.
  • the tin channeling path is also increased by 1.8 times of the original plan; at the same time, the overall path needs horizontal stress to peel off, while the original plan only needs vertical interface stress.
  • the peeling increases the difficulty of peeling, which reduces the possibility of delamination between the circuit device 100 and the molding compound 300.
  • the second contact surface is a green oil layer covering the surface of the substrate 200.
  • the green oil layer includes a second bonding layer 210 and a second protruding layer 220 that are integrally arranged on the second protruding layer 220. It includes at least one second protrusion 221, wherein one side of the second bonding layer 210 is bonded to the substrate 200, the other side of the second bonding layer 210 is provided with the second protrusion layer 220, and the second The at least one second protrusion 221 of the protruding layer 220 and the at least one second groove provided on the molding compound 300 are in one-to-one correspondence with each other, so as to realize the adhesion of the second contact surface and the molding compound 300.
  • the second protrusion layer 220 includes two second protrusions 221 with an interval of 20 ⁇ m, and the shape of the second protrusion 221 is a square of 20 ⁇ m*20 ⁇ m, then At this time, the length of the second contact surface becomes 180 ⁇ m.
  • the contact area of the improved second contact surface in the embodiment of the present application is increased by 1.8 times; two solder joints 400 The path is changed from the straight path of the original plan to the tortuous path.
  • the tin channeling path is also increased by 1.8 times of the original plan; at the same time, the overall path needs horizontal stress to peel off, while the original plan only needs vertical interface stress. Peeling increases the difficulty of peeling, which reduces the possibility of delamination between the substrate 200 and the molding compound 300.
  • first protrusion 121 and the second protrusion 221 are not limited in the embodiment of the present application. As an example, the following selects several options for the first protrusion 121 and the second protrusion 221 The shape is explained in detail.
  • first protrusion 121 and the second protrusion 221 when they are rectangular, they can be square or rectangular, wherein one side of the rectangle is attached to the first contact surface or the second contact surface and is integratedly arranged, thereby achieving an increase in the contact area the goal of.
  • first protrusion 121 and the second protrusion 221 are in an inverted trapezoid shape, they include a longer upper bottom, a shorter lower bottom, and two waists of equal length connecting the upper bottom and the lower bottom.
  • the bottom bottom is attached to the first contact surface or the second contact surface and arranged integrally.
  • the inverted trapezoidal protrusion structure can increase more contact area and further increase the difficulty of delamination of the contact surface.
  • first protrusion 121 and the second protrusion 221 are triangular, they include a base and two hypotenuses, wherein the base is attached to the first contact surface or the second contact surface and is integrally arranged, and the triangular structure can be realized
  • the contact area increases, and the processing procedure is simpler than rectangular or inverted trapezoid.
  • first protrusion 121 and the second protrusion 221 may have the same shape or different shapes.
  • first protrusion 121 is rectangular
  • second protrusion 221 is inverted trapezoid, or the first protrusion 121 is triangular.
  • the second protrusion 221 is rectangular; or when there are multiple first protrusions 121 or multiple second protrusions 221, the shape of each first protrusion 121 or second protrusion 221 may also be different. Not limited.
  • circuit device 100 may be any one of a chip 101, a capacitor 102, or an inductor 103, where:
  • the chip 101 may be a wafer level chip scale packaging (WLCSP), wherein the first contact surface of the WLCSP and the plastic packaging material 300 is covered with a poly The imide resin PI layer, the first protrusion layer 120 is a protrusion layer on the PI layer processed by photolithography.
  • WLCSP wafer level chip scale packaging
  • the circuit device 100 is a capacitor 102
  • the first contact surface of the capacitor 102 and the molding compound 300 is covered with a ceramic layer
  • the first protruding layer 120 is a protruding layer processed by laser carving on the ceramic layer.
  • the first protruding layer 120 provided on the first contact surface of the inductor 103 and the plastic molding compound 300 is used in the process of manufacturing the inductor 103 by compression molding.
  • a first protruding layer 120 is provided on the first contact surface of the inductor 103 after molding.
  • circuit device 100 may also be another circuit device 100, which is not limited in the embodiment of the present application.
  • the first protrusion and the second protrusion may be provided on the first contact surface and the second contact surface respectively, or only the protrusions may be provided on the first contact surface. , Or only provide protrusions on the second contact surface.
  • the process of reflow soldering it is found that delamination occurs only on the first contact surface of the circuit device and the plastic compound, and no delamination occurs on the second contact surface of the substrate and the plastic compound. It is only necessary to provide protrusions on the first contact surface, so that while maintaining packaging performance, manufacturing costs can be saved, manufacturing processes can be simplified, and production efficiency can be improved.
  • the specific arrangement of the protrusions on the first contact surface has been disclosed above and will not be repeated here.
  • the package for preventing delamination of tin channeling provided by the embodiments of this application, without changing the EMC model, between any two adjacent solder joints connecting the electronic device and the substrate, through the electronic device and the plastic packaging material
  • the first contact surface, and/or the second contact surface between the substrate and the molding compound is provided with protrusions, thereby changing the connection interface between the molding compound and the circuit device and/or the substrate from a single parallel interface to a tortuous interface, so that the molding compound and The peeling stress between circuit devices or substrates is changed from vertical to horizontal.
  • the contact area increases, which increases the bonding force, thereby increasing the difficulty of delamination between the plastic packaging material and the circuit devices or substrates; at the same time, plastic packaging
  • the tortuous interface between the material and the circuit device or the substrate increases the interface connection path of the solder joints on both sides, thereby increasing the difficulty of tin channeling and reducing the risk of short circuit failure.
  • the embodiment of the present application also provides a package manufacturing method for preventing delamination of tin delamination, which is used to manufacture the package for preventing delamination of tin delamination provided by the embodiment of this application.
  • a package manufacturing method for preventing delamination of tin delamination which is used to manufacture the package for preventing delamination of tin delamination provided by the embodiment of this application.
  • the package manufacturing method for preventing delamination of tin delamination includes the following steps:
  • the first surface is the contact surface between the circuit device and the plastic molding compound.
  • different processing methods are used on the first surface to obtain the first protrusion. The following is for different circuit devices The processing method of the first protrusion on the type will be described in detail.
  • the chip may be a wafer level chip scale packaging (WLCSP), which includes the following steps:
  • the first surface of the chip is sequentially coated with a first polyimide resin PI layer and a second polyimide resin PI layer.
  • the function of arranging the PI layer on the chip surface includes: 1. Preventing package cracking caused by shrinkage of the packaging material and thermal shock during surface bonding; 2. Avoiding the non-polar silicon dioxide passivation film on the chip surface Cracks; 3. As an interlayer insulating layer between the chip and the substrate. Setting the first protrusion on the PI layer does not affect the structure of the chip itself, and at the same time can increase the contact area between the chip and the plastic molding compound.
  • Photolithography is performed on the second PI layer to obtain the first protrusion layer.
  • the first protrusion layer includes at least one first protrusion; wherein, a first PI layer and a second PI layer are sequentially coated on the first surface, and the second PI layer disposed on the outside is only lithographically aligned.
  • the layer is processed to obtain the first protruding layer, so that the first PI layer is used as the first bonding layer to be bonded to the circuit device, and plays the original role of the PI layer.
  • the second PI layer subjected to photolithography is disposed on the first PI layer as a protrusion layer, so that the first protrusion layer is disposed on the PI layer.
  • the above method can also be directly coating the first surface of the chip with a PI layer twice the thickness of the prior art, and then performing photolithography on the PI layer to obtain the first protrusion layer.
  • a protrusion layer includes at least one first protrusion.
  • the circuit device is a capacitor
  • the ceramic layer is directly laser-engraved, and the ceramic layer on the first surface is etched by laser-engraving, so as to be on the outside of the ceramic layer.
  • a first protrusion layer is obtained on the surface, and the first protrusion layer includes at least one first protrusion.
  • the circuit device is an inductor
  • the processing technology of the inductor is made by compression molding, it is only necessary to modify the mold before the compression mold, and to provide a second protruding layer on the first surface of the mold.
  • the concave layer is lowered, and then the mold is used for compression molding to obtain an inductor with a first protrusion layer on the first surface, and the first protrusion layer includes at least one first protrusion.
  • the first protrusion and the second protrusion may be provided on the first contact surface and the second contact surface, respectively, or only the protrusion may be provided on the first contact surface, or only the protrusion may be provided on the second contact surface.
  • the process of reflow soldering it is found that delamination occurs only on the first contact surface of the circuit device and the plastic compound, and no delamination occurs on the second contact surface of the substrate and the plastic compound. It is only necessary to provide protrusions on the first contact surface, so that while maintaining packaging performance, manufacturing costs can be saved, manufacturing processes can be simplified, and production efficiency can be improved. Therefore, both steps 701 and 702 can be performed, or only one of them can be performed.
  • step 702 the following steps may be specifically included:
  • a first green oil layer and a second green oil layer are sequentially coated on the second surface of the substrate.
  • the second surface is the surface where the substrate and the molding compound are in contact
  • the green oil used in the green oil layer is a liquid photoresist, which is an acrylic oligomer.
  • a protective layer it is coated on the circuit and substrate that do not need to be soldered on the substrate, or used as a solder resist. The purpose is to protect the formed circuit pattern for a long time.
  • by providing protrusions on the green oil layer the contact area between the green oil layer and the molding compound is increased, thereby preventing the substrate and the molding compound from delamination during the reflow soldering process.
  • Photolithography is performed on the second green oil layer to obtain a second protrusion layer.
  • the second protrusion layer includes at least one second protrusion, wherein a first green oil layer and a second green oil layer are sequentially coated on the second surface, and the second green oil layer disposed on the outside is only aligned by photolithography.
  • the second protruding layer is obtained by processing, so that the first green oil layer is attached to the substrate as the second bonding layer, and plays the original role of the green oil layer.
  • the second green oil layer subjected to photoetching is provided as a protrusion layer on the first green oil layer, thereby realizing that the second protrusion layer is provided on the green oil layer.
  • the above method can also be directly coating the second surface of the substrate with a green oil layer twice the thickness of the prior art, and then performing photolithography on the green oil layer to obtain the second protruding layer.
  • the two protrusion layers include at least one second protrusion.
  • solder paste can be placed between the circuit device and the substrate, and then the solder paste can be soldered to obtain solder joints for connecting the circuit device and the substrate, where any two adjacent solder joints The first protrusion and/or the second protrusion are provided, so as to prevent the delamination between the adjacent solder joints.
  • the molding compound can be an epoxy resin molding material EMC.
  • the EMC is initially liquid.
  • the liquid EMC is filled between the circuit device and the substrate.
  • the liquid EMC is bonded to the circuit device and the substrate.
  • the solid EMC will form a groove that matches the first protrusion and/or the second protrusion.
  • the first surface is the first contact surface of the circuit device and the molding compound, and the second surface That is, it is the second contact surface where the substrate and the plastic molding compound are in contact, so that the plastic molding compound is bonded to the circuit device and the substrate through the first contact surface and the second contact surface.
  • first protrusion and the second protrusion are not limited in the embodiment of the present application.
  • first protrusion and the second protrusion may be any of rectangular, inverted trapezoid, or triangular.
  • shape of the first protrusion and the second protrusion may be different, or when there are multiple first protrusions or multiple second protrusions, the shape of each first protrusion or second protrusion may also be different. This application is not limited.
  • protrusions with different shapes can be obtained.
  • specific processing steps please refer to the content disclosed above, and the embodiments of this application will not be repeated.
  • the chips mentioned in the embodiments of the present application may include a central processing unit (Central Processing Unit, CPU), and may also include other general-purpose processors, digital signal processors (Digital Signal Processor, DSP), and application specific integrated circuits (Application Specific Integrated Circuits). Specific Integrated Circuit, ASIC), ready-made programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • the general-purpose processor may be a microprocessor or the processor may also be any conventional processor or the like.
  • the package disclosed may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the circuits is only a logical function division, and there may be other divisions in actual implementation, for example, multiple circuits or components may be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or circuits, and may be in electrical, mechanical or other forms.
  • circuit devices described as separate components may or may not be physically separated, and the components displayed as circuits may or may not be physical circuits, that is, they may be located in one place, or they may be distributed on multiple network circuits. . Some or all of the circuits may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the size of the sequence number of the above-mentioned processes does not mean the order of execution. Some or all of the steps can be executed in parallel or one after the other, and the execution order of the processes should be based on their functions and The internal logic is determined, and should not constitute any limitation to the implementation process of the embodiments of the present application.
  • each device embodiment is used to execute the circuit provided by the corresponding circuit embodiment, so each device embodiment can refer to the correlation in the related circuit embodiment Part of understanding.
  • the device structure diagrams given in the device embodiments of this application only show the simplified design of the corresponding device.
  • the device may include any number of transmitters, receivers, processors, memories, etc., to implement the functions or operations performed by the device in the device embodiments of the present application, and all devices that can implement the present application All are within the protection scope of this application.

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Abstract

本申请公开了一种防止分层窜锡的封装，可用于电路封装中，例如晶圆片级芯片规模封装，包括：通过焊点焊接的基板和电路器件，以及填充在二者之间的塑封料，在连接电路器件与基板的任意两个相邻的焊点之间：该电路器件与该塑封料贴合的第一接触面，或者，该基板与该塑封料贴合的第二接触面中的至少一个接触面上设置有突起，该塑封料上设置有与该突起适配的凹槽；本申请还提供一种防止分层窜锡的封装制造方法，用于制造该防止分层窜锡的封装，通过在电子器件和/或基板上设置突起的结构，增大与塑封料的接触面积，降低塑封料与电子器件或基板的接触面在回流焊过程中发生分层的概率，增加窜锡短路的难度，降低短路失效风险。

Description

一种防止分层窜锡的封装及制造方法
本申请要求在2019年5月8日提交中国国家知识产权局、申请号为201910380538.2的中国专利申请的优先权，发明名称为“一种防止分层窜锡的封装及制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及电路封装技术领域，具体涉及一种防止分层窜锡的封装及制造方法。
背景技术
随着5G的到来，手机等便携式电子产品的功能愈发集成，在有限的单板面积上需要添加更多的功能模块。而系统级封装(system in package,SIP)作为小型化发展的一种重要技术手段成为当今解决单板尺寸瓶颈的一个重要发展方向。但是SIP封装内塑封料(epoxy molding compounds,EMC)与基板，或者，塑封料与芯片的聚酰亚胺树脂层(polyimide,PI)之间常常在回流焊的过程中分层，进而导致两侧焊点沿分层界面形成窜锡导通，最终短路失效，这类分层窜锡失效往往难以完全解决，从而成为此类封装板级应用的重要挑战之一。
现有技术中，通过选用与基板或PI层粘结力更强的EMC型号，或高温模量更低的EMC型号来解决上述问题，然而，由于EMC两侧分别为芯片PI层及基板，材料性质不同，如果两侧均发生分层窜锡失效，不能保证一定能选取到与两侧材料粘结力均增加的EMC型号。同时更换EMC型号除影响分层之外，还会涉及整体封装的抗温度冲击能力、湿度应力及温度应力等可靠性，在解决分层问题的同时不能保证其他可靠性阈度不会发生降低。
因此，现有技术中所存在的上述问题还有待于改进。
发明内容
本发明实施例提供一种防止分层窜锡的封装及制造方法，能够通过在电子器件和/或基板上设置突起结构，从而实现增大与塑封料的接触面积，降低塑封料与电子器件或基板间的接触面发生分层的概率，增加窜锡短路的难度，降低短路失效风险。
有鉴于此，本申请第一方面提供一种防止分层窜锡的封装，包括基板、塑封料及电路器件，该塑封料可以是环氧树脂模塑材料(epoxy molding compounds，EMC)，该电路器件可以是芯片、电感或电容，该电路器件通过焊点与该基板连接，该塑封料填充设置在该电路器件与该基板之间，其中，针对连接该电路器件与该基板的任意两个相邻的焊点之间：该电路器件与该塑封料贴合的第一接触面，或者，该基板与该塑封料贴合的第二接触面中的至少一个接触面上设置有突起，该塑封料上设置有与该突起适配的凹槽。
本实施例，该突起方向为朝向塑封料方向的突起，由于塑封料填充设置在电路器件和基板之间，因此，塑封料上对应与每个突起设置有对应的凹槽，从而实现塑封料与电路器件和/或基板的贴合，由此，第一接触面和/或第二接触面由现有技术中的水平面变成了曲折面，从而实现了塑封料与电路器件和/或基板之间更大的接触面积，同时，延长了两个相邻焊点间的界面路径；一方面，塑封料与电路器件和/或基板之间更大的接触面积将第一接触面和/或第二接触面的剥离应力由单纯的垂直应力变为水平方向的应力，提高了分层的难度，从而降低分层发生的可能性；另一方面，两个相邻焊点间界面路径的延长，即使发生了分层，相邻两个融化的焊点形成的锡液需要经过更长得到路径才能导通成为锡桥，因而 也降低了窜锡发生的可能性。
结合上述第一方面，在第一种可能的实现方式中，该第一接触面包括一体化设置的第一贴合层和第一突起层，该第一接触面可以是聚酰亚胺树脂层或陶瓷层，该第一突起层包括至少一个第一突起，其中，该第一贴合层的一侧与该电路器件贴合，该第一贴合层的另一侧设置有该第一突起层，该第一突起层的该至少一个第一突起与设置在该塑封料上的至少一个第一凹槽一一对应且相互适配，以实现该第一接触面与该塑封料的贴合。
本实施例中，相较于现有技术中水平面结构的第一接触面，本申请实施例改进后的第一接触面为曲折路径，接触面积增加，同时，一体化设置的第一贴合层和第一突起层中，第一贴合层与电路器件贴合，并不影响第一接触面原有功能的实现，只是在第一贴合层的基础上增加第一突起层，实现了将第一接触面由水平面变为曲折路径的目的。
结合上述第一方面，在第二种可能的实现方式中，该第二接触面为绿油层，该绿油层包括一体化设置的第二贴合层和第二突起层，该第二突起层上包括至少一个第二突起，其中，该第二贴合层的一侧与该基板贴合，该第二贴合层的另一侧设置有该第二突起层，该第二突起层的该至少一个第二突起与设置在该塑封料上的至少一个第二凹槽一一对应且相互适配，以实现该第二接触面与该塑封料的贴合。
本实施例中，相较于现有技术中水平面结构的第二接触面，本申请实施例改进后的第二接触面为曲折路径，接触面积增加，同时，一体化设置的第二贴合层和第二突起层中，第二贴合层与基本贴合，并不影响第二接触面原有功能的实现，只是在第二贴合层的基础上增加第二突起层，实现了将第二接触面由水平面变为曲折路径的目的。
结合上述第一方面或第一方面第一及第二种可能的实现方式，在第三种可能的实现方式中，该突起的形状为矩形、倒梯形或三角形中的任意一种。
本实施例中，为了增加第一接触面或第二接触面与塑封料的接触面积，该突起可以为各种形状，其中，矩形结构能够在方便加工的同时有效增大接触面积，倒梯形能够提供更大地接触面积，三角形能够提升加工效率。
结合上述第一方面或第一方面第一至第三种可能的实现方式，在第四种可能的实现方式中，该电路器件为芯片、电容或电感中的任意一种。
本实施例中，芯片、电容及电感皆为封装中的常用器件，其中，该芯片可以为晶圆片级芯片规模封装(wafer Level chip scale packaging，WLCSP)，本实施例所提供的方法能够适用包括芯片、电容及电感在内的电路器件。
从以上技术方案可以看出，本申请实施例具有以下优点：
本发明实施例中，提供了一种防止分层窜锡的封装，包括：基板、塑封料及电路器件，该电路器件通过焊点与该基板连接，该塑封料填充设置在该电路器件与该基板之间，其中，针对该电路器件与该基板连接的两个焊点之间：该电路器件与该塑封料贴合的第一接触面，或者，该基板与该塑封料贴合的第二接触面中的至少一个接触面上设置有突起，该塑封料上设置有与该突起适配的凹槽。从而在两个焊点之间，将塑封料与电路器件和/或基板的连接界面由单一平行界面改为曲折界面，从而使得塑封料与电路器件或基板之间的剥离应力由垂直方向改为水平方向，同时接触面积增加，增大了结合力，从而增大了塑封料与电路器件或基板之间发生分层的难度；同时，塑封料与电路器件或基板之间的曲折界面增加了 两侧焊点的界面连接路径，从而增加窜锡短路的难度，降低短路失效风险。
本申请第二方面提供一种防止分层窜锡的封装制造方法，包括：对电路器件的第一表面进行加工，得到第一突起；和/或，对基板的第二表面进行加工，得到第二突起；其中，该加工可以为光刻、镭雕或压模；将该电路器件的该第一表面相对该基板的该第二表面通过焊点焊接，其中，任意两个相邻的该焊点之间设置有该第一突起和/或该第二突起；在该电路器件与该基板之间填充塑封料，得到防止分层窜锡的封装。
本实施例中，分别在电路器件和基板面对塑封料的表面进行加工，得到第一突起和第二突起结构，之后将电路器件和基板焊接，并填充塑封料，从而使得塑封料与电路器件或基板的接触面由现有技术中的水平面变为曲面，；一方面，塑封料与电路器件和/或基板之间更大的接触面积将第一表面和/或第二表面的剥离应力由单纯的垂直应力变为水平方向的应力，提高了分层的难度，从而降低分层发生的可能性；另一方面，两个相邻焊点间界面路径的延长，即使发生了分层，相邻两个融化的焊点形成的锡液需要经过更长得到路径才能导通成为锡桥，因而也降低了窜锡发生的可能性。
结合上述第二方面，在第一种可能的实现方式中，该电路器件为芯片，则该在电路器件的第一表面进行加工，以得到第一突起，包括：对覆盖在该芯片的第一表面上的聚酰亚胺树脂PI层进行光刻，得到第一突起层，该第一突起层上包括至少一个该第一突起。
本实施例中，聚酰亚胺树脂PI层为覆盖在芯片表面的材料，直接在PI层的表面进行光刻，一方面不影响PI层原有功能的实现，同时，将PI层与塑封料的接触面由水平面变成了水平面。
结合上述第二方面第一种可能的实现方式中，在第二种可能的实现方式中，该对覆盖在该芯片的第一表面上的聚酰亚胺树脂PI层进行光刻之前，还包括：在该芯片的该第一表面上依次涂覆第一PI层和第二PI层；该对覆盖在该芯片的第一表面上的聚酰亚胺树脂PI层进行光刻，包括：对该第二PI层进行光刻，得到该第一突起层。
本实施例中，在芯片的表面依次涂覆第一PI层和第二PI层，其中第一PI层和第二PI层的厚度均等于现有技术中PI层的厚度，其中，第一PI层作为第一贴合层，起到保护芯片的作用，起到原有PI层的功能，第二PI层经过光刻后留下多个突起，从而形成一体化设置在第一PI层上的突起层。
结合上述第二方面，在第三种可能的实现方式中，该电路器件为电容，则该在电路器件的第一表面进行加工，以得到第一突起，包括：对该电容的第一表面上的陶瓷层进行镭雕，得到第一突起层，该第一突起层上包括至少一个该第一突起。
本实施例中，陶瓷层为设置在电容器件表面与塑封料接触的接触层，因此，通过镭雕的方式在陶瓷层的表面进行雕刻，以得到第一突起层。从而使得第一表面上具有至少一个突起，以增大第一表面与塑封料的接触面积。
结合上述第二方面，在第四种可能的实现方式中，该电路器件为电感，则该在电路器件的第一表面进行加工，以得到第一突起，包括：通过对该电感进行压模处理，在该电感的第一表面上得到第一突起层，该第一突起层上包括至少一个该第一突起；将该第一表面不设置有该第一突起层的一面与该电感连接，得到第一表面上设置有第一突起层的该电感。
本实施例中，电感为通过压模制成的器件，因此为了在电感的表面上得到第一突起层， 只需要在压模的过程中，对压模的模具进行改进，即可直接通过压模得到第一表面上具有第一突起层的电感器件。
结合上述第二方面，在第五种可能的实现方式中，该对基板的第二表面进行加工，得到第二突起，包括：对覆盖设置在该基板的该第二表面的绿油层进行光刻，得到第二突起层，该第二突起层上包括至少一个该第二突起。
本实施例中，该绿油层所使用的绿油即液态光致阻焊剂，是一种丙烯酸低聚物。作为一种保护层，涂覆在基板上不需焊接的线路和基材上，或用作阻焊剂。目的是长期保护所形成的线路图形，直接在绿油层的表面进行光刻，一方面不影响绿油层原有功能的实现，同时，将绿油层与塑封料的接触面由水平面变成了水平面。
结合上述第二方面第五种可能的实现方式，在第六种可能的实现方式中，该对覆盖设置在该基板的该第二表面的绿油层进行光刻，得到第二突起层之前，还包括：在该基板的该第二表面依次涂覆第一绿油层和第二绿油层；该对该基板的该第二表面的绿油层进行光刻，得到第二突起层，包括：对该第二绿油层进行光刻，得到该第二突起层。
本实施例中，在基本的表面依次涂覆第一绿油层和第二绿油层，其中第一绿油层和第二绿油层的厚度均等于现有技术中绿油层的厚度，其中，第一绿油层作为第二贴合层，起到保护芯片的作用，起到原有绿油层的功能，第二绿油层经过光刻后留下多个突起，从而形成一体化设置在第一绿油层上的突起层。
结合上述第一方面及第一方面第一至第六任意一种可能的实现方式，在第七中可能的实现方式中，该对电路器件的第一表面进行加工，得到第一突起，包括：对该电路器件的第一表面进行加工，得到矩形、倒梯形或三角形的该第一突起；该对基板的第二表面进行加工，得到第二突起，包括：对该基板的第二表面进行加工，得到矩形、倒梯形或三角形的该第二突起。
本实施例中，为了增加第一表面或第二表面与塑封料的接触面积，该突起可以为各种形状，其中，矩形结构能够在方便加工的同时有效增大接触面积，倒梯形能够提供更大地接触面积，三角形能够提升加工效率，在加工的过程中对电路器件或基板的表面进行相应的加工，以获得需要制得的目标图形。
从以上技术方案可以看出，本申请实施例具有以下优点：
本发明实施例中，提供了一种防止分层窜锡的封装制造方法，其特征在于，包括：对电路器件的第一表面进行加工，得到第一突起；和/或，对基板的第二表面进行加工，得到第二突起；将该电路器件的该第一表面相对该基板的该第二表面通过焊点焊接；在该电路器件与该基板之间填充塑封料，得到防止分层窜锡的封装。通过光刻的方式，在电路器件和/或基板的表面加工出突起，之后通过焊点焊接实现基板与电路器件的连接，在该电路器件与该基板之间填充塑封料，制得防止分层窜锡的封装，从而使得塑封料与电路器件和/或基板的连接界面由单一平行界面变为曲折界面。
附图说明
图1为现有技术中电路封装的示意图；
图2为现有技术中电路封装发生分层窜锡的示意图；
图3为现有技术中电路封装的结构示意图；
图4为本申请实施例中防止分层窜锡的封装的结构示意图；
图5为本申请实施例中防止分层窜锡的封装中第一接触面的结构示意图；
图6为本申请实施例中防止分层窜锡的封装中第二接触面的结构示意图；
图7为本申请实施例中防止分层窜锡的封装制造方法的流程图。
具体实施方式
本发明实施例提供一种防止分层窜锡的封装及制造方法，能够通过在电子器件和/或基板上设置突起结构，从而实现增大与EMC的接触面积，降低塑封料发生分层的概率，增加窜锡短路的难度，降低短路失效风险。
为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本申请保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
随着电子技术的发展，智能终端，例如手机、平板电脑等电子产品的功能愈发集成，在有限的单板面积上需要添加更多的功能模块。而系统级封装(system in package,SIP)作为小型化发展的一种重要技术手段成为当今解决单板尺寸瓶颈的一个重要发展方向。
如图1所示，SIP通过焊点400将电路器件100，例如芯片101、电容102或电感103焊接在基板200上，之后在基板200和电路器件100之间填充塑封料300(epoxy molding compounds,EMC)，以得到系统级封装SIP。
在实际过程中，如图2所示，塑封料300与电路器件100贴合的第一接触面，或者，塑封料300与基板200贴合的第二接触面常常在回流焊的过程中分层，进而导致两侧焊点400沿分层界面形成窜锡导通的窜锡锡桥500，最终短路失效，这类分层窜锡失效往往难以完全解决，从而成为此类封装板级应用的重要挑战之一。
具体结构请参阅图3，如图3所示，图3为现有技术中未进行改进的SIP，包括基板200、电路器件100及塑封料300，其中，基板200和电路器件100之间通过焊点400焊接，该塑封料300填充在基板200和电路器件100之间，同时将基板200和电路器件100封装在一起，构成一个完整的SIP，其中，该塑封料300可以为环氧树脂模塑材料(epoxy molding compounds，EMC)，在任意两个焊点400之间，塑封料300与电路器件100的接触面为第一接触面，塑封料300与基板200的接触面为第二接触面，其中，基板200与塑封料300之间可以通过绿油层201接触，由于第一接触面与第二接触面均为水平面，在第一接触面和第二接触面上，塑封料300与电 路器件100或基板200的结合力为垂直方向上的应力，在回流焊的过程中，已经焊接在基板200上的电路器件100由于温度的升高，第一接触面或第二接触面上会发生开裂，导致分层窜锡现象的发生。
当前，通过选用与第一接触面和第二接触面粘结力更强的EMC型号，或高温模量更低的EMC型号来解决上述问题，然而，由于EMC两侧的第一接触面和第二接触面所贴合的分别为电路器件100及基板200，材料性质不同，如果两侧均发生分层窜锡失效，不能保证一定能选取到与两侧材料粘结力均增加的EMC型号。同时更换EMC型号除影响分层之外，还会涉及整体封装的抗温度冲击能力、湿度应力及温度应力等可靠性，在解决分层问题的同时不能保证其他可靠性阈度不会发生降低。
为了解决上述问题，本申请实施例提供一种防止分层窜锡的封装，能够在电路器件100和/或基板200上设置突起结构，从而实现增大与EMC的接触面积，降低塑封料300发生分层的概率，增加窜锡短路的难度，降低短路失效风险。为便于理解，以下结合附图对本申请实施例做具体说明。
请参阅图4，如图4所示，本申请实施例所提供的防止分层窜锡的封装，包括基板200、塑封料300及电路器件100，该电路器件100通过焊点400与该基板200连接，该塑封料300填充设置在该电路器件100与该基板200之间，其中，在连接该电路器件100与该基板200的任意两个相邻的焊点400之间：
该电路器件100与该塑封料300贴合的第一接触面，或者，该基板200与该塑封料300贴合的第二接触面中的至少一个接触面上设置有突起，该塑封料300上设置有与该突起适配的凹槽。
本实施例中，该突起方向为朝向塑封料300方向的突起，由于塑封料300填充设置在电路器件100和基板200之间，因此，塑封料300上对应与每个突起设置有对应的凹槽，从而实现塑封料300与电路器件100和/或基板200的贴合，由此，第一接触面和/或第二接触面由现有技术中的水平面变成了曲折面，从而实现了塑封料300与电路器件100和/或基板200之间更大的接触面积，同时，延长了两个相邻焊点400间的界面路径；一方面，塑封料300与电路器件100和/或基板200之间更大的接触面积将第一接触面和/或第二接触面的剥离应力由单纯的垂直应力变为水平方向的应力，提高了分层的难度，从而降低分层发生的可能性；另一方面，两个相邻焊点400间界面路径的延长，即使发生了分层，相邻两个融化的焊点400形成的锡液需要经过更长得到路径才能导通成为锡桥，因而也降低了窜锡发生的可能性。
需要说明的是，为了维护封装结构工作的稳定性，第一接触面和第二接触面仅仅是在原有的基础上增加了突起，第一接触面和第二接触面本身的结构不发生改变，为便于理解，以下结合附图对本种情况做具体说明。
请参阅图5及图6，如图5所示，第一接触面包括一体化设置的第一贴合层110和第一突起层120，该第一突起层120包括至少一个第一突起121，其中，该第一贴合层110的一侧与该电路器件100贴合，该第一贴合层110的另一侧设置有该第一突起层120，该第一突起层120的该至少一个第一突起121与设置在该塑封料300上的至少一个第一凹槽一一对应且相互适配，以实现该第一接触面与该塑封料300的贴合。
本实施例中，假设相邻的两个焊点400间隔距离为100μm，第一突起层120包括两个间 隔20μm的第一突起121，该第一突起121的形状为20μm*20μm的正方形，则此时第一接触面的长度变为180μm，相较于现有技术中水平面结构的第一接触面，本申请实施例改进后的第一接触面的接触面积增加了1.8倍；两焊点400路径由原方案的直线路径改为曲折路径，仍以上例对比，则窜锡路径也增长为原方案1.8倍；同时整体路径需要水平方向的应力才能剥离，而原方案仅需要垂直界面应力即可剥离，剥离难度增加，降低了电路器件100与塑封料300之间发生分层的可能性。
如图6所示，第二接触面为覆盖设置在基板200表面上的绿油层，该绿油层包括一体化设置的第二贴合层210和第二突起层220，该第二突起层220上包括至少一个第二突起221，其中，该第二贴合层210的一侧与该基板200贴合，该第二贴合层210的另一侧设置有该第二突起层220，该第二突起层220的该至少一个第二突起221与设置在该塑封料300上的至少一个第二凹槽一一对应且相互适配，以实现该第二接触面与该塑封料300的贴合。
本实施例中，假设相邻的两个焊点400间隔距离为100μm，第二突起层220包括两个间隔20μm的第二突起221，该第二突起221的形状为20μm*20μm的正方形，则此时第二接触面的长度变为180μm，相较于现有技术中水平面结构的第二接触面，本申请实施例改进后的第二接触面的接触面积增加了1.8倍；两焊点400路径由原方案的直线路径改为曲折路径，仍以上例对比，则窜锡路径也增长为原方案1.8倍；同时整体路径需要水平方向的应力才能剥离，而原方案仅需要垂直界面应力即可剥离，剥离难度增加，降低了基板200与塑封料300之间发生分层的可能性。
需要说明的是，对于上述第一突起121和第二突起221的具体形状，本申请实施例并不进行限定，作为一种举例，以下对第一突起121和第二突起221的几种可选的形状进行详细说明。
矩形，第一突起121和第二突起221为矩形时，可以为正方形，或长方形，其中，该矩形的一个边与第一接触面或第二接触面贴合并一体化设置，从而实现增加接触面积的目的。
倒梯形，第一突起121和第二突起221为倒梯形时，包括一条较长的上底、一条较短的下底以及连接该上底和下底的两条长度相等的腰，其中，该下底与第一接触面或第二接触面贴合并一体化设置，倒梯形的突起结构能够增加更多的接触面积，同时进一步增加接触面发生分层的难度。
三角形，第一突起121和第二突起221为三角形时，包括一条底边和两条斜边，其中，该底边与第一接触面或第二接触面贴合并一体化设置，三角形结构能够实现接触面积的增加，同时加工程序较矩形或倒梯形而言更加简单。
需要说明的是，第一突起121与第二突起221可以是相同的形状，也可以为不同的形状，例如第一突起121为矩形，第二突起221为倒梯形，或者第一突起121为三角形，第二突起221为矩形；或者当具有多个第一突起121或多个第二突起221时，每个第一突起121或第二突起221的形状也可以不同，对此本申请实施例并不进行限定。
需要进一步说明的是，上述电路器件100可以为芯片101、电容102或电感103中的任意一种，其中，
当电路器件100为芯片101时，该芯片101可以是晶圆片级芯片规模封装(wafer Level chip scale packaging，WLCSP)，其中，该WLCSP与塑封料300接触的第一接触面上覆盖设 置有聚酰亚胺树脂PI层，上述第一突起层120为通过光刻加工所述PI层上的突起层。
当电路器件100为电容102时，该电容102与塑封料300接触的第一接触面上覆盖设置有陶瓷层，上述第一突起层120为通过镭雕加工在所述陶瓷层上的突起层。
当电路器件100为电感103时，该电感103与塑封料300接触的第一接触面上设置的第一突起层120，是在压模制造电感103的过程中，通过对模具进行改进，使得压模后制得的电感103第一接触面上设置有第一突起层120。
需要说明的是，上述电路器件100还可以是其他的电路器件100，对此本申请实施例并不进行限定。
可选地，在上述实施例中，根据具体使用需求的不同，可以在第一接触面和第二接触面上分别设置第一突起和第二突起，也可以仅在第一接触面上设置突起，或者仅在第二接触面上设置突起。例如，在回流焊的过程中发现，只有电路器件与塑封料接触的第一接触面上会发生分层现象，基板与塑封料接触的第二接触面上不发生分层，因此，只需在第一接触面上设置突起即可，从而可以在保持封装性能的同时，节省制造成本，简化制造工艺，从而提升生产的效率。在第一接触面上设置突起的具体设置方式上述公开的内容，此处不再赘述。
本申请实施例所提供的防止分层窜锡的封装，在不更换EMC型号的前提下，在电子器件与基板连接的任意两个相邻的焊点之间，通过在电子器件与塑封料的第一接触面，和/或，基板与塑封料的第二接触面上设置突起，从而将塑封料与电路器件和/或基板的连接界面由单一平行界面改为曲折界面，从而使得塑封料与电路器件或基板之间的剥离应力由垂直方向改为水平方向，同时接触面积增加，增大了结合力，从而增大了塑封料与电路器件或基板之间发生分层的难度；同时，塑封料与电路器件或基板之间的曲折界面增加了两侧焊点的界面连接路径，从而增加窜锡短路的难度，降低短路失效风险。
本申请实施例还提供一种防止分层窜锡的封装制造方法，用于制造本申请实施例所提供的防止分层窜锡的封装，为便于理解，以下结合说明书附图，对该方法进行详细说明。
请参阅图7，如图7所示，本申请实施例所提供的防止分层窜锡的封装制造方法包括以下步骤：
701、对电路器件的第一表面进行加工，得到第一突起。
本实施例中，该第一表面为电路器件与塑封料接触的表面，其中，根据电路器件类型的不同，对第一表面采用不同的加工方式，以得到该第一突起，以下针对不同电路器件类型上第一突起的加工方式进行详细说明。
当电路器件为芯片时，该芯片可以是晶圆片级芯片规模封装(wafer Level chip scale packaging，WLCSP)，包括以下步骤：
在芯片的第一表面上依次涂覆第一聚酰亚胺树脂PI层和第二聚酰亚胺树脂PI层。
本实施例中，在芯片表面设置PI层的作用包括：1、防止因封装材料的收缩及表面黏贴时的热冲击所造成的封装龟裂；2、避免芯片表面无极二氧化硅钝化膜龟裂；3、作为芯片与基板间的层间绝缘层。在PI层上设置第一突起，不影响芯片本身的结构，同时能够增加芯片与塑封料的接触面积。
对第二PI层进行光刻，得到第一突起层。
本实施例中，该第一突起层上包括至少一个第一突起；其中，第一表面上依次涂覆有第一PI层和第二PI层，仅通过光刻对设置在外侧的第二PI层进行加工得到第一突起层，从而使得第一PI层作为第一贴合层与电路器件贴合，起到PI层原本的作用。之后经过光刻的第二PI层作为突起层设置在第一PI层上，从而实现了在PI层上设置第一突起层。
可选地，上述方式也可以是直接在芯片的第一表面上涂覆厚度为现有技术中两倍的PI层，之后在该PI层上进行光刻，以得到第一突起层，该第一突起层上包括至少一个第一突起。
当电路器件为电容时，由于电容与基板接触的第一表面上设置有陶瓷层，因此直接对该陶瓷层进行镭雕，通过镭雕蚀刻第一表面的陶瓷层，从而在该陶瓷层的外表面得到第一突起层，该第一突起层上包括至少一个第一突起。
当电路器件为电感时，由于电感的加工工艺是通过压模制成，因此，只需要在压模之前，模具进行改造，在模具的第一表面上设置与第一突起层相适配的第一下凹层，之后通过该模具进行压模，即可得到第一表面上设置有第一突起层的电感，该第一突起层上包括至少一个第一突起。
702、对基板的第二表面进行加工，得到第二突起。
本实施例中，可以在第一接触面和第二接触面上分别设置第一突起和第二突起，也可以仅在第一接触面上设置突起，或者仅在第二接触面上设置突起。例如，在回流焊的过程中发现，只有电路器件与塑封料接触的第一接触面上会发生分层现象，基板与塑封料接触的第二接触面上不发生分层，因此，只需在第一接触面上设置突起即可，从而可以在保持封装性能的同时，节省制造成本，简化制造工艺，从而提升生产的效率。因此，步骤701和702可以均执行，或者只执行其中的一个步骤。
在执行步骤702时，具体可以包括以下步骤：
在基板的第二表面依次涂覆第一绿油层和第二绿油层。
本实施例中，该第二表面为基板与塑封料接触的表面，该绿油层所使用的绿油即液态光致阻焊剂，是一种丙烯酸低聚物。作为一种保护层，涂覆在基板上不需焊接的线路和基材上，或用作阻焊剂。目的是长期保护所形成的线路图形。本申请实施例中，通过在绿油层上设置突起，增大绿油层与塑封料的接触面积，从而防止基板与塑封料在回流焊的过程中发生分层。
对第二绿油层进行光刻，得到第二突起层。
本实施例中，第二突起层上包括至少一个第二突起，其中，第二表面上依次涂覆有第一绿油层和第二绿油层，仅通过光刻对设置在外侧的第二绿油层进行加工得到第二突起层，从而使得第一绿油层作为第二贴合层与基板贴合，起到绿油层原本的作用。之后经过光刻的第二绿油层作为突起层设置在第一绿油层上，从而实现了在绿油层上设置第二突起层。
可选地，上述方式也可以是直接在基板的第二表面上涂覆厚度为现有技术中两倍的绿油层，之后在该绿油层上进行光刻，以得到第二突起层，该第二突起层上包括至少一个第二突起。
703、将电路器件的第一表面相对基板的第二表面通过焊点焊接。
本实施例中，可以在电路器件和基板之间设置锡膏，之后对该锡膏进行焊接，以得到 用于连接电路器件和基板的焊点，其中，任意两个相邻的焊点之间设置有第一突起和/或第二突起，从而防止相邻的焊点之间放生分层窜锡现象。
704、在电路器件与基板之间填充塑封料，得到防止分层窜锡的封装。
本实施例中，塑封料可以为环氧树脂模塑材料EMC，EMC初始为液体，将液态的EMC填充在电路器件与基板之间，液态EMC与电路器件和基板相贴合，待EMC凝固后，固态的EMC上就会形成与第一突起和/或第二突起相适配的凹槽，此时，该第一表面即为电路器件与塑封料接触的第一接触面，该第二表面即为基板与塑封料接触的第二接触面，从而实现了塑封料通过第一接触面及第二接触面与电路器件和基板的贴合。
需要说明的是，对于上述第一突起和第二突起的具体形状，本申请实施例并不进行限定，作为一种举例，第一突起和第二突起可以为矩形、倒梯形或三角形中的任意一种，其中，第一突起和第二突起的形状可以不同，或者当具有多个第一突起或多个第二突起时，每个第一突起或第二突起的形状也可以不同，对此本申请并不进行限定。
可选地，在加工的过程中，只需将突起加工为不同的形状，即可得到形状不同的突起，具体加工步骤可以参阅上述公开的内容，本申请实施例不再赘述。
应理解，本申请实施例中提及的芯片可以包括中央处理单元(Central Processing Unit，CPU)，还可以包括其他通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现成可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
在本申请所提供的实施例中，应该理解到，所揭露的封装，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述电路的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个电路或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或电路的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的电路器件可以是或者也可以不是物理上分开的，作为电路显示的部件可以是或者也可以不是物理电路，即可以位于一个地方，或者也可以分布到多个网络电路上。可以根据实际的需要选择其中的部分或者全部电路来实现本实施例方案的目的。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，部分或全部步骤可以并行执行或先后执行，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的电路器件、基板及塑封料的具体结构，可以参考前述实施例中的对应结构，在此不再赘述。
本申请各结构实施例之间相关部分可以相互参考；各装置实施例所提供的装置用于执行对应的电路实施例所提供的电路，故各装置实施例可以参考相关的电路实施例中的相关部分进行理解。
本申请各装置实施例中给出的装置结构图仅示出了对应的装置的简化设计。在实际应用中，该装置可以包含任意数量的发射器，接收器，处理器，存储器等，以实现本申请各装置实施例中该装置所执行的功能或操作，而所有可以实现本申请的装置都在本申请的保护范围之内。
在本申请实施例中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。在本申请实施例和所附实施例书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。本申请中字符“/”，一般表示前后关联对象是一种“或”的关系。
以上对本发明实施例所提供的防止分层窜锡的封装及制造方法进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (13)

  1. 一种防止分层窜锡的封装，其特征在于，包括基板、塑封料及电路器件，所述电路器件通过焊点与所述基板连接，所述塑封料填充设置在所述电路器件与所述基板之间，其中，针对连接所述电路器件与所述基板的任意两个相邻的焊点之间：
    所述电路器件与所述塑封料贴合的第一接触面，或者，所述基板与所述塑封料贴合的第二接触面中的至少一个接触面上设置有突起，所述塑封料上设置有与所述突起适配的凹槽。
  2. 根据权利要求1所述的防止分层窜锡的封装，其特征在于，所述第一接触面包括一体化设置的第一贴合层和第一突起层，所述第一突起层包括至少一个第一突起，其中，所述第一贴合层的一侧与所述电路器件贴合，所述第一贴合层的另一侧设置有所述第一突起层，所述第一突起层的所述至少一个第一突起与设置在所述塑封料上的至少一个第一凹槽一一对应且相互适配，以实现所述第一接触面与所述塑封料的贴合。
  3. 根据权利要求1所述的防止分层窜锡的封装，其特征在于，所述第二接触面为绿油层，所述绿油层包括一体化设置的第二贴合层和第二突起层，所述第二突起层上包括至少一个第二突起，其中，所述第二贴合层的一侧与所述基板贴合，所述第二贴合层的另一侧设置有所述第二突起层，所述第二突起层的所述至少一个第二突起与设置在所述塑封料上的至少一个第二凹槽一一对应且相互适配，以实现所述第二接触面与所述塑封料的贴合。
  4. 根据权利要求1至3任一所述的防止分层窜锡的封装，其特征在于，所述突起的形状为矩形、倒梯形或三角形中的任意一种。
  5. 根据权利要求1至4任一所述的防止分层窜锡的封装，其特征在于，所述电路器件为芯片、电容或电感中的任意一种。
  6. 一种防止分层窜锡的封装制造方法，其特征在于，包括：
    对电路器件的第一表面进行加工，得到第一突起；
    和/或，对基板的第二表面进行加工，得到第二突起；
    将所述电路器件的所述第一表面相对所述基板的所述第二表面通过焊点焊接，其中，任意两个相邻的所述焊点之间设置有所述第一突起和/或所述第二突起；
    在所述电路器件与所述基板之间填充塑封料，得到防止分层窜锡的封装。
  7. 根据权利要求6所述的方法，其特征在于，所述电路器件为芯片，则所述在电路器件的第一表面进行加工，以得到第一突起，包括：
    对覆盖在所述芯片的第一表面上的聚酰亚胺树脂PI层进行光刻，得到第一突起层，所述第一突起层上包括至少一个所述第一突起。
  8. 根据权利要求7所述的方法，其特征在于，所述对覆盖在所述芯片的第一表面上的聚酰亚胺树脂PI层进行光刻之前，还包括：
    在所述芯片的所述第一表面上依次涂覆第一PI层和第二PI层；
    所述对覆盖在所述芯片的第一表面上的聚酰亚胺树脂PI层进行光刻，包括：
    对所述第二PI层进行光刻，得到所述第一突起层。
  9. 根据权利要求6所述的方法，其特征在于，所述电路器件为电容，则所述在电路器件的第一表面进行加工，以得到第一突起，包括：
    对所述电容的第一表面上的陶瓷层进行镭雕，得到第一突起层，所述第一突起层上包 括至少一个所述第一突起。
  10. 根据权利要求6所述的方法，其特征在于，所述电路器件为电感，则所述在电路器件的第一表面进行加工，以得到第一突起，包括：
    通过对所述电感进行压模处理，在所述电感的第一表面上得到第一突起层，所述第一突起层上包括至少一个所述第一突起；
    将所述第一表面不设置有所述第一突起层的一面与所述电感连接，得到第一表面上设置有第一突起层的所述电感。
  11. 根据权利要求6所述的方法，其特征在于，所述对基板的第二表面进行加工，得到第二突起，包括：
    对覆盖设置在所述基板的所述第二表面的绿油层进行光刻，得到第二突起层，所述第二突起层上包括至少一个所述第二突起。
  12. 根据权利要求11所述的方法，其特征在于，所述对覆盖设置在所述基板的所述第二表面的绿油层进行光刻，得到第二突起层之前，还包括：
    在所述基板的所述第二表面依次涂覆第一绿油层和第二绿油层；
    所述对所述基板的所述第二表面的绿油层进行光刻，得到第二突起层，包括：
    对所述第二绿油层进行光刻，得到所述第二突起层。
  13. 根据权利要求6至12任一所述的方法，其特征在于，所述对电路器件的第一表面进行加工，得到第一突起，包括：
    对所述电路器件的第一表面进行加工，得到矩形、倒梯形或三角形的所述第一突起；
    所述对基板的第二表面进行加工，得到第二突起，包括：
    对所述基板的第二表面进行加工，得到矩形、倒梯形或三角形的所述第二突起。
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CN110211935A (zh) * 2019-05-08 2019-09-06 华为技术有限公司 一种防止分层窜锡的封装及制造方法
CN110767614A (zh) * 2019-10-10 2020-02-07 华为技术有限公司 封装结构和电子装置
CN111477554A (zh) * 2020-04-23 2020-07-31 苏州英嘉通半导体有限公司 一种芯片倒装封装中间结构及倒装封装方法
CN114823650A (zh) * 2022-03-31 2022-07-29 江苏长电科技股份有限公司 封装结构及其制造方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004319665A (ja) * 2003-04-15 2004-11-11 Sharp Corp 表面実装部品および表面実装部品の実装方法および実装基板
CN101110398A (zh) * 2006-07-21 2008-01-23 日月光半导体制造股份有限公司 覆晶封装件及其制造方法
US20080135279A1 (en) * 2006-12-11 2008-06-12 Nec Electronics Corporation Printed wiring board having plural solder resist layers and method for production thereof
US20090212406A1 (en) * 2008-02-22 2009-08-27 Panasonic Corporation Semiconductor device and method of manufacturing the same
CN102709259A (zh) * 2011-03-28 2012-10-03 力成科技股份有限公司 非数组凸块的覆晶模封构造与方法
US20130134606A1 (en) * 2011-11-25 2013-05-30 Samsung Electronics Co., Ltd. Semiconductor packages
JP2013131508A (ja) * 2010-04-06 2013-07-04 Murata Mfg Co Ltd 電子装置
CN110211935A (zh) * 2019-05-08 2019-09-06 华为技术有限公司 一种防止分层窜锡的封装及制造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005093780A (ja) * 2003-09-18 2005-04-07 Toppan Printing Co Ltd 半導体装置
JP2009152317A (ja) * 2007-12-19 2009-07-09 Panasonic Corp 半導体装置およびその製造方法
CN102237470B (zh) * 2010-04-29 2013-11-06 展晶科技(深圳)有限公司 发光二极管封装结构及其制造方法以及其基座的制造方法
CN103311205A (zh) * 2013-05-16 2013-09-18 华天科技（西安）有限公司 一种防止芯片凸点短路的封装件及其制造工艺
US9490226B2 (en) * 2014-08-18 2016-11-08 Qualcomm Incorporated Integrated device comprising a heat-dissipation layer providing an electrical path for a ground signal

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004319665A (ja) * 2003-04-15 2004-11-11 Sharp Corp 表面実装部品および表面実装部品の実装方法および実装基板
CN101110398A (zh) * 2006-07-21 2008-01-23 日月光半导体制造股份有限公司 覆晶封装件及其制造方法
US20080135279A1 (en) * 2006-12-11 2008-06-12 Nec Electronics Corporation Printed wiring board having plural solder resist layers and method for production thereof
US20090212406A1 (en) * 2008-02-22 2009-08-27 Panasonic Corporation Semiconductor device and method of manufacturing the same
JP2013131508A (ja) * 2010-04-06 2013-07-04 Murata Mfg Co Ltd 電子装置
CN102709259A (zh) * 2011-03-28 2012-10-03 力成科技股份有限公司 非数组凸块的覆晶模封构造与方法
US20130134606A1 (en) * 2011-11-25 2013-05-30 Samsung Electronics Co., Ltd. Semiconductor packages
CN110211935A (zh) * 2019-05-08 2019-09-06 华为技术有限公司 一种防止分层窜锡的封装及制造方法

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