WO2020215819A1 - 差分时钟交叉点检测电路及检测方法 - Google Patents

差分时钟交叉点检测电路及检测方法 Download PDF

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WO2020215819A1
WO2020215819A1 PCT/CN2020/070598 CN2020070598W WO2020215819A1 WO 2020215819 A1 WO2020215819 A1 WO 2020215819A1 CN 2020070598 W CN2020070598 W CN 2020070598W WO 2020215819 A1 WO2020215819 A1 WO 2020215819A1
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Prior art keywords
differential clock
capacitor
cross point
mos tube
terminal
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PCT/CN2020/070598
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English (en)
French (fr)
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徐鸣远
李梁
刘军
沈晓峰
王健安
付东兵
陈光炳
黄兴发
陈玺
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中国电子科技集团公司第二十四研究所
重庆吉芯科技有限公司
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Application filed by 中国电子科技集团公司第二十四研究所, 重庆吉芯科技有限公司 filed Critical 中国电子科技集团公司第二十四研究所
Priority to US17/602,993 priority Critical patent/US11353505B2/en
Publication of WO2020215819A1 publication Critical patent/WO2020215819A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31706—Testing of digital circuits involving differential digital signals, e.g. testing differential signal circuits, using differential signals for testing

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  • the present invention relates to the technical field of signal processing, in particular to a differential clock crossing point detection circuit and detection method.
  • a clock circuit is required to drive the internal signal processing unit to process the input signal (for example, the digital-to-analog converter needs a clock to convert digital signals to analog signals and output the conversion results through the clock), and in order to obtain excellent noise and For dynamic performance, the clock generally adopts a differential form and requires the clock to have an ideal duty cycle and crossover point.
  • a detection circuit is needed to detect the position of the output clock cross point, and then the differential clock is adjusted by the adjustment circuit.
  • the existing differential clock crossing point detection circuit generally uses 4 MOS devices.
  • the gates of the 2 NMOSs are respectively connected to the positive and negative ends of the clock.
  • the output is pulled down, and the gates of the 2 PMOSs are respectively Connect the positive and negative ends of the clock, and pull up the output when the two PMOSs are turned on through the differential clock at the same time, such as the cross point detection circuit in patent US9154148B2.
  • the cross point detection circuit determines the cross point position of the differential clock by collecting static current. The structure and detection process of the point detection circuit are more complicated.
  • the purpose of the present invention is to provide a differential clock cross-point detection circuit, which is used to solve the complex problem of the structure and detection process of the cross-point detection circuit in the prior art.
  • the present invention provides a differential clock crossing point detection circuit, including: a first MOS tube, a second MOS tube, and a capacitor;
  • the drain terminal of the first MOS tube is connected to the negative terminal of the differential clock, the gate terminal of the first MOS tube is connected to the positive terminal of the differential clock, and the source terminal of the first MOS tube is connected to the second MOS tube
  • the drain terminal of the second MOS tube is connected to the negative terminal of the differential clock, the source terminal of the second MOS tube is connected to the output terminal through a node; one end of the capacitor is connected to the node, the capacitor The other end is grounded.
  • the capacitor includes a polar capacitor, the positive terminal of the polar capacitor is connected to the node, and the negative terminal of the polar capacitor is grounded.
  • the differential clock crossing point detection circuit further includes a resistor, and the resistor is connected in series between the source terminal of the second MOS transistor and the node.
  • the present invention also provides a differential clock cross point detection method, which includes the steps:
  • the magnitudes of the first output voltage and the second output voltage are compared, and the relative positions of the two cross points before and after the differential clock are determined accordingly.
  • the capacitor collects and stores the negative terminal voltage of the differential clock when the first MOS transistor and the second MOS transistor simultaneously open a time window The part inside.
  • the time constant of the capacitor is much larger than the frequency of the differential clock, so that the negative terminal voltage of the differential clock is stored on the capacitor.
  • the step of comparing the magnitudes of the first output voltage and the second output voltage, and judging the relative positions of the two cross points before and after the differential clock accordingly includes:
  • the adjusted cross point is lower than the cross point before adjustment; if the first output voltage is less than the second output voltage, the adjusted cross point The cross point of is higher than the cross point before adjustment.
  • the differential clock crossing point detection circuit of the present invention has the following beneficial effects:
  • the detection circuit of the present invention uses the input clock to collect the input clock through the structural design of two MOS tubes and one capacitor, and does not need to collect static current.
  • the detection circuit has a simple structure principle and easy operation.
  • FIG. 1 shows a schematic diagram of the circuit structure of the differential clock cross point detection circuit of the present invention.
  • Figure 2 shows the waveform of a clock cycle when the cross point of the differential clock is higher from the center.
  • Figure 3 shows a waveform diagram of a clock cycle when the cross point of the differential clock is lower from the center.
  • Figure 4 shows a waveform diagram of one clock cycle with the differential clock crossing point in the center.
  • the differential clock cross point detection circuit in the prior art has a complicated structure and cumbersome operation. Based on this, the present invention provides a differential clock cross point detection circuit with a simple structure and easy operation.
  • the differential clock crossing point detection circuit of the present invention includes: a first MOS tube M1, a second MOS tube M2, and a capacitor C; the drain terminal of the first MOS tube is connected to the negative terminal CLK- of the differential clock , The gate terminal of the first MOS tube is connected to the positive terminal CLK+ of the differential clock, the source terminal of the first MOS tube is connected to the drain terminal of the second MOS tube; the gate terminal of the second MOS tube is connected to the negative terminal CLK- of the differential clock, the The source terminal of the second MOS transistor is connected to the output terminal Vout through the node a; one end of the capacitor C is connected to the node A, and the other end of the capacitor C is grounded to Vss.
  • the differential clock crossing point detection circuit further includes a resistor R, which is connected in series between the source terminal of the second MOS transistor M2 and the node A.
  • the capacitor C adopts a polarized capacitor with a larger capacitance value, such as a common aluminum electrolytic capacitor, as shown in FIG. 1, the positive terminal is connected to node A, and the negative terminal is grounded Vss.
  • Figure 2 shows the waveform diagram of a clock cycle when the cross point of the differential clock is higher from the center.
  • the input waveform diagrams of the positive and negative ends of the detected differential clock are 100 and 110 respectively.
  • the first MOS tube M1 and the second MOS tube M2 are turned on and turned off at the same time.
  • the first MOS tube M1 and the second MOS tube M2 are turned on at the same time in the area indicated by the dotted lines ab and cd.
  • the tube M1 and the second MOS tube M2 are turned off at the same time on the left side of a, and the right side of bc and d.
  • C is the capacitance value of capacitor C
  • V 1 is the average voltage of signal 110 in the ab region
  • V 2 is the average voltage of the signal 110 in the cd area
  • the capacitor C collects and stores the negative terminal voltage of the differential clock.
  • the first MOS tube M1 and the second MOS tube M2 open the time window at the same time (the ab and cd areas shown by the dotted line in Figure 2-4 The part within) is the average value of charges Q 1 and Q 2 .
  • the time constant ⁇ of the resistor R and the capacitor C is far greater than the frequency of the differential clock, so that the capacitor C can be slowly in multiple clock cycles Accumulate the trend of change, and finally reach a stable average of Q 1 and Q 2 .
  • the averaged charge stored on the capacitor C will be converted into a voltage through the node A and output at the output terminal Vout.
  • the output voltage of the output terminal Vout is collected, and the position of the input differential clock crossing point is determined based on this.
  • the signal 110 on the average voltage V ab area than the average voltage V 1 in the region 2 is slightly larger cd 2 , And the area where the first MOS tube M1 and the second MOS tube M2 are turned on at the same time is large, the entire average voltages V 1 and V 2 are relatively large, and the average value of the two is obviously greater than half of the peak voltage of the signal 110; if the differential clock The cross point is at the center position, as shown in Figure 3, the average voltage V 1 of the signal 110 in the ab area is equal to the average voltage V 2 in the cd area, and the first MOS transistor M1 and the second MOS transistor M2 are turned on simultaneously The value of the entire average voltage V 1 and V 2 is moderate, and the average value of the two is approximately equal to half of the peak voltage of the signal 110; if the differential clock crossing point is lower from the center, as shown in Figure 4, the signal 110 The average voltage V 1 on the ab area is slightly smaller
  • the output voltage output by the output terminal Vout is the integration of the negative terminal of the differential clock when the first MOS tube M1 and the second MOS tube M2 are opened at the same time.
  • the integration result is converted into a voltage output on the capacitor C, and the cross point is at The output voltage when the position is high from the center is higher than the output voltage when the cross point is in the middle position and the cross point is low from the center, and the output voltage when the cross point is in the center position is higher than the output when the cross point is low from the center.
  • the voltage is high. It can be seen that the output voltage of the output terminal Vout reflects the position of the cross point of the differential clock.
  • the present invention also provides a differential clock cross point detection method based on the above differential clock cross point detection circuit, which includes the steps:
  • the step S4 of comparing the magnitude of the first output voltage and the second output voltage and judging the relative positions of the two cross points before and after the differential clock includes:
  • the adjusted cross point is lower than the cross point before adjustment; if the first output voltage is less than the second output voltage, the adjusted cross point The cross point of is higher than the cross point before adjustment.
  • the main structure of the differential clock crossing point detection circuit of the present invention is two MOS transistors and a capacitor, and the input clock is used to collect the input clock.
  • the structure is relatively simple; the output voltage of the output terminal is adjusted before and after the differential clock crossing point is adjusted. The relative position of the cross point of the differential clock before and after adjustment can be judged.
  • the detection principle is simple and easy to use; and the time constant ⁇ of resistance and capacitance is much greater than the frequency of the differential clock, making the final collected output voltage value more stable. Improve the reliability of the test results.

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Abstract

一种差分时钟交叉点检测电路及检测方法，差分时钟交叉点检测电路包括：第一MOS管(M1)、第二MOS管(M2)及电容(C)；第一MOS管(M1)的漏端接差分时钟的负端(CLK-)，第一MOS管(M1)的栅端接差分时钟的正端(CLK+)，第一MOS管(M1)的源端接第二MOS管(M2)的漏端；第二MOS管(M2)的栅端接差分时钟的负端(CLK-)，第二MOS管(M2)的源端通过节点接输出端；电容(C)的一端接节点(A)，电容(C)的另一端接地。差分时钟交叉点检测电路的结构相对简单，通过比较差分时钟交叉点调整前后输出端的输出电压的大小，就可以判断出调整前后差分时钟交叉点的相对位置，检测原理简单、易上手。

Description

差分时钟交叉点检测电路及检测方法 技术领域
本发明涉及信号处理技术领域，特别是涉及一种差分时钟交叉点检测电路及检测方法。
背景技术
在信号处理电路中，都需要时钟电路驱动内部信号处理单元处理输入信号(如数模转换器需要时钟进行数字信号到模拟信号的转换并通过时钟把转换结果输出)，而为了得到优秀的噪声和动态性能，时钟一般采用差分形式，并且要求时钟有理想的占空比和交叉点。针对差分时钟交叉点，需要检测电路来探测输出时钟交叉点的位置，再通过调节电路对差分时钟进行交叉点调节。
而现有的差分时钟交叉点检测电路一般采用4个MOS器，2个NMOS的栅极分别接时钟正负端，通过差分时钟同时开启两个NMOS时使输出下拉，2个PMOS的栅极分别接时钟正负端，通过差分时钟同时开启两个PMOS时使输出上拉，如专利US9154148B2里的交叉点检测电路，该交叉点检测电路通过采集静态电流来判断差分时钟的交叉点位置，整个交叉点检测电路的结构及检测过程比较复杂。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种差分时钟交叉点检测电路，用于解决现有技术中交叉点检测电路的结构及检测过程复杂问题。
为实现上述目的及其他相关目的，本发明提供一种差分时钟交叉点检测电路，包括：第一MOS管、第二MOS管及电容；
所述第一MOS管的漏端接差分时钟的负端，所述第一MOS管的栅端接所述差分时钟的正端，所述第一MOS管的源端接所述第二MOS管的漏端；所述第二MOS管的栅端接所述差分时钟的负端，所述第二MOS管的源端通过节点接输出端；所述电容的一端接所述节点，所述电容的另一端接地。
可选地，所述电容包括有极性电容，所述有极性电容的正端接所述节点，所述有极性电容的负端接地。
可选地，所述差分时钟交叉点检测电路还包括电阻，所述电阻串联在所述第二MOS管的源端与所述节点之间。
为了实现上述目的及其他相关目的，本发明还提供一种差分时钟交叉点检测方法，包括 步骤：
提供上述任意一项所述的差分时钟交叉点检测电路；
通过所述电容对所述差分时钟的负端电压进行采集存储，并通过所述输出端进行输出，得到第一输出电压；
对所述差分时钟的交叉点进行调整，再次对所述差分时钟的负端电压进行采集存储并输出，得到第二输出电压；以及
比较所述第一输出电压与所述第二输出电压的大小，并据此判断所述差分时钟前后两个交叉点的相对位置。
可选地，根据所述差分时钟交叉点检测电路的结构，所述电容采集存储的是所述差分时钟的负端电压在所述第一MOS管和所述第二MOS管的同时开启时间窗口内的那一部分。
可选地，所述电容的时间常数远大于所述差分时钟的频率，使得所述电容上存储的是所述差分时钟的负端电压在多个时钟周期中所述第一MOS管和所述第二MOS管的同时开启时间窗口内的平均值。
可选地，所述比较所述第一输出电压与所述第二输出电压的大小，并据此判断所述差分时钟前后两个交叉点的相对位置的步骤包括：
若所述第一输出电压大于所述第二输出电压，则调整后的交叉点相对于则调整前的交叉点偏低；若所述第一输出电压小于所述第二输出电压，则调整后的交叉点相对于则调整前的交叉点偏高。
如上所述，本发明的差分时钟交叉点检测电路具有以下有益效果：
本发明的检测电路通过两个MOS管和一个电容的结构设计利用输入时钟采集输入时钟，不需要采集静态电流，检测电路的结构原理简单、易操作。
附图说明
图1显示为本发明的差分时钟交叉点检测电路的电路结构示意图。
图2显示为差分时钟交叉点离中心偏高的一个时钟周期波形图。
图3显示为差分时钟交叉点离中心偏低的一个时钟周期波形图。
图4显示为差分时钟交叉点在中心的一个时钟周期波形图。
零件标号说明
M1  第一MOS管
M2  第二MOS管
R     电阻
C     电容
CLK+  差分时钟的正端
CLK-  差分时钟的负端
Vout  输出端
Vss   地端
A     节点
100   差分时钟的正端波形图
110   差分时钟的负端波形图
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图4。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技术的人士了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。
如前述在背景技术中所提及的，现有技术中的差分时钟交叉点检测电路的结构复杂、操作繁琐，基于此，本发明提供一种结构简单、易操作的差分时钟交叉点检测电路。
详细地，如图1所示，本发明的差分时钟交叉点检测电路包括：第一MOS管M1、第二MOS管M2及电容C；第一MOS管的漏端接差分时钟的负端CLK-，第一MOS管的栅端接差分时钟的正端CLK+，第一MOS管的源端接第二MOS管的漏端；第二MOS管的栅端接差分时钟的负端CLK-，所述第二MOS管的源端通过节点a接输出端Vout；电容C的一端接节点A，电容C的另一端接地Vss。此外，所述差分时钟交叉点检测电路还包括电阻R，电 阻R串联在第二MOS管M2的源端与节点A之间。
可选地，电容C采用电容值较大的有极性电容如常见的铝电解电容，如图1所示，其正端接节点A、负端接地Vss。
在本发明的一个实施例中，采用标准65nm CMOS工艺，差分时钟频率在1GHz时，第一MOS管M1的宽长比为W/L＝120nm/60nm，第二MOS管M2的宽长比为W/L＝120nm/60nm，电阻R的电阻值为1kΩ，电容C的电容值为200fF。
如图2所示为差分时钟交叉点离中心偏高的一个时钟周期波形图，被检测的差分时钟的正端、负端输入波形图分别为100和110，结合图1和图2可知，所述差分时钟交叉点检测电路的工作原理如下：
在一个时钟周期内，第一MOS管M1和第二MOS管M2同时开启和同时关断，第一MOS管M1和第二MOS管M2同时开启在虚线a-b和c-d所示的区域，第一MOS管M1和第二MOS管M2同时关断在a的左边、b-c和d的右边区域，而在第一MOS管M1和第二MOS管M2同时开启情况下，信号110通过电阻R到达电容C上，此时计算存储到电容C上的电荷，在a-b区域内，电容C上存储的电荷为
Q 1＝CV 1，
其中，C为电容C的电容值，V 1为信号110在a-b区域上的平均电压；
同理，在c-d区域内，电容C上存储的电荷为
Q 2＝CV 2
其中，V 2为信号110在c-d区域上的平均电压；
故在一个时钟周期内，电容C采集存储的是差分时钟的负端电压在第一MOS管M1和第二MOS管M2的同时开启时间窗口(图2-4中虚线所示的a-b及c-d区域)内的那一部分，也就是电荷Q 1与Q 2的平均值。
此外，为消除偶然因素、保证电容C上采取存储电荷值的稳定可靠，取电阻R和电容C的时间常数τ远远大于差分时钟的频率，使得电容C就能在多个时钟周期内慢慢积累变化趋势，最后达到稳定的Q 1与Q 2的平均值。多个时钟周期后，电容C上存储的平均后的电荷会通过节点A转换为电压在输出端Vout输出，采集输出端Vout的输出电压，并据此判断出输入的差分时钟交叉点位置。
详细地，参见图2-图4，如果差分时钟交叉点离中心偏高，如图2所示，则信号110在a-b区域上的平均电压V 1比在c-d区域上的平均电压V 2略大，且第一MOS管M1和第二MOS管M2同时开启的区域大，整个平均电压V 1和V 2都比较大，二者的平均值明显要大于信号 110的电压峰值的一半；如果差分时钟交叉点在中心位置，如图3所示，则信号110在a-b区域上的平均电压V 1与在c-d区域上的平均电压V 2相等，且第一MOS管M1和第二MOS管M2同时开启的区域适中，整个平均电压V 1和V 2的值适中，二者的平均值约等于信号110的电压峰值的一半；如果差分时钟交叉点离中心偏低，如图4所示，则信号110在a-b区域上的平均电压V 1比在c-d区域上的平均电压V 2略小，且第一MOS管M1和第二MOS管M2开启的区域小，整个平均电压V 1和V 2都比较小，二者的平均值明显小于信号110的电压峰值的一半。
基于上述分析可知，输出端Vout输出的输出电压就是第一MOS管M1和第二MOS管M2的同时开启窗口对差分时钟的负端的积分，积分结果在电容C上转换成电压输出，交叉点在离中心偏高位置时的输出电压比交叉点在中间位置和交叉点离中心偏低位置时的输出电压高，且交叉点在中心位置时的输出电压比交叉点离中心偏低位置时的输出电压高。可见，输出端Vout的输出电压的高低反映了差分时钟的交叉点位置。
因此，本发明还提供一种基于上述差分时钟交叉点检测电路的差分时钟交叉点检测方法，包括步骤：
S1、提供上述差分时钟交叉点检测电路；
S2、通过电容C对差分时钟的负端电压110进行采集存储，并通过输出端Vout进行输出，得到第一输出电压；
S3、对差分时钟的交叉点进行调整，再次对差分时钟的负端电压110进行采集存储并输出，得到第二输出电压；以及
S4、比较所述第一输出电压与所述第二输出电压的大小，并据此判断差分时钟前后两个交叉点的相对位置。
详细地，通过比较所述第一输出电压与所述第二输出电压的大小，并判断差分时钟前后两个交叉点的相对位置的步骤S4包括：
若所述第一输出电压大于所述第二输出电压，则调整后的交叉点相对于则调整前的交叉点偏低；若所述第一输出电压小于所述第二输出电压，则调整后的交叉点相对于则调整前的交叉点偏高。
综上所述，本发明差分时钟交叉点检测电路的主要结构为两个MOS管和一个电容，并利用输入时钟采集输入时钟，结构相对简单；通过比较差分时钟交叉点调整前后输出端的输出电压的大小，就可以判断出调整前后差分时钟交叉点的相对位置，检测原理简单、易上手；且电阻和电容的时间常数τ远远大于差分时钟的频率，使得最终采集输出的输出电压值更稳 定，提高了检测结果的可靠性。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (7)

  1. 一种差分时钟交叉点检测电路，其特征在于，包括：第一MOS管、第二MOS管及电容；
    所述第一MOS管的漏端接差分时钟的负端，所述第一MOS管的栅端接所述差分时钟的正端，所述第一MOS管的源端接所述第二MOS管的漏端；所述第二MOS管的栅端接所述差分时钟的负端，所述第二MOS管的源端通过节点接输出端；所述电容的一端接所述节点，所述电容的另一端接地。
  2. 根据权利要求1所述的差分时钟交叉点检测电路，其特征在于，所述电容包括有极性电容，所述有极性电容的正端接所述节点，所述有极性电容的负端接地。
  3. 根据权利要求1或2所述的差分时钟交叉点检测电路，其特征在于，所述差分时钟交叉点检测电路还包括电阻，所述电阻串联在所述第二MOS管的源端与所述节点之间。
  4. 一种差分时钟交叉点检测方法，其特征在于，包括步骤：
    提供权利要求1至3中任意一项所述的差分时钟交叉点检测电路；
    通过所述电容对所述差分时钟的负端电压进行采集存储，并通过所述输出端进行输出，得到第一输出电压；
    对所述差分时钟的交叉点进行调整，再次对所述差分时钟的负端电压进行采集存储并输出，得到第二输出电压；以及
    比较所述第一输出电压与所述第二输出电压的大小，并据此判断所述差分时钟前后两个交叉点的相对位置。
  5. 根据权利要求4所述的差分时钟交叉点检测方法，其特征在于，根据所述差分时钟交叉点检测电路的结构，所述电容采集存储的是所述差分时钟的负端电压在所述第一MOS管和所述第二MOS管的同时开启时间窗口内的那一部分。
  6. 根据权利要求5所述的差分时钟交叉点检测方法，其特征在于，所述电容的时间常数远大于所述差分时钟的频率，使得所述电容上存储的是所述差分时钟的负端电压在多个时钟周期中所述第一MOS管和所述第二MOS管的同时开启时间窗口内的平均值。
  7. 根据权利要求4所述的差分时钟交叉点检测方法，其特征在于，所述比较所述第一输 出电压与所述第二输出电压的大小，并据此判断所述差分时钟前后两个交叉点的相对位置的步骤包括：
    若所述第一输出电压大于所述第二输出电压，则调整后的交叉点相对于则调整前的交叉点偏低；若所述第一输出电压小于所述第二输出电压，则调整后的交叉点相对于则调整前的交叉点偏高。
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