WO2020215738A1 - 一种芯片互连结构及其制备方法 - Google Patents
一种芯片互连结构及其制备方法 Download PDFInfo
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- WO2020215738A1 WO2020215738A1 PCT/CN2019/123823 CN2019123823W WO2020215738A1 WO 2020215738 A1 WO2020215738 A1 WO 2020215738A1 CN 2019123823 W CN2019123823 W CN 2019123823W WO 2020215738 A1 WO2020215738 A1 WO 2020215738A1
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- B22F1/05—Metallic powder characterised by the size or surface area of the particles
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Definitions
- the present invention relates to the field of chip package interconnection, and more specifically to the preparation technology of metal film for sintering.
- nano-silver sintering has gradually become the mainstream of power semiconductor device packaging interconnection, and major packaging application manufacturers at home and abroad have entered practical and large-scale use.
- nano-silver sintering patents, materials, processes and equipment are mainly controlled by foreign manufacturers, and their development in China is greatly restricted.
- the nano-silver sintering technology also has shortcomings: 1) The high price of silver material itself limits its wide use. 2) The thermal expansion coefficients of the backside materials of silver and SiC chips are different, and other intermediate metal layers need to be added to improve interconnection performance, thereby increasing process complexity and cost. 3) Electromigration exists in the silver layer, which is not conducive to long-term reliable application of power devices.
- Nano-copper particles similar to nano-silver can be melted under low temperature conditions, and the melting point after sintering is close to copper elemental material (1083°C), which can construct a stable metal interconnection layer. Its single-component metal characteristics avoid the service reliability problem under the thermal cycling effect of alloy materials, realize copper-copper bonding, solve the problem of thermal expansion coefficient matching between the chip and the substrate, and avoid the reliability problem caused by electromigration. Compared with nano-silver particles, it effectively reduces the material and processing costs of interconnect packaging. More importantly, it can further promote the practical application and industrialization of the "All copper" concept from the field of chip packaging applications, and promote the innovative development of the semiconductor industry.
- the first prior art is a patent document with the publication number CN103262172A, which discloses a sintered material and a thin layer prepared from the sintered material, and an adhesion method of the material.
- the thin layer is composed of metal powder, solder paste, adhesive and solvent.
- the metal powder includes gold, palladium, silver, copper, aluminum, silver-palladium alloy or gold-palladium alloy, and may further include one or more functional additives.
- the metal powder includes nanoparticles.
- the metal powder is applied to the substrate, and the material on the substrate is dried to form a thin layer.
- the substrate material includes polyester fiber.
- the disadvantage of the prior art is that the nano metal layer on the substrate has a single composition and size, which results in a large porosity after sintering and poor electrical and thermal conductivity.
- the second prior art is the patent document with publication number CN105492198A, which discloses a composite and multilayer silver film for electrical parts and mechanical parts, in which reinforcing particles or fibers are added to the sinterable silver layer to increase its strength.
- a reinforced metal foil layer is added to the slightly decomposable silver particle layer. Its composition can be silver, copper, gold or any other metal or any alloy, or it can be a metal polymer or ceramic foil, or it can be composite or Plating structure with different metal and alloy layers.
- the reinforced metal foil layer can be applied in solid, perforated or grid form.
- the problem with the prior art is that the addition of the multilayer composite metal film and the reinforced metal foil layer increases the number of interfaces of the connection layer after sintering, thereby possibly reducing the connection strength; in addition, the single-size silver particle layer is sintered.
- the porosity is large, which reduces thermal conductivity, electrical conductivity and shear stress, thereby reducing reliability.
- the third prior art is a Chinese patent application with a patent publication number CN106660120A, which discloses a discrete sintered material and a fixing method using it.
- the material includes metal powder and a substrate.
- the metal powder includes shell-structured nanoparticles and the substrate includes a polymer.
- the disadvantage of this method is that on the one hand, a large sintered metal film is used.
- the gas generated at the center position has no effective channel to remove, which may cause problems such as large porosity of the interconnection layer after sintering; printing or pouring is used directly
- the method of preparing discrete shapes may cause the shape of the discrete pieces to depend on the design of the printing screen, and it is difficult to change the shape; it also causes problems such as rough edges, uneven thickness, and low resolution.
- the present invention provides a chip interconnection structure, which includes:
- N pieces of nano metal film N ⁇ 2
- the nano metal film chip includes first size nano metal particles and second size nano metal particles,
- the diameter of the first size nano metal particles is different from that of the second size nano metal particles.
- the nano metal particle material is copper.
- the nano metal particle material is gold, palladium, silver, copper, aluminum, silver-palladium alloy, gold-palladium alloy, copper-silver alloy, copper-silver-nickel alloy or copper-aluminum alloy.
- the larger-size nano-metal particles have a diameter of 1nm ⁇ D ⁇ 10 ⁇ m; the first-size nano-metal particles and the second-size Among the size nano metal particles, the diameter of the smaller size nano metal particles is 0.5nm ⁇ d ⁇ 20nm.
- the nano metal film chips are located between the chip and the substrate, and the nano metal film chips are arranged at intervals; one or more nano metal film chips are arranged between the chip and the substrate, and different layers of the nano metal film chips are arranged. There is a continuous nano metal film between.
- the multilayer nano metal chip includes:
- the first organic medium material layer is the first organic medium material layer
- the second organic medium material layer is the second organic medium material layer
- the first organic medium material layer contains first-size nano metal particles
- the first organic medium material layer contains second-size nano metal particles
- the first size nano metal particles and the second size nano metal particles have different diameters.
- the multi-layer nano metal film chip distribution mode is:
- N N 1 +N 2 +...+N n .
- a method for connecting a chip interconnection structure includes:
- Step 1 Prepare a nano metal film, the nano metal film includes first size nano metal particles and second size nano metal particles, the first size nano metal particles and the second size nano metal particles have different diameters;
- Step 2 Cutting the nano metal film to obtain N nano metal film pieces
- Step 3 Attach one side of the nano metal film chip to the bottom of the chip
- Step 4 Attach the substrate and the other side of the nano metal film chip
- Step 5 Interconnect the chip and the substrate.
- the nano metal particle material is copper.
- the nano metal particle material is gold, palladium, silver, copper, aluminum, silver-palladium alloy, gold-palladium alloy, copper-silver alloy, copper-silver-nickel alloy or copper-aluminum alloy.
- the larger-size nano-metal particles have a diameter of 1nm ⁇ D ⁇ 10 ⁇ m; the first-size nano-metal particles and the second-size Among the size nano metal particles, the diameter of the smaller size nano metal particles is 0.5nm ⁇ d ⁇ 20nm.
- the nano metal film chips are located between the chip and the substrate, and the nano metal film chips are arranged at intervals; one or more nano metal film chips are arranged between the chip and the substrate, and different layers of the nano metal film chips are arranged. There is a continuous nano metal film between.
- the distribution mode of the nano metal film pieces of the one layer includes:
- the nano metal film pieces are attached to the bottom of the chip according to length A and width B.
- the multi-layer nano metal film chip distribution mode includes:
- a 31 th the length, total width B 31 the N 1 th metal adhesive film pieces are arranged according to the design of the bottom of the chip, and then dried to obtain a first metal film layer;
- the metal film pieces of the length A 3n and the width B 3n totaling N n are adhered to the bottom of the n-1th metal film layer according to the designed arrangement, and then dried to obtain the nth metal film layer.
- the step 3 and step 4 further include drying treatment.
- the step 4 further includes:
- Step 5.1 Peel off the supporting substrate
- Step 5.2 Place the chip with the multilayer metal film on the substrate
- Step 5.3 Heat the multi-layer metal film chip in the sintering furnace, select whether to have pressure assist, and interconnect the substrate and the multi-layer metal film chip.
- the metal film is set as a plurality of discontinuous small pieces and arranged between the chip and the substrate according to the pre-designed arrangement.
- the small piece gaps left by the discrete arrangement can be used as channels for gas exhaust during sintering, which is beneficial to the improvement of compactness after sintering. This improves the thermal conductivity of the interconnection layer; at the same time, as the sintering progresses, due to the limitation of the z-direction, the metal film pieces will deform in the x and y directions, and contact each other to form a dense sintered layer, which is compared with using a single piece
- the large metal film can effectively reduce the tilt problem in the chip bonding process.
- FIG. 1 is a schematic diagram of a discontinuous nano-copper sintered film provided by Embodiment 1 of the present invention.
- FIG. 2 is a schematic diagram of a structure method using a single-layer discontinuous metal film sintered interconnection provided in the second embodiment.
- FIG 3 is a schematic diagram of a structure method using a multilayer discontinuous metal film sintered interconnection provided in the third embodiment.
- FIG. 4 is a schematic diagram of a structure method using a multilayer periodic discontinuous metal film sintered interconnection provided by the fourth embodiment.
- This embodiment provides a chip substrate connection structure and method using a nano metal film, as shown in FIG. 1, including:
- the metal film includes an organic carrier and nano metal particles
- the metal film may have a single-layer structure or a multilayer structure
- the single-layer structure may include first-size nano-metal particles and second-size nano-metal particles mixed together;
- the multilayer structure includes a layer of nano metal particles of a first size and a layer of nano metal particles of a second size
- the diameter of the first size nano metal particles is different from that of the second size nano metal particles.
- the nano metal particle material is copper.
- the nano metal particle material is gold, palladium, silver, copper, aluminum, silver-palladium alloy, gold-palladium alloy, copper-silver alloy, copper-silver-nickel alloy or copper-aluminum alloy.
- the larger-size nano-metal particles have a diameter of 1 nm ⁇ D ⁇ 10 ⁇ m.
- the pre-formed metal film pieces can be formed by forging, shearing or programmable laser cutting to obtain a sequence of discrete structured films in a specific shape.
- discontinuous means that the metal film at the bottom of the chip is not a complete piece, but multiple pieces with a certain interval. Arranged small metal film structure.
- the discontinuous metal film sintered interconnection structure is characterized in that the sizes of the N metal film pieces are all the same; or all are different; or a combination of the same and different sizes of multilayer metal films.
- the discontinuous metal film sintered interconnection structure is characterized in that the positions of the N metal film pieces are arranged in an n ⁇ n square matrix (as shown in FIG. 1); the N metal film pieces The size of is set according to [(1/N)-k] which is the area of the bottom surface of the chip, k is the designed chip pitch, and the range of k is 10 ⁇ m to 2mm.
- This embodiment provides a chip substrate connection structure and method using a single-layer nano metal film, as shown in FIG. 2.
- the single-layer structure may include first-size nano-metal particles and second-size nano-metal particles mixed together;
- the mixing methods include: 1) directly prepare the mixed solution; 2) prepare solutions, pastes, and films of large-size particles, and inject small-size particles by physical impact;
- the nano metal particle material is copper.
- the nano metal particle material is gold, palladium, silver, copper, aluminum, silver-palladium alloy, gold-palladium alloy, copper-silver alloy, copper-silver-nickel alloy or copper-aluminum alloy.
- the larger-size nano-metal particles have a diameter of 1 nm ⁇ D ⁇ 10 ⁇ m.
- the preparation steps include:
- Step 1 Preparation of a single-layer metal film
- Step 2 Cut the metal film to obtain N metal film pieces
- Step 3 Paste the metal film to the bottom of the chip to be interconnected, as shown in FIG. 2, taking a 3x3 chip arrangement as an example;
- Step 4 Heating the chip with the metal film attached to obtain a chip with the metal film attached
- Step 5 Interconnect the substrate and the metal film chip.
- step 1 includes:
- Step 1.1 configure a mixed solution of nano metal particles with a first size and a nano metal with a second size to prepare a metal paste;
- Step 1.2 Put the metal paste on the supporting substrate, and dry the supporting substrate to form a metal film;
- step 5 includes:
- Step 5.1 Peel off the supporting substrate.
- Step 5.2 Place the multilayer metal film chip on the substrate
- Step 5.3 Heat the multi-layer metal film chip in the sintering furnace, select whether to have pressure assist, and interconnect the substrate and the multi-layer metal film chip.
- the system is optionally sintered at 200-280°C for 10 minutes in a sintering furnace, so that the substrate and the chip are interconnected.
- test results show that the chip and substrate system interconnected by the discontinuous copper film has a porosity of less than 25% after sintering, effective exhaust of gas, thermal conductivity greater than 100 (W/mK), and shear stress greater than 10MPa.
- the shear stress is still greater than 8 MPa after 1000 thermal cycles at a temperature of -40 to 150°C.
- This embodiment provides a chip substrate connection structure and method using a multilayer nano metal film, as shown in FIG. 3.
- the multi-layer non-continuous metal film includes
- the first organic medium material layer is the first organic medium material layer
- the second organic medium material layer is the second organic medium material layer
- the first organic medium material layer contains first-size nano metal particles
- the first organic medium material layer contains second-size nano metal particles
- the first size nano metal particles and the second size nano metal particles have different diameters.
- the nano metal particle material is copper.
- the nano metal particle material is gold, palladium, silver, copper, aluminum, silver-palladium alloy, gold-palladium alloy, copper-silver alloy, copper-silver-nickel alloy or copper-aluminum alloy.
- the preparation steps include
- Step 1 Preparation of multilayer metal film
- Step 2 Cut the metal film to obtain N metal film pieces
- Step 3 Paste the metal film to the bottom of the chip to be interconnected, as shown in Figure 3, taking a 3x3 chip arrangement as an example;
- Step 4 Heating the chip with the metal film attached to obtain a chip with the metal film attached
- Step 5 Interconnect the substrate and the metal film chip.
- step 5 includes:
- Step 5.1 Peel off the supporting substrate.
- Step 5.2 Place the multilayer metal film chip on the substrate
- Step 5.3 Heat the multi-layer metal film chip in the sintering furnace, select whether to have pressure assist, and interconnect the substrate and the multi-layer metal film chip.
- the system is optionally sintered at 200-280°C for 20 minutes in a sintering furnace, so that the substrate and the chip are interconnected.
- the test result shows that the porosity after sintering is further increased to less than 20% by using the chip and substrate system interconnected by the discontinuous copper film.
- This embodiment provides a chip substrate connection structure and method using periodic multilayer nano metal films, as shown in FIG. 4.
- the multi-layer discontinuous metal film includes:
- the first organic medium material layer is the first organic medium material layer
- the second organic medium material layer is the second organic medium material layer
- the first organic medium material layer contains first-size nano metal particles
- the first organic medium material layer contains second-size nano metal particles
- the first size nano metal particles and the second size nano metal particles have different diameters.
- the first material layer and the second material layer have different length, width and height dimensions
- the nano metal particle material is copper.
- the nano metal particle material is gold, palladium, silver, copper, aluminum, silver-palladium alloy, gold-palladium alloy, copper-silver alloy, copper-silver-nickel alloy or copper-aluminum alloy.
- the method for sintering interconnections using a multilayer discontinuous metal film specifically includes the following steps:
- Step 1 Preparation of multilayer metal film A, B;
- Step 2 Cut the metal film to obtain N metal film small pieces b (number 10 in FIG. 4);
- Step 3 Paste the metal film A on the bottom of the chip to be interconnected and dry
- Step 4 Paste the N metal film pieces b on the bottom of the metal film A according to the designed arrangement, and dry;
- Step 5 Paste another metal film A to the bottom of the n metal film pieces b, and dry;
- Step 6 heating the chip with the metal film attached to obtain a chip with the metal film attached
- Step 7 Interconnect the substrate and the metal film chip.
- test results show that using the discontinuous copper film interconnected chip and substrate system, the porosity after sintering is increased to less than 20%, and the gas is effectively discharged.
- the original continuous metal film is set into a plurality of discontinuous small pieces and arranged in a pre-designed arrangement between the chip and the substrate, discretely arranged
- the gap between the small pieces of the cloth can be used as a channel for gas exhaust during sintering, which is beneficial to the improvement of the compactness after sintering, thereby improving the thermal conductivity of the interconnection layer; at the same time, as the sintering progresses, the metal film small pieces are If it is restricted, it will deform in the x and y directions and contact each other to form a dense sintered layer.
- the discontinuous multi-sheet metal film structure adopted by the present invention can effectively reduce the tilt problem in the chip bonding process. Therefore, the structure and process are also suitable for interconnecting power chips of larger sizes in the future.
- Nano metal particles prepared by chemical methods in the packaging field are difficult to achieve the preparation and subsequent stable retention of nano metal particles with a particle size of less than 20 nm or even less than 1 nm. Although the operation and environment are strictly controlled, the particle size range of the same batch is still There are technical problems of poor distribution concentration and large dispersion, which will affect the performance of the metal film after sintering to varying degrees.
- the above-mentioned metal particle size design adopted in the present invention achieves the effects of improving the compactness of the metal layer and reducing the porosity after sintering, which cannot be achieved by the combination of nano metal particles of other diameter sizes.
- the present invention preferably uses nano-copper instead of nano-silver materials, thereby effectively reducing the material and processing of interconnect packaging cost.
- the sintering nano-copper film made of nano-copper powder and paste has the excellent characteristics of copper materials, but also has the portability and easy formability of metal sintered films. It is the first choice for the next generation of electrical interconnection.
- the discontinuous nano metal sintered film for chip solidification and the method provided by the present invention solve the problems of high porosity, low thermal conductivity and chip tilt of the original metal sintered film, which is beneficial to the improvement of compactness after sintering and improves
- the thermal conductivity of the interconnection layer is improved, and it is the first choice for the next generation of electrical interconnection.
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Abstract
Description
Claims (18)
- 一种芯片互连结构,其特征在于,包括:芯片,N个纳米金属膜小片,N≥2,基板,所述纳米金属膜小片包括第一尺寸纳米金属颗及第二尺寸纳米金属颗粒,所述第一尺寸纳米金属颗粒与所述第二尺寸纳米金属颗粒直径不同。
- 如权利要求1所述利用纳米金属膜的芯片基板连接结构,其特征在于,所述纳米金属颗粒材料为铜。
- 如权利要求1所述芯片互连结构,其特征在于,所述纳米金属颗粒材料为金、钯、银、铜、铝、银钯合金、金钯合金、铜银合金、铜银镍合金或铜铝合金。
- 如权利要求1所述芯片互连结构,其特征在于,所述第一尺寸纳米金属颗粒与所述第二尺寸纳米金属颗粒中,较大尺寸的纳米金属颗粒直径为1nm<D<10μm;所述第一尺寸纳米金属颗粒与所述第二尺寸纳米金属颗粒中,较小尺寸的纳米金属颗粒直径为0.5nm<d<20nm。
- 如权利要求1所述芯片互连结构,其特征在于,所述纳米金属膜小片位于芯片和基板之间,纳米金属膜小片之间间隔排列;芯片和基板之间排列有一层或多层纳米金属膜小片并且多层纳米金属膜小片的不同层之间具有连续的纳米金属膜。
- 如权利要求5所述芯片互连结构,其特征在于,所述N个单层纳米金属小片按照长A 1个,宽B 1个排列,N=A 1*B 1。
- 如权利要求5所述芯片互连结构,其特征在于,所述N个多层纳米金属小片按照长A 2个,宽B 2个排列,N=A 2*B 2。
- 如权利要求7所述芯片互连结构,其特征在于,所述多层纳米金属小片包括:第一有机介质材料层,第二有机介质材料层;所述第一有机介质材料层中包含第一尺寸纳米金属颗粒,所述第一有机介质材料层中包含第二尺寸纳米金属颗粒;所述第一尺寸纳米金属颗粒与第二尺寸纳米金属颗粒直径不同。
- 如权利要求5所述芯片互连结构,其特征在于,所述多层的纳米金属膜小片分布方式为:第一金属膜层,所述第一金属膜层包括长A 31个,宽B 31个排列的单层纳米金属膜小片或多层纳米金属膜小片,N 1=A 31*B 31;第二金属膜层,所述第二金属膜层包括长A 32个,宽B 32个排列的单层纳米金属膜小片或多层纳米金属膜小片,N 2=A 32*B 32;……第n金属膜层,所述第n金属膜层包括长A 3n个,宽B 3n个排列的单层纳米金属膜小片或多层纳米金属膜小片,N n=A 3n*B 3n;N=N 1+N 2+…+N n。
- 一种芯片互连结构连接方法,其特征在于,包括:步骤1:制备纳米金属膜,所述纳米金属膜包括第一尺寸纳米金属颗及第二尺寸纳米金属颗粒,所述第一尺寸纳米金属颗粒与所述第二尺寸纳米金属颗粒直径不同;步骤2:切割所述纳米金属膜,获得N个纳米金属膜小片;步骤3:将所述纳米金属膜小片一面和芯片底部贴合;步骤4:将基板和纳米金属膜小片的另一面贴合;步骤5:将芯片和基板互连。
- 如权利要求10所述芯片互连结构连接方法,其特征在于,所述纳米金属颗粒材料为铜。
- 如权利要求10所述芯片互连结构连接方法,其特征在于,所述纳米金属颗粒材料为金、钯、银、铜、铝、银钯合金、金钯合金、铜银合金、铜银镍合金或铜铝合金。
- 如权利要求10所述芯片互连结构连接方法,其特征在于,所述第一尺寸纳米金属颗粒与所述第二尺寸纳米金属颗粒中,较大尺寸的纳米金属颗粒直径为1nm<D<10μm;所述第一尺寸纳米金属颗粒与所述第二尺寸纳米金属颗粒中,较小尺寸的纳米金属颗粒直径为0.5nm<d<20nm。
- 如权利要求10所述芯片互连结构连接方法,其特征在于,所述纳米金属膜小片位于芯片和基板之间,纳米金属膜小片之间间隔排列;芯片和基板之间排列有一层或多层纳米金属膜小片并且多层纳米金属膜小片的不同层之间具有连续的纳米金属膜。
- 如权利要求14所述芯片互连结构连接方法,其特征在于,所述一层的纳米金属膜小片分布方式包括:将所述纳米金属膜小片按照长A个,宽B个贴至芯片底部。
- 如权利要求14所述芯片互连结构连接方法,其特征在于,所述多层的纳米金属膜小片分布方式包括:将所述长A 31个,宽B 31个共N 1个金属膜小片按照设计排列黏贴至所述芯片底部,然后进行干燥处理,获得第一金属膜层;将所述长A 32个,宽B 32个共N 2个金属膜小片按照设计排列黏贴至所述第一金属膜层底部,然后进行干燥处理,获得第二金属膜层;……将所述长A 3n个,宽B 3n个共N n个金属膜小片按照设计排列黏贴至所述第n-1金属膜层底部,然后进行干燥处理,获得第n金属膜层。
- 如权利要求10所述芯片互连结构连接方法,其特征在于,所述步骤3、步骤4还包括干燥处理。
- 如权利要求10所述芯片互连结构连接方法,其特征在于,所述步骤5还包括:步骤5.1:剥离支撑基材;步骤5.2:将所述贴好多层金属膜的芯片置于基板上;步骤5.3:在烧结炉中对多层金属膜芯片进行加热,选择有无压力辅助,互连基板与多层金属膜芯片。
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CN111446045B (zh) * | 2020-05-27 | 2021-12-10 | 北京康普锡威科技有限公司 | 混合尺寸纳米铜膏及其制备方法 |
CN111933603A (zh) * | 2020-06-28 | 2020-11-13 | 深圳第三代半导体研究院 | 一种半导体芯片封装结构及其制备方法 |
CN111942726B (zh) * | 2020-06-29 | 2022-04-19 | 深圳第三代半导体研究院 | 一种烧结工艺 |
CN116190269B (zh) * | 2023-02-14 | 2023-12-26 | 纳宇半导体材料(宁波)有限责任公司 | 一种芯片粘结和封装互连工艺用保护装置及互连方法 |
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CN104668551A (zh) * | 2015-01-28 | 2015-06-03 | 哈尔滨工业大学深圳研究生院 | 一种用作热界面材料的双峰分布纳米银膏及其制备方法 |
US20170062379A1 (en) * | 2015-08-26 | 2017-03-02 | Apple Inc. | Anisotropic conductive film structures |
CN110071050A (zh) * | 2019-04-24 | 2019-07-30 | 深圳第三代半导体研究院 | 一种芯片互连结构及其制备方法 |
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CN113782505A (zh) * | 2021-09-24 | 2021-12-10 | 哈尔滨工业大学 | 一种金刚石散热片的表面平滑化及连接方法 |
CN113782505B (zh) * | 2021-09-24 | 2022-11-01 | 哈尔滨工业大学 | 一种金刚石散热片的表面平滑化及连接方法 |
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