WO2020206930A1 - 阵列基板母板 - Google Patents

阵列基板母板 Download PDF

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Publication number
WO2020206930A1
WO2020206930A1 PCT/CN2019/105462 CN2019105462W WO2020206930A1 WO 2020206930 A1 WO2020206930 A1 WO 2020206930A1 CN 2019105462 W CN2019105462 W CN 2019105462W WO 2020206930 A1 WO2020206930 A1 WO 2020206930A1
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WO
WIPO (PCT)
Prior art keywords
capacitors
switching transistors
array substrate
switching
electrode plate
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PCT/CN2019/105462
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English (en)
French (fr)
Inventor
李文英
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020206930A1 publication Critical patent/WO2020206930A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present disclosure relates to the field of liquid crystal display technology, and in particular to an array substrate mother board.
  • Liquid crystal displays have become display terminals for mobile communication equipment, computers, televisions, etc., due to their high display quality, low price, and convenient portability.
  • Due to the array gate drive (Gate The driver On Array (GOA) technology can simplify the manufacturing process of the display panel, eliminate the binding process in the horizontal scan line direction, increase productivity, reduce product costs, and improve the integration of the display panel, making it more suitable for making narrow bezels or Borderless display products to meet the visual pursuit of modern people, therefore, various LCD manufacturers have gradually adopted GOA technology as the LCD panel drive technology.
  • GOA Gate On Array
  • the liquid crystals need to be aligned to form a pretilt angle.
  • This process needs to be powered on while UV light is applied to complete. Therefore, the power-on signal contact points (that is, pads, or electrodes) required for power-on are considered during the design of the display panel, so that the external power supply can provide the signals required by the display panel.
  • the GOA signal required for a single display panel is at least a dozen to twenty. Therefore, a large glass substrate requires more power-on signal contact points.
  • the size of a large glass substrate is generally 2200*2500mm, and approximately 18 32-inch (inch) display panels can be cut out.
  • each display panel needs to drive two box test signal contact points (16*2 in total). Therefore, the box test signal contact points required for this large glass substrate are 18 *16*2 pcs.
  • a photo-curing process is carried out, so it is necessary to add one signal contact point required by the switching transistor to each group of signal contact points. Therefore, the entire large glass substrate requires 18 Switch transistors.
  • the reason why so many signal contact points need to be added is that the signals provided by the array test and the box test to the display panel are all AC/DC signals with timing. Therefore, the signals provided There are many types and numbers.
  • the high-frequency clock signals CK1 to CK6 and the low-frequency signals LC1 and LC2 are different signals.
  • the signals provided are all DC signals, and the above-mentioned high-frequency clock signals CK1 to CK6 may be the same DC signals. Therefore, during the photocuring process, the different high-frequency clock signals CK1 ⁇ CK6 provided to the display panel can be combined into the same signal, that is, only a single signal contact point is required, and the entire test signal contact point can be greatly reduced .
  • the self-heating effect produced by it is more serious, and it may even be burnt directly during the power supply process and cannot be used.
  • the etching speed and the etching speed in the plane are different, which may also easily cause the specific instability of the manufactured switching transistor, and thus produce abnormal switching characteristics. The problem.
  • the purpose of the present disclosure is to provide an array substrate mother board, by optimizing the design of the signal lead-in area in the array substrate mother plate, so as to ensure the normal function of the switching transistor in the signal lead-in area and the normal light curing process.
  • the present disclosure provides an array substrate mother board, which includes a plurality of display panels and at least one signal lead-in area.
  • the signal lead-in area includes a plurality of first switching transistors, a plurality of first capacitors, and A second capacitor; the first gate of each of the first switching transistors is respectively connected to the first input terminal of an external controller, the second electrode plate of each of the first capacitors and each of the first The first electrode plate of the two capacitors; the first source of each first switch transistor is connected to the second input terminal of the controller and the corresponding first electrode plate of the first capacitor; each The first drain of the first switching transistor is respectively connected to the corresponding display panel and the corresponding second electrode plate of the second capacitor; each display panel includes a plurality of second switching transistors, and the display The second switching transistor of the panel is of the same type as the first switching transistor of the signal lead-in region, and the width of the second channel region of the second switching transistor is smaller than the first channel of the first switching transistor Zone width; the first input terminal is used to
  • the present disclosure provides an array substrate motherboard.
  • the array substrate motherboard includes a plurality of display panels and at least one signal lead-in area.
  • the signal lead-in area includes a plurality of first switching transistors, multiple A first capacitor and a plurality of second capacitors; the first gate of each of the first switching transistors is respectively connected to the first input terminal of an external controller and the second electrode plate of each of the first capacitors And the first electrode plate of each of the second capacitors, the first source of each of the first switching transistors are respectively connected to the second input terminal of the controller and the corresponding first capacitor of the first capacitor Electrode plate; the first drain of each of the first switching transistors is respectively connected to the corresponding display panel and the corresponding second electrode plate of the second capacitor.
  • each of the display panels includes a plurality of second switching transistors, and the second switching transistors of the display panel are of the same type as the first switching transistors of the signal lead-in area
  • the width of the second channel region of the second switching transistor is smaller than the width of the first channel region of the first switching transistor.
  • the first switch transistor and the second switch transistor are both PMOS transistors.
  • the array substrate motherboard includes a base substrate, all the first switching transistors, all the second switching transistors, all the first capacitors, and all the second capacitors Are all disposed on the base substrate, each of the first switching transistors includes a first gate, a first source, and a first drain, and each of the second switching transistors includes a second gate, a second Source and second drain; all the first gates, all the second gates, all the second electrode plates of the first capacitors and all the first electrode plates of the second capacitors are in the same layer All the first source, all the second source and the first electrode plates of all the first capacitors are arranged in the same layer; all the first drains, all the second drains and The second electrode plates of all the second capacitors are arranged in the same layer.
  • each of the first switching transistors further includes a first gate insulating layer and a first active layer that are stacked, and the first gate insulating layer and the first active layer The layer is arranged between the first gate and the first source and the first drain; each of the second switching transistors further includes a second gate insulating layer and a second active The second gate insulating layer and the second active layer are arranged between the second gate and the second source and the second drain.
  • the first channel region of each of the first switching transistors is located on the top of the first active layer and between the first source and the first drain
  • the second channel region of the second switching transistor is located on the top of the second active layer and between the second source and the second drain.
  • the first input terminal is used to receive a switch control signal
  • the switch control signal is used to control the corresponding first switch transistor to turn on.
  • the second input terminal is used to receive a clock signal.
  • the turn-on voltage of all the first switch transistors is 1V.
  • the width of the first channel region of all the first switching transistors ranges from 200 ⁇ m to 2000 ⁇ m, and the width of the second channel region of all the second switching transistors is 20 ⁇ m.
  • the advantage of the present disclosure is that the array substrate mother board of the present disclosure optimizes the design of the signal lead-in area in the array substrate mother plate to ensure that the first switching transistor in the signal lead-in area functions normally, and the light curing process is normal .
  • FIG. 1 is a schematic diagram of the structure of an array substrate mother board in an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of the principle of the signal method given by the light curing process of the display panel in the embodiment of the present disclosure.
  • FIG 3 is a schematic cross-sectional view of the first switching transistor, the second switching transistor, the first capacitor, and the second capacitor in the array substrate motherboard in the embodiment of the present disclosure.
  • the embodiments of the present disclosure provide an array substrate mother board. The detailed description will be given below.
  • the present disclosure provides an array substrate mother board.
  • the array substrate mother board 400 includes a plurality of display panels 420 and at least one signal introduction area 410. As shown in FIG. 1, in this embodiment, there are six signal lead-in areas 410, and two sides of the array substrate motherboard 400 are respectively provided, and three are respectively provided on each side. Of course, in some other embodiments, the number of the signal lead-in area may also be one. In addition, the number of the display panels 420 is eighteen. The number of the display panels 420 and the number of the signal lead-in areas 410 can be determined according to actual needs, and are not limited to the number in this embodiment.
  • the signal introduction area 410 includes a plurality of first switch transistors 412, a plurality of first capacitors 413 and a plurality of second capacitors 414.
  • the first gate 452 of each first switching transistor 412 is connected to the first input terminal 431 of an external controller 430, the second electrode plate 454 of each first capacitor 413, and each The first electrode plate 455 of the second capacitor 414, the first source 458 of each first switch transistor 412 is connected to the second input terminal 432 of the controller 430 and the corresponding first capacitor 413
  • the first electrode plate 462, and the first drain 459 of each of the first switching transistors 412 are respectively connected to the corresponding display panel 420 and the corresponding second electrode plate 463 of the second capacitor 414.
  • the first input terminal 431 is used to receive a switch control signal Switch, and the switch control signal is used to control the corresponding first switch transistor 412 to turn on.
  • the second input terminal 432 is used to receive a clock signal CK.
  • the second input terminal 432 may also receive other control signals, such as a low-frequency control signal (LC1 signal).
  • each of the display panels 420 includes a plurality of second switch transistors 421, the second switch transistors 421 of the display panel 420 and the first switch of the signal lead-in area 410
  • the transistors 412 are of the same type.
  • the first switching transistor 412 and the second switching transistor 421 are both PMOS transistors, that is, both are low-conduction transistors.
  • the first switch transistor 412 and the second switch transistor 421 are both NMOS transistors, that is, both are high-conduction transistors.
  • first switch transistor 412 the second switch transistor 421, the first capacitor 413, and the second capacitor 414 will be further described below.
  • the array substrate mother board 400 includes a base substrate 451, and all the first switching transistors 412, all the second switching transistors 421, all the first capacitors 413, and all the second capacitors 414 are Set on the same base substrate 451.
  • the base substrate 451 may be a glass substrate, a plastic substrate or a base substrate thereof.
  • each of the first switching transistors 412 includes a first gate 452, a first source 458, and a first drain 459
  • each of the second switching transistors 421 includes a second gate 453 and a second source. 460 and second drain 461.
  • All the first gates 452, all the second gates 453, all the second electrode plates 454 of the first capacitor 413, and all the first electrode plates 455 of the second capacitor 414 are arranged in the same layer.
  • All the first source electrodes 458, all the second source electrodes 460 and all the first electrode plates 462 of the first capacitor 413 are arranged in the same layer.
  • All the first drain electrodes 459, all the second drain electrodes 461 and all the second electrode plates 463 of the second capacitor 414 are arranged in the same layer.
  • first electrode plate 462 of the first capacitor 413 can be connected to the first source 458 (or its metal trace) through a metal trace, and is connected to the second electrode of the first capacitor 413
  • the plate 454 is arranged correspondingly.
  • the second electrode plate 463 of the second capacitor 414 can be connected to the first drain 459 (or its metal trace) through a metal trace, and is connected to the second capacitor 414
  • the first electrode plate 455 is correspondingly arranged.
  • the connection manner of the first electrode plate 462 of the first capacitor 413 and the first source 458 is not limited to the above manner.
  • the connection method is not limited to the above method.
  • each of the first switching transistors 412 further includes a first gate insulating layer 456 and a first active layer 457 that are stacked, each of the first gate insulating layer 456 and the first active layer 457 is arranged between the first gate 452 and the first source 458 and the first drain 459.
  • the first channel region A of the first switching transistor 412 is located on the top of the first active layer 457 and in the region between the first source 458 and the first drain 459.
  • each of the second switching transistors 421 further includes a second gate insulating layer 457 and a second active layer 458 (because the second gate insulating layer 457 and the first gate insulating layer 457 use the same material The production is completed at the same time, so the same reference number is used.
  • each of the second gate insulating layer 457 and the first Two active layers 458 are provided between the second gate 453 and the second source 460 and the second drain 461.
  • the second channel region B of the second switching transistor 421 is located on the top of the second active layer 458 and in the region between the second source electrode 460 and the second drain electrode 461.
  • the width of the second channel region B of the second switching transistor 421 is smaller than the width of the first channel region A of the first switching transistor 412.
  • the width of the first channel region A of the first switching transistor 412 ranges from 200 ⁇ m to 2000 ⁇ m, and the width of the second channel region B of the second switching transistor 421 is 20 ⁇ m.
  • the channel width of the switching transistor of the existing signal lead-in region 410 is generally 20000 ⁇ m.
  • the first channel width A of the first switching transistor 412 in this disclosure is 200 ⁇ m to 2000 ⁇ m, the channel width is common, and the first channel width A of the first switching transistor 412 in the signal introduction area 410 differs from the second channel width B of the second switching transistor 421 in the display panel 420 by 1 to 2 orders of magnitude, so that it is easier to achieve in production. That is to say, the channel width of the switching transistor in the existing signal lead-in area is generally 20000 ⁇ m. Therefore, the etching speed in the process of making the channel of the signal lead-in area is relatively different from that of the channel of the display panel 420.
  • the process of the first switching transistor 412 of the signal introduction area 410 of the present disclosure is basically the same as that of the second switching transistor 421 of the display panel 420, thereby enhancing the controllability of the process and ensuring the first switching transistor of the signal introduction area 410 412 functions normally.
  • the width of the channel region A of the first switching transistor 412 of the present disclosure is smaller than the channel width of the existing switching transistor, the first switching transistor 412 of the present disclosure can be turned on with a relatively small voltage, for example, The turn-on voltage of the first switch transistor 412 is 1V, and the turn-on voltage of the existing switch transistor is 5V. In this way, the power consumption of the signal introduction area 410 in the present disclosure is lower.
  • the first gate 452, the second gate 453, the second electrode plate 454 of the first capacitor 413, and the first electrode plate 455 of the second capacitor 414 are in the same layer.
  • the first source 458, the second source 460 and the first electrode plate 462 of the first capacitor 413 are arranged in the same layer.
  • the first drain 459, the second drain 461 and the second electrode plate 463 of the second capacitor 414 are arranged in the same layer. That is, in the signal lead-in area 410, the first switch transistor 412 is connected to the first capacitor 413 and the second capacitor 414, respectively.
  • the charges are first stored in the first capacitor 413 and the second capacitor 414, and these charges can pass through the second capacitor after the signal source of the gate of the first switching transistor 412 is turned off.
  • a capacitor 413 and a second capacitor 414 are continuously discharged to provide the display panel 420 to supplement the signal loss during the transmission process, so as to realize the purpose of turning on the first switching transistor 412 and transmitting the signal to the display panel 420.
  • the ability to transmit signals (for example, clock signals) can be enhanced.
  • the channel region width A of the first switching transistor 412 of the signal introduction region 410 in the present disclosure is smaller than the channel region width of the existing switching transistor and the driving force is relatively small, the first switching transistor 412 cooperates with the first switching transistor.
  • the operation of the capacitor 413 and the second capacitor 414 can reduce the loss in the process of transmitting signals (for example, clock signals) while ensuring the driving force required for testing the display panel 420.
  • the first switch transistor 412 works in conjunction with the first capacitor 413 and the second capacitor 414 to provide sufficient driving force, the first switch transistor 412 can drive multiple display panels 420 at the same time, for example, three display panels. The panel 420, but not limited thereto. That is, when the first switching transistor 412 is turned on, the clock signal can be simultaneously transmitted to the three display panels 420 for light curing (HVA curing).
  • the signal introduction area 410 uses the first capacitor 413 and the second capacitor 414, it can also effectively prevent the signal interference effect of the ITO electrode on the switching transistor in the signal transmission process in the prior art, thereby further improving the signal transmission effect , And also ensure the normal light curing process. That is to say, the improved design of the first switching transistor 412 in the signal introduction area 410 of the present disclosure can not only realize the normal formation of the liquid crystal pretilt angle of the display panel 420 after the cell is formed, but also will not be caused by the serious spontaneous combustion effect of the switching transistor. The problem of not being able to give the required signal for the normal pretilt angle.
  • the subject of this application can be manufactured and used in industry and has industrial applicability.

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Abstract

一种阵列基板母板，该阵列基板母板包括多个显示面板和至少一信号引入区，信号引入区包括多个第一开关晶体管、多个第一电容和多个第二电容；每一第一开关晶体管的第一栅极分别连接至一外部的控制器的第一输入端、每一第一电容的第二电极板和每一第二电容的第一电极板；每一第一开关晶体管的第一源极分别连接至控制器的第二输入端和对应的第一电容的第一电极板；每一第一开关晶体管的第一漏极分别连接至对应的显示面板和对应的第二电容的第二电极板，每一显示面板包括多个第二开关晶体管，第二开关晶体管的第二沟道区宽度小于第一开关晶体管的第一沟道区宽度，通过对信号引入区进行优化设计，以保证信号引入区的开光晶体管功能正常，并且保证光固化制程正常。

Description

阵列基板母板 技术领域
本揭示涉及液晶显示技术领域，尤其涉及一种阵列基板母板。
 背景技术
液晶显示器以其高显示品质、价格低廉、携带方便等优点而成为移动通讯设备、电脑、电视等的显示终端。由于阵列栅极驱动(Gate driver On Array，简称GOA)技术能够简化显示面板的制作工序，省去水平扫描线方向的绑定工艺，提升产能、降低产品成本，同时提升显示面板的集成度，使之更适合制作窄边框或无边框显示产品，以满足现代人们的视觉追求，因此，各液晶显示厂商已逐渐采用GOA技术作为液晶显示器的面板驱动技术。
在显示面板制造过程中，阵列基板和彩膜基板合成后，需要对液晶进行配向以形成预倾角。此工序需要加电同时进行UV光照才能完成。于是，在显示面板设计时会考虑加电所需的加电信号接触点（即pad，或称电极），以使外部电源提供显示面板所需的信号。随着GOA技术的引入，单个显示面板所需的GOA信号至少在十几个至二十几个，因此，一个大型玻璃基板需要更多的加电信号接触点。
例如在一个G8.5面板的生产线中，大型玻璃基板的尺寸一般为2200*2500mm，大致可切割出18块32英寸（inch）的显示面板。每个显示面板在成盒测试(即检测面板是否正常)中，需要驱动两组成盒测试信号接触点（共16*2个），因此，该大型玻璃基板需要的成盒测试信号接触点为18*16*2个。另外，在成盒后液晶形成预倾角过程中，会进行光固化制程，于是需要在每组的信号接触点中增加1个开关晶体管所需的信号接触点，因此，整个大型玻璃基板需要18个开关晶体管。在阵列测试和成盒测试中，需要添加如此多的信号接触点的原因在于，阵列测试和成盒测试所提供给显示面板的信号均为具有时序的交流/直流信号，因此，所提供的信号种类多，数量也多，例如高频时钟信号CK1～CK6、低频信号LC1、LC2为不同信号。而在光固化制程时，所提供的信号均为直流信号，上述的高频时钟信号CK1～CK6可以为相同的直流信号。于是，在进行光固化制程时，可以将提供给显示面板的不同高频时钟信号CK1～CK6合并为相同的信号，即仅需单个信号接触点，进而整个测试信号接触点可以大幅度地减小。
对于单个显示面板而言，可以通过一个开关晶体管将所有使用相同信号的信号线合并为一条信号线。这种设计方案中的开关晶体管为超大型晶体管。因此，例如32inch显示面板，开关晶体管的沟道宽度W=50000um，若显示面板尺寸更大，则开关晶体管的沟道宽度会更大，这是由于从信号测试点所输入的一个相同信号，若不计算信号线等阻抗，该信号要能够驱动相当于3个显示面板的负载，因此，为了能够足够的驱动力，在实际使用中，会采用超大型开关晶体管来加以实施。
 技术问题
然而，当使用超大型开关晶体管时，由于其产生的自热效应比较严重，甚至在给电过程中可能会被直接烧毁而无法使用。而且，超大型开关晶体管在其制备过程中，尤其是做作沟道过程中，刻蚀速度和面内的刻蚀速度不同，也容易造成制成的开关晶体管的特定不稳定，进而产生开关特性异常的问题。
因此，如何通过对现有用于GOA显示面板的外围电路的改进，以降低超大型开关晶体管所造成的较严重自热效应、光固化功能失效等风险，是液晶显示技术发展过程中亟待解决的问题。
 技术解决方案
本揭示的目的在于，提供一种阵列基板母板，通过对所述阵列基板母板中的信号引入区进行优化设计，以保证的信号引入区的开关晶体管功能正常，并且保证光固化制程正常。
根据本揭示的一方面，本揭示提供一种阵列基板母板，其中包括多个显示面板和至少一信号引入区，所述信号引入区包括多个第一开关晶体管、多个第一电容和多个第二电容；每一所述第一开关晶体管的第一栅极分别连接至一外部的控制器的第一输入端、每一所述第一电容的第二电极板和每一所述第二电容的第一电极板；每一所述第一开关晶体管的第一源极分别连接至所述控制器的第二输入端和对应的所述第一电容的第一电极板；每一所述第一开关晶体管的第一漏极分别连接至对应的所述显示面板和对应的所述第二电容的第二电极板；每一所述显示面板包括多个第二开关晶体管，所述显示面板的所述第二开关晶体管与所述信号引入区的所述第一开关晶体管的类型相同，所述第二开关晶体管的第二沟道区宽度小于所述第一开关晶体管的第一沟道区宽度；所述第一输入端用于接收一开关控制信号，所述开关控制信号用于控制对应的第一开关晶体管导通；所述第二输入端用于接收一时钟信号。
根据本揭示的另一方面，本揭示提供一种阵列基板母板，所述阵列基板母板包括多个显示面板和至少一信号引入区，所述信号引入区包括多个第一开关晶体管、多个第一电容和多个第二电容；每一所述第一开关晶体管的第一栅极分别连接至一外部的控制器的第一输入端、每一所述第一电容的第二电极板和每一所述第二电容的第一电极板，每一所述第一开关晶体管的第一源极分别连接至所述控制器的第二输入端和对应的所述第一电容的第一电极板；每一所述第一开关晶体管的第一漏极分别连接至对应的所述显示面板和对应的所述第二电容的第二电极板。
在本揭示的一实施例中，每一所述显示面板包括多个第二开关晶体管，所述显示面板的所述第二开关晶体管与所述信号引入区的所述第一开关晶体管的类型相同，所述第二开关晶体管的第二沟道区宽度小于所述第一开关晶体管的第一沟道区宽度。
在本揭示的一实施例中，所述第一开关晶体管和所述第二开关晶体管均为PMOS管。
在本揭示的一实施例中，所述阵列基板母板包括一衬底基板，所有所述第一开关晶体管、所有所述第二开关晶体管、所有所述第一电容和所有所述第二电容均设置在所述衬底基板上，每一所述第一开关晶体管包括第一栅极、第一源极和第一漏极，每一所述第二开关晶体管包括第二栅极、第二源极和第二漏极；所有所述第一栅极、所有所述第二栅极、所有所述第一电容的第二电极板和所有所述第二电容的第一电极板为同层设置；所有所述第一源极、所有所述第二源极和所有所述第一电容的第一电极板为同层设置；所有所述第一漏极、所有所述第二漏极和所有所述第二电容的第二电极板为同层设置。
在本揭示的一实施例中，每一所述第一开关晶体管还包括层叠设置的第一栅极绝缘层和第一有源层，所述第一栅极绝缘层和所述第一有源层设置在所述第一栅极与所述第一源极和所述第一漏极之间；每一所述第二开关晶体管还包括层叠设置的第二栅极绝缘层和第二有源层，所述第二栅极绝缘层和第二有源层设置在所述第二栅极与所述第二源极和所述第二漏极之间。
在本揭示的一实施例中，每一所述第一开关晶体管的第一沟道区位于所述第一有源层的顶部且在所述第一源极和所述第一漏极之间的区域，所述第二开关晶体管的第二沟道区位于所述第二有源层的顶部且在所述第二源极和所述第二漏极之间的区域。
在本揭示的一实施例中，所述第一输入端用于接收一开关控制信号，所述开关控制信号用于控制对应的第一开关晶体管导通。
在本揭示的一实施例中，所述第二输入端用于接收一时钟信号。
在本揭示的一实施例中，所有所述第一开关晶体管的开启电压为1V。
在本揭示的一实施例中，所有所述第一开关晶体管的第一沟道区宽度范围为200µm至2000µm，所有所述第二开关晶体管的第二沟道区宽度为20µm。
 有益效果
本揭示的优点在于，本揭示所述阵列基板母板通过对所述阵列基板母板中的信号引入区进行优化设计，以保证信号引入区的第一开关晶体管功能正常，并且保证光固化制程正常。
 附图说明
为了更清楚地说明本揭示实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本揭示的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本揭示一实施例中的阵列基板母板的结构示意图。
图2是本揭示所述实施例中的显示面板进行光固化制程所给信号方式的原理示意图。
图3是本揭示所述实施例中的阵列基板母板中的第一开关晶体管、第二开关晶体管、第一电容、第二电容的截面示意图。
 本发明的实施方式
下面将结合本揭示实施例中的附图，对本揭示实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本揭示一部分实施例，而不是全部的实施例。基于本揭示中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本揭示保护的范围。
本揭示的说明书和权利要求书以及上述附图中的术语“第一”、“第二”、“第三”等（如果存在）是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应当理解，这样描述的对象在适当情况下可以互换。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含。
在本专利文档中，下文论述的附图以及用来描述本揭示公开的原理的各实施例仅用于说明，而不应解释为限制本揭示公开的范围。所属领域的技术人员将理解，本揭示的原理可在任何适当布置的系统中实施。将详细说明示例性实施方式，在附图中示出了这些实施方式的实例。此外，将参考附图详细描述根据示例性实施例的终端。附图中的相同附图标号指代相同的元件。
本揭示说明书中使用的术语仅用来描述特定实施方式，而并不意图显示本揭示的概念。除非上下文中有明确不同的意义，否则，以单数形式使用的表达涵盖复数形式的表达。在本揭示说明书中，应理解，诸如“包括”、“具有”以及“含有”等术语意图说明存在本揭示说明书中揭示的特征、数字、步骤、动作或其组合的可能性，而并不意图排除可存在或可添加一个或多个其他特征、数字、步骤、动作或其组合的可能性。附图中的相同参考标号指代相同部分。
本揭示实施例提供一种阵列基板母板。以下将分别进行详细说明。
参阅图1至图3。本揭示提供一种阵列基板母板，所述阵列基板母板400包括多个显示面板420和至少一信号引入区410。如图1所示，在本实施例中，所述信号引入区410为六个，且分别设置所述阵列基板母板400的两侧，每一侧分别设置三个。当然，在其他部分实施例中，所述信号引入区的数量也可以为一个。另外，所述显示面板420的数量为十八个。所述显示面板420的数量和信号引入区410的数量可以根据实际需要而确定，而不仅限于本实施例中的数量。
如图2所示，所述信号引入区410包括多个第一开关晶体管412、多个第一电容413和多个第二电容414。每一所述第一开关晶体管412的第一栅极452分别连接至一外部的控制器430的第一输入端431、每一所述第一电容413的第二电极板454和每一所述第二电容414的第一电极板455，每一所述第一开关晶体管412的第一源极458分别连接至所述控制器430的第二输入端432和对应的所述第一电容413的第一电极板462，每一所述第一开关晶体管412的第一漏极459分别连接至对应的所述显示面板420和对应的所述第二电容414的第二电极板463。其中，所述第一输入端431用于接收一开关控制信号Switch，所述开关控制信号用于控制对应的第一开关晶体管412导通。所述第二输入端432用于接收一时钟信号CK，当然在其他部分实施例中，所述第二输入端432也可以接收其他控制信号，例如低频控制信号（LC1信号）。
如图3所示，在本实施例中，每一所述显示面板420包括多个第二开关晶体管421，所述显示面板420的第二开关晶体管421与所述信号引入区410的第一开关晶体管412的类型相同。例如，所述第一开关晶体管412和所述第二开关晶体管421均为PMOS管，即均为低导通晶体管。或在其他部分实施例中，所述第一开关晶体管412和所述第二开关晶体管421均为NMOS管，即均为高导通晶体管。
以下将进一步说明第一开关晶体管412、第二开关晶体管421、第一电容413、第二电容414的具体结构。
在本实施例中，所述阵列基板母板400包括一衬底基板451，所有所述第一开关晶体管412、所有所述第二开关晶体管421、所有第一电容413和所有第二电容414均设置在同一所述衬底基板451上。所述衬底基板451可以为玻璃基板、塑料基板或其衬底基板。
其中，每一所述第一开关晶体管412包括第一栅极452、第一源极458和第一漏极459，每一所述第二开关晶体管421包括第二栅极453、第二源极460和第二漏极461。所有所述第一栅极452、所有所述第二栅极453、所有所述第一电容413的第二电极板454和所有所述第二电容414的第一电极板455为同层设置。所有所述第一源极458、所有所述第二源极460和所有所述第一电容413的第一电极板462为同层设置。所有所述第一漏极459、所有所述第二漏极461和所有所述第二电容414的第二电极板463为同层设置。进一步而言，所述第一电容413的第一电极板462可以通过金属走线连接至所述第一源极458（或其金属走线），且与所述第一电容413的第二电极板454对应设置，同样，所述第二电容414的第二电极板463可以通过金属走线连接至所述第一漏极459（或其金属走线），且与所述第二电容414的第一电极板455对应设置。所述第一电容413的第一电极板462与所述第一源极458的连接方式不仅限于上述方式，同样，所述第二电容414的第二电极板463与所述第一漏极459的连接方式也不仅限于上述方式。本领域技术人员可以通过常规的方式将第一电容413、第二电容414的两个第一电极板和第二电极板与所述第一开关晶体管412的第一栅极452、第一源极458和第一漏极459相连，在此不再详述。
进一步，每一所述第一开关晶体管412还包括层叠设置的第一栅极绝缘层456和第一有源层457，每一所述第一栅极绝缘层456和所述第一有源层457设置在所述第一栅极452与所述第一源极458和所述第一漏极459之间。所述第一开关晶体管412的第一沟道区A位于所述第一有源层457的顶部且在所述第一源极458和所述第一漏极459之间的区域。同样，每一所述第二开关晶体管421还包括层叠设置的第二栅极绝缘层457和第二有源层458（由于第二栅极绝缘层457与第一栅极绝缘层457采用相同材料同时制作完成，故采用相同标号。同样，第二有源层458与第一有源层458采用相同材料同时制作完成，故采用相同标号），每一所述第二栅极绝缘层457和第二有源层458设置在所述第二栅极453与所述第二源极460和所述第二漏极461之间。所述第二开关晶体管421的第二沟道区B位于所述第二有源层458的顶部且在所述第二源极460和所述第二漏极461之间的区域。
在本实施例中，所述第二开关晶体管421的第二沟道区B宽度小于所述第一开关晶体管412的第一沟道区A宽度。具体地，例如，所述第一开关晶体管412的第一沟道区A宽度范围为200µm至2000µm，所述第二开关晶体管421的第二沟道区B宽度为20µm。现有信号引入区410的开关晶体管的沟道宽度一般为20000µm，相较于现有的沟道宽度为超大型的开关晶体管，本揭示所述第一开关晶体管412的第一沟道宽度A为200µm至2000µm，属于沟道宽度为普通型，且信号引入区410的第一开关晶体管412的第一沟道宽度A与显示面板420内的第二开关晶体管421的第二沟道宽度B相差为1至2个量级，这样，在制作上更容易实现。也就是说，现有信号引入区的开关晶体管的沟道宽度一般为20000µm，因此，在做信号引入区的沟道过程中的刻蚀速度与做显示面板420的沟道的刻蚀速度相差较大，于是会造成信号引导引入区的开关晶体管特性不稳定，并引起开关特性异常。而本揭示信号引入区410的所述第一开关晶体管412的工艺基本相同于显示面板420的第二开关晶体管421，从而增强了工艺的可控性，以及保证信号引入区410的第一开关晶体管412功能正常。另外，由于本揭示所述第一开关晶体管412的沟道区A宽度小于现有开关晶体管的沟道宽度，因此，本揭示的第一开关晶体管412可以用较小的电压使其开启，例如所述第一开关晶体管412的开启电压为1V，现有的开关晶体管的开启电压5V，这样，本揭示所述信号引入区410的功耗较低。
在本实施例中，所述第一栅极452、所述第二栅极453、所述第一电容413的第二电极板454和所述第二电容414的第一电极板455为同层设置。所述第一源极458、所述第二源极460和所述第一电容413的第一电极板462为同层设置。所述第一漏极459、所述第二漏极461和所述第二电容414的第二电极板463为同层设置。也就是说，在信号引入区410中，所述第一开关晶体管412分别与第一电容413和第二电容414相连。于是，在第一开关晶体管412为开态时，电荷会先存储于在第一电容413和第二电容414中，这些电荷会在第一开关晶体管412的栅极的信号源关闭后可以通过第一电容413和第二电容414持续地放电，以提供给显示面板420，从而补充信号在传递过程中的损耗，以实现开启第一开关晶体管412，并将信号传递至显示面板420的目的。另外,通过设置第一电容413和第二电容414能够增强输送信号（例如时钟信号）的能力。
因此，尽管本揭示所述信号引入区410的第一开关晶体管412的沟道区宽度A比现有开关晶体管的沟道区宽度小，驱动力相对较小，但是第一开关晶体管412配合第一电容413和第二电容414工作，能够保证测试显示面板420所需的驱动力的前提下，降低传送信号（例如时钟信号）过程中的损耗。此外，由于所述第一开关晶体管412配合第一电容413和第二电容414同时工作，提供足够的驱动力，因此，第一开关晶体管412可以同时驱动多个显示面板420，例如为三个显示面板420，但是不限于此。也就是说，当开启第一开关晶体管412时，可以将时钟信号同时传送至三个显示面板420，以供光固化（HVA curing）制程之用。
另外，由于信号引入区410使用了第一电容413和第二电容414，因此，也能够有效地防止现有技术在信号传递过程中ITO电极对开关晶体管的信号干扰影响，从而进一步提高信号传输效果，也保证光固化制程正常。也就是说，本揭示所述信号引入区410的第一开关晶体管412的改进设计，不仅可以实现显示面板420在成盒后液晶预倾角的正常形成,而且不会有开关晶体管自燃效应严重所引发的无法给正常预倾角所需信号的问题。
以上所述仅是本揭示的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本揭示原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本揭示的保护范围。
 工业实用性
本申请的主题可以在工业中制造和使用，具备工业实用性。

Claims (11)

  1. 一种阵列基板母板，其中包括多个显示面板和至少一信号引入区，所述信号引入区包括多个第一开关晶体管、多个第一电容和多个第二电容；每一所述第一开关晶体管的第一栅极分别连接至一外部的控制器的第一输入端、每一所述第一电容的第二电极板和每一所述第二电容的第一电极板；每一所述第一开关晶体管的第一源极分别连接至所述控制器的第二输入端和对应的所述第一电容的第一电极板；每一所述第一开关晶体管的第一漏极分别连接至对应的所述显示面板和对应的所述第二电容的第二电极板；
    每一所述显示面板包括多个第二开关晶体管，所述显示面板的所述第二开关晶体管与所述信号引入区的所述第一开关晶体管的类型相同，所述第二开关晶体管的第二沟道区宽度小于所述第一开关晶体管的第一沟道区宽度；
    所述第一输入端用于接收一开关控制信号，所述开关控制信号用于控制对应的第一开关晶体管导通；
    所述第二输入端用于接收一时钟信号。
  2. 一种阵列基板母板，其中包括多个显示面板和至少一信号引入区，所述信号引入区包括多个第一开关晶体管、多个第一电容和多个第二电容；每一所述第一开关晶体管的第一栅极分别连接至一外部的控制器的第一输入端、每一所述第一电容的第二电极板和每一所述第二电容的第一电极板；每一所述第一开关晶体管的第一源极分别连接至所述控制器的第二输入端和对应的所述第一电容的第一电极板；每一所述第一开关晶体管的第一漏极分别连接至对应的所述显示面板和对应的所述第二电容的第二电极板。
  3. 根据权利要求2所述的阵列基板母板，其中每一所述显示面板包括多个第二开关晶体管，所述显示面板的所述第二开关晶体管与所述信号引入区的所述第一开关晶体管的类型相同，所述第二开关晶体管的第二沟道区宽度小于所述第一开关晶体管的第一沟道区宽度。
  4. 根据权利要求3所述的阵列基板母板，其中所述第一开关晶体管和所述第二开关晶体管均为PMOS管。
  5. 根据权利要求3所述的阵列基板母板，其中所述阵列基板母板包括一衬底基板，所有所述第一开关晶体管、所有所述第二开关晶体管、所有所述第一电容和所有所述第二电容均设置在所述衬底基板上，每一所述第一开关晶体管包括第一栅极、第一源极和第一漏极，每一所述开关第二晶体管包括第二栅极、第二源极和第二漏极；所有所述第一栅极、所有所述第二栅极、所有所述第一电容的第二电极板和所有所述第二电容的第一电极板为同层设置；所有所述第一源极、所有所述第二源极和所有所述第一电容的第一电极板为同层设置；所有所述第一漏极、所有所述第二漏极和所有所述第二电容的第二电极板为同层设置。
  6. 根据权利要求5所述的阵列基板母板，其中每一所述第一开关晶体管还包括层叠设置的一第一栅极绝缘层和一第一有源层，所述第一栅极绝缘层和所述第一有源层设置在所述第一栅极与所述第一源极和所述第一漏极之间；每一所述第二开关晶体管还包括层叠设置的一第二栅极绝缘层和一第二有源层，所述第二栅极绝缘层和第二有源层设置在所述第二栅极与所述第二源极和所述第二漏极之间。
  7. 根据权利要求6所述的阵列基板母板，其中每一所述第一开关晶体管的第一沟道区位于所述第一有源层的顶部且在所述第一源极和所述第一漏极之间的区域；每一所述第二开关晶体管的第二沟道区位于所述第二有源层的顶部且在所述第二源极和所述第二漏极之间的区域。
  8. 根据权利要求2所述的阵列基板母板，其中所述第一输入端用于接收一开关控制信号，所述开关控制信号用于控制对应的第一开关晶体管导通。
  9. 根据权利要求2所述的阵列基板母板，其中所述第二输入端用于接收一时钟信号。
  10. 根据权利要求2所述的阵列基板母板，其中所有所述第一开关晶体管的开启电压为1V。
  11. 根据权利要求3所述的阵列基板母板，其中所有所述第一开关晶体管的第一沟道区宽度范围为200µm至2000µm，所有所述第二开关晶体管的第二沟道区宽度为20µm。
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