WO2021109370A1 - 阵列基板及其制备方法、显示面板 - Google Patents

阵列基板及其制备方法、显示面板 Download PDF

Info

Publication number
WO2021109370A1
WO2021109370A1 PCT/CN2020/081444 CN2020081444W WO2021109370A1 WO 2021109370 A1 WO2021109370 A1 WO 2021109370A1 CN 2020081444 W CN2020081444 W CN 2020081444W WO 2021109370 A1 WO2021109370 A1 WO 2021109370A1
Authority
WO
WIPO (PCT)
Prior art keywords
data line
display panel
array substrate
line
substrate
Prior art date
Application number
PCT/CN2020/081444
Other languages
English (en)
French (fr)
Inventor
郭文均
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/763,331 priority Critical patent/US11217608B2/en
Publication of WO2021109370A1 publication Critical patent/WO2021109370A1/zh

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136263—Line defects

Definitions

  • This application relates to the field of display technology, and in particular to an array substrate and a display panel.
  • the source and drain layers are used to prepare the data lines.
  • the data lines are single-sided input signals, and the signals transmitted by each signal line are different, so that the data lines cannot be cross-linked with each other. After the signal line is disconnected , It will cause the breakpoint to be far away from the signal input terminal to produce bad bright lines and affect the display.
  • the existing display panel cannot solve the technical problem of poor display caused by the disconnection of the data line.
  • the present application provides an array substrate and a display panel, which are used to solve the technical problem that the existing display panel cannot solve the poor display caused by the disconnection of the data line.
  • the present application provides an array substrate, which includes:
  • the source and drain layer is disposed on one side of the substrate, and the source and drain layer is etched to form a first data line;
  • the array substrate further includes a second data line, and the distance between the first data line and the connection hole of the second data line is at least equal to the length of one sub-pixel.
  • the array substrate further includes a second metal layer and an interlayer insulating layer, the interlayer insulating layer is disposed between the second metal layer and the source and drain layers, and the first The two metal layers are etched to form the second plate of the capacitor and the second data line, the interlayer insulating layer is formed with a first via hole, and the second data line and the first data line pass through the first via ⁇ Hole connection.
  • the array substrate further includes an active layer, the source and drain layers are etched to form a compensation signal line, and the compensation signal line has the same direction as the first data line.
  • the compensation signal line is connected to the active layer through the connection hole.
  • the interlayer insulating layer further includes second via holes, the source and drain layers are etched to form power voltage lines, and the power voltage lines in adjacent columns pass through the second via holes, respectively. The two opposite sides of the second electrode plate are connected.
  • the array substrate further includes a first metal layer, which is etched to form scan lines, a first electrode plate of a capacitor, and a compensation signal line.
  • the direction of the compensation signal line is the same.
  • the distance between the adjacent connecting holes of the first data line and the second data line is equal to twice the sum of the length of the sub-pixel and the distance between adjacent sub-pixels .
  • the distance between the adjacent connecting holes of the first data line and the second data line is equal to the sum of the length of the sub-pixel and the distance between the adjacent sub-pixels.
  • the projections of the first data line and the second data line on the substrate coincide.
  • the projection of the second data line on the substrate is located on one side of the projection of the first data line on the substrate.
  • the present application provides a display panel, which includes an array substrate, and the array substrate includes:
  • the source and drain layer is disposed on one side of the substrate, and the source and drain layer is etched to form a first data line;
  • the array substrate further includes a second data line, and the distance between the first data line and the connection hole of the second data line is at least equal to the length of one sub-pixel.
  • the display panel includes an OLED display panel.
  • the display panel includes a liquid crystal display panel.
  • the display panel further includes a second metal layer and an interlayer insulating layer, the interlayer insulating layer is disposed between the second metal layer and the source and drain layers, and the second metal layer is engraved
  • the second electrode plate of the capacitor and the second data line are formed by etching, the interlayer insulating layer is formed with a first via hole, and the second data line and the first data line are connected through the first via hole.
  • the display panel provided by the present application, it further includes an active layer, the source and drain layers are etched to form a compensation signal line, the direction of the compensation signal line is the same as the direction of the first data line, and the compensation signal line passes The connection hole is connected to the active layer.
  • the interlayer insulating layer further includes a second via hole, the source and drain layers are etched to form a power supply voltage line, and the power supply voltage lines of adjacent columns pass through the second via hole respectively. The two opposite sides of the second electrode plate are connected.
  • the display panel further includes a first metal layer.
  • the first metal layer is etched to form a scan line, a first electrode plate of the capacitor, and a compensation signal line. Go the same.
  • the distance between the adjacent connecting holes of the first data line and the second data line is equal to twice the sum of the length of the sub-pixel and the distance between the adjacent sub-pixels .
  • the distance between the adjacent connecting holes of the first data line and the second data line is equal to the sum of the length of the sub-pixel and the distance between the adjacent sub-pixels.
  • the projections of the first data line and the second data line on the substrate coincide.
  • the projection of the second data line on the substrate is located on one side of the projection of the first data line on the substrate.
  • the present application provides an array substrate and a display panel.
  • the array substrate includes a substrate and a source/drain layer.
  • the source/drain layer is disposed on one side of the substrate, and the source/drain layer is etched to form a first A data line, wherein the array substrate further includes a second data line, and the distance between the first data line and the connection hole of the second data line is at least equal to the length of one sub-pixel; and the second data line is provided in the array substrate.
  • the data line connects the first data line with the second data line, so that after the first data line is disconnected, the signal can be transmitted from the second data line, which solves the problem that the existing display panel cannot solve the display caused by the disconnection of the data line Bad technical problem.
  • FIG. 1 is a first schematic diagram of an array substrate provided by an embodiment of the application.
  • FIG. 2 is a second schematic diagram of the array substrate provided by an embodiment of the application.
  • FIG. 3 is a third schematic diagram of the array substrate provided by an embodiment of the application.
  • FIG. 4 is a first schematic diagram of the connection between the first data line and the second data line provided by an embodiment of the application.
  • FIG. 5 is a second schematic diagram of the connection between the first data line and the second data line provided by an embodiment of the application.
  • FIG. 6 is a schematic diagram of a display panel provided by an embodiment of the application.
  • the present application provides an array substrate and a display panel.
  • the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the application, and are not used to limit the application.
  • the present application aims at the technical problem that the existing display panel cannot solve the poor display caused by the disconnection of the data line, and the embodiments of the present application are used to solve the problem.
  • an array substrate which includes:
  • the source/drain layer 119 is disposed on the side of the substrate 111, and the source/drain layer is etched to form a first data line 1191;
  • the array substrate further includes a second data line 1171, and the distance between the first data line 1191 and the connection hole of the second data line 1171 is at least equal to the length of one sub-pixel.
  • An embodiment of the present application provides an array substrate.
  • the array substrate includes a substrate and a source/drain layer.
  • the source/drain layer is disposed on one side of the substrate, and the source/drain layer is etched to form first data.
  • the array substrate further includes a second data line, and the distance between the first data line and the connecting hole of the second data line is at least equal to the length of one sub-pixel; by arranging the second data line in the array substrate
  • the first data line is connected with the second data line, so that after the first data line is disconnected, the signal can be transmitted from the second data line, which solves the problem that the existing display panel cannot solve the display failure caused by the disconnection of the data line Technical issues.
  • an embodiment of the present application provides an array substrate, which includes a substrate 111, a barrier layer 112, an active layer 113, and a first gate arranged in sequence.
  • the insulating layer 114, the first metal layer 115, the second gate insulating layer 116, the second metal layer 117, the interlayer insulating layer 118, the source and drain layer 119, the first metal layer 115 is etched to form a first scan line 1151 .
  • the second scan line 1152, the third scan line 1154 and the light-emitting signal line 1153, the source and drain layer 119 is etched to form a first data line 1191, a power supply voltage line 1192 and a compensation signal line 1193.
  • the second metal layer is used to prepare the lateral compensation signal line, so that the compensation signal line transmits the compensation signal.
  • the compensation signal line is prepared using the source and drain layer, so that the data line can be prepared on the second metal layer. Therefore, the data line can be cross-linked, so that after the data line is disconnected, the area where the break point is far away from the signal input terminal will cause display failure, thereby solving the existing display panel technology that cannot solve the display failure caused by the data line disconnection. problem.
  • connecting holes 21 which include a first connecting hole 211 and a second connecting hole 212, where the first connecting hole 211 represents the metal of the source and drain layers.
  • the wiring is connected to the first plate of the capacitor formed by the first metal layer 115 through the first connection hole 211, and the second connection hole 212 represents the capacitance of the capacitor formed by the power supply voltage line 1192 through the second connection hole 212 and the second metal layer 117
  • the second electrode plate is connected, and the remaining connecting holes are all connecting holes corresponding to the film layers in the overlapping area.
  • the array substrate further includes a second metal layer 117 and an interlayer insulating layer 118, and the interlayer insulating layer 118 is disposed on the second metal layer 117.
  • the second metal layer 117 is etched to form the second electrode plate 1172 and the second data line 1171 of the capacitor, the interlayer insulating layer 118 is formed with a first via 313, the The second data line 1171 and the first data line 1191 are connected through the first via 313; the second data line is formed by etching on the second metal layer so that the second data line and the first data line pass through the first via Hole connection, so that the signal is transmitted on the first data line and the second data line, when the first data line is disconnected, the signal can be transmitted along the second data line, so that only the breakpoint needs to be cut off, so that the signal can continue Transfer, so as to avoid the breakpoint far away from the signal input terminal and display poor display.
  • connection hole 31 in FIG. 3 includes a first via hole 313, a second via hole 312, and a third connection hole 311.
  • the first via hole 313 is a via hole formed on an interlayer insulating layer to Connect the first data line with the second data line
  • the second via hole 312 is a via hole formed by the interlayer insulating layer to connect the power supply voltage line to the second plate of the capacitor
  • the third connection hole is the source and drain layer
  • the connecting holes of the first electrode plate of the capacitor formed by the metal traces in the first metal layer, and the remaining connecting holes are the connecting holes in the overlapping area of the corresponding film layer.
  • the array substrate further includes an active layer 113, the source and drain layers 119 are etched to form a compensation signal line 1193, and the compensation signal line 1193 is connected to the first
  • the data lines 1191 have the same direction.
  • the compensation signal line 1193 is connected to the active layer through the connection hole.
  • the compensation signal line is arranged in the source and drain layer, and then the compensation signal line is connected to the active layer through the connection hole, so that the compensation signal line compensates the circuit, and the second data is set
  • the line cross-links the first data line and the second data line, so that the compensation signal line works normally; at the same time, because the power supply voltage line is connected to the active layer, the power supply voltage line and the compensation signal line form mutually cross-linked signal lines. As a result, a problem occurs in the power supply voltage line or one of the compensation signal lines, and the circuit can work normally, thereby displaying normally.
  • the interlayer insulating layer 118 further includes a second via 312, the source and drain layer 119 is etched to form a power supply voltage line 1192, and the adjacent columns
  • the power supply voltage line 1192 is respectively connected to two opposite sides of the second electrode plate 1172 through the second via 312.
  • the power supply voltage line in the first column on the left is connected to the first column on the left.
  • the left side of the second plate of the column is connected, the power supply voltage line of the second column on the right is connected to the right of the second plate of the first column on the left, and the left of the second plate of the second column on the right.
  • the power voltage lines from the third column to the last column are connected to the second plate of the capacitor, so that all the power voltage lines are connected to the second plate of the capacitor, and the second via is set to make the power voltage line Connected to the second plate, so that after the second data line separates the second plate, the power voltage line continues to be connected to the second plate, so that the power voltage lines interact with each other, and the second plate interacts.
  • the power supply voltage line can still work normally through interaction, and the second electrode plate can also work normally; so that the second data line is arranged on the second metal layer to separate the second electrode of the capacitor
  • the second electrode plate can still be cross-linked when it is connected to the board, so as to avoid problems with a single second electrode plate, causing a greater impact on the circuit, and making the display normal.
  • the array substrate further includes a first metal layer 115.
  • the first metal layer 115 is etched to form a first scan line 1151, a second scan line 1152, and a third scan line.
  • the first scan line, the second scan line, and the third scan line represent scan lines of various levels.
  • the first scan line represents the first scan line
  • the second scan line represents the second level scan line
  • the third scan line represents the third level scan line.
  • the array substrate further includes a first metal layer, and the first metal layer is etched to form a scan line, a first electrode plate of the capacitor, and a compensation signal line.
  • the scan line and the compensation signal The direction of the lines is the same.
  • the compensation signal lines can be arranged on the first metal layer, so that the compensation signal lines are still routed laterally, and the second data line is arranged on the The second metal layer enables the first data line to cross-link with the second data line, thereby avoiding poor display caused by disconnection of the first data line.
  • the distance L between the adjacent connecting holes 411 of the first data line 1191 and the second data line 1171 is equal to the length L1 of the sub-pixel 41 and the adjacent sub-pixel
  • the sum of the distance L2 between the two, that is, L L1+L2, that is, when the connecting hole is correspondingly set, a connecting hole can be set one sub-pixel apart, so that when the sub-pixel has a problem, cut off a sub-pixel between the connecting holes.
  • the first data line in the pixel is sufficient, so as to minimize the influence of the disconnection on the display effect, and only the sub-pixel at the disconnection can make the display proceed normally.
  • the connecting hole in FIG. 4 and FIG. 5 is the first via hole in FIG. 3.
  • the connecting hole is set at the midpoint between adjacent sub-pixels, that is, L3 is equal to L2. One-half of that.
  • the projections of the first data line and the second data line on the substrate coincide.
  • the second data line can be arranged under the first data line, Therefore, when the first data line and the second data line are arranged, the arrangement positions of the first data line and the second data line are correspondingly overlapped.
  • the first data line is overlapped and arranged above the second data line.
  • the projection of the second data line on the substrate is located on the side of the projection of the first data line on the substrate. As shown in FIG. 3, the second data line is on the substrate. The projection on the bottom does not coincide with the projection of the first data line on the substrate. Even if the first data line is staggered from the second data line, when the first data line is set, the first data line is set according to the conventional setting position.
  • the second data line is arranged in the area between the second plates of the capacitor, so that the arrangement position of the second data line is determined. When the second data line is arranged, the second data line will not affect other wirings.
  • the first data line and the second data line are connected in parallel. While avoiding the first data line breakpoint to affect the display, when a single data line is used, the impedance of the data line is relatively large, so that the signal is in the data. During online transmission, a large voltage drop will occur.
  • the parallel connection of the first data line and the second data line reduces the impedance of the data line, so that the voltage drop on the data line is reduced, thereby alleviating This solves the problem of voltage drop on the data line in the circuit.
  • the breakpoint when a breakpoint occurs on the first data line, the breakpoint is cut off, so that both sides of the breakpoint can be displayed normally, thereby avoiding the interruption when the data line breaks in the existing display panel. None of the sub-pixels after the dot can be displayed normally, so that the picture of the display panel is abnormal. In the embodiment of the present application, the sub-pixels on both sides of the breakpoint are all displayed normally, so that the displayed picture is normal.
  • an embodiment of the present application provides a display panel.
  • the display panel includes an array substrate, and the array substrate includes:
  • the source/drain layer 119 is disposed on the side of the substrate 111, and the source/drain layer is etched to form a first data line 1191;
  • the array substrate further includes a second data line 1171, and the distance between the first data line 1191 and the connection hole of the second data line 1171 is at least equal to the length of one sub-pixel.
  • An embodiment of the present application provides a display panel, the display panel includes an array substrate, the array substrate includes a substrate and a source/drain layer, the source/drain layer is disposed on one side of the substrate, and the source/drain A first data line is formed by layer etching, wherein the array substrate further includes a second data line, and the distance between the first data line and the connection hole of the second data line is at least equal to the length of one sub-pixel;
  • the second data line is provided in the array substrate so that the first data line is connected to the second data line, so that after the first data line is disconnected, the signal can be transmitted from the second data line, which solves the problem of the existing display panel.
  • the technical problem of poor display caused by the disconnection of the data line is a display substrate, the array substrate includes a substrate and a source/drain layer, the source/drain layer is disposed on one side of the substrate, and the source/drain
  • a first data line is formed by layer etching, wherein the array substrate further includes
  • the display panel includes an OLED display panel
  • the OLED display panel includes an array substrate, a planarization layer 211 disposed on the array substrate, and
  • the pixel electrode layer 212 on the layer, the pixel definition layer 214 disposed on the pixel electrode layer, the luminescent material layer 213 disposed in the light-emitting area where the pixel definition layer 214 is defined are disposed on the pixel definition layer 214
  • the upper common electrode layer 215, in the OLED display panel, the array substrate will use a low-temperature polysilicon array substrate, while in the low-temperature polysilicon array substrate, the uniformity of all polysilicon semiconductors cannot be ensured, which will cause the threshold voltage to drift and affect the display effect.
  • a compensation circuit is used to compensate for the impact of threshold voltage drift, but the data line in the circuit will be broken and will have a greater impact on the display effect.
  • the first data line and the second data line are arranged to make The first data line and the second data line are cross-linked, thereby avoiding a greater impact on the display panel when the first data line is disconnected, and allowing the OLED display panel to display normally.
  • the display panel includes a liquid crystal display panel
  • the liquid crystal display panel includes an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate.
  • the first data line and the second data line are set in the LCD panel, so that when the data line is disconnected in the LCD panel, the LCD panel can still display normally, thereby solving the problem of the existing display panel that cannot solve the display failure caused by the data line disconnection.
  • the array substrate further includes a second metal layer and an interlayer insulating layer, and the interlayer insulating layer is disposed between the second metal layer and the source and drain layers.
  • the second metal layer is etched to form the second plate of the capacitor and the second data line
  • the interlayer insulating layer is formed with a first via hole, and the second data line passes through the first data line. The first via is connected.
  • the array substrate further includes an active layer, the source and drain layers are etched to form a compensation signal line, and the compensation signal line is aligned with the first data line. In the same direction, the compensation signal line is connected to the active layer through the connection hole.
  • the interlayer insulating layer further includes a second via hole, the source and drain layers are etched to form power voltage lines, and power voltage lines in adjacent columns pass through the The second via holes are respectively connected to two opposite sides of the second electrode plate.
  • the array substrate further includes a first metal layer, and the first metal layer is etched to form a scan line, a first electrode plate of a capacitor, and a compensation signal line.
  • the scanning line has the same direction as the compensation signal line.
  • the distance between the adjacent connecting holes of the first data line and the second data line is equal to the length of the sub-pixel and the distance between the adjacent sub-pixels The sum of twice.
  • the distance between the adjacent connecting holes of the first data line and the second data line is equal to the length of the sub-pixel and the distance between the adjacent sub-pixels. with.
  • the projections of the first data line and the second data line on the substrate coincide.
  • the projection of the second data line on the substrate is located on one side of the projection of the first data line on the substrate.
  • the embodiments of the present application provide an array substrate and a display panel.
  • the array substrate includes a substrate and a source/drain layer, the source/drain layer is disposed on one side of the substrate, and the source/drain layer is etched to form The first data line, wherein the array substrate further includes a second data line, and the distance between the first data line and the connection hole of the second data line is at least equal to the length of one sub-pixel;
  • the second data line connects the first data line with the second data line, so that after the first data line is disconnected, the signal can be transmitted from the second data line, which solves the problem that the existing display panel cannot solve the problem of the disconnection of the data line The display of poor technical issues.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本申请提供一种阵列基板和显示面板，该阵列基板通过设置第二数据线，使得第一数据线与第二数据线连接，从而在第一数据线断线后，信号可从第二数据线传递，解决了现有显示面板存在无法解决数据线断线造成的显示不良的技术问题。

Description

阵列基板及其制备方法、显示面板 技术领域
本申请涉及显示技术领域，尤其是涉及一种阵列基板和显示面板。
 背景技术
现有显示面板中会采用源漏极层制备数据线，数据线为单边输入信号，且每根信号线传输的信号不同，使得数据线之间无法相互交联，在信号线出现断线后，会导致断点处远离信号输入端产生亮线不良从而影响显示。
所以，现有显示面板存在无法解决数据线断线造成的显示不良的技术问题。
 技术问题
本申请提供一种阵列基板和显示面板，用于解决现有显示面板存在无法解决数据线断线造成的显示不良的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种阵列基板，该阵列基板包括：
衬底；
源漏极层，设置于所述衬底一侧，所述源漏极层刻蚀形成有第一数据线；
其中，所述阵列基板还包括第二数据线，所述第一数据线与第二数据线的连接孔的距离至少等于一个子像素的长度。
在本申请提供的阵列基板中，所述阵列基板还包括第二金属层和层间绝缘层，所述层间绝缘层设置于所述第二金属层与源漏极层之间，所述第二金属层刻蚀形成电容的第二极板和第二数据线，所述层间绝缘层形成有第一过孔，所述第二数据线与所述第一数据线通过所述第一过孔连接。
在本申请提供的阵列基板中，所述阵列基板还包括有源层，所述源漏极层刻蚀形成补偿信号线，所述补偿信号线走向与所述第一数据线走向相同，所述补偿信号线通过连接孔与有源层连接。
在本申请提供的阵列基板中，所述层间绝缘层还包括第二过孔，所述源漏极层刻蚀形成电源电压线，相邻列的电源电压线通过所述第二过孔分别连接所述第二极板的相对设置的两侧。
在本申请提供的阵列基板中，所述阵列基板还包括第一金属层，所述第一金属层刻蚀形成扫描线、电容的第一极板和补偿信号线，所述扫描线与所述补偿信号线的走向相同。
在本申请提供的阵列基板中，所述第一数据线与所述第二数据线的相邻连接孔的距离，等于子像素的长度的与相邻子像素之间的距离的和的两倍。
在本申请提供的阵列基板中，所述第一数据线与所述第二数据线的相邻连接孔的距离，等于子像素的长度与相邻子像素之间的距离的和。
在本申请提供的阵列基板中，所述第一数据线与所述第二数据线在衬底上的投影重合。
在本申请提供的阵列基板中，所述第二数据线在衬底上的投影位于所述第一数据线在衬底上的投影的一侧。
同时，本申请提供一种显示面板，该显示面板包括阵列基板，所述阵列基板包括：
衬底；
源漏极层，设置于所述衬底一侧，所述源漏极层刻蚀形成有第一数据线；
其中，所述阵列基板还包括第二数据线，所述第一数据线与第二数据线的连接孔的距离至少等于一个子像素的长度。
在本申请提供的显示面板中，所述显示面板包括OLED显示面板。
在本申请提供的显示面板中，所述显示面板包括液晶显示面板。
在本申请提供的显示面板中，还包括第二金属层和层间绝缘层，所述层间绝缘层设置于所述第二金属层与源漏极层之间，所述第二金属层刻蚀形成电容的第二极板和第二数据线，所述层间绝缘层形成有第一过孔，所述第二数据线与所述第一数据线通过所述第一过孔连接。
在本申请提供的显示面板中，还包括有源层，所述源漏极层刻蚀形成补偿信号线，所述补偿信号线走向与所述第一数据线走向相同，所述补偿信号线通过连接孔与有源层连接。
在本申请提供的显示面板中，所述层间绝缘层还包括第二过孔，所述源漏极层刻蚀形成电源电压线，相邻列的电源电压线通过所述第二过孔分别连接所述第二极板的相对设置的两侧。
在本申请提供的显示面板中，还包括第一金属层，所述第一金属层刻蚀形成扫描线、电容的第一极板和补偿信号线，所述扫描线与所述补偿信号线的走向相同。
在本申请提供的显示面板中，所述第一数据线与所述第二数据线的相邻连接孔的距离，等于子像素的长度的与相邻子像素之间的距离的和的两倍。
在本申请提供的显示面板中，所述第一数据线与所述第二数据线的相邻连接孔的距离，等于子像素的长度与相邻子像素之间的距离的和。
在本申请提供的显示面板中，所述第一数据线与所述第二数据线在衬底上的投影重合。
在本申请提供的显示面板中，所述第二数据线在衬底上的投影位于所述第一数据线在衬底上的投影的一侧。
 有益效果
本申请提供一种阵列基板和显示面板，该阵列基板包括衬底和源漏极层，所述源漏极层设置于所述衬底一侧，所述源漏极层刻蚀形成有第一数据线，其中，所述阵列基板还包括第二数据线，所述第一数据线与所述第二数据线的连接孔的距离至少等于一个子像素的长度；通过在阵列基板中设置第二数据线，使得第一数据线与第二数据线连接，从而在第一数据线断线后，信号可从第二数据线传递，解决了现有显示面板存在无法解决数据线断线造成的显示不良的技术问题。
 附图说明
图1为本申请实施例提供的阵列基板的第一示意图。
图2为本申请实施例提供的阵列基板的第二示意图。
图3为本申请实施例提供的阵列基板的第三示意图。
图4为本申请实施例提供的第一数据线与第二数据线连接的第一示意图。
图5为本申请实施例提供的第一数据线与第二数据线连接的第二示意图。
图6为本申请实施例提供的显示面板的示意图。
 本发明的实施方式
本申请提供一种阵列基板和显示面板，为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
本申请针对现有显示面板存在无法解决数据线断线造成的显示不良的技术问题，本申请实施例用以解决该问题。
如图1、图3所示，本申请提供一种阵列基板，该阵列基板包括：
衬底111；
源漏极层119，设置于所述衬底111一侧，所述源漏极层刻蚀形成有第一数据线1191；
其中，所述阵列基板还包括第二数据线1171，所述第一数据线1191与所述第二数据线1171的连接孔的距离至少等于一个子像素的长度。
本申请实施例提供一种阵列基板，该阵列基板包括衬底和源漏极层，所述源漏极层设置于所述衬底一侧，所述源漏极层刻蚀形成有第一数据线，其中，所述阵列基板还包括第二数据线，所述第一数据线与所述第二数据线的连接孔的距离至少等于一个子像素的长度；通过在阵列基板中设置第二数据线，使得第一数据线与第二数据线连接，从而在第一数据线断线后，信号可从第二数据线传递，解决了现有显示面板存在无法解决数据线断线造成的显示不良的技术问题。
在一种实施例中，如图1、图2所示，本申请实施例提供一种阵列基板，该阵列基板包括依次设置的衬底111、阻挡层112、有源层113、第一栅极绝缘层114、第一金属层115、第二栅极绝缘层116、第二金属层117、层间绝缘层118、源漏极层119，第一金属层115刻蚀形成有第一扫描线1151、第二扫描线1152第三扫描线1154和发光信号线1153，源漏极层119刻蚀形成有第一数据线1191、电源电压线1192和补偿信号线1193，在现有阵列基板中，会使用第二金属层制备横向的补偿信号线，使得补偿信号线传递补偿信号，而在本申请实施例中，将补偿信号线使用源漏极层制备，使得可在第二金属层制备数据线，从而使得数据线能够交联，使得数据线不会在出现断线后，断点远离信号输入端的区域产生显示不良，从而解决了现有显示面板存在无法解决数据线断线造成的显示不良的技术问题。
需要说明的是，在图2中，不同膜层通过连接孔21连接，所述连接孔21包括第一连接孔211和第二连接孔212，其中第一连接孔211表示源漏极层的金属走线通过第一连接孔211与第一金属层115形成的电容的第一极板连接，第二连接孔212表示电源电压线1192通过第二连接孔212与第二金属层117形成的电容的第二极板连接，其余连接孔均为相应连接重叠区域的膜层的连接孔。
在一种实施例中，如图1、图3所示，所述阵列基板还包括第二金属层117和层间绝缘层118，所述层间绝缘层118设置于所述第二金属层117与源漏极层119之间，所述第二金属层117刻蚀形成电容的第二极板1172和第二数据线1171，所述层间绝缘层118形成有第一过孔313，所述第二数据线1171与所述第一数据线1191通过所述第一过孔313连接；在第二金属层刻蚀形成第二数据线，使第二数据线与第一数据线通过第一过孔连接，从而使得信号在第一数据线和第二数据线上传递，在第一数据线出现断线问题时，信号可沿第二数据线传递，从而只需切断断点，使得信号能继续传递，从而避免断点远离信号输入端出现显示不良。
需要说明的是，在图3中连接孔31包括第一过孔313、第二过孔312和第三连接孔311，所述第一过孔313为层间绝缘层上形成的过孔，以使第一数据线与第二数据线连接，第二过孔312为层间绝缘层形成的过孔，以使电源电压线与电容的第二极板连接，第三连接孔为源漏极层中的金属走线与第一金属层形成的电容的第一极板的连接孔，其余连接孔为相应膜层重叠区域的连接孔。
在一种实施例中，如图3所示，所述阵列基板还包括有源层113，所述源漏极层119刻蚀形成补偿信号线1193，所述补偿信号线1193与所述第一数据线1191走向相同，所述补偿信号线1193通过连接孔与有源层连接，在第二金属层上设置第二数据线后，考虑到将补偿信号线设置在第二金属层会导致第二数据线和补偿信号线之间发生短路，通过在源漏极层设置补偿信号线，然后通过连接孔使得补偿信号线和有源层连接，使得补偿信号线对电路进行补偿，在设置第二数据线使第一数据线与第二数据线交联的同时，使得补偿信号线正常工作；同时，由于电源电压线连接有源层，使得电源电压线和补偿信号线形成相互交联的信号线，使得电源电压线或者补偿信号线中的一信号线出现问题，电路能正常工作，从而正常显示。
在一种实施例中，如图1、图3所示，所述层间绝缘层118还包括第二过孔312，所述源漏极层119刻蚀形成电源电压线1192，相邻列的电源电压线1192通过所述第二过孔312分别连接所述第二极板1172的相对设置的两侧，在图3中可以看到，左侧第一列的电源电压线与左侧第一列的第二极板的左侧连接，右侧第二列的电源电压线分别与左侧第一列的第二极板的右侧连接、与右侧第二列的第二极板的左侧连接，相应的第三列直至最后一列的电源电压线与电容的第二极板连接，使得所有的电源电压线与电容的第二极板连接，通过设置第二过孔，使得电源电压线与第二极板连接，从而使得在第二数据线分隔开第二极板后，电源电压线继续与第二极板连接，从而使得电源电压线之间发生交互，第二极板交互，使得在一电源电压线出现短路时，电源电压线依然可以通过交互正常工作，同时第二极板也可以正常工作；使得在第二数据线设置在第二金属层分隔开电容的第二极板时，第二极板依然能够交联，从而避免单个第二极板出现问题，造成对电路产生较大的影响，使得显示正常。
在一种实施例中，如图3所示，所述阵列基板还包括第一金属层115，所述第一金属层115刻蚀形成第一扫描线1151、第二扫描线1152、第三扫描线1154、发光信号线1153和电容的第一极板1155，所述第一扫描线、第二扫描线和第三扫描线代表各级扫描线，例如第一扫描线代表第一级扫描线、第二扫描线代表第二级扫描线、第三扫描线代表第三级扫描线。
在一种实施例中，所述阵列基板还包括第一金属层，所述第一金属层刻蚀形成扫描线、电容的第一极板和补偿信号线，所述扫描线与所述补偿信号线的走向相同，考虑到现有的补偿信号线在第二金属层横向走线，可将补偿信号线设置在第一金属层，使得补偿信号线依然横向走线，而第二数据线设置在第二金属层，从而使得第一数据线与第二数据线交联，从而避免第一数据线出现断线造成的显示不良。
在一种实施例中，如图4所示，所述第一数据线1191与所述第二数据线1171的相邻连接孔411的距离L，等于子像素的长度L1与相邻子像素41之间的距离L2的和的两倍，即L=（L1+L2）*2，即对应设置连接孔时，可相隔两个子像素设置一个连接孔，使得在子像素出现问题时，切断介于连接孔之间的两个子像素中的第一数据线即可，使得信号能继续向后传递，从而使得显示面板能够正常显示。
在一种实施例中，如图5所示，所述第一数据线1191与所述第二数据线1171的相邻连接孔411的距离L，等于子像素41的长度L1与相邻子像素之间的距离L2的和，即L=L1+L2，即对应设置连接孔时，可相隔一个子像素即设置一个连接孔，使得子像素出现问题时，切断介于连接孔之间的一个子像素中的第一数据线即可，从而使得最小程度的减小断线对显示效果的影响，只需断线处子像素即可使得显示进行正常进行。
需要说明的是，图4、图5中的连接孔即为图3中的第一过孔，图4、图5中将连接孔设置于相邻子像素之间的中点，即L3等于L2的二分之一。
在一种实施例中，所述第一数据线与所述第二数据线在衬底上的投影重合，在设置第二数据线时，可将第二数据线设置在第一数据线下，从而在设置第一数据线与第二数据线时，第一数据线与第二数据线的设置位置对应重合，在设置第二数据线后，第一数据线重合设置在第二数据线上方即可，无需再考虑第二数据线的设置位置，使得第一数据线与第二数据线对应重合。
在一种实施例中，所述第二数据线在衬底上的投影位于所述第一数据线在衬底上的投影的一侧，如图3所示，所述第二数据线在衬底上的投影与所述第一数据线在衬底上的投影不重合，即使第一数据线与第二数据线错开，在设置第一数据线时，第一数据线按常规设置位置设置，而第二数据线设置在电容的第二极板之间的区域，使得第二数据线的设置位置确定，在设置第二数据线时，第二数据线不会对其他走线产生影响。
在本申请实施例中，第一数据线和第二数据线并联，在避免第一数据线断点影响显示的同时，现有采用单条数据线时，数据线的阻抗较大，使得信号在数据线上传输时，会出现较大的压降，而在本申请实施例中，第一数据线和第二数据线并联降低了数据线上的阻抗，使得数据线上的压降降低，从而缓解了电路中数据线出现压降的问题。
在本申请实施例中，在第一数据线上出现断点时，采用切断断点，使得断点两侧能够正常显示，从而避免了在现有显示面板中，数据线出现断点时，断点后的子像素均不能正常显示，使得显示面板的画面出现异常，而本申请实施例中，断点两侧的子像素均正常显示，从而使得显示的画面正常。
如图6所示，本申请实施例提供一种显示面板，该显示面板包括阵列基板，所述阵列基板包括：
衬底111；
源漏极层119，设置于所述衬底111一侧，所述源漏极层刻蚀形成有第一数据线1191；
其中，所述阵列基板还包括第二数据线1171，所述第一数据线1191与所述第二数据线1171的连接孔的距离至少等于一个子像素的长度。
本申请实施例提供一种显示面板，该显示面板包括阵列基板，所述阵列基板包括衬底和源漏极层，所述源漏极层设置于所述衬底一侧，所述源漏极层刻蚀形成有第一数据线，其中，所述阵列基板还包括第二数据线，所述第一数据线与所述第二数据线的连接孔的距离至少等于一个子像素的长度；通过在阵列基板中设置第二数据线，使得第一数据线与第二数据线连接，从而在第一数据线断线后，信号可从第二数据线传递，解决了现有显示面板存在无法解决数据线断线造成的显示不良的技术问题。
在一种实施例中，如图6所示，所述显示面板包括OLED显示面板，所述OLED显示面板包括阵列基板、设置于所述阵列基板上的平坦化层211、设置于所述平坦化层上的像素电极层212、设置于所述像素电极层上的像素定义层214、设置于所述像素定义层214定义处的发光区域中的发光材料层213，设置于所述像素定义层214上公共电极层215，在OLED显示面板中，阵列基板会使用低温多晶硅阵列基板，而在低温多晶硅阵列基板中，无法确保所有的多晶硅半导体的均一性，会导致阈值电压漂移，影响显示效果，会采用补偿电路对阈值电压漂移产生的影响进行补偿，但电路中数据线会出现断线对显示效果产生较大的影响，而本申请实施例中通过设置第一数据线和第二数据线，使得第一数据线和第二数据线交联，从而避免了第一数据线出现断线时对显示面板产生较大的影响，使OLED显示面板正常显示。
在一种实施例中，所述显示面板包括液晶显示面板，所述液晶显示面板包括阵列基板、彩膜基板、以及设置于所述阵列基板和彩膜基板之间的液晶层，通过在阵列基板中设置第一数据线和第二数据线，使得液晶显示面板中出现数据线断线时，液晶显示面板依然能够正常显示，从而解决了现有显示面板存在无法解决数据线断线造成的显示不良的技术问题。
在一种实施例中，在所述显示面板中，所述阵列基板还包括第二金属层和层间绝缘层，所述层间绝缘层设置于所述第二金属层与源漏极层之间，所述第二金属层刻蚀形成电容的第二极板和第二数据线，所述层间绝缘层形成有第一过孔，所述第二数据线与所述第一数据线通过所述第一过孔连接。
在一种实施例中，在所述显示面板中，所述阵列基板还包括有源层，所述源漏极层刻蚀形成补偿信号线，所述补偿信号线走向与所述第一数据线走向相同，所述补偿信号线通过连接孔与有源层连接。
在一种实施例中，在所述显示面板中，所述层间绝缘层还包括第二过孔，所述源漏极层刻蚀形成电源电压线，相邻列的电源电压线通过所述第二过孔分别连接所述第二极板的相对设置的两侧。
在一种实施例中，在所述显示面板中，所述阵列基板还包括第一金属层，所述第一金属层刻蚀形成扫描线、电容的第一极板和补偿信号线，所述扫描线与所述补偿信号线的走向相同。
在一种实施例中，在所述显示面板中，所述第一数据线与所述第二数据线的相邻连接孔的距离，等于子像素的长度的与相邻子像素之间的距离的和的两倍。
在一种实施例中，在所述显示面板中，所述第一数据线与所述第二数据线的相邻连接孔的距离，等于子像素的长度与相邻子像素之间的距离的和。
在一种实施例中，在所述显示面板中，所述第一数据线与所述第二数据线在衬底上的投影重合。
在一种实施例中，在所述显示面板中，所述第二数据线在衬底上的投影位于所述第一数据线在衬底上的投影的一侧。
根据以上实施例可知：
本申请实施例提供一种阵列基板和显示面板，该阵列基板包括衬底和源漏极层，所述源漏极层设置于所述衬底一侧，所述源漏极层刻蚀形成有第一数据线，其中，所述阵列基板还包括第二数据线，所述第一数据线与所述第二数据线的连接孔的距离至少等于一个子像素的长度；通过在阵列基板中设置第二数据线，使得第一数据线与第二数据线连接，从而在第一数据线断线后，信号可从第二数据线传递，解决了现有显示面板存在无法解决数据线断线造成的显示不良的技术问题。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种阵列基板，其包括：
    衬底；
    源漏极层，设置于所述衬底一侧，所述源漏极层刻蚀形成有第一数据线；
    其中，所述阵列基板还包括第二数据线，所述第一数据线与第二数据线的连接孔的距离至少等于一个子像素的长度。
  2. 如权利要求1所述的阵列基板，其中，还包括第二金属层和层间绝缘层，所述层间绝缘层设置于所述第二金属层与源漏极层之间，所述第二金属层刻蚀形成电容的第二极板和第二数据线，所述层间绝缘层形成有第一过孔，所述第二数据线与所述第一数据线通过所述第一过孔连接。
  3. 如权利要求2所述的阵列基板，其中，还包括有源层，所述源漏极层刻蚀形成补偿信号线，所述补偿信号线走向与所述第一数据线走向相同，所述补偿信号线通过连接孔与有源层连接。
  4. 如权利要求3所述的阵列基板，其中，所述层间绝缘层还包括第二过孔，所述源漏极层刻蚀形成电源电压线，相邻列的电源电压线通过所述第二过孔分别连接所述第二极板的相对设置的两侧。
  5. 如权利要求2所述的阵列基板，其中，还包括第一金属层，所述第一金属层刻蚀形成扫描线、电容的第一极板和补偿信号线，所述扫描线与所述补偿信号线的走向相同。
  6. 如权利要求2所述的阵列基板，其中，所述第一数据线与所述第二数据线的相邻连接孔的距离，等于子像素的长度的与相邻子像素之间的距离的和的两倍。
  7. 如权利要求2所述的阵列基板，其中，所述第一数据线与所述第二数据线的相邻连接孔的距离，等于子像素的长度与相邻子像素之间的距离的和。
  8. 如权利要求1所述的阵列基板，其中，所述第一数据线与所述第二数据线在衬底上的投影重合。
  9. 如权利要求1所述的阵列基板，其中，所述第二数据线在衬底上的投影位于所述第一数据线在衬底上的投影的一侧。
  10. 一种显示面板，其包括阵列基板，所述阵列基板包括：
    衬底；
    源漏极层，设置于所述衬底一侧，所述源漏极层刻蚀形成有第一数据线；
    其中，所述阵列基板还包括第二数据线，所述第一数据线与第二数据线的连接孔的距离至少等于一个子像素的长度。
  11. 如权利要求10所述的显示面板，其中，所述显示面板包括OLED显示面板。
  12. 如权利要求10所述的显示面板，其中，所述显示面板包括液晶显示面板。
  13. 如权利要求10所述的显示面板，其中，还包括第二金属层和层间绝缘层，所述层间绝缘层设置于所述第二金属层与源漏极层之间，所述第二金属层刻蚀形成电容的第二极板和第二数据线，所述层间绝缘层形成有第一过孔，所述第二数据线与所述第一数据线通过所述第一过孔连接。
  14. 如权利要求13所述的显示面板，其中，还包括有源层，所述源漏极层刻蚀形成补偿信号线，所述补偿信号线走向与所述第一数据线走向相同，所述补偿信号线通过连接孔与有源层连接。
  15. 如权利要求14所述的显示面板，其中，所述层间绝缘层还包括第二过孔，所述源漏极层刻蚀形成电源电压线，相邻列的电源电压线通过所述第二过孔分别连接所述第二极板的相对设置的两侧。
  16. 如权利要求13所述的显示面板，其中，还包括第一金属层，所述第一金属层刻蚀形成扫描线、电容的第一极板和补偿信号线，所述扫描线与所述补偿信号线的走向相同。
  17. 如权利要求13所述的显示面板，其中，所述第一数据线与所述第二数据线的相邻连接孔的距离，等于子像素的长度的与相邻子像素之间的距离的和的两倍。
  18. 如权利要求13所述的显示面板，其中，所述第一数据线与所述第二数据线的相邻连接孔的距离，等于子像素的长度与相邻子像素之间的距离的和。
  19. 如权利要求10所述的显示面板，其中，所述第一数据线与所述第二数据线在衬底上的投影重合。
  20. 如权利要求10所述的显示面板，其中，所述第二数据线在衬底上的投影位于所述第一数据线在衬底上的投影的一侧。
PCT/CN2020/081444 2019-12-02 2020-03-26 阵列基板及其制备方法、显示面板 WO2021109370A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/763,331 US11217608B2 (en) 2019-12-02 2020-03-26 Array substrate and manufacturing method thereof, and display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201911213389.7 2019-12-02
CN201911213389.7A CN111025798B (zh) 2019-12-02 2019-12-02 阵列基板和显示面板

Publications (1)

Publication Number Publication Date
WO2021109370A1 true WO2021109370A1 (zh) 2021-06-10

Family

ID=70203872

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/081444 WO2021109370A1 (zh) 2019-12-02 2020-03-26 阵列基板及其制备方法、显示面板

Country Status (2)

Country Link
CN (1) CN111025798B (zh)
WO (1) WO2021109370A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111474790A (zh) * 2020-05-14 2020-07-31 深圳市华星光电半导体显示技术有限公司 阵列基板和液晶显示面板
CN112086576B (zh) * 2020-09-07 2022-09-09 武汉华星光电半导体显示技术有限公司 一种显示面板及制程方法
US20230337485A1 (en) * 2020-09-18 2023-10-19 Sharp Kabushiki Kaisha Display device
CN115244701A (zh) * 2021-02-08 2022-10-25 京东方科技集团股份有限公司 显示基板及显示装置
CN113053921B (zh) * 2021-03-12 2022-09-27 武汉华星光电半导体显示技术有限公司 一种阵列基板、显示面板以及显示装置
CN113178460B (zh) * 2021-04-07 2023-12-12 武汉华星光电半导体显示技术有限公司 Oled显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020171782A1 (en) * 2001-05-21 2002-11-21 Lg. Philips Lcd Co., Ltd Array substrate for a liquid crystal display device and manufacturing method for the same
KR20050067859A (ko) * 2003-12-29 2005-07-05 엘지.필립스 엘시디 주식회사 횡전계 방식 액정표시장치 및 그 제조방법
CN104409455A (zh) * 2014-11-17 2015-03-11 京东方科技集团股份有限公司 一种基板及其制造方法、显示装置
CN108281468A (zh) * 2018-01-23 2018-07-13 京东方科技集团股份有限公司 一种显示基板的制造方法、显示基板、显示装置
CN110299384A (zh) * 2019-06-10 2019-10-01 昆山国显光电有限公司 一种显示面板
CN110690225A (zh) * 2019-09-02 2020-01-14 武汉华星光电半导体显示技术有限公司 阵列基板、及其数据线断点修补方法和显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW507189B (en) * 2001-02-23 2002-10-21 Chi Mei Optoelectronics Corp Liquid crystal display capable of repairing the defects of data line
CN103268746B (zh) * 2012-12-07 2016-08-03 上海天马微电子有限公司 一种像素驱动电路、发光二极管显示屏及显示设备
CN107340659A (zh) * 2017-06-20 2017-11-10 惠科股份有限公司 一种显示面板、显示装置和显示面板的修复方法
CN107807485A (zh) * 2017-11-30 2018-03-16 上海天马微电子有限公司 阵列基板、显示面板和显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020171782A1 (en) * 2001-05-21 2002-11-21 Lg. Philips Lcd Co., Ltd Array substrate for a liquid crystal display device and manufacturing method for the same
KR20050067859A (ko) * 2003-12-29 2005-07-05 엘지.필립스 엘시디 주식회사 횡전계 방식 액정표시장치 및 그 제조방법
CN104409455A (zh) * 2014-11-17 2015-03-11 京东方科技集团股份有限公司 一种基板及其制造方法、显示装置
CN108281468A (zh) * 2018-01-23 2018-07-13 京东方科技集团股份有限公司 一种显示基板的制造方法、显示基板、显示装置
CN110299384A (zh) * 2019-06-10 2019-10-01 昆山国显光电有限公司 一种显示面板
CN110690225A (zh) * 2019-09-02 2020-01-14 武汉华星光电半导体显示技术有限公司 阵列基板、及其数据线断点修补方法和显示装置

Also Published As

Publication number Publication date
CN111025798A (zh) 2020-04-17
CN111025798B (zh) 2021-06-25

Similar Documents

Publication Publication Date Title
WO2021109370A1 (zh) 阵列基板及其制备方法、显示面板
KR100719423B1 (ko) 액티브 매트릭스 기판 및 표시 장치
KR100318539B1 (ko) 액정 표시 장치용 박막 트랜지스터 기판
CN100462820C (zh) 液晶显示面板
JP2007292879A (ja) 液晶表示装置
KR20130096605A (ko) 액정표시장치 및 액정표시장치의 리페어 방법
KR100313245B1 (ko) 리페어 기능을 갖는 액정표시소자
US20150116620A1 (en) Display device
JPWO2011086782A1 (ja) アレイ基板、及び、液晶表示パネル
KR20060118208A (ko) 박막 트랜지스터 표시판
KR20020004253A (ko) 액정표시소자 및 배열 기판 형성 방법
US20230110225A1 (en) Array substrate, display panel and display device having the array substrate
JP4293867B2 (ja) 画素の大型化に対応したｉｐｓ液晶ディスプレイ
WO2021042625A1 (zh) 阵列基板、及其数据线断点修补方法和显示装置
US20230213825A1 (en) Lcd panel and lcd device
JPH09325363A (ja) 液晶表示装置の修復方法
KR100318537B1 (ko) 액정 표시 장치용 박막 트랜지스터 기판 및 그 수리 방법
KR20040074931A (ko) 표시 장치용 전극 기판
US11217608B2 (en) Array substrate and manufacturing method thereof, and display panel
KR100616443B1 (ko) 박막 트랜지스터 액정표시소자의 박막 트랜지스터 어레이 기판
US20200303420A1 (en) Array substrate, method for repairing same, and display device
US20200124924A1 (en) Array substrate, display panel and display device
JP3519275B2 (ja) アクティブマトリクス型液晶表示装置
JP2558847B2 (ja) 断線欠陥の補修の可能なマトリクス型画像表示装置及び断線の救済方法
WO2020124869A1 (zh) 阵列基板及显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20895273

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20895273

Country of ref document: EP

Kind code of ref document: A1