WO2020073561A1 - 一种走线结构及液晶面板 - Google Patents

一种走线结构及液晶面板 Download PDF

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Publication number
WO2020073561A1
WO2020073561A1 PCT/CN2019/072803 CN2019072803W WO2020073561A1 WO 2020073561 A1 WO2020073561 A1 WO 2020073561A1 CN 2019072803 W CN2019072803 W CN 2019072803W WO 2020073561 A1 WO2020073561 A1 WO 2020073561A1
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Prior art keywords
metal layer
cross
wire
wiring
area
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PCT/CN2019/072803
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English (en)
French (fr)
Inventor
陈帅
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深圳市华星光电技术有限公司
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Publication of WO2020073561A1 publication Critical patent/WO2020073561A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/22—Antistatic materials or arrangements

Definitions

  • the invention relates to the technical field of liquid crystal display, in particular to a wiring structure and a liquid crystal panel which can improve the anti-ESD performance of the liquid crystal panel.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the GOA technology is a technology that uses the existing TFT-LCD array manufacturing process to fabricate the gate row driving circuit on an array (Array) substrate, and realizes a driving method of progressively scanning the gate.
  • the GOA technology can save the gate IC, which is beneficial to the design and cost reduction of the narrow border on the side of the gate driver of the display screen, and is widely used and researched. As a result, the reliability of the panel has received more and more attention, among which Electro-Static discharge (ESD) is a very important content.
  • ESD Electro-Static discharge
  • ESD refers to the charge transfer caused by objects with different electrostatic potentials being close to or in direct contact with each other.
  • ESD is a common source of near-field hazards, which can form high voltages, strong electric fields, instantaneous large currents, and accompanied by strong electromagnetic radiation to form electrostatic discharge electromagnetic pulses.
  • the gate drive circuit of a non-GOA technology liquid crystal panel includes VGH, VGL, and STV traces
  • the gate drive circuit of a GOA technology liquid crystal panel includes CK1-CK8, VSS, LC1-LC2, and STV traces. line. The greater the number of traces on the panel, the more cross-wires become, and ESD becomes more and more common.
  • FIG. 1A is a schematic diagram of the first embodiment of the existing LCD panel wiring structure
  • FIG. 1B is a schematic diagram of the second embodiment of the existing LCD panel wiring structure
  • FIG. 1C is a conventional GOA circuit structure unit Cross-sectional view of the wiring structure at the location of the line and the cross-over line.
  • Figure 1A shows the structure of the trace in the form of wider traces
  • Figure 1B shows the structure of the trace in the form of finer traces, both of which are through structures from top to bottom, that is, at the position of the incoming line No special design. Since this wiring structure has no crossover at the incoming position, when ESD occurs, it must be in the GOA circuit area (the area indicated by the dashed box in FIGS.
  • the first metal layer trace (Metal1) 11 is provided with a SiNx insulating layer 13 and the second metal layer trace (Metal2) 12 is provided on the SiNx insulating layer 13. Since this routing structure has a cross-over line at the position of the incoming line, ESD usually occurs at the cross-line position, that is, ESD usually occurs at the cross-line position of Metal1 and Metal2, and the impact is that the line is broken, The short circuit, which in turn affects the potential signal in the liquid crystal panel, causes an abnormal screen display.
  • the purpose of the present invention is to provide a wiring structure and a liquid crystal panel, which can realize that when ESD occurs in the wiring of the liquid crystal panel, it can avoid the circuit from being affected and cause functional defects, and improve the stability and reliability of the liquid crystal panel.
  • the present invention provides a wiring structure, a first cross-wire structure area is provided at each incoming position, and the first cross-wire structure area includes first metal layer traces stacked in sequence , An insulating layer and a second metal layer trace, the line entry position is a section before the first metal layer trace enters the circuit area; the first metal layer trace is in the first cross-over structure
  • the area includes a plurality of connected metal wires, the insulating layer covers the plurality of connected metal wires, the second metal layer wiring is in a floating connection state;
  • the wiring structure further includes A second cross-wire structure area between the line position and the circuit area, the second cross-wire structure area including a first metal layer trace, an insulating layer, and a second metal layer trace stacked in sequence;
  • the insulating layer is made of SiNx material.
  • the present invention also provides a wiring structure, a first cross-wire structure area is provided at each incoming position, and the first cross-wire structure area includes a first metal layer that is sequentially stacked.
  • the structure area includes a plurality of connected metal lines, the insulating layer covers the plurality of connected metal lines, and the second metal layer traces are in a floating connection state.
  • the wiring structure includes a second cross-wire structure area provided between the position of the incoming line and the circuit area, and the second cross-wire structure area includes first The metal layer wiring, the insulating layer and the second metal layer wiring.
  • the first metal layer trace is a hollow structure in the first cross-wire structure area, and the floating second metal layer trace is provided on the insulating layer on the hollow structure on.
  • the first metal layer traces bifurcate into multiple traces after entering the first cross-wire structure area and merge into one trace after leading out the first cross-wire structure area
  • the floating second metal layer traces are provided on the insulating layers on the plurality of traces.
  • the insulating layer is made of SiNx material.
  • the present invention also provides a liquid crystal panel, the liquid crystal panel includes a circuit area and a wiring structure; the wiring structure is provided with a first cross-wire structure area at each incoming position, the The first cross-wire structure area includes a first metal layer trace, an insulating layer, and a second metal layer trace that are sequentially stacked, and the position of the line entry is a section before the first metal layer trace enters the circuit area
  • the first metal layer traces include multiple connected metal lines in the first jumper structure area, the insulating layer covers the multiple connected metal lines, and the second metal layer traces It is floating.
  • the present invention guides ESD to occur in the first cross-wire structure area by setting the first cross-wire structure area at all incoming positions, thereby avoiding the circuit from being affected and causing poor functionality.
  • ESD occurs in the wiring of the LCD panel, although disconnection and short circuit may occur, it does not affect the functional characteristics of the product. It can improve the anti-ESD performance of the LCD panel, thereby improving the stability and reliability of the LCD panel.
  • FIG. 1A is a schematic diagram of Embodiment 1 of a conventional liquid crystal panel wiring structure
  • FIG. 1C a cross-sectional view of the cross-wire and the wiring structure of the existing GOA circuit structural unit at the cross-wire position;
  • FIG. 2B is a cross-sectional view of the first cross-wire structure area of the wiring structure shown in FIG. 2A;
  • FIG. 3 is a schematic diagram of a second embodiment of the wiring structure of the present invention.
  • the first feature “above” or “below” the second feature may include the first and second features in direct contact, or may include the first and second features Contact not directly but through other features between them.
  • the first feature is “above”, “above” and “above” the second feature includes that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is higher in level than the second feature.
  • the first feature is “below”, “below” and “below” the second feature includes that the first feature is directly below and obliquely below the second feature, or simply means that the first feature is less horizontal than the second feature.
  • the wiring structure provided by the present invention is provided with a first jumper structure region at each wire entry position, and the first jumper structure region includes a first metal layer trace, an insulating layer, and a second metal layered in sequence.
  • Layer wiring where the wire entry position is a section before the first metal layer wiring enters the circuit area; the first metal layer wiring includes a plurality of connected metals in the first cross-wire structure region Wire, the insulating layer covers the plurality of connected metal wires, and the second metal layer is in a floating state.
  • the wiring structure includes a second cross-wire structure area provided between the wire entry position and the circuit area, and the second cross-wire structure area includes a first metal layer stacked in sequence The trace, the insulating layer and the second metal layer trace.
  • the circuit signal in the LCD panel is directly connected to the LCD panel through the C-board (integrated circuit board), and the signal is transmitted to the circuit area through the wiring in the LCD panel ,
  • a section before entering the circuit area is defined as the line entry position.
  • ESD often occurs at the first crossover location in the path from the C-board to the end of the circuit area. Therefore, in the present invention, the first cross-wire structure area is provided at all the wire-entry positions, and by providing some cross-wire structures at the wire-entry position before the charge enters the circuit area, the ESD is guided to occur at the first wire-entry position Structure area, so as to prevent the circuit from being affected and causing poor functionality.
  • the wiring structure of the present invention is provided with the first cross-wire structure area at all incoming positions.
  • the first cross-wire structure area is arranged before other cross-wires of the wiring structure to protect other cross-wires. effect.
  • An insulating layer (for example, SiNx material can be used) is provided between different metal layers for insulation.
  • the wiring structure includes a second cross-wire structure area provided between the wire entry position and the circuit area, and the second cross-wire structure area includes a first metal layer walk that is sequentially stacked Wiring, insulation layer and second metal layer. That is, the normal crossover is set after the first crossover structure area of the present invention, and the guiding ESD occurs in the first crossover structure area, so as to prevent the circuit from being affected and causing malfunction.
  • FIG. 2A is a schematic diagram of the first embodiment of the wiring structure according to the present invention
  • FIG. 2B is a cross-sectional view of the wiring structure shown in FIG. 2A
  • the dashed box in FIG. 2A represents the GOA circuit area.
  • the first metal layer trace 21 is a hollow structure 211 in the first cross-wire structure area 20, and the floating second metal layer trace 22 is provided on the insulating layer 23 on the hollow structure 211.
  • the first metal layer trace (Metal1) 21 is wider. Therefore, the first metal layer trace 21 of the first cross-wire structure area 20 at the wire entry position is designed as a hollow structure 211, and the hollow structure 211 is substantially It is a plurality of connected metal wires.
  • An insulating layer (for example, SiNx material can be used) 23 is provided on the hollow structure 211 to insulate the first and second metal layer traces 21 and 22 on the insulating layer 23
  • a floating second metal layer trace (Metal2) 22 is provided; the hollow structure 211 makes the first metal layer trace 21 short-circuited with the same layer of metal in the first cross-wire structure region 20.
  • the routing structure described in the present invention can guide the location where ESD occurs to the first cross-wire structure area 20. Since this location contains multiple connected metal lines, even if ESD occurs on one of the lines, it will not affect Circuit signal.
  • the existing wiring structure is a through structure from top to bottom. Since there is no cross-over structure at the position of the incoming line, it will definitely be in the GOA circuit area when ESD occurs. However, if ESD occurs in the GOA circuit area, such disconnection and short circuit cannot be avoided and repaired under normal circumstances.
  • the wiring structure includes a second cross-wire structure area 29 disposed between the incoming position and the circuit area, and the second cross-wire structure area 29 includes first stacked layers
  • the trace 22 is made of the same material, but the second metal layer trace 22 here is a jumper that is normally connected to other components, not a floating state.
  • FIG. 3 a schematic diagram of a second embodiment of the wiring structure according to the present invention.
  • the dotted frame in the figure represents the GOA circuit area.
  • the first metal layer trace 31 branches into a plurality of traces 311 after entering the first cross-wire structure area 30 and merges into one trace after leading out the first cross-wire structure area 30, and the floating second metal layer walks
  • the line 32 is disposed on an insulating layer (not shown in the figure) on the plurality of traces 311.
  • the first metal layer trace (Metal1) 31 is narrow and cannot be designed into a hollow structure.
  • the first metal layer trace 31 is branched into multiple traces 311, Multiple traces 311 are short-circuited, and an insulating layer (for example, SiNx material can be used) is provided on the multiple traces 311 to insulate the first and second metal layer traces, and a floating layer is provided on the insulating layer Connected (floating) the second metal layer trace (Metal2) 32.
  • an insulating layer for example, SiNx material can be used
  • a floating layer is provided on the insulating layer Connected (floating) the second metal layer trace (Metal2) 32.
  • the invention also provides a liquid crystal panel.
  • the liquid crystal panel includes a circuit area and a wiring structure.
  • the wiring structure is provided with a first cross-wire structure area at each position of the incoming wire, and the first cross-wire structure area includes a first metal layer trace, an insulating layer and a second metal layer trace that are sequentially stacked ,
  • the line entry position is a section before the first metal layer trace enters the circuit area;
  • the first metal layer trace includes a plurality of connected metal lines in the first cross-wire structure area, so
  • the insulating layer covers the plurality of connected metal wires, and the second metal layer is in a floating state.
  • the wiring structure includes a second cross-wire structure area provided between the wire entry position and the circuit area, and the second cross-wire structure area includes a first metal layer stacked in sequence The trace, the insulating layer and the second metal layer trace.
  • the first metal layer trace 21 can be set to the hollow structure 211 in the first jumper structure area 20, and the floating second metal layer trace 22 is set on the insulating layer 23 on the hollow structure 211, as shown in FIG. 2A- The first embodiment shown in 2B.
  • the first metal layer trace (Metal1) 21 is wider. Therefore, the first metal layer trace 21 of the first cross-wire structure region 20 at the wire entry position is designed as a hollow structure 211, and the hollow structure 211 In essence, it is a plurality of connected metal wires.
  • An insulating layer (for example, SiNx layer) 23 is provided on the hollow structure 211 to insulate the first and second metal layer traces 21 and 22, and an insulating layer 23 is provided on the insulating layer 23.
  • the routing structure described in the present invention can guide the location where ESD occurs to the first cross-wire structure area 20. Since this location contains multiple connected metal lines, even if ESD occurs on one of the lines, it will not affect Circuit signal.
  • the existing wiring structure is a through structure from top to bottom. Since there is no cross-over structure at the position of the incoming line, it will definitely be in the GOA circuit area when ESD occurs. However, if ESD occurs in the GOA circuit area, such disconnection and short circuit cannot be avoided and repaired under normal circumstances.
  • the first metal layer trace 31 may also be configured to branch into a plurality of traces 311 after entering the first cross-line structure area 30 and merge into one trace after leading out the first cross-line structure area 30, the floating first
  • the two metal layer traces 32 are disposed on the insulating layers on the multiple traces 311, as shown in FIG. 3 in the second embodiment.
  • the first metal layer trace (Metal1) 31 is narrow and cannot be designed into a hollow structure.
  • the first metal layer trace 31 is branched into multiple traces 311 , Multiple traces 311 are short-circuited, an insulating layer (for example, SiNx material can be used) is provided on the multiple traces 311 to insulate the first and second metal layer traces, and a layer is provided on the insulating layer Floating second metal layer trace (Metal2) 32.
  • an insulating layer for example, SiNx material can be used
  • Metal2 Floating second metal layer trace
  • the liquid crystal panel may use GOA technology, and the gate driving circuit of the liquid crystal panel using GOA technology includes CK1-CK8, VSS, LC1-LC2, and STV wiring.
  • the liquid crystal panel may also use non-GOA technology, and the gate drive circuit of the liquid crystal panel using non-GOA technology includes VGH, VGL, and STV traces.
  • Each wiring adopts the above-mentioned wiring structure, and a first cross-wire structure area is provided at the position of the incoming line to guide ESD to occur in the first cross-wire structure area, so as to prevent the circuit from being affected and causing poor functionality.
  • the circuit signal in the liquid crystal panel is directly connected to the liquid crystal panel through the C-board (integrated circuit board), and the signal is transmitted to the circuit area (such as the GOA circuit area) through the wiring in the liquid crystal panel, and enters the section before the circuit area
  • the position is defined as the incoming line position.
  • ESD often occurs at the first crossover location in the path from the C-board to the end of the circuit area.
  • By setting the first cross-line structure area at all the incoming lines that is, setting some cross-line structures before the charge enters the circuit area, guiding ESD to occur in the first cross-line structure area, thereby avoiding the circuit from being affected and causing poor functionality .
  • ESD occurs in the wiring of the LCD panel, although disconnection and short circuit may occur, it does not affect the functional characteristics of the product. It can improve the anti-ESD performance of the LCD panel, thereby improving the stability and reliability of the LCD panel.
  • the wiring structure of the present invention is provided with the first cross-wire structure area at all incoming positions.
  • the first cross-wire structure area is arranged before other cross-wires of the wiring structure to protect other cross-wires. effect.
  • An insulating layer (for example, SiNx material can be used) is provided between different metal layers for insulation.
  • the wiring structure includes a second cross-wire structure area provided between the wire entry position and the circuit area, and the second cross-wire structure area includes a first metal layer walk that is sequentially stacked Wiring, insulation layer and second metal layer. That is, the normal crossover is set after the first crossover structure area of the present invention, and the guiding ESD occurs in the first crossover structure area, so as to prevent the circuit from being affected and causing malfunction.

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Abstract

一种走线结构及液晶面板，走线结构在每一进线位置处设有第一跨线结构区（20），第一跨线结构区（20）包括依次层叠设置的第一金属层走线（21）、绝缘层（23）以及第二金属层走线（22），进线位置处为第一金属层走线（21）进入电路区之前的一段位置；第一金属层走线（21）在第一跨线结构区（20）包含多条相连的金属线，绝缘层（23）覆盖在多条相连的金属线上，第二金属层走线（22）为浮接状态。通过在所有进线位置处设置第一跨线结构区（20），引导ESD发生在第一跨线结构区（20），从而避免电路受到影响造成功能性不良。当液晶面板的走线发生ESD后，虽然会发生断线、短路的情况，但并不影响产品的功能特性，可以提高液晶面板防ESD性能，进而提高液晶面板的使用稳定性和可靠性。

Description

一种走线结构及液晶面板 技术领域
本发明涉及液晶显示技术领域，尤其涉及一种可以提高液晶面板防ESD性能的走线结构及液晶面板。
 背景技术
随着光电与半导体技术的发展，液晶显示器(Liquid Crystal Display，LCD)也得到了蓬勃发展。在诸多液晶显示器中，薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，简称TFT-LCD)具有高空间利用效率、低消耗功率、无辐射以及低电磁干扰等优越特性。在当今信息社会，TFT-LCD已经广泛应用于生活的各个方面，从小尺寸的手机、摄像机、数码相机，中尺寸的笔记本电脑、台式机，大尺寸的家用电视，到大型投影设备等。TFT-LCD在轻、薄优势的基础上，加上完美的画面及快速的响应特性，在显示器市场上独占鳌头。
随着液晶面板技术的不断发展，阵列基板行驱动(Gate Driver on Array，简称GOA)技术被广泛应用到液晶面板的电路设计中，为此，越来越多的相关电路走线也同样被集成到面板上。GOA技术是利用现有TFT-LCD阵列制程将栅极行驱动电路制作在阵列(Array)基板上，实现对栅极逐行扫描的驱动方式的一项技术。GOA技术可以节省栅极芯片(Gate IC)，有利于显示屏栅极行驱动(Gate Driver)侧窄边框(narrow border)的设计和成本的降低，得到广泛地应用和研究。随之而来面板的信赖性问题越来越受到关注，其中静电放电（Electro-Static discharge，简称ESD）就是非常重要的一项内容。ESD是指具有不同静电电位的物体互相靠近或直接接触引起的电荷转移。ESD是一种常见的近场危害源，可形成高电压、强电场、瞬时大电流，并伴有强电磁辐射，形成静电放电电磁脉冲。
通常情况下，非GOA技术的液晶面板的栅极驱动电路包含VGH、VGL、STV走线，而采用GOA技术的液晶面板的栅极驱动电路则包含CK1-CK8、VSS、LC1-LC2、STV走线。面板的走线数量越多，跨线也变得越多，ESD也变得越来越高发。
 技术问题
参考图1A-1C，其中，图1A为现有液晶面板走线结构实施例一的示意图，图1B为现有液晶面板走线结构实施例二的示意图，图1C为现有GOA电路结构单元跨线及跨线位置处走线结构剖视图。图1A所示为走线较宽形态下的走线结构，图1B所示为走线较细形态下的走线结构，两者均为从上至下的贯穿结构，即在进线位置处并未进行特别设计。这种走线结构由于在进线位置处无跨线，则当发生ESD时就一定会在GOA电路区（图1A以及图1B中虚框所示区域）。倘若发生ESD的位置在GOA电路区，通常情况下这种断线、短路是无法被避免和修复的。图1C中，第一金属层走线（Metal1）11上设有SiNx绝缘层13，第二金属层走线（Metal2）12设在SiNx绝缘层13上。这种走线结构由于在进线位置处设有跨线，ESD通常会发生在跨线位置，即ESD通常会发生在Metal1、Metal2的跨线位置处，造成的影响则是走线断线、短路，进而影响液晶面板中的电位信号，造成画面显示异常。
 技术解决方案
本发明的目的在于，提供一种走线结构及液晶面板，可以实现当液晶面板的走线发生ESD后，避免电路受到影响造成功能性不良，提高液晶面板的使用稳定性和可靠性。
为实现上述目的，本发明提供了一种走线结构，在每一进线位置处设有第一跨线结构区，所述第一跨线结构区包括依次层叠设置的第一金属层走线、绝缘层以及第二金属层走线，所述进线位置处为所述第一金属层走线进入电路区之前的一段位置；所述第一金属层走线在所述第一跨线结构区包含多条相连的金属线，所述绝缘层覆盖在所述多条相连的金属线上，所述第二金属层走线为浮接状态；所述走线结构还包括设于所述进线位置处与所述电路区之间的第二跨线结构区，所述第二跨线结构区包括依次层叠设置的第一金属层走线、绝缘层以及第二金属层走线；所述绝缘层采用SiNx材料制备。
为实现上述目的，本发明还提供了一种走线结构，在每一进线位置处设有第一跨线结构区，所述第一跨线结构区包括依次层叠设置的第一金属层走线、绝缘层以及第二金属层走线，所述进线位置处为所述第一金属层走线进入电路区之前的一段位置；所述第一金属层走线在所述第一跨线结构区包含多条相连的金属线，所述绝缘层覆盖在所述多条相连的金属线上，所述第二金属层走线为浮接状态。
在一实施例中，所述走线结构包括设于所述进线位置处与所述电路区之间的第二跨线结构区，所述第二跨线结构区包括依次层叠设置的第一金属层走线、绝缘层以及第二金属层走线。
在一实施例中，所述第一金属层走线在所述第一跨线结构区为镂空结构，浮接的所述第二金属层走线设于所述镂空结构上的所述绝缘层上。
在一实施例中，所述第一金属层走线在进入所述第一跨线结构区后分叉成多条走线并在引出所述第一跨线结构区后合并成一条走线，浮接的所述第二金属层走线设于所述多条走线上的所述绝缘层上。
在一实施例中，所述绝缘层采用SiNx材料制备。
为实现上述目的，本发明还提供了一种液晶面板，所述液晶面板包括电路区和走线结构；所述走线结构在每一进线位置处设有第一跨线结构区，所述第一跨线结构区包括依次层叠设置的第一金属层走线、绝缘层以及第二金属层走线，所述进线位置处为所述第一金属层走线进入电路区之前的一段位置；所述第一金属层走线在所述第一跨线结构区包含多条相连的金属线，所述绝缘层覆盖在所述多条相连的金属线上，所述第二金属层走线为浮接状态。
 有益效果
本发明通过在所有进线位置处设置第一跨线结构区，引导ESD发生在第一跨线结构区，从而避免电路受到影响造成功能性不良。当液晶面板的走线发生ESD后，虽然会发生断线、短路的情况，但并不影响产品的功能特性，可以提高液晶面板防ESD性能，进而提高液晶面板的使用稳定性和可靠性。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1A，现有液晶面板走线结构实施例一的示意图；
图1B，现有液晶面板走线结构实施例二的示意图；
图1C，现有GOA电路结构单元跨线及跨线位置处走线结构剖视图；
图2A，本发明走线结构第一实施例的示意图；
图2B为图2A所示走线结构第一跨线结构区的剖视图；
图3，本发明走线结构第二实施例的示意图。
 本发明的实施方式
下面详细描述本发明的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
本发明提供的走线结构，在每一进线位置处设有第一跨线结构区，所述第一跨线结构区包括依次层叠设置的第一金属层走线、绝缘层以及第二金属层走线，所述进线位置处为所述第一金属层走线进入电路区之前的一段位置；所述第一金属层走线在所述第一跨线结构区包含多条相连的金属线，所述绝缘层覆盖在所述多条相连的金属线上，所述第二金属层走线为浮接状态。
可选的，所述走线结构包括设于所述进线位置处与所述电路区之间的第二跨线结构区，所述第二跨线结构区包括依次层叠设置的第一金属层走线、绝缘层以及第二金属层走线。
在这里，我们对进线位置处进行简单说明：液晶面板中的电路信号是通过C-board（集成电路板）直接接入液晶面板的，并通过液晶面板中的走线将信号传递至电路区，进入电路区之前的一段位置定义为进线位置处。通常情况下，ESD经常会发生在从C-board至电路区尾端这段路径中最先遇到的跨线位置处。因此，本发明在所有进线位置处均设置第一跨线结构区，通过在电荷进入电路区之前的进线位置处设置一些跨线结构，引导ESD发生在进线位置处的第一跨线结构区，从而避免电路受到影响造成功能性不良。也即，本发明所述的走线结构当液晶面板的走线发生ESD后，虽然会发生断线、短路的情况，但并不影响产品的功能特性，可以提高液晶面板防ESD性能，进而提高液晶面板的使用稳定性和可靠性。
本发明的走线结构在所有进线位置处均有设置所述第一跨线结构区，此第一跨线结构区设置在走线结构的其它跨线之前，以起到保护其他跨线的作用。不同金属层之间均设置绝缘层（例如可以采用SiNx材料制备）用以绝缘。具体的，所述走线结构包括设于所述进线位置处与所述电路区之间的第二跨线结构区，所述第二跨线结构区包括依次层叠设置的第一金属层走线、绝缘层以及第二金属层走线。也即，正常的跨线设于本发明所述第一跨线结构区之后，引导ESD发生在第一跨线结构区，从而避免电路受到影响造成功能性不良。
以下以采用GOA技术的液晶面板为例，对本发明所述的走线结构进行详细说明。
参考图2A-2B，其中，图2A为本发明所述的走线结构第一实施例的示意图，图2B为图2A所示走线结构剖视图，图2A中虚线框中代表GOA电路区。第一金属层走线21在第一跨线结构区20为镂空结构211，浮接的第二金属层走线22设在镂空结构211上的绝缘层23上。本实施例中第一金属层走线（Metal1）21较宽，因此将进线位置处的第一跨线结构区20的第一金属层走线21设计成镂空结构211，在镂空结构211实质是就是多条相连的金属线，在镂空结构211上面设置一层绝缘层（例如可以采用SiNx材料制备）23用以使第一、二金属层走线21、22绝缘，且在绝缘层23上面设置一层浮接的（floating）的第二金属层走线（Metal2）22；镂空结构211使得第一金属层走线21在第一跨线结构区20同层金属短接。当发生ESD时，本发明所述的走线结构可将发生ESD位置引导至第一跨线结构区20，由于此位置处包含多条相连的金属线，即使其中一条线路发生ESD也不会影响电路信号。而现有的走线结构为从上至下的贯穿结构，由于在进线位置处无跨线结构，则当发生ESD时就一定会在GOA电路区。而倘若在GOA电路区发生ESD，通常情况下这种断线、短路是无法被避免和修复的。
可选的，所述走线结构包括设于所述进线位置处与所述电路区之间的第二跨线结构区29，所述第二跨线结构区29包括依次层叠设置的第一金属层走线21、绝缘层（未标示于图中）以及第二金属层走线22；此处的第二金属层走线22与第一跨线结构区20的浮接的第二金属层走线22采用相同材质，但此处的第二金属层走线22为正常连接其它组件的跨线，而非浮接状态。
参考图3，本发明所述的走线结构第二实施例的示意图，图中虚线框中代表GOA电路区。第一金属层走线31在进入第一跨线结构区30后分叉成多条走线311并在引出第一跨线结构区30后合并成一条走线，浮接的第二金属层走线32设于多条走线311上的绝缘层（未标示于图中）上。本实施例中第一金属层走线（Metal1）31较窄无法设计成镂空结构，因此在进入第一跨线结构区30后将第一金属层走线31分叉为多条走线311，多条走线311短接，在多条走线311上面设置一层绝缘层（例如可以采用SiNx材料制备）用以使第一、二金属层走线绝缘，且在绝缘层上面设置一层浮接的（floating）的第二金属层走线（Metal2）32。当发生ESD时，本发明所述的走线结构可将发生ESD位置引导至第一跨线结构区，由于此位置处包含多条相连的金属线，即使其中一条线路发生ESD也不会影响电路信号。
本发明还提供一种液晶面板，所述的液晶面板包括电路区和走线结构。所述走线结构在每一进线位置处设有第一跨线结构区，所述第一跨线结构区包括依次层叠设置的第一金属层走线、绝缘层以及第二金属层走线，所述进线位置处为所述第一金属层走线进入电路区之前的一段位置；所述第一金属层走线在所述第一跨线结构区包含多条相连的金属线，所述绝缘层覆盖在所述多条相连的金属线上，所述第二金属层走线为浮接状态。
可选的，所述走线结构包括设于所述进线位置处与所述电路区之间的第二跨线结构区，所述第二跨线结构区包括依次层叠设置的第一金属层走线、绝缘层以及第二金属层走线。
第一金属层走线21可以设置为在第一跨线结构区20可以为镂空结构211，浮接的第二金属层走线22设在镂空结构211上的绝缘层23上，如图2A-2B所示第一实施例。在该实施例中第一金属层走线（Metal1）21较宽，因此将进线位置处的第一跨线结构区20的第一金属层走线21设计成镂空结构211，在镂空结构211实质是就是多条相连的金属线，在镂空结构211上面设置一层绝缘层（例如SiNx层）23用以使第一、二金属层走线21、22绝缘，且在绝缘层23上面设置一层浮接的（floating）的第二金属层走线（Metal2）22；镂空结构211使得第一金属层走线21在第一跨线结构区20同层金属短接。当发生ESD时，本发明所述的走线结构可将发生ESD位置引导至第一跨线结构区20，由于此位置处包含多条相连的金属线，即使其中一条线路发生ESD也不会影响电路信号。而现有的走线结构为从上至下的贯穿结构，由于在进线位置处无跨线结构，则当发生ESD时就一定会在GOA电路区。而倘若在GOA电路区发生ESD，通常情况下这种断线、短路是无法被避免和修复的。
第一金属层走线31也可以设置为在进入第一跨线结构区30后分叉成多条走线311并在引出第一跨线结构区30后合并成一条走线，浮接的第二金属层走线32设于多条走线311上的绝缘层上，如图3所示第二实施例。在该实施例中第一金属层走线（Metal1）31较窄无法设计成镂空结构，因此在进入第一跨线结构区30后将第一金属层走线31分叉为多条走线311，多条走线311短接，在多条走线311上面设置一层绝缘层（例如可以采用SiNx材料制备）用以使第一、二金属层走线绝缘，且在绝缘层上面设置一层浮接的（floating）的第二金属层走线（Metal2）32。当发生ESD时，本发明所述的走线结构可将发生ESD位置引导至第一跨线结构区，由于此位置处包含多条相连的金属线，即使其中一条线路发生ESD也不会影响电路信号。
所述液晶面板可以采用GOA技术，采用GOA技术的液晶面板的栅极驱动电路包含CK1-CK8、VSS、LC1-LC2、STV走线。所述液晶面板也可以采用非GOA技术，采用非GOA技术的液晶面板的栅极驱动电路包含VGH、VGL、STV走线。每一走线采用上述走线结构，在进线位置处设置第一跨线结构区，引导ESD发生在第一跨线结构区，从而避免电路受到影响造成功能性不良。
液晶面板中的电路信号是通过C-board（集成电路板）直接接入液晶面板的，并通过液晶面板中的走线将信号传递至电路区（例如GOA电路区），进入电路区之前的一段位置定义为进线位置处。通常情况下，ESD经常会发生在从C-board至电路区尾端这段路径中最先遇到的跨线位置处。通过在所有进线位置处均设置第一跨线结构区，也即在电荷进入电路区之前设置一些跨线结构，引导ESD发生在第一跨线结构区，从而避免电路受到影响造成功能性不良。当液晶面板的走线发生ESD后，虽然会发生断线、短路的情况，但并不影响产品的功能特性，可以提高液晶面板防ESD性能，进而提高液晶面板的使用稳定性和可靠性。
本发明的走线结构在所有进线位置处均有设置所述第一跨线结构区，此第一跨线结构区设置在走线结构的其它跨线之前，以起到保护其他跨线的作用。不同金属层之间均设置绝缘层（例如可以采用SiNx材料制备）用以绝缘。具体的，所述走线结构包括设于所述进线位置处与所述电路区之间的第二跨线结构区，所述第二跨线结构区包括依次层叠设置的第一金属层走线、绝缘层以及第二金属层走线。也即，正常的跨线设于本发明所述第一跨线结构区之后，引导ESD发生在第一跨线结构区，从而避免电路受到影响造成功能性不良。
 工业实用性
本申请的主题可以在工业中制造和使用，具备工业实用性。

Claims (13)

  1. 一种走线结构，其中，在每一进线位置处设有第一跨线结构区，所述第一跨线结构区包括依次层叠设置的第一金属层走线、绝缘层以及第二金属层走线，所述进线位置处为所述第一金属层走线进入电路区之前的一段位置；所述第一金属层走线在所述第一跨线结构区包含多条相连的金属线，所述绝缘层覆盖在所述多条相连的金属线上，所述第二金属层走线为浮接状态；所述走线结构还包括设于所述进线位置处与所述电路区之间的第二跨线结构区，所述第二跨线结构区包括依次层叠设置的第一金属层走线、绝缘层以及第二金属层走线；所述绝缘层采用SiNx材料制备。
  2. 如权利要求1所述的走线结构，其中，所述第一金属层走线在所述第一跨线结构区为镂空结构，浮接的所述第二金属层走线设于所述镂空结构上的所述绝缘层上。
  3. 如权利要求1所述的走线结构，其中，所述第一金属层走线在进入所述第一跨线结构区后分叉成多条走线并在引出所述第一跨线结构区后合并成一条走线，浮接的所述第二金属层走线设于所述多条走线上的所述绝缘层上。
  4. 一种走线结构，其中，在每一进线位置处设有第一跨线结构区，所述第一跨线结构区包括依次层叠设置的第一金属层走线、绝缘层以及第二金属层走线，所述进线位置处为所述第一金属层走线进入电路区之前的一段位置；所述第一金属层走线在所述第一跨线结构区包含多条相连的金属线，所述绝缘层覆盖在所述多条相连的金属线上，所述第二金属层走线为浮接状态。
  5. 如权利要求4所述的走线结构，其中，所述走线结构包括设于所述进线位置处与所述电路区之间的第二跨线结构区，所述第二跨线结构区包括依次层叠设置的第一金属层走线、绝缘层以及第二金属层走线。
  6. 如权利要求4所述的走线结构，其中，所述第一金属层走线在所述第一跨线结构区为镂空结构，浮接的所述第二金属层走线设于所述镂空结构上的所述绝缘层上。
  7. 如权利要求4所述的走线结构，其中，所述第一金属层走线在进入所述第一跨线结构区后分叉成多条走线并在引出所述第一跨线结构区后合并成一条走线，浮接的所述第二金属层走线设于所述多条走线上的所述绝缘层上。
  8. 如权利要求4所述的走线结构，其中，所述绝缘层采用SiNx材料制备。
  9. 一种液晶面板，所述液晶面板包括电路区和走线结构；其中，所述走线结构在每一进线位置处设有第一跨线结构区，所述第一跨线结构区包括依次层叠设置的第一金属层走线、绝缘层以及第二金属层走线，所述进线位置处为所述第一金属层走线进入电路区之前的一段位置；所述第一金属层走线在所述第一跨线结构区包含多条相连的金属线，所述绝缘层覆盖在所述多条相连的金属线上，所述第二金属层走线为浮接状态。
  10. 如权利要求9所述的液晶面板，其中，所述走线结构包括设于所述进线位置处与所述电路区之间的第二跨线结构区，所述第二跨线结构区包括依次层叠设置的第一金属层走线、绝缘层以及第二金属层走线。
  11. 如权利要求9所述的液晶面板，其中，所述第一金属层走线在所述第一跨线结构区为镂空结构，浮接的所述第二金属层走线设于所述镂空结构上的所述绝缘层上。
  12. 如权利要求9所述的液晶面板，其中，所述第一金属层走线在进入所述第一跨线结构区后分叉成多条走线并在引出所述第一跨线结构区后合并成一条走线，浮接的所述第二金属层走线设于所述多条走线上的所述绝缘层上。
  13. 如权利要求9所述的液晶面板，其中，所述液晶面板采用GOA技术。
PCT/CN2019/072803 2018-10-11 2019-01-23 一种走线结构及液晶面板 WO2020073561A1 (zh)

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Publication number Priority date Publication date Assignee Title
CN109212855A (zh) * 2018-10-11 2019-01-15 深圳市华星光电技术有限公司 一种走线结构及液晶面板
CN111367130A (zh) * 2020-04-27 2020-07-03 Tcl华星光电技术有限公司 阵列基板、显示面板及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN203480178U (zh) * 2013-07-30 2014-03-12 京东方科技集团股份有限公司 阵列基板和显示装置
CN104362154A (zh) * 2014-11-17 2015-02-18 深圳市华星光电技术有限公司 一种阵列基板及其制备方法
CN104701313A (zh) * 2015-03-11 2015-06-10 京东方科技集团股份有限公司 阵列基板及制作方法、显示装置
CN105118822A (zh) * 2015-08-26 2015-12-02 上海中航光电子有限公司 换线结构
US20170155245A1 (en) * 2015-11-27 2017-06-01 Samsung Electronics Co., Ltd. Display drive chip
CN109212855A (zh) * 2018-10-11 2019-01-15 深圳市华星光电技术有限公司 一种走线结构及液晶面板

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1115016A (ja) * 1997-06-20 1999-01-22 Hitachi Ltd 液晶表示装置
CN101093297A (zh) * 2006-06-23 2007-12-26 中华映管股份有限公司 液晶显示器的静电防护电路
CN101290408B (zh) * 2007-04-17 2010-04-14 北京京东方光电科技有限公司 一种薄膜晶体管显示器
CN101201520B (zh) * 2007-12-27 2010-09-08 昆山龙腾光电有限公司 一种具有静电防护功能的液晶显示装置阵列基板
CN203707119U (zh) * 2013-05-30 2014-07-09 上海天马微电子有限公司 静电防护结构及平板x射线图像探测器
CN103941440B (zh) * 2013-12-30 2017-02-15 上海中航光电子有限公司 一种阵列基板、显示面板及显示器
CN107731791B (zh) * 2017-11-20 2020-07-21 深圳市华星光电技术有限公司 一种提高跨线区静电击伤修复良率的结构

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN203480178U (zh) * 2013-07-30 2014-03-12 京东方科技集团股份有限公司 阵列基板和显示装置
CN104362154A (zh) * 2014-11-17 2015-02-18 深圳市华星光电技术有限公司 一种阵列基板及其制备方法
CN104701313A (zh) * 2015-03-11 2015-06-10 京东方科技集团股份有限公司 阵列基板及制作方法、显示装置
CN105118822A (zh) * 2015-08-26 2015-12-02 上海中航光电子有限公司 换线结构
US20170155245A1 (en) * 2015-11-27 2017-06-01 Samsung Electronics Co., Ltd. Display drive chip
CN109212855A (zh) * 2018-10-11 2019-01-15 深圳市华星光电技术有限公司 一种走线结构及液晶面板

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