WO2020191793A1 - 一种氧化铪基铁电栅场效应晶体管及其制备方法 - Google Patents

一种氧化铪基铁电栅场效应晶体管及其制备方法 Download PDF

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WO2020191793A1
WO2020191793A1 PCT/CN2019/080759 CN2019080759W WO2020191793A1 WO 2020191793 A1 WO2020191793 A1 WO 2020191793A1 CN 2019080759 W CN2019080759 W CN 2019080759W WO 2020191793 A1 WO2020191793 A1 WO 2020191793A1
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layer
hafnium oxide
substrate
thin film
gate electrode
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English (en)
French (fr)
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廖敏
曾斌建
周益春
廖佳佳
彭强祥
郇延伟
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湘潭大学
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7887—Programmable transistors with more than two possible different levels of programmation

Definitions

  • the invention relates to the field of electronic technology, in particular to a hafnium oxide-based ferroelectric gate field effect transistor and a preparation method thereof.
  • FeFET ferroelectric gate field effect transistor
  • One is the floating gate type FeFET whose gate structure is metal electrode (M)/ferroelectric thin film (F)/metal electrode (M)/buffer layer (I)/semiconductor (S), namely MFMIS, the other is MFIS-FET, that is, the gate structure is metal electrode (M)/ferroelectric film (F)/buffer layer (I)/semiconductor (S), namely MFIS.
  • MFMIS-FET memory has better retention performance, and can adjust the area of the floating gate and the control gate to increase the storage window of the device, reduce the erase voltage and improve the fatigue performance.
  • One is MFMIS-FET with a gate structure of Pt/SrBi 2 Ta 2 O 9 /Pt/SrTa 2 O 6 /SiON/Si.
  • the SrBi 2 Ta 2 O 9 iron By designing the area of the control gate and the floating gate, the SrBi 2 Ta 2 O 9 iron The electric film can be in a saturated polarization state at a small working voltage, achieving a larger storage window and excellent retention performance.
  • the SrBi 2 Ta 2 O 9 ferroelectric thin film material has poor shrinkage and the thickness is generally greater than 200 nm.
  • the inert metal Pt is more difficult to etch, making it based on Pt/SrBi 2 Ta 2 O 9 /Pt/SrTa 2 O 6 /SiON/Si structure of MFMIS-FET scale reduction process is limited.
  • This structure uses poly-Si as a floating gate, the process is simpler, and it can also prevent the Pb (Zr 0.52 Ti 0.48 ) O 3 from diffusing to the substrate, which is more conducive to the integration of ferroelectric and semiconductor processes.
  • the Pb(Zr 0.52 Ti 0.48 )O 3 film has poor shrinkage, and the thickness is generally greater than 70nm.
  • Pb is a volatile element that increases the difficulty of process integration.
  • the top electrode still uses inert Pt, making it based on Pt/Pb( Zr 0.52 Ti 0.48 ) O 3 /Poly-Si/SiO 2 /Si structure of MFMIS-FET scale reduction process is limited.
  • the shortcomings of the gate structure are: the floating gate (bottom electrode) and the control gate (top electrode) of the gate structure use TaN electrodes, but TaN During the annealing process, the electrode easily reacts with the hafnium oxide-based ferroelectric film to form an interface layer, and the diffusion of metal elements may occur, thus reducing the electrical performance of the device; when the device size is further reduced, the electrical performance degradation phenomenon is more obvious.
  • the purpose of the present invention is to provide a hafnium oxide-based ferroelectric gate field effect transistor and a preparation method thereof in view of the reliability problems existing in the existing floating gate type ferroelectric gate field effect transistor technology and the deficiencies in the process. In order to realize the highly reliable integration of the device.
  • the first aspect of the present invention provides a hafnium oxide-based ferroelectric gate field effect transistor, comprising: a substrate; an isolation region is provided on the periphery of the substrate, and the upper surface thereof is not lower than the The upper surface of the substrate, and the bottom surface is not lower than the bottom surface of the substrate; the gate structure includes a buffer layer, a floating gate electrode, and a hafnium oxide-based ferroelectric film layered on the middle of the upper surface of the substrate sequentially from bottom to top Layer, control gate electrode and thin film electrode layer; sidewalls are arranged on the outside of the gate structure, the inner surface of which is close to the gate structure; the source region and the drain region are oppositely arranged on both sides of the gate structure, The inner side of the isolation region extends toward the middle of the substrate, and its upper surface is flush with the substrate, and the bottom surface is not lower than the bottom surface of the isolation region; the first metal silicide layer is formed by the isolation region The inner side extend
  • the buffer layer material is any one or more of SiO 2 , SiON, Al 2 O 3 , La 2 O 3 , HfO 2 , HfON, HfSiON, and aluminum-doped HfO 2 (Al:HfO 2 ) kind.
  • the thickness of the buffer layer is 3-10 nm.
  • the thickness of the floating gate electrode and the control gate electrode are both 5-50 nm.
  • the material of the thin film electrode layer is any one or more of polysilicon, amorphous silicon, W, TaN, TiN, and HfN x (0 ⁇ x ⁇ 1.1).
  • the thickness of the thin film electrode layer is 10-200 nm.
  • the material of the first metal silicide layer and the second metal silicide layer is any one of TiSi 2 , CoSi 2 , and NiSi 2 .
  • the thickness of the first metal silicide layer and the second metal silicide layer are both 5-30 nm.
  • the doping elements in the hafnium oxide-based ferroelectric thin film layer are zirconium (Zr), aluminum (Al), silicon (Si), yttrium (Y), strontium (Sr), lanthanum (La), lutetium ( At least one of Lu), gadolinium (Gd), scandium (Sc), neodymium (Nd), germanium (Ge), nitrogen (N); further preferably, the doping element is zirconium (Zr), aluminum ( At least one of Al), silicon (Si), and lanthanum (La).
  • the thickness of the hafnium oxide-based ferroelectric thin film layer is 3-20 nm.
  • the second aspect of the present invention provides a method for preparing the above-mentioned hafnium oxide-based ferroelectric gate field effect transistor, including:
  • the process of forming the buffer layer is an atomic layer deposition process, a chemical vapor deposition process, a chemical oxidation process or a thermal oxidation process;
  • the process of forming the floating gate electrode is an atomic layer deposition process, a chemical vapor deposition process or a magnetron sputtering process;
  • the process of forming the doped hafnium oxide thin film layer is an atomic layer deposition process, a metal organic chemical vapor deposition process or a magnetron sputtering process;
  • control gate electrode on the upper surface of the doped hafnium oxide thin film layer; preferably, the process of forming the control gate electrode is a magnetron sputtering process, a chemical vapor deposition process, or an atomic layer deposition process;
  • the process of forming the thin film electrode layer is a magnetron sputtering process or a chemical vapor deposition process.
  • etching process described in S4 is a reactive ion etching process.
  • the operation described in S7 includes: using an ion implantation process to form a first heavily doped region and a second heavily doped region on the first lightly doped region and the second lightly doped region on both sides of the sidewall spacer, respectively Area.
  • the process of depositing motor metal in S8 is a magnetron sputtering process or a chemical vapor deposition process.
  • the rapid thermal annealing operation described in S9 further includes:
  • the doped hafnium oxide-based thin film layer forms a ferroelectric phase, forming a doped hafnium oxide-based ferroelectric thin film layer.
  • the annealing temperature is 400-1000° C., and the annealing time is 1-60 seconds; and/or the rapid thermal annealing operation is performed in vacuum or inert gas; preferably, The inert gas is N 2 or Ar.
  • etching process described in S10 is a wet etching process.
  • HfN x (0 ⁇ x ⁇ 1.1) with excellent thermal stability as the floating gate electrode and control gate electrode, and HfN x (0 ⁇ x ⁇ 1.1) as the Hf series metal, it is a good solution to the existing technology
  • the floating gate electrode and the control gate electrode react with the interface of the hafnium oxide-based ferroelectric thin film during the crystallization annealing process, avoid element diffusion, and improve the electrical reliability of the hafnium oxide-based ferroelectric gate field effect transistor.
  • the preparation method of the hafnium oxide-based ferroelectric gate field effect transistor provided by the present invention is a front gate process, which can achieve high integration density, and introduces a self-aligned process, that is, the gate structure formed after etching is used as a mask, Then an ion implantation process is used to form lightly doped regions on both sides of the gate structure. This method can reduce the process difficulty.
  • the implanted ions are activated to form the source and drain regions of the hafnium oxide-based ferroelectric gate field effect transistor; on the other hand, the doped hafnium oxide film layer is crystallized to form a ferroelectric phase , That is, a hafnium oxide-based ferroelectric film is formed; a metal silicide layer can also be formed on the source region, the drain region and the gate structure to reduce the contact resistance.
  • FIG. 1 is a schematic structural diagram of a hafnium oxide-based ferroelectric gate field effect transistor provided by an embodiment of the present invention
  • FIG. 2 is a flowchart of a method for manufacturing a hafnium oxide-based ferroelectric gate field effect transistor according to an embodiment of the present invention
  • 3a-3f are schematic diagrams of the manufacturing process of hafnium oxide-based ferroelectric gate field effect transistors provided by embodiments of the present invention.
  • FIG. 1 is a schematic structural diagram of a hafnium oxide-based ferroelectric gate field effect transistor provided by an embodiment of the present invention.
  • an embodiment of the present invention provides a hafnium oxide-based ferroelectric gate field effect transistor, including: a substrate 1, an isolation region 2, a gate structure 3, a sidewall 4, a source region 5, a drain region 6, a first The metal silicide layer 71 and the second metal silicide layer 72.
  • the substrate 1 is p-type or n-type doped single crystal silicon or silicon-on-insulator (Silicon-On-Insulator, referred to as SOI for short).
  • the p-type doping is the doping element boron (B); the n-type doping is the doping element phosphorus (P) or arsenic (As).
  • the isolation region 2 is arranged on the periphery of the substrate 1, and its upper surface is not lower than the upper surface of the substrate 1, and the bottom surface is not lower than the bottom surface of the substrate 1.
  • the material of the isolation region 2 is at least one of SiO 2 and Si 3 N 4 .
  • the gate structure 3 includes a buffer layer 31, a floating gate electrode 32, a hafnium oxide-based ferroelectric thin film layer 33b, a control gate electrode 34, and a thin film electrode layer 35 stacked in the middle of the upper surface of the substrate 1 from bottom to top.
  • the material of the buffer layer 31 is any one or more of SiO 2 , SiON, Al 2 O 3 , La 2 O 3 , HfO 2 , HfON, HfSiON, and aluminum-doped HfO 2 (Al:HfO 2 ) .
  • the buffer layer 31 has a thickness of 3-10 nm.
  • the doping elements in the hafnium oxide-based ferroelectric thin film layer 33b are zirconium (Zr), aluminum (Al), silicon (Si), yttrium (Y), strontium (Sr), lanthanum (La), lutetium ( At least one of Lu), gadolinium (Gd), scandium (Sc), neodymium (Nd), germanium (Ge), and nitrogen (N).
  • the doping element in the hafnium oxide-based ferroelectric thin film layer 33b is at least one of zirconium (Zr), aluminum (Al), silicon (Si), and lanthanum (La).
  • the thickness of the hafnium oxide-based ferroelectric thin film layer 33b is 3-20 nm.
  • the material of the floating gate electrode 32 and the control gate electrode 34 is HfN x , and the number of N atoms in HfN x is 0 ⁇ x ⁇ 1.1.
  • the thickness of the floating gate electrode 32 and the control gate electrode 34 are both 5-50 nm.
  • the material of the thin film electrode layer 35 is any one or more of polysilicon, amorphous silicon, W, TaN, TiN, and HfN x (0 ⁇ x ⁇ 1.1).
  • the thickness of the thin-film electrode layer 35 is 10-200 nm.
  • the side wall 4 is arranged outside the grid structure 3, and its inner surface is close to the grid structure 3.
  • the source region 5 and the drain region 6 are oppositely arranged on both sides of the gate structure 3, and are formed from the inner side of the isolation region 2 extending toward the middle of the substrate 1, the upper surface of which is flush with the substrate 1, and the bottom surface is not lower than the isolation region 2. The bottom surface.
  • the first metal silicide layer 71 is formed by extending from the inner side of the isolation region 2 toward the sidewall spacer 4, the upper surface of which is higher than the upper surface of the substrate 1, and the bottom surface is higher than the bottom surface of the isolation region 2, and the first metal silicide layer 71
  • the length of is smaller than the length of the source region 5 or the drain region 6.
  • the length of the first metal silicide layer 71 refers to the size along the inner side of the isolation region 2 toward the sidewall 4 extending direction, that is, the size in the left-right direction in FIG. 1; the length of the source region 5 (or drain region 6) refers to the length along the isolation region 2
  • the inner side of the zone 2 faces the dimension of the extending direction of the middle of the substrate 1.
  • the second metal silicide layer 72 is disposed on the upper surface of the gate structure 3 and the lower surface thereof is close to the gate structure 3.
  • the material of the first metal silicide layer 71 and the second metal silicide layer 72 is any one of TiSi 2 , CoSi 2 , and NiSi 2 .
  • the thickness of the first metal silicide layer 71 and the second metal silicide layer 72 are both 5-30 nm.
  • the material of the source region 5 and the drain region 6 when the material of the substrate 1 is p-type doped, the material of the source region 5 and the drain region 6 is n-type doped single crystal silicon or silicon-on-insulator; or, when the material of the substrate 1 In the case of n-type doping, the material of the source region 5 and the drain region 6 is p-type doped single crystal silicon or silicon-on-insulator.
  • the hafnium oxide-based ferroelectric gate field effect transistor includes: a substrate 1, an isolation region 2, a gate structure 3, a sidewall spacer 4, a source region 5, a drain region 6, and a first metal silicide The material layer 71 and the second metal silicide layer 72.
  • the substrate 1 is p-type doped single crystal silicon; the p-type doped is doped element boron (B).
  • the isolation region 2 is arranged on the periphery of the substrate 1, and its upper surface is not lower than the upper surface of the substrate 1, and the bottom surface is not lower than the bottom surface of the substrate 1, wherein the material of the isolation region 2 is SiO 2 .
  • the gate structure 3 includes a buffer layer 31, a floating gate electrode 32, a hafnium oxide-based ferroelectric thin film layer 33b, a control gate electrode 34, and a thin film electrode layer 35 which are sequentially stacked on the upper surface of the substrate 1 from bottom to top;
  • the material of layer 31 is HfO 2 and the thickness is 5 nm;
  • the doping element in the hafnium oxide-based ferroelectric thin film layer 33b is zirconium (Zr), the doping amount is 50%, and the thickness is 10 nm;
  • the material of 34 is HfN and the thickness is 10 nm;
  • the material of the thin film electrode layer 35 is polysilicon with the thickness of 50 nm.
  • the side wall 4 is arranged outside the gate structure 3, and its inner surface is close to the gate structure 3; the material of the side wall 4 is SiO 2 ; the lateral width of the gate structure 3 is equal to the distance between the two side walls 4.
  • the source region 5 and the drain region 6 are arranged on opposite sides of the gate structure 3, and are formed from the inner side of the isolation region 2 extending toward the middle of the substrate 1.
  • the upper surface is flush with the substrate 1, and the bottom surface is higher than that of the isolation region 2.
  • the bottom surface; the doping element of the source region 5 and the drain region 6 is phosphorus.
  • the source region 5 includes an activated first lightly doped region 51b and an activated first heavily doped region 52b;
  • the drain region 6 includes an activated second lightly doped region 61b and an activated second heavily doped region 62b .
  • the activated first lightly doped region 51b and the activated second lightly doped region 61b are formed by annealing the lightly doped region, the activated first heavily doped region 52b and the activated second heavily doped region 62b are heavily doped
  • the impurity area is formed after annealing.
  • the first metal silicide layer 71 is formed by extending from the inner side of the isolation region 2 toward the sidewall spacer 4, the upper surface of which is higher than the substrate 1, the bottom surface is higher than the bottom surface of the isolation region 2, and the length of the first metal silicide layer 71 is less than The length of the source region 5 and the drain region 6; the material of the first metal silicide layer 71 is TiSi 2 ; the thickness of the first metal silicide layer 71 is 10 nm.
  • the second metal silicide layer 72 is disposed on the upper surface of the gate structure 3, and its lower surface is close to the gate structure 3.
  • the material of the second metal silicide layer 72 is TiSi 2 ; the thickness of the second metal silicide layer 72 is 10 nm .
  • the positions of the source region 5 and the drain region 6 shown in FIG. 1 are only taken as an example, but the present invention is not limited thereto, and the positions of the source region 5 and the drain region 6 can be exchanged.
  • FIG. 2 is a flowchart of a method for manufacturing a hafnium oxide-based ferroelectric gate field effect transistor provided by an embodiment of the present invention.
  • 3a-3f are schematic diagrams of the manufacturing process of hafnium oxide-based ferroelectric gate field effect transistors provided by embodiments of the present invention.
  • the embodiment of the present invention also provides a method for preparing a hafnium oxide-based ferroelectric gate field effect transistor, which is used for the preparation of the hafnium oxide-based ferroelectric gate field effect transistor in the foregoing embodiment, including:
  • an isolation region 2 is provided on the periphery of the substrate 1, the upper surface of the isolation region 2 is not lower than the upper surface of the substrate 1, and the bottom surface is higher than the bottom surface of the substrate 1.
  • step S3 the operation of forming a multilayer film structure in step S3 includes the following steps:
  • the process for forming the buffer layer 31 is an atomic layer deposition process, a chemical vapor deposition process, a chemical oxidation process, or a thermal oxidation process.
  • the material of the floating gate electrode 32 is HfN x , the number of N atoms in HfN x is 0 ⁇ x ⁇ 1.1; the thickness of the floating gate electrode 32 is 5-50 nm.
  • the process of forming the floating gate electrode 32 is an atomic layer deposition process, a chemical vapor deposition process, or a magnetron sputtering process.
  • the doping elements in the doped hafnium oxide thin film layer 33a are zirconium (Zr), aluminum (Al), silicon (Si), yttrium (Y), strontium (Sr), lanthanum (La), lutetium (Lu), At least one of gadolinium (Gd), scandium (Sc), neodymium (Nd), germanium (Ge), and nitrogen (N).
  • the process for forming the doped hafnium oxide thin film layer 33a is an atomic layer deposition process, a metal organic chemical vapor deposition process, or a magnetron sputtering process.
  • control gate electrode 34 formed on the upper surface of the doped hafnium oxide thin film layer 33a.
  • the material of the control gate electrode 34 is HfN x , the number of N atoms in HfN x is 0 ⁇ x ⁇ 1.1; the thickness of the control gate electrode 34 is 5-50 nm.
  • the process of forming the control gate electrode 34 is a magnetron sputtering process, a chemical vapor deposition process, or an atomic layer deposition process.
  • the process of forming the thin film electrode layer 35 is a magnetron sputtering process or a chemical vapor deposition process.
  • the etching process is a reactive ion etching process.
  • the lightly doped drain process of S5 includes the following steps:
  • a first lightly doped region 51a and a second lightly doped region 61a are formed on both sides of the gate structure 3 by an ion implantation method.
  • the step of S6 includes: depositing an insulating dielectric layer on the device structure formed in S5 using a chemical vapor deposition process, and then etching the insulating dielectric layer using a reactive ion etching process to form the sidewall spacer 4.
  • the material of the insulating dielectric layer is at least one of SiO 2 and Si 3 N 4 .
  • the first lightly doped region 51a and the second lightly doped region 61a on both sides of the sidewall spacer 4 respectively form a first heavily doped region 52a and a second heavily doped region 62a.
  • an ion implantation process is used to form a first heavily doped region 52a and a second heavily doped region 62a on the first lightly doped region 51a and the second lightly doped region 61a on both sides of the sidewall spacer 4, respectively.
  • the process of depositing electrode metal is a magnetron sputtering process or a chemical vapor deposition process.
  • the electrode metal is any one of Ti, Co, and Ni.
  • the step of activating the ions implanted in steps S5 and S7 to form the source region 5 and the drain region 6 includes:
  • step S91 and step S92 includes but is not limited to the above sequence.
  • the sequence of step S91 and step S92 can be performed synchronously, or can be appropriately adjusted according to actual needs.
  • step S9 further includes:
  • the doped hafnium oxide-based thin film layer forms a ferroelectric phase, that is, a hafnium oxide-based ferroelectric thin film layer 33b is formed.
  • the annealing temperature is 400-1000°C.
  • the annealing time is 1-60 seconds.
  • the rapid thermal annealing operation is performed in vacuum or inert gas.
  • the inert gas is N 2 or Ar.
  • the material of the first metal silicide layer 71 and the second metal silicide layer 72 is any one of TiSi 2 , CoSi 2 , and NiSi 2 .
  • the thickness of the first metal silicide layer 71 and the second metal silicide layer 72 are both 5-30 nm.
  • the etching process is a wet etching process.
  • the positions of the first lightly doped region 51a and the second lightly doped region 61a shown in FIG. 3d and FIG. 3e are merely examples, but the present invention is not limited thereto.
  • the first lightly doped region The positions of 51a and the second lightly doped region 61a can be exchanged. Accordingly, the positions of the first heavily doped region 52a and the second lightly doped region 62a in FIG. 3e, and the activated first lightly doped region in FIG. 3f
  • the positions of the region 51b and the activated second lightly doped region 61b, the positions of the activated first heavily doped region 52b and the activated second heavily doped region 62b are adjusted accordingly.
  • the method for preparing the hafnium oxide-based ferroelectric gate field effect transistor of the present invention is introduced.
  • embodiment 1 provides a method for preparing a hafnium oxide-based ferroelectric gate field effect transistor, wherein the selected substrate 1 is p-type doped Si (p-Si), the The preparation method includes the following steps:
  • Step 1 Referring to FIG. 2 and FIG. 3a, first, the substrate 1 is cleaned using a standard cleaning process according to the process flow S1. Then, the isolation region 2 is formed by a local oxidation of silicon (LOCOS) process according to the process flow S2, and the area outside the isolation region 2 is defined as an active region.
  • LOCS local oxidation of silicon
  • Step 2 With reference to Figures 2 and 3b, first use a standard cleaning process to clean the substrate 1 again to remove the oxide layer on the surface of the active area.
  • an atomic layer deposition process is used to deposit a buffer layer 31 with a thickness of 5 nm.
  • the material is HfO 2 .
  • Step 3 Referring to FIGS. 2 and 3b, according to the process flow S32, a magnetron sputtering process is used to form HfN with a thickness of 10 nm as the floating gate electrode 32 on the buffer layer 31 formed in the step 2.
  • Step 4 Referring to FIGS. 2 and 3b, according to the process flow S33, an atomic layer deposition process is used to deposit a doped hafnium oxide thin film layer 33a with a thickness of 10 nm on the floating gate electrode 32 formed in step 3, wherein the doped hafnium oxide thin film layer
  • the material of 33a is Hf 0.5 Zr 0.5 O 2 .
  • Step 5 Referring to FIGS. 2 and 3b, according to the process flow S34, a magnetron sputtering process is used to deposit HfN with a thickness of 10 nm as the control gate electrode 34 on the doped hafnium oxide thin film layer 33a.
  • Step 6 Referring to FIGS. 2 and 3b, according to the process flow S35, a thin film electrode layer 35 with a thickness of 50 nm is deposited on the HfN control gate electrode 34 described in step 5 by using a chemical vapor deposition process.
  • the material of the thin film electrode layer 35 is polysilicon.
  • Step 7 Referring to FIG. 2 and FIG. 3c, according to the process flow S4, the multi-layer thin film structure formed in Step 2 to Step 6 is etched by the reactive ion etching technique to form the gate structure 3.
  • Step 8 Referring to Figures 2 and 3d, according to the lightly doped drain process (LDD) in the process flow S5, the gate structure 3 formed in step 7 is used as a mask, and the ion implantation method is used to line the gate structure 3 from both sides As ions are implanted into the bottom 1 to form the first lightly doped region 51a and the second lightly doped region 61a, respectively.
  • LDD lightly doped drain process
  • the material of the substrate 1 is p-type doped Si (p-Si), where the first lightly doped region 51a and the second lightly doped region 61a are low energy shallow junction lightly doped n regions (n-).
  • Step 9 Referring to Figures 2 and 3e, according to the process flow S6, a layer of silicon dioxide with a thickness of 100nm is deposited on the gate structure 3 and the substrate 1 by a chemical vapor deposition method, and then a dry etching process is used to etch After this layer of silicon dioxide is etched away, due to the anisotropy, part of silicon dioxide remains on both sides of the gate structure 3 to form sidewall spacers 4.
  • Step 10 Referring to Figures 2 and 3f, according to the process flow S7, after the sidewall 4 is completed, ion implantation technology is used to inject phosphorous ions into the substrate 1 from both sides of the sidewall 4 to inject phosphorous ions on both sides of the sidewall 4 A lightly doped region 51a and a second lightly doped region 61a form a first heavily doped region 52a and a second heavily doped region 62a, respectively.
  • the material of the substrate 1 is p-type doped Si (p-Si), where the first heavily doped region 52a and the second heavily doped region 62a are n-type heavily doped regions (n+ ).
  • Step 11 Referring to FIG. 2 and FIG. 3f, according to the process flow S8, a layer of electrode metal Ti with a thickness of 50 nm is deposited on the gate structure 3 and the substrate 1 using a magnetron sputtering process.
  • Step 12 Referring to Figure 2 and Figure 3f, according to the process flow S9, the device structure formed in step 11 is subjected to rapid thermal annealing (RTA), the annealing temperature is 500°C, the annealing time is about 60 seconds, and the annealing is in a N 2 atmosphere get on.
  • RTA rapid thermal annealing
  • the steps of rapid thermal annealing include:
  • a first metal silicide layer 71 is formed over the source region 5 and the drain region 6, and a second metal silicide layer 72 is formed on the upper surface of the gate structure 3.
  • Step 13 Referring to FIG. 2 and FIG. 3f, according to the process flow S10, the electrode metal deposited in step 11 and unreacted in step 12 is annealed by a wet process to obtain a hafnium oxide-based ferroelectric gate field effect transistor.
  • embodiment 2 provides a method for manufacturing a hafnium oxide-based ferroelectric gate field effect transistor, wherein the selected substrate 1 is a p-type SOI substrate, and the manufacturing method includes the following steps:
  • Step 1 Referring to FIG. 2 and FIG. 3a, first, the substrate 1 is cleaned using a standard cleaning process according to the process flow S1. Then, according to the process flow S2, the silicon substrate at the isolation region 2 is etched by a reactive ion etching process to form an island (Mesa) structure on the substrate 1 to achieve isolation, and the area outside the isolation region 2 is defined as an active region.
  • the silicon substrate at the isolation region 2 is etched by a reactive ion etching process to form an island (Mesa) structure on the substrate 1 to achieve isolation, and the area outside the isolation region 2 is defined as an active region.
  • Step 2 With reference to Figures 2 and 3b, first use a standard cleaning process to clean the substrate 1 again to remove the oxide layer on the surface of the active area.
  • a 5nm buffer layer 31 is deposited using a chemical vapor deposition process.
  • the material is Al 2 O 3 .
  • Step 3 Referring to FIGS. 2 and 3b, according to the process flow S32, a chemical vapor deposition process is used to form HfN 0.5 with a thickness of 20 nm as the floating gate electrode 32 on the buffer layer 31 formed in step 2;
  • Step 4 Referring to Figures 2 and 3b, according to the process flow S33, an atomic layer deposition process is used to deposit a doped hafnium oxide thin film layer 33a with a thickness of 15 nm on the floating gate electrode 32 formed in step 3, and the doped hafnium oxide thin film layer 33a
  • the material is Al-doped hafnium oxide (Al:HfO 2 ), and the doping content is 4.8%.
  • Step 5 Referring to FIG. 2 and FIG. 3b, according to the process flow S34, a chemical vapor deposition process is used to deposit HfN 0.5 with a thickness of 5 nm as the control gate electrode 34 on the doped hafnium oxide thin film layer 33a.
  • Step 6 Referring to FIGS. 2 and 3b, according to the process flow S35, a thin film electrode layer 35 with a thickness of 50 nm is deposited on the HfN 0.5 control gate electrode 34 in step 5 by using a magnetron sputtering process.
  • the thin film electrode layer 35 is made of W.
  • Step 7 Referring to FIG. 2 and FIG. 3c, according to the process flow S4, the multi-layer thin film structure formed in Step 2 to Step 6 is etched by the reactive ion etching technique to form the gate structure 3.
  • Step 8 Referring to Figures 2 and 3d, according to the lightly doped drain process (LDD) in the process flow S5, the gate structure 3 formed in step 7 is used as a mask, and the ion implantation method is adopted from both sides of the gate structure 3 As ions are implanted into the substrate 1 to form the first lightly doped region 51a and the second lightly doped region 61a, respectively.
  • LDD lightly doped drain process
  • the material of the substrate 1 is p-type doped Si (p-Si), where the first lightly doped region 51a and the second lightly doped region 61a are low energy shallow junction lightly doped n regions (n-)51a.
  • Step 9 Referring to Figure 2 and Figure 3e, according to the process flow S6, first, a chemical vapor deposition method is used to deposit a layer of silicon dioxide with a thickness of 120nm to cover the gate structure 3 and the substrate 1, and then a dry etching process is used to etch After this layer of silicon dioxide is etched away, due to the anisotropy, part of silicon dioxide remains on both sides of the gate structure 3 to form sidewall spacers 4.
  • Step 10 Referring to Figures 2 and 3f, according to the process flow S7, after the sidewall 4 is completed, ion implantation technology is used to inject phosphorous ions into the substrate 1 from both sides of the sidewall 4 to inject phosphorous ions on both sides of the sidewall 4 A lightly doped region 51a and a second lightly doped region 61a form a first heavily doped region 52a and a second heavily doped region 62a, respectively.
  • the material of the substrate 1 is p-type doped Si (p-Si), where the first heavily doped region 52a and the second heavily doped region 62a are n-type heavily doped regions (n+ ).
  • Step 11 Referring to FIG. 2 and FIG. 3f, according to the process flow S8, a layer of electrode metal Ni with a thickness of 80 nm is deposited on the gate structure 3 and the substrate 1 using a magnetron sputtering process.
  • Step 12 Referring to Figure 2 and Figure 3f, according to the process flow S9, the structure formed in step 1 to step 11 is subjected to rapid thermal annealing (RTA), the annealing temperature is 700°C, the annealing time is about 30 seconds, and the annealing is in N 2 atmosphere In progress.
  • RTA rapid thermal annealing
  • the formation principle and process of the hafnium oxide-based ferroelectric thin film 33b, the source region 5, the drain region 6, the first metal silicide layer 71, and the second metal silicide layer 72 are the same as those of the first embodiment, and are not here. Repeat it again.
  • Step 13 Referring to FIG. 2 and FIG. 3f, according to the process flow S10, the electrode metal deposited in step 11 and unreacted in step 12 is annealed by a wet process to obtain a hafnium oxide-based ferroelectric gate field effect transistor.
  • implementation 3 provides a method for preparing a hafnium oxide-based ferroelectric gate field effect transistor, wherein the selected substrate 1 is n-type doped silicon (n-Si), the preparation The method includes the following steps:
  • Step 1 Referring to FIG. 2 and FIG. 3a, first, the substrate 1 is cleaned using a standard cleaning process according to the process flow S1. Then, according to the process flow S2, an isolation region 2 is formed on the substrate 1 through a shallow trench isolation (STI) technology, and the area outside the isolation region 2 is defined as an active region.
  • STI shallow trench isolation
  • Step 2 Referring to Figure 2 and Figure 3b, first use a standard cleaning process to clean the substrate 1 again to remove the oxide layer on the surface of the active area.
  • process flow S31 first use a chemical oxidation process to grow 0.7nm SiO on the substrate 1 2. Then, an atomic layer deposition process is used to deposit La 2 O 3 of 3 nm, and the grown SiO 2 and La 2 O 3 together serve as the buffer layer 31.
  • Step 3 Referring to FIGS. 2 and 3b, according to the process flow S32, a magnetron sputtering deposition process is used to form HfN 0.8 with a thickness of 15 nm as the floating gate electrode 32 on the buffer layer 31 formed in Step 2.
  • Step 4 Referring to Figures 2 and 3b, according to the process flow S33, a magnetron sputtering deposition process is used to deposit a doped hafnium oxide thin film layer 33a with a thickness of 8 nm on the floating gate electrode 32 formed in step 3, and the doped hafnium oxide thin film layer
  • the material of 33a is Si-doped hafnium oxide (Si:HfO 2 ), and the doping content is 4%.
  • Step 5 Referring to FIG. 2 and FIG. 3b, according to the process flow S34, a magnetron sputtering process is used to deposit HfN 1.1 with a thickness of 5 nm on the doped hafnium oxide thin film layer 33a as the control gate electrode 34.
  • Step 6 Referring to Figure 2 and Figure 3b, according to the process flow S35, a thin film electrode layer 35 with a thickness of 80nm is deposited on the HfN 1.1 control gate electrode 34 described in step 5 by using a chemical vapor deposition process.
  • the material of the thin film electrode layer 35 is TiN .
  • Step 7 Referring to FIG. 2 and FIG. 3c, according to the process flow S4, the multi-layer thin film structure formed in Step 2 to Step 6 is etched by the reactive ion etching technique to form the gate structure 3.
  • Step 8 Referring to Figures 2 and 3d, according to the lightly doped drain process (LDD) in the process flow S5, the gate structure 3 formed in step 7 is used as a mask, and the ion implantation method is adopted from both sides of the gate structure 3 B ions are implanted into the substrate 1 to form first lightly doped regions 51a and second lightly doped regions 61a, respectively.
  • LDD lightly doped drain process
  • the material of the substrate 1 is n-type doped silicon (n-Si), where the first lightly doped region 51a and the second lightly doped region 61a are low energy shallow junction lightly doped p regions ( p-).
  • Step 9 Referring to Figures 2 and 3e, according to the process flow S6, a layer of silicon dioxide with a thickness of 150nm is deposited on the gate structure 3 and the substrate 1 by a chemical vapor deposition method, and then a dry etching process is used to etch After this layer of silicon dioxide is etched away, due to the anisotropy, part of silicon dioxide remains on both sides of the gate structure 3 to form sidewall spacers 4.
  • Step 10 Referring to Figures 2 and 3f, according to the process flow S7, after the sidewall 4 is completed, ion implantation technology is used to inject B ions into the substrate 1 from both sides of the sidewall 4 to inject B ions on both sides of the sidewall 4 A lightly doped region 51a and a second lightly doped region 61a form a first heavily doped region 52a and a second heavily doped region 62a, respectively.
  • the material of the substrate 1 is n-type doped silicon (n-Si), where the first heavily doped region 52a and the second heavily doped region 62a are n-type heavily doped regions (p+ ).
  • Step 11 Referring to FIG. 2 and FIG. 3f, according to the process flow S8, a layer of electrode metal Co with a thickness of 100 nm is deposited on the gate structure 3 and the substrate 1 using a magnetron sputtering process.
  • Step 12 Referring to Figure 2 and Figure 3f, according to the process flow S9, the device structure formed in step 11 is subjected to rapid thermal annealing (RTA), the annealing temperature is 1000°C, the annealing time is about 1 second, and the annealing is performed in an Ar atmosphere .
  • RTA rapid thermal annealing
  • the formation principle and process of the hafnium oxide-based ferroelectric thin film layer 33b, the source region 5, the drain region 6, the first metal silicide layer 71 and the second metal silicide layer 72 are the same as those of the first embodiment. No longer.
  • Step 13 Referring to FIG. 2 and FIG. 3f, according to the process flow S10, the electrode metal deposited in step 11 and unreacted in step 12 is annealed by a wet process to obtain a hafnium oxide-based ferroelectric gate field effect transistor.
  • the preparation method of the hafnium oxide-based ferroelectric gate field effect transistor in this embodiment adopts the hafnium oxide-based ferroelectric thin film, so that the prepared hafnium oxide-based ferroelectric gate field effect transistor has better scalability and can improve the memory
  • the storage density of the ferroelectric gate field effect transistor in the prior art is solved, the technical problem of the poor shrinkage of the ferroelectric gate field effect transistor in the prior art and the limitation of the scaling process of the device is solved; by adopting the HfN x (0 ⁇ x ⁇ 1.1) with excellent thermal stability
  • HfN x (0 ⁇ x ⁇ 1.1) As a floating gate electrode and a control gate electrode, HfN x (0 ⁇ x ⁇ 1.1) as a Hf-based metal can solve the problem that the floating gate electrode and the control gate electrode in the prior art will interact with the hafnium oxide-based iron during the crystallization annealing process.
  • the interface reaction of the electrical thin film avoids element diffusion and improves the electrical reliability of the ferroelectric gate field effect transistor.
  • HfN x is easy to etch, which is beneficial to device integration and solves the problem of floating gate electrodes and control gate electrodes in the prior art. Integration process problems caused when using Pt electrodes.
  • the invention aims to protect a hafnium oxide-based ferroelectric gate field effect transistor and a preparation method thereof, and has the following beneficial technical effects:
  • HfN x (0 ⁇ x ⁇ 1.1) with excellent thermal stability as the floating gate electrode and control gate electrode, and HfN x (0 ⁇ x ⁇ 1.1) as the Hf series metal, it is a good solution to the existing technology
  • the floating gate electrode and the control gate electrode react with the interface of the hafnium oxide-based ferroelectric thin film during the crystallization annealing process, thereby avoiding element diffusion and improving the electrical reliability of the ferroelectric gate field effect transistor.
  • the preparation method of the hafnium oxide-based ferroelectric gate field effect transistor provided by the present invention is a front gate process, which can achieve high integration density, and introduces a self-aligned process, that is, the gate structure formed after etching is used as a mask, Then an ion implantation process is used to form lightly doped regions on both sides of the gate structure. This method can reduce the process difficulty.
  • the implanted ions are activated to form the source and drain regions of the hafnium oxide-based ferroelectric gate field effect transistor; on the other hand, the doped hafnium oxide film layer is crystallized to form a ferroelectric phase , That is, a hafnium oxide-based ferroelectric film is formed; a metal silicide layer can also be formed on the source region, the drain region and the gate structure to reduce the contact resistance.

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Abstract

一种氧化铪基铁电栅场效应晶体管，包括：衬底；隔离区，设置在衬底的周边；栅结构，包括由下至上依次层叠设置在衬底上表面中部的缓冲层、浮栅电极、氧化铪基铁电薄膜层、控制栅电极和薄膜电极层；侧墙，设置在栅结构外侧；源区和漏区，相对设置在栅结构的两侧，由隔离区的内侧朝衬底的中部延伸形成；第一金属硅化物层，由隔离区的内侧朝侧墙延伸形成；第二金属硅化物层，设置在栅结构上表面，且其下表面紧贴栅结构；浮栅电极和控制栅电极的材料为HfN x，0<x≤1.1。本发明引入浮栅电极，可改善器件的工作特性，而采用热稳定性能优异的HfN x(0<x≤1.1)作为浮栅电极和控制栅电极，可缓解器件制备过程中的界面反应和元素扩散现象，提高了器件的电学可靠性。

Description

一种氧化铪基铁电栅场效应晶体管及其制备方法
本申请基于申请号为201910233623.6、申请日为2019年3月26日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明涉及电子技术领域，尤其涉及一种氧化铪基铁电栅场效应晶体管及其制备方法。
背景技术
随着信息技术的不断发展，现有的计算机存储架构以及DRAM和FLASH等主流存储器越来越难以满足高速计算和低功耗的需求，发展新型存储器技术已成为必然趋势。2016年发布的国际器件与系统路线图(IRDS)指出，铁电栅场效应晶体管(FeFET)存储器是目前最具前景的新型存储器技术之一，具有存取速度快、功耗低、非挥发性和结构简单等优势。FeFET与传统的场效应晶体管(MOSFET)结构类似，以铁电薄膜材料替代栅氧介质层作为存储介质。目前，FeFET存储器的结构主要可分为两种，一是浮栅型FeFET，其栅结构为金属电极(M)/铁电薄膜(F)/金属电极(M)/缓冲层(I)/半导体(S)，即MFMIS，另一种是MFIS-FET，即栅结构为金属电极(M)/铁电薄膜(F)/缓冲层(I)/半导体(S)，即MFIS。相比MFIS-FET存储器，MFMIS-FET存储器具有更好的保持性能，且可以调节浮栅和控制栅的面积增加器件的存储窗口、降低擦写电压和提高疲劳性能。
现有技术中存在的浮栅型铁电栅场效应晶体管主要有以下三种，但这三种铁电栅场效应晶体管分别存在如下缺陷：
1、一种是栅结构为Pt/SrBi 2Ta 2O 9/Pt/SrTa 2O 6/SiON/Si的MFMIS-FET，通过设计控制栅和浮栅的面积，使SrBi 2Ta 2O 9铁电薄膜在较小的工作电压时即可处于饱和极化状态，实现了较大的存储窗口和优异的保持性能。然而， SrBi 2Ta 2O 9铁电薄膜材料的微缩性较差，厚度一般大于200nm，另一方面惰性金属Pt较难刻蚀，使得基于Pt/SrBi 2Ta 2O 9/Pt/SrTa 2O 6/SiON/Si结构的MFMIS-FET等比例缩小工艺受限。
2、一种是Pt/Pb(Zr 0.52Ti 0.48)O 3/Poly-Si/SiO 2/Si的n型MFPIS-FET。该结构将poly-Si作为浮栅，工艺更为简单，还可以阻挡Pb(Zr 0.52Ti 0.48)O 3的成分向衬底扩散，更有利于铁电工艺和半导体工艺的集成。但是，Pb(Zr 0.52Ti 0.48)O 3薄膜的微缩性较差，厚度一般大于70nm，且Pb为易挥发性元素增加了工艺集成难度，而顶电极依然采用惰性Pt，使得基于Pt/Pb(Zr 0.52Ti 0.48)O 3/Poly-Si/SiO 2/Si结构的MFMIS-FET等比例缩小工艺受限。
3、一种是氧化铪基铁电薄膜的MFMIS栅结构，该栅结构存在的不足之处是：该栅结构的浮栅(底电极)和控制栅(顶电极)均采用TaN电极，但TaN电极在退火过程中易与氧化铪基铁电薄膜反应生成界面层，且可能发生金属元素的扩散，因而降低了器件的电学性能；当进一步地缩小器件尺寸时，其电学性能退化现象更加明显。
发明内容
(一)发明目的
本发明的目的是针对现有浮栅型铁电栅场效应晶体管技术中存在的可靠性问题，以及工艺方面的不足等问题，提供一种氧化铪基铁电栅场效应晶体管及其制备方法，以实现该器件的高可靠集成。
(二)技术方案
为解决上述问题，本发明的第一方面提供了一种氧化铪基铁电栅场效应晶体管，包括：衬底；隔离区，设置在所述衬底的周边，其上表面不低于所述衬底的上表面，且底面不低于所述衬底的底面；栅结构，包括由下至上依次层叠设置在所述衬底上表面中部的缓冲层、浮栅电极、氧化铪基铁电薄膜层、控制栅电极和薄膜电极层；侧墙，设置在所述栅结构外侧，其内表面紧 贴所述栅结构；源区和漏区，相对设置在所述栅结构的两侧，由所述隔离区的内侧朝向所述衬底的中部延伸形成，其上表面与所述衬底齐平，且底面不低于所述隔离区的底面；第一金属硅化物层，由所述隔离区的内侧朝向所述侧墙延伸形成，其上表面高于所述衬底的上表面，底面高于所述隔离区的底面，且所述第一金属硅化物层的长度小于所述源区或漏区的长度；第二金属硅化物层，设置在所述栅结构上表面，且其下表面紧贴所述栅结构；所述浮栅电极和控制栅电极的材料为HfN x，其中，0<x≤1.1。
进一步的，所述的缓冲层材料为SiO 2、SiON、Al 2O 3、La 2O 3、HfO 2、HfON、HfSiON、铝掺杂HfO 2(Al:HfO 2)中的任意一种或多种。
进一步的，所述缓冲层的厚度为3～10nm。
进一步的，所述浮栅电极和控制栅电极的厚度均为5～50nm。
进一步的，所述薄膜电极层的材料为多晶硅、非晶硅、W、TaN、TiN和HfN x(0＜x≤1.1)中的任意一种或多种。
进一步的，所述薄膜电极层的厚度为10～200nm。
进一步的，所述第一金属硅化物层和第二金属硅化物层的材料为TiSi 2，CoSi 2，NiSi 2中的任意一种。
进一步的，所述第一金属硅化物层和第二金属硅化物层的厚度均为5～30nm。
进一步的，所述氧化铪基铁电薄膜层中的掺杂元素为锆(Zr)、铝(Al)、硅(Si)、钇(Y)、锶(Sr)、镧(La)、镥(Lu)、钆(Gd)、钪(Sc)、钕(Nd)、锗(Ge)、氮(N)中的至少一种；进一步优选的，所述掺杂元素为锆(Zr)、铝(Al)、硅(Si)和镧(La)中的至少一种。
进一步的，所述氧化铪基铁电薄膜层的厚度为3～20nm。
本发明第二方面提供了一种上述氧化铪基铁电栅场效应晶体管的制备方法，包括：
S1，清洗衬底；
S2，在所述衬底的周边设置隔离区，所述隔离区的上表面不低于所述衬 底的上表面，且底面不低于所述衬底的底面；
S3，在所述衬底上形成多层薄膜结构；
S4，刻蚀S3形成的所述多层薄膜结构，形成栅结构；
S5，在所述衬底上、栅结构的两侧采用轻掺杂漏工艺分别形成第一轻掺杂区和第二轻掺杂区；
S6，在所述栅结构的两侧形成侧墙，所述侧墙的内表面紧贴所述栅结构；
S7，在所述侧墙两侧的第一轻掺杂区和第二轻掺杂区分别形成第一重掺杂区和第二重掺杂区；
S8，在S7形成的器件结构上沉积电极金属；
S9，将S8所形成的器件结构进行快速热退火，以激活步骤S5和S7中注入的离子以形成源区和漏区，以及在所述源区和漏区上方形成第一金属硅化物层，并在所述栅结构上表面形成第二金属硅化物层；
S10，刻蚀掉S8沉积的而S9退火未反应的电极金属，得到所述的氧化铪基铁电栅场效应晶体管。
进一步的，S3所述的形成多层薄膜结构的操作包括以下步骤：
S31，在所述衬底上表面形成缓冲层；优选的，形成缓冲层的工艺为原子层沉积工艺、化学气相沉积工艺、化学氧化工艺或热氧化工艺；
S32，在所述缓冲层上表面形成浮栅电极；优选的，形成浮栅电极的工艺为原子层沉积工艺、化学气相沉积工艺或磁控溅射工艺；
S33，在所述浮栅电极上表面形成掺杂氧化铪薄膜层；优选的，形成掺杂氧化铪薄膜层的工艺为原子层沉积工艺、金属有机物化学气相沉积工艺或磁控溅射工艺；
S34，在所述掺杂氧化铪薄膜层上表面形成控制栅电极；优选的，形成控制栅电极的工艺为磁控溅射工艺、化学气相沉积工艺、或原子层沉积工艺；
S35，在所述控制栅电极上表面形成薄膜电极层；优选的，形成薄膜电极层的工艺为磁控溅射工艺或化学气相沉积工艺。
进一步的，S4所述的刻蚀工艺为反应离子刻蚀工艺。
进一步的，S7所述的操作包括：采用离子注入工艺，在所述侧墙两侧的第一轻掺杂区和第二轻掺杂区分别形成第一重掺杂区和第二重掺杂区。
进一步的，S8所述的沉积电机金属的工艺为磁控溅射工艺或化学气相沉积工艺。
进一步的，S9所述的快速热退火操作中，还包括：
所述掺杂的氧化铪基薄膜层形成铁电相，形成掺杂的氧化铪基铁电薄膜层。
进一步的，S9所述的快速热退火操作中，退火温度为400～1000℃，退火时间为1～60秒；和/或所述快速热退火操作在真空或惰性气体中进行；优选的，所述惰性气体为N 2或Ar。
进一步的，S10所述的刻蚀工艺为湿法刻蚀工艺。
(三)有益效果
本发明的上述技术方案具有如下有益的技术效果：
1、通过采用热稳定性能优异的HfN x(0<x≤1.1)作为浮栅电极和控制栅电极，HfN x(0<x≤1.1)作为Hf系金属，很好的解决了现有技术中的浮栅电极和控制栅电极在结晶退火过程中与氧化铪基铁电薄膜的界面反应，避免了元素扩散，提高了氧化铪基铁电栅场效应晶体管的电学可靠性。
2、本发明提供的氧化铪基铁电栅场效应晶体管的制备方法为前栅工艺，能够实现高的集成密度，并且引入自对准工艺，即以刻蚀后形成的栅结构为掩膜，然后采用离子注入工艺，在栅结构两侧形成轻掺杂区，这种方法可降低工艺难度。
3.采用RTA技术，简化了工艺操作，一方面激活了注入的离子形成氧化铪基铁电栅场效应晶体管的源区和漏区；另一方面使掺杂氧化铪薄膜层结晶形成铁电相，即形成氧化铪基铁电薄膜；还可在源区、漏区和栅结构上形成金属硅化物层，降低了接触电阻。
附图说明
图1是本发明实施例提供的氧化铪基铁电栅场效应晶体管的结构示意图；
图2是本发明实施例提供的氧化铪基铁电栅场效应晶体管的制备方法的流程图；
图3a-3f是本发明实施例提供的氧化铪基铁电栅场效应晶体管的制备过程示意图。
附图标记：
1：衬底；2：隔离区；3：栅结构；31：缓冲层；32：浮栅电极；33a：掺杂氧化铪薄膜层；33b：氧化铪基铁电薄膜层(由32a退火后形成)；34：控制栅电极；35：薄膜电极层；4：侧墙；5：源区；51a：第一轻掺杂区；52a：第一重掺杂区；51b:激活的第一轻掺杂区(由51a退火后形成)：52b：激活的第一重掺杂区(由52a退火后形成)：6：漏区；61a：第二轻掺杂区；62a：第二重掺杂区；61b:激活的第二轻掺杂区(由61a退火后形成)：62b：激活的第二重掺杂区(由62a退火后形成)；71：第一金属硅化物层；72：第二金属硅化物层。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明了，下面结合具体实施方式并参照附图，对本发明进一步详细说明。应该理解，这些描述只是示例性的，而并非要限制本发明的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本发明的概念。
在本发明的描述中，需要说明的是，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。
图1是本发明实施例提供的氧化铪基铁电栅场效应晶体管的结构示意图。
请参照图1，本发明实施例提供一种氧化铪基铁电栅场效应晶体管，包 括：衬底1、隔离区2、栅结构3、侧墙4、源区5、漏区6、第一金属硅化物层71和第二金属硅化物层72。
可选的，衬底1为p型或n型掺杂的单晶硅或绝缘体上硅(即Silicon-On-Insulator，简称为SOI)。
优选的，p型掺杂为掺杂元素硼(B)；n型为掺杂元素磷(P)或砷(As)。
隔离区2，设置在衬底1的周边，其上表面不低于衬底1的上表面，且底面不低于衬底1的底面。
可选的，隔离区2的材料为SiO 2、Si 3N 4中的至少一种。
栅结构3，包括由下至上依次层叠设置在衬底1上表面中部的缓冲层31、浮栅电极32、氧化铪基铁电薄膜层33b、控制栅电极34和薄膜电极层35。
可选的，缓冲层31材料为SiO 2、SiON、Al 2O 3、La 2O 3、HfO 2、HfON、HfSiON、铝掺杂HfO 2(Al:HfO 2)中的任意一种或多种。
可选的，缓冲层31厚度为3～10nm。
可选的，氧化铪基铁电薄膜层33b中的掺杂元素为锆(Zr)、铝(Al)、硅(Si)、钇(Y)、锶(Sr)、镧(La)、镥(Lu)、钆(Gd)、钪(Sc)、钕(Nd)、锗(Ge)、氮(N)中的至少一种。
优选的，氧化铪基铁电薄膜层33b中的掺杂元素为锆(Zr)、铝(Al)、硅(Si)和镧(La)中的至少一种。
可选的，氧化铪基铁电薄膜层33b的厚度为3～20nm。
可选的，浮栅电极32和控制栅电极34的材料为HfN x，HfN x中N原子数量为0＜x≤1.1。
可选的，浮栅电极32和控制栅电极34的厚度均为5～50nm。
可选的，薄膜电极层35的材料为多晶硅、非晶硅、W、TaN、TiN、HfN x(0＜x≤1.1)中的任意一种或多种。
可选的，薄膜电极层35的厚度为10～200nm。
侧墙4，设置栅结构3外侧，其内表面紧贴栅结构3。
源区5和漏区6，相对设置在栅结构3的两侧，由隔离区2的内侧朝向 衬底1的中部延伸形成，其上表面与衬底1齐平，且底面不低于隔离区2的底面。
第一金属硅化物层71，由隔离区2的内侧朝向侧墙4延伸形成，其上表面高于衬底1的上表面，底面高于隔离区2的底面，且第一金属硅化物层71的长度小于源区5或漏区6的长度。第一金属硅化物层71的长度是指沿隔离区2的内侧朝向侧墙4延伸方向的尺寸，即图1中左右方向的尺寸；源区5(或漏区6)的长度是指沿隔离区2的内侧朝向衬底1的中部延伸方向的尺寸。
第二金属硅化物层72，设置在栅结构3上表面，且其下表面紧贴栅结构3。
可选的，第一金属硅化物层71和第二金属硅化物层72的材料为TiSi 2，CoSi 2，NiSi 2中的任意一种。
可选的，第一金属硅化物层71和第二金属硅化物层72的厚度均为5～30nm。
在上述实施例中，当衬底1的材料为p型掺杂时，源区5和漏区6的材料为n型掺杂的单晶硅或绝缘体上硅；或者，当衬底1的材料为n型掺杂时，源区5和漏区6的材料为p型掺杂的单晶硅或绝缘体上硅。
在本发明的一个具体实施例中，该氧化铪基铁电栅场效应晶体管包括：衬底1、隔离区2、栅结构3、侧墙4、源区5、漏区6、第一金属硅化物层71和第二金属硅化物层72。
衬底1为p型掺杂的单晶硅；p型掺杂为掺杂元素硼(B)。
隔离区2，设置在衬底1的周边，其上表面不低于衬底1的上表面，且底面不低于衬底1的底面，其中，隔离区2的材料为SiO 2。
栅结构3，包括由下至上依次层叠设置在衬底1上表面中部的缓冲层31、浮栅电极32、氧化铪基铁电薄膜层33b、控制栅电极34、薄膜电极层35；其中，缓冲层31的材料为HfO 2,厚度为5nm；氧化铪基铁电薄膜层33b中的掺杂元素为锆(Zr)，掺杂量为50％，厚度为10nm；浮栅电极32和控制栅电极 34的材料为HfN，厚度均为10nm；薄膜电极层35的材料为多晶硅、厚度为50nm。
侧墙4，设置在栅结构3外侧，其内表面紧贴栅结构3；侧墙4的材料为SiO 2；栅结构3的横向宽度等于两个侧墙4之间的距离。
源区5和漏区6，相对设置在栅结构3的两侧，由隔离区2的内侧朝向衬底1的中部延伸形成，其上表面与衬底1齐平，底面高于隔离区2的底面；源区5和漏区6的掺杂元素为磷。
具体地，源区5包括激活的第一轻掺杂区51b和激活的第一重掺杂区52b；漏区6包括激活的第二轻掺杂区61b和激活的第二重掺杂区62b。激活的第一轻掺杂区51b和激活的第二轻掺杂区61b由轻掺杂区退火后形成，激活的第一重掺杂区52b和激活的第二重掺杂区62b由重掺杂区退火后形成。
第一金属硅化物层71，由隔离区2的内侧朝向侧墙4延伸形成，其上表面高于衬底1，底面高于隔离区2的底面，且第一金属硅化物层71的长度小于源区5和漏区6的长度；第一金属硅化物层71的材料为TiSi 2；第一金属硅化物层71的厚度为10nm。
第二金属硅化物层72，设置在栅结构3上表面，且其下表面紧贴栅结构3，第二金属硅化物层72的材料为TiSi 2；第二金属硅化物层72的厚度为10nm。
在本实施例中，图1所示源区5和漏区6的位置仅作为示例，但本发明不以此为限制，源区5和漏区6的位置可以调换。
图2是本发明实施例提供的氧化铪基铁电栅场效应晶体管的制备方法的流程图。
图3a-3f是本发明实施例提供的氧化铪基铁电栅场效应晶体管的制备过程示意图。
请参照图2和图3，本发明实施例还提供一种氧化铪基铁电栅场效应晶体管的制备方法，用于上述实施例中的氧化铪基铁电栅场效应晶体管的制备，包括：
S1，清洗衬底1。
S2，在衬底1的周边设置隔离区2，隔离区2的上表面不低于衬底1的上表面，且底面高于衬底1的底面。
S3，在衬底1上形成多层薄膜结构。
其中，步骤S3形成多层薄膜结构的操作包括以下步骤：
S31，在衬底1上表面形成缓冲层31。
可选的，形成缓冲层31的工艺为原子层沉积工艺、化学气相沉积工艺、化学氧化工艺或热氧化工艺。
S32，在缓冲层31上表面形成浮栅电极32。其中，浮栅电极32的材料为HfN x，HfN x中N原子数量为0＜x≤1.1；浮栅电极32的厚度为5～50nm。
可选的，形成浮栅电极32的工艺为原子层沉积工艺、化学气相沉积工艺或磁控溅射工艺。
S33，在浮栅电极32上表面形成掺杂氧化铪薄膜层33a。其中，掺杂氧化铪薄膜层33a中的掺杂元素为锆(Zr)、铝(Al)、硅(Si)、钇(Y)、锶(Sr)、镧(La)、镥(Lu)、钆(Gd)、钪(Sc)、钕(Nd)、锗(Ge)、氮(N)中的至少一种。
可选的，形成掺杂氧化铪薄膜层33a的工艺为原子层沉积工艺、金属有机物化学气相沉积工艺或磁控溅射工艺。
S34，在掺杂氧化铪薄膜层33a上表面形成控制栅电极34。其中，控制栅电极34的材料为HfN x，HfN x中N原子数量为0＜x≤1.1；控制栅电极34的厚度为5～50nm。
可选的，形成控制栅电极34的工艺为磁控溅射工艺、化学气相沉积工艺、或原子层沉积工艺。
S35，在控制栅电极34上表面形成薄膜电极层35。
可选的，形成薄膜电极层35的工艺为磁控溅射工艺或化学气相沉积工艺。
S4，刻蚀S3形成的多层薄膜结构，形成栅结构3。
可选的，刻蚀工艺为反应离子刻蚀工艺。
S5，在衬底1上、栅结构3的两侧采用轻掺杂漏工艺形成分别形成第一 轻掺杂区51a和第二轻掺杂区61a。
可选的，S5的轻掺杂漏工艺包括以下步骤：
以S4形成的栅结构3为掩模，采用离子注入方法在栅结构3的两侧分别形成第一轻掺杂区51a和第二轻掺杂区61a。
S6，在栅结构3的两侧形成侧墙4，侧墙4的内表面紧贴栅结构3。
具体地，S6的步骤包括：采用化学气相沉积工艺在S5形成的器件结构上沉积绝缘介质层，然后采用反应离子刻蚀工艺刻蚀绝缘介质层以形成侧墙4。
可选的，绝缘介质层的材料为SiO 2、Si 3N 4中的至少一种。
S7，在侧墙4两侧的第一轻掺杂区51a和第二轻掺杂区61a分别形成第一重掺杂区52a和第二重掺杂区62a。
可选的，采用离子注入工艺，在侧墙4两侧的第一轻掺杂区51a和第二轻掺杂区61a分别形成第一重掺杂区52a和第二重掺杂区62a。
S8，在S7形成的器件结构上沉积电极金属。
可选的，沉积电极金属的工艺为磁控溅射工艺或化学气相沉积工艺。
可选的，电极金属为Ti、Co、Ni中的任意一种。
S9，将S8所形成的器件结构进行快速热退火，以激活步骤S5和S7中注入的离子以形成源区5和漏区6，以及在源区5和漏区6上方形成第一金属硅化物层71，并在栅结构3上表面形成第二金属硅化物层72。
其中，激活步骤S5和S7中注入的离子以形成源区5和漏区6的步骤包括：
S91，激活第一轻掺杂区51a和第一重掺杂区52a中注入的离子形成激活的第一轻掺杂区51b和激活的第一重掺杂区52b，该激活的第一轻掺杂区51b和激活的第一重掺杂区52b构成源区5。
S92，激活第二轻掺杂区61a和第二重掺杂区62a中注入的离子形成激活的第二轻掺杂区61b和激活的第二重掺杂区62b，该激活的第二轻掺杂区61b和激活的第二重掺杂区62b构成漏区6。
步骤S91和步骤S92的顺序包括但不限于上述顺序，步骤S91和步骤S92的顺序可同步进行，也可根据实际需要适当调整。
其中，在步骤S9快速热退火操作中，还包括：
掺杂氧化铪基薄膜层形成铁电相，即形成氧化铪基铁电薄膜层33b。
可选的，步骤S9的快速热退火操作中，退火温度为400～1000℃。
可选的，步骤S9的快速热退火操作中，退火时间为1～60秒。
可选的，快速热退火操作在真空或惰性气体中进行。
优选的，惰性气体为N 2或Ar。
可选的，第一金属硅化物层71和第二金属硅化物层72的材料为TiSi 2、CoSi 2、NiSi 2中的任意一种。
可选的，第一金属硅化物层71和第二金属硅化物层72的厚度均为5～30nm。
S10，刻蚀掉S8沉积的而S9退火未反应的电极金属，得到氧化铪基铁电栅场效应晶体管。
可选的，刻蚀工艺为湿法刻蚀工艺。
在上述实施例中，图3d和图3e中所示第一轻掺杂区51a、第二轻掺杂区61a的位置仅作为示例，但本发明不以此为限制，第一轻掺杂区51a和第二轻掺杂区61a的位置可以调换，相应的，图3e中第一重掺杂区52a、第二轻掺杂区62a的位置，以及图3f中的激活的第一轻掺杂区51b和激活的第二轻掺杂区61b的位置，激活的第一重掺杂区52b和激活的第二重掺杂区62b的位置相应调整。
下面结合具体实施例，介绍本发明的氧化铪基铁电栅场效应晶体管的制备方法。
实施例1
请参照图2以及图3a-3f，实施例1提供了一种氧化铪基铁电栅场效应晶体管的制备方法，其中，所选衬底1为p型掺杂Si(p-Si)，该制备方法包括以下步骤：
步骤一：参照图2和图3a，首先根据工艺流程S1采用标准清洗工艺清洗衬底1。然后根据工艺流程S2通过硅局部氧化(LOCOS)工艺形成隔离区2，隔离区2外的区域定义为有源区。
步骤二：参照图2和图3b，首先采用标准清洗工艺再次清洗衬底1，去除有源区表面的氧化层，根据工艺流程S31采用原子层沉积工艺沉积5nm的缓冲层31，缓冲层31的材料为HfO 2。
步骤三：参照图2和图3b，根据工艺流程S32采用磁控溅射工艺在步骤二形成的缓冲层31上形成厚度为10nm的HfN作为浮栅电极32。
步骤四：参照图2和图3b，根据工艺流程S33采用原子层沉积工艺在步骤三形成的浮栅电极32上沉积厚度为10nm的掺杂氧化铪薄膜层33a，其中，掺杂氧化铪薄膜层33a的材料为Hf 0.5Zr 0.5O 2。
步骤五：参照图2和图3b，根据工艺流程S34采用磁控溅射工艺在掺杂氧化铪薄膜层33a上沉积厚度为10nm的HfN作为控制栅电极34。
步骤六：参照图2和图3b，根据工艺流程S35采用化学气相沉积工艺在步骤五所述的HfN控制栅电极34上沉积厚度为50nm的薄膜电极层35，薄膜电极层35的材料为多晶硅。
步骤七：参照图2和图3c，根据工艺流程S4采用反应离子刻蚀技术刻蚀步骤二至步骤六形成的多层薄膜结构，形成栅结构3。
步骤八：参照图2和图3d，根据工艺流程S5中的轻掺杂漏工艺(LDD)，以步骤七形成的栅结构3为掩模，采用离子注入方法，从栅结构3两侧往衬底1中注入As离子以分别形成第一轻掺杂区51a和第二轻掺杂区61a。
在该实施例1中，衬底1的材料为p型掺杂Si(p-Si)，此处第一轻掺杂区51a和第二轻掺杂区61a为低能量浅结轻掺n区域(n-)。
步骤九：参照图2和图3e，根据工艺流程S6，首先采用化学气相沉积法沉积一层厚度为100nm的二氧化硅覆盖在栅结构3和衬底1上，随后用干法刻蚀工艺刻蚀掉这一层二氧化硅，由于各向异性，在栅结构3的两侧保留了部分二氧化硅，形成侧墙4。
步骤十：参照图2和图3f，根据工艺流程S7，在侧墙4完成后，采用离子注入技术，从侧墙4两侧往衬底1中注入磷离子以在侧墙4两侧的第一轻掺杂区51a和第二轻掺杂区61a分别形成第一重掺杂区52a和第二重掺杂区62a。
在该实施例1中，衬底1的材料为p型掺杂Si(p-Si)，此处第一重掺杂区52a和第二重掺杂区62a为n型重掺杂区(n+)。
步骤十一：参照图2和图3f，根据工艺流程S8，采用磁控溅射工艺沉积一层厚度为50nm的电极金属Ti覆盖在栅结构3和衬底1上。
步骤十二：参照图2和图3f，根据工艺流程S9，将步骤十一形成的器件结构进行快速热退火(RTA)，退火温度为500℃，退火时间约60秒，退火在N 2气氛中进行。
具体地，快速热退火的步骤包括：
1、激活第一轻掺杂区51a和第一重掺杂区52a中注入的离子形成激活的第一轻掺杂区51b和激活的第一重掺杂区52b，该激活的第一轻掺杂区51b和激活的第一重掺杂区52b构成源区5。
2、激活第二轻掺杂区61a和第二重掺杂区62a中注入的离子，形成激活的第二轻掺杂区61b和激活的第二重掺杂区62b，该激活的第二轻掺杂区61b和激活的第二重掺杂区62b构成漏区6。
3、使掺杂氧化铪薄膜层33a结晶形成氧化铪基铁电薄膜33b。
4、在源区5和漏区6上方形成第一金属硅化物层71，以及在栅结构3上表面形成第二金属硅化物层72。
步骤十三：参照图2和图3f，根据工艺流程S10，采用湿法工艺刻蚀掉步骤十一沉积的而步骤十二退火未反应的电极金属，得到氧化铪基铁电栅场效应晶体管。
实施例2
请参照图2以及图3a-3f，实施例2提供了一种氧化铪基铁电栅场效应晶体管的制备方法，其中，所选衬底1为p型SOI基板，该制备方法包括以 下步骤：
步骤一：参照图2和图3a，首先根据工艺流程S1采用标准清洗工艺清洗衬底1。然后根据工艺流程S2采用反应离子刻蚀工艺刻蚀隔离区2处的硅衬底，以在衬底1上形成孤岛(Mesa)结构实现隔离，隔离区2外的区域定义为有源区。
步骤二：参照图2和图3b，首先采用标准清洗工艺再次清洗衬底1，去除有源区表面的氧化层，根据工艺流程S31采用化学气相沉积工艺沉积5nm的缓冲层31，缓冲层31的材料为Al 2O 3。
步骤三：参照图2和图3b，根据工艺流程S32采用化学气相沉积工艺在步骤二形成的缓冲层31上形成厚度为20nm的HfN 0.5作为浮栅电极32；
步骤四：参照图2和图3b，根据工艺流程S33采用原子层沉积工艺在步骤三形成的浮栅电极32上沉积厚度为15nm的掺杂氧化铪薄膜层33a，掺杂氧化铪薄膜层33a的材料为Al掺杂氧化铪(Al:HfO 2)，掺杂含量为4.8％。
步骤五：参照图2和图3b，根据工艺流程S34采用化学气相沉积工艺在掺杂氧化铪薄膜层33a上沉积厚度为5nm的HfN 0.5作为控制栅电极34。
步骤六：参照图2和图3b，根据工艺流程S35采用磁控溅射工艺在步骤五HfN 0.5控制栅电极34上沉积厚度为50nm的薄膜电极层35，薄膜电极层35的材料为W。
步骤七：参照图2和图3c，根据工艺流程S4采用反应离子刻蚀技术刻蚀步骤二至步骤六形成的多层薄膜结构，形成栅结构3。
步骤八：参照图2和图3d，根据工艺流程S5中的轻掺杂漏工艺(LDD)，以步骤七形成的栅结构3为掩模，采用离子注入方法，从栅结构3的两侧往衬底1中注入As离子以分别形成第一轻掺杂区51a和第二轻掺杂区61a。
在该实施例2中，衬底1的材料为p型掺杂Si(p-Si)，此处第一轻掺杂区51a和第二轻掺杂区61a为低能量浅结轻掺n区域(n-)51a。
步骤九：参照图2和图3e，根据工艺流程S6，首先采用化学气相沉积法沉积一层厚度为120nm的二氧化硅覆盖在栅结构3和衬底1上，随后用干法 刻蚀工艺刻蚀掉这一层二氧化硅，由于各向异性，在栅结构3的两侧保留了部分二氧化硅，形成侧墙4。
步骤十：参照图2和图3f，根据工艺流程S7，在侧墙4完成后，采用离子注入技术，从侧墙4两侧往衬底1中注入磷离子以在侧墙4两侧的第一轻掺杂区51a和第二轻掺杂区61a分别形成第一重掺杂区52a和第二重掺杂区62a。
在该实施例2中，衬底1的材料为p型掺杂Si(p-Si)，此处第一重掺杂区52a和第二重掺杂区62a为n型重掺杂区(n+)。
步骤十一：参照图2和图3f，根据工艺流程S8，采用磁控溅射工艺沉积一层厚度为80nm的电极金属Ni覆盖在栅结构3和衬底1上。
步骤十二：参照图2和图3f，根据工艺流程S9，将步骤一至步骤十一形成的结构进行快速热退火(RTA)，退火温度为700℃，退火时间约30秒，退火在N 2气氛中进行。在该步骤中，氧化铪基铁电薄膜33b、源区5、漏区6、第一金属硅化物层71和第二金属硅化物层72的形成原理和过程与实施例1相同，在此不再赘述。
步骤十三：参照图2和图3f，根据工艺流程S10，采用湿法工艺刻蚀掉步骤十一沉积的而步骤十二退火未反应的电极金属，得到氧化铪基铁电栅场效应晶体管。
实施例3
请参照图2以及图3a-3f，实施3提供了一种氧化铪基铁电栅场效应晶体管的制备方法，其中，所选衬底1为n型掺杂硅(n-Si)，该制备方法包括以下步骤：
步骤一：参照图2和图3a，首先根据工艺流程S1采用标准清洗工艺清洗衬底1。然后根据工艺流程S2通过浅槽隔离(STI)技术在衬底1上形成隔离区2，隔离区2外的区域定义为有源区。
步骤二：参照图2和图3b，首先采用标准清洗工艺再次清洗衬底1，去除有源区表面的氧化层，根据工艺流程S31，首先采用化学氧化工艺在衬底1 上生长0.7nm的SiO 2，然后采用原子层沉积工艺沉积3nm的La 2O 3，生长的SiO 2和La 2O 3一起作为缓冲层31。
步骤三：参照图2和图3b，根据工艺流程S32采用磁控溅射沉积工艺在步骤二形成的缓冲层31上形成厚度为15nm的HfN 0.8作为浮栅电极32。
步骤四：参照图2和图3b，根据工艺流程S33采用磁控溅射沉积工艺在步骤三形成的浮栅电极32上沉积厚度为8nm的掺杂氧化铪薄膜层33a，掺杂氧化铪薄膜层33a的材料为Si掺杂氧化铪(Si:HfO 2)，掺杂含量为4％。
步骤五：参照图2和图3b，根据工艺流程S34采用磁控溅射工艺在掺杂氧化铪薄膜层33a上沉积厚度为5nm的HfN 1.1作为控制栅电极34。
步骤六：参照图2和图3b，根据工艺流程S35采用化学气相沉积工艺在步骤五所述的HfN 1.1控制栅电极34上沉积厚度为80nm的薄膜电极层35，薄膜电极层35的材料为TiN。
步骤七：参照图2和图3c，根据工艺流程S4采用反应离子刻蚀技术刻蚀步骤二至步骤六形成的多层薄膜结构，形成栅结构3。
步骤八：参照图2和图3d，根据工艺流程S5中的轻掺杂漏工艺(LDD)，以步骤七形成的栅结构3为掩模，采用离子注入方法，从栅结构3的两侧往衬底1中注入B离子以分别形成第一轻掺杂区51a和第二轻掺杂区61a。
在实施例3中，衬底1的材料为n型掺杂硅(n-Si)，此处第一轻掺杂区51a和第二轻掺杂区61a为低能量浅结轻掺p区域(p-)。
步骤九：参照图2和图3e，根据工艺流程S6，首先采用化学气相沉积法沉积一层厚度为150nm的二氧化硅覆盖在栅结构3和衬底1上，随后用干法刻蚀工艺刻蚀掉这一层二氧化硅，由于各向异性，在栅结构3的两侧保留了部分二氧化硅，形成侧墙4。
步骤十：参照图2和图3f，根据工艺流程S7，在侧墙4完成后，采用离子注入技术，从侧墙4两侧往衬底1中注入B离子以在侧墙4两侧的第一轻掺杂区51a和第二轻掺杂区61a分别形成第一重掺杂区52a和第二重掺杂区62a。
在该实施例3中，衬底1的材料为n型掺杂硅(n-Si)，此处第一重掺杂区52a和第二重掺杂区62a为n型重掺杂区(p+)。
步骤十一：参照图2和图3f，根据工艺流程S8，采用磁控溅射工艺沉积一层厚度为100nm的电极金属Co覆盖在栅结构3和衬底1上。
步骤十二：参照图2和图3f，根据工艺流程S9，将步骤十一形成的器件结构进行快速热退火(RTA)，退火温度为1000℃，退火时间约1秒，退火在Ar气氛中进行。在该步骤中，氧化铪基铁电薄膜层33b、源区5、漏区6、第一金属硅化物层71和第二金属硅化物层72的形成原理和过程与实施例1相同，在此不再赘述。
步骤十三：参照图2和图3f，根据工艺流程S10，采用湿法工艺刻蚀掉步骤十一沉积的而步骤十二退火未反应的电极金属，得到氧化铪基铁电栅场效应晶体管。
本实施例中的氧化铪基铁电栅场效应晶体管的制备方法，通过采用氧化铪基铁电薄膜，使得制备的氧化铪基铁电栅场效应晶体管具有较好的可微缩性，可提高存储器的存储密度，解决了现有技术中的铁电栅场效应晶体管微缩性较差，器件的等比例缩小工艺受限的技术问题；通过采用热稳定性能优异的HfN x(0<x≤1.1)作为浮栅电极和控制栅电极，HfN x(0<x≤1.1)作为Hf系金属，很好的解决了现有技术中的浮栅电极和控制栅电极在结晶退火过程中与氧化铪基铁电薄膜的界面反应，避免了元素扩散，提高了铁电栅场效应晶体管的电学可靠性；另外，HfN x容易刻蚀，有利于器件集成，解决了现有技术中浮栅电极和控制栅电极采用Pt电极时导致的集成工艺问题。
本发明旨在保护一种氧化铪基铁电栅场效应晶体管及其制备方法，具有如下有益的技术效果：
1、通过采用热稳定性能优异的HfN x(0<x≤1.1)作为浮栅电极和控制栅电极，HfN x(0<x≤1.1)作为Hf系金属，很好的解决了现有技术中的浮栅电极和控制栅电极在结晶退火过程中与氧化铪基铁电薄膜的界面反应，避免了元素扩散，提高了铁电栅场效应晶体管的电学可靠性。
2.本发明提供的氧化铪基铁电栅场效应晶体管的制备方法为前栅工艺，能够实现高的集成密度，并且引入自对准工艺，即以刻蚀后形成的栅结构为掩膜，然后采用离子注入工艺，在栅结构两侧形成轻掺杂区，这种方法可降低工艺难度。
3.采用RTA技术，简化了工艺操作，一方面激活了注入的离子形成氧化铪基铁电栅场效应晶体管的源区和漏区；另一方面使掺杂氧化铪薄膜层结晶形成铁电相，即形成氧化铪基铁电薄膜；还可在源区、漏区和栅结构上形成金属硅化物层，降低了接触电阻。
应当理解的是，本发明的上述具体实施方式仅仅用于示例性说明或解释本发明的原理，而不构成对本发明的限制。因此，在不偏离本发明的精神和范围的情况下所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。此外，本发明所附权利要求旨在涵盖落入所附权利要求范围和边界、或者这种范围和边界的等同形式内的全部变化和修改例。

Claims (10)

  1. 一种氧化铪基铁电栅场效应晶体管，其特征在于，包括：
    衬底(1)；
    隔离区(2)，设置在所述衬底(1)的周边，其上表面不低于所述衬底(1)的上表面，且底面不低于所述衬底(1)的底面；
    栅结构(3)，包括由下至上依次层叠设置在所述衬底(1)上表面中部的缓冲层(31)、浮栅电极(32)、氧化铪基铁电薄膜层(33b)、控制栅电极(34)和薄膜电极层(35)；
    侧墙(4)，设置在所述栅结构(3)外侧，其内表面紧贴所述栅结构(3)；
    源区(5)和漏区(6)，相对设置在所述栅结构(3)的两侧，由所述隔离区(2)的内侧朝向所述衬底(1)的中部延伸形成，其上表面与所述衬底(1)齐平，且底面不低于所述隔离区(2)的底面；
    第一金属硅化物层(71)，由所述隔离区(2)的内侧朝向所述侧墙(4)延伸形成，其上表面高于所述衬底(1)的上表面，底面高于所述隔离区(2)的底面，且所述第一金属硅化物层(71)的长度小于所述源区(5)或漏区(6)的长度；
    第二金属硅化物层(72)，设置在所述栅结构(3)上表面，且其下表面紧贴所述栅结构(3)；
    所述浮栅电极(32)和控制栅电极(34)的材料为HfN x，其中，0<x≤1.1。
  2. 根据权利要求1所述的氧化铪基铁电栅场效应晶体管，其特征在于，
    所述缓冲层(31)的材料为SiO 2、SiON、Al 2O 3、La 2O 3、HfO 2、HfON、HfSiON、铝掺杂HfO 2(Al:HfO 2)中的任意一种或多种；
    所述缓冲层(31)的厚度为3～10nm。
  3. 根据权利要求1-2任一项所述的氧化铪基铁电栅场效应晶体管，其特征在于，
    所述浮栅电极(32)和控制栅电极(34)的厚度均为5～50nm。
  4. 根据权利要求1-3任一项所述的氧化铪基铁电栅场效应晶体管，其特 征在于，
    所述薄膜电极层(35)的材料为多晶硅、非晶硅、W、TaN、TiN和HfN x(0＜x≤1.1)中的任意一种或多种；
    所述薄膜电极层(35)的厚度为10～200nm。
  5. 根据权利要求1-4任一项所述的氧化铪基铁电栅场效应晶体管，其特征在于，
    所述第一金属硅化物层(71)和第二金属硅化物层(72)的材料为TiSi 2、CoSi 2和NiSi 2中的任意一种；
    所述第一金属硅化物层(71)和第二金属硅化物层(72)的厚度均为5～30nm。
  6. 根据权利要求1-5中任一项所述的氧化铪基铁电栅场效应晶体管，其特征在于，
    所述氧化铪基铁电薄膜层(33b)中的掺杂元素为锆(Zr)、铝(Al)、硅(Si)、钇(Y)、锶(Sr)、镧(La)、镥(Lu)、钆(Gd)、钪(Sc)、钕(Nd)、锗(Ge)、氮(N)中的至少一种；
    所述氧化铪基铁电薄膜层(33b)的厚度为3～20nm。
  7. 一种氧化铪基铁电栅场效应晶体管的制备方法，其特征在于，包括：
    S1，清洗衬底(1)；
    S2，在所述衬底(1)的周边设置隔离区(2)，所述隔离区(2)的上表面不低于所述衬底(1)的上表面，且底面高于所述衬底(1)的底面；
    S3，在所述衬底(1)上形成多层薄膜结构；
    S4，刻蚀S3形成的所述多层薄膜结构，形成栅结构(3)；进一步的，所述刻蚀工艺为反应离子刻蚀工艺；
    S5，在所述衬底(1)上、栅结构(3)的两侧采用轻掺杂漏工艺分别形成第一轻掺杂区(51a)和第二轻掺杂区(61a)；
    S6，在所述栅结构(3)的两侧形成侧墙(4)，所述侧墙(4)的内表面紧贴所述栅结构(3)；
    S7，在所述侧墙(4)两侧的第一轻掺杂区(51a)和第二轻掺杂区(61a)分别形成第一重掺杂区(52a)和第二重掺杂区(62a)；进一步的，采用离子注入工艺，在所述侧墙(4)两侧的第一轻掺杂区(51a)和第二轻掺杂区(61a)分别形成第一重掺杂区(52a)和第二重掺杂区(62a)；
    S8，在S7形成的器件结构上沉积电极金属；进一步的，所述沉积电极金属的工艺为磁控溅射工艺或化学气相沉积工艺；
    S9，将S8所形成的器件结构进行快速热退火，以激活步骤S5和S7中注入的离子以形成源区(5)和漏区(6)，以及在所述源区(5)和漏区(6)上方形成第一金属硅化物层(71)，并在所述栅结构(3)上表面形成第二金属硅化物层(72)；
    S10，刻蚀掉S8沉积的而S9退火未反应的电极金属，得到所述的氧化铪基铁电栅场效应晶体管；进一步的，所述的刻蚀工艺为湿法刻蚀工艺。
  8. 根据权利要求7所述的氧化铪基铁电栅场效应晶体管的制备方法，其特征在于，S3所述的形成多层薄膜结构的操作包括以下步骤：
    S31，在所述衬底(1)上表面形成缓冲层(31)；优选的，形成缓冲层(31)的工艺为原子层沉积工艺、化学气相沉积工艺、化学氧化工艺或热氧化工艺；
    S32，在所述缓冲层(31)上表面形成浮栅电极(32)；优选的，形成浮栅电极(32)的工艺为原子层沉积工艺、化学气相沉积工艺或磁控溅射工艺；
    S33，在所述浮栅电极(32)上表面形成掺杂氧化铪薄膜层(33a)；优选的，形成掺杂氧化铪薄膜层(33a)的工艺为原子层沉积工艺、金属有机物化学气相沉积工艺或磁控溅射工艺；
    S34，在所述掺杂氧化铪薄膜层(33a)上表面形成控制栅电极(34)；优选的，形成控制栅电极(34)的工艺为磁控溅射工艺、化学气相沉积工艺、或原子层沉积工艺；
    S35，在所述控制栅电极(34)上表面形成薄膜电极层(35)；优选的，形成薄膜电极层(35)的工艺为磁控溅射工艺或化学气相沉积工艺。
  9. 根据权利要求8所述的氧化铪基铁电栅场效应晶体管的制备方法，其 特征在于，S9所述的快速热退火操作中，还包括：
    所述掺杂氧化铪基薄膜层(33a)形成铁电相，即形成氧化铪基铁电薄膜层(33b)。
  10. 根据权利要求7所述的氧化铪基铁电栅场效应晶体管的制备方法，其特征在于，
    S9所述的快速热退火操作中，退火温度为400～1000℃，退火时间为1～60秒；和/或
    所述快速热退火操作在真空或惰性气体中进行；优选的，所述惰性气体为N 2或Ar。
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